Re: [Freedreno] [PATCH v2 2/9] drm/msm/dpu: simplify CDP programming
On 5/2/2023 8:05 AM, Dmitry Baryshkov wrote:
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 17 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 17 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 19 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 19 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 11 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 +++---
8 files changed, 45 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index bac4aa807b4b..e7b65f6f53d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -140,7 +140,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct
dpu_encoder_phys *phys_enc,
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
struct dpu_hw_wb *hw_wb;
struct dpu_hw_wb_cfg *wb_cfg;
- struct dpu_hw_cdp_cfg cdp_cfg;
if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
DPU_ERROR("invalid encoder\n");
@@ -163,18 +162,10 @@ static void dpu_encoder_phys_wb_setup_fb(struct
dpu_encoder_phys *phys_enc,
hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
if (hw_wb->ops.setup_cdp) {
- memset(_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
-
- cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf->cdp_cfg
- [DPU_PERF_CDP_USAGE_NRT].wr_enable;
- cdp_cfg.ubwc_meta_enable =
- DPU_FORMAT_IS_UBWC(wb_cfg->dest.format);
- cdp_cfg.tile_amortize_enable =
- DPU_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
- DPU_FORMAT_IS_TILE(wb_cfg->dest.format);
- cdp_cfg.preload_ahead = DPU_WB_CDP_PRELOAD_AHEAD_64;
-
- hw_wb->ops.setup_cdp(hw_wb, _cfg);
+ const struct dpu_perf_cfg *perf =
phys_enc->dpu_kms->catalog->perf;
+
+ hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format,
+
perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);
}
if (hw_wb->ops.setup_outaddress)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 1bf717290dab..731199030336 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -592,13 +592,13 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp
*ctx,
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
- struct dpu_hw_cdp_cfg *cfg)
+ const struct dpu_format *fmt,
+ bool enable)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- u32 cdp_cntl = 0;
u32 cdp_cntl_offset = 0;
- if (!ctx || !cfg)
+ if (!ctx)
return;
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
@@ -607,16 +607,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
else
cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
- if (cfg->enable)
- cdp_cntl |= BIT(0);
- if (cfg->ubwc_meta_enable)
- cdp_cntl |= BIT(1);
- if (cfg->tile_amortize_enable)
- cdp_cntl |= BIT(2);
- if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64)
- cdp_cntl |= BIT(3);
-
- DPU_REG_WRITE(>hw, cdp_cntl_offset, cdp_cntl);
+ dpu_setup_cdp(>hw, cdp_cntl_offset, fmt, enable);
}
static void _setup_layer_ops(struct dpu_hw_sspp *c,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 7a8d11ba618d..86bf4b2cda77 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -177,14 +177,6 @@ struct dpu_hw_pipe_qos_cfg {
bool danger_safe_en;
};
-/**
- * enum CDP preload ahead address size
- */
-enum {
- DPU_SSPP_CDP_PRELOAD_AHEAD_32,
- DPU_SSPP_CDP_PRELOAD_AHEAD_64
-};
-
/**
* struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
* @size: size to prefill in bytes, or zero to disable
@@ -331,10 +323,12 @@ struct dpu_hw_sspp_ops {
/**
* setup_cdp - setup client driven prefetch
* @pipe: Pointer to software pipe context
-* @cfg: Pointer to cdp configuration
+* @fmt: format used by the sw
[Freedreno] [PATCH v2 2/9] drm/msm/dpu: simplify CDP programming
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 17 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 17 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 19 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 19 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 11 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 +++---
8 files changed, 45 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index bac4aa807b4b..e7b65f6f53d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -140,7 +140,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct
dpu_encoder_phys *phys_enc,
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
struct dpu_hw_wb *hw_wb;
struct dpu_hw_wb_cfg *wb_cfg;
- struct dpu_hw_cdp_cfg cdp_cfg;
if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
DPU_ERROR("invalid encoder\n");
@@ -163,18 +162,10 @@ static void dpu_encoder_phys_wb_setup_fb(struct
dpu_encoder_phys *phys_enc,
hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
if (hw_wb->ops.setup_cdp) {
- memset(_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
-
- cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf->cdp_cfg
- [DPU_PERF_CDP_USAGE_NRT].wr_enable;
- cdp_cfg.ubwc_meta_enable =
- DPU_FORMAT_IS_UBWC(wb_cfg->dest.format);
- cdp_cfg.tile_amortize_enable =
- DPU_FORMAT_IS_UBWC(wb_cfg->dest.format) ||
- DPU_FORMAT_IS_TILE(wb_cfg->dest.format);
- cdp_cfg.preload_ahead = DPU_WB_CDP_PRELOAD_AHEAD_64;
-
- hw_wb->ops.setup_cdp(hw_wb, _cfg);
+ const struct dpu_perf_cfg *perf =
phys_enc->dpu_kms->catalog->perf;
+
+ hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format,
+
perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);
}
if (hw_wb->ops.setup_outaddress)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 1bf717290dab..731199030336 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -592,13 +592,13 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp
*ctx,
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
- struct dpu_hw_cdp_cfg *cfg)
+ const struct dpu_format *fmt,
+ bool enable)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
- u32 cdp_cntl = 0;
u32 cdp_cntl_offset = 0;
- if (!ctx || !cfg)
+ if (!ctx)
return;
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
@@ -607,16 +607,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
else
cdp_cntl_offset = SSPP_CDP_CNTL_REC1;
- if (cfg->enable)
- cdp_cntl |= BIT(0);
- if (cfg->ubwc_meta_enable)
- cdp_cntl |= BIT(1);
- if (cfg->tile_amortize_enable)
- cdp_cntl |= BIT(2);
- if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64)
- cdp_cntl |= BIT(3);
-
- DPU_REG_WRITE(>hw, cdp_cntl_offset, cdp_cntl);
+ dpu_setup_cdp(>hw, cdp_cntl_offset, fmt, enable);
}
static void _setup_layer_ops(struct dpu_hw_sspp *c,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 7a8d11ba618d..86bf4b2cda77 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -177,14 +177,6 @@ struct dpu_hw_pipe_qos_cfg {
bool danger_safe_en;
};
-/**
- * enum CDP preload ahead address size
- */
-enum {
- DPU_SSPP_CDP_PRELOAD_AHEAD_32,
- DPU_SSPP_CDP_PRELOAD_AHEAD_64
-};
-
/**
* struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
* @size: size to prefill in bytes, or zero to disable
@@ -331,10 +323,12 @@ struct dpu_hw_sspp_ops {
/**
* setup_cdp - setup client driven prefetch
* @pipe: Pointer to software pipe context
-* @cfg: Pointer to cdp configuration
+* @fmt: format used by the sw pipe
+* @enable: whether the CDP should be
