Re: [Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
On 05/12/2022 17:37, Robert Foss wrote: Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++- 1 file changed, 195 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 434f8e8b12c1..fb1c616c5e89 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include #include #include #include @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 { }; }; + mdss: mdss@ae0 { + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae0 0 0x1000>; + reg-names = "mdss"; + + interconnects = <_noc MASTER_MDP0 0 _virt SLAVE_EBI1 0>, + <_noc MASTER_MDP1 0 _virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = < MDSS_GDSC>; + resets = < DISP_CC_MDSS_CORE_BCR>; + + clocks = < DISP_CC_MDSS_AHB_CLK>, +< GCC_DISP_HF_AXI_CLK>, +< GCC_DISP_SF_AXI_CLK>, +< DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = < GCC_DISP_HF_AXI_CLK>, + < GCC_DISP_SF_AXI_CLK>, + < DISP_CC_MDSS_AHB_CLK>, + < DISP_CC_MDSS_MDP_LUT_CLK>, + < DISP_CC_MDSS_MDP_CLK>, + < DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <1920>; + + operating-points-v2 = <_opp_table>; + power-domains = < SM8350_MMCX>; + + interrupt-parent = <>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { With the 8280 patchset [1], it was decided that mdss nodes should now have a mdss_ prefix in their labels, to keep them near each other when referencing them in device DTSes. + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <>; + interrupts = <4>; + + clocks = < DISP_CC_MDSS_BYTE0_CLK>, +< DISP_CC_MDSS_BYTE0_INTF_CLK>, +< DISP_CC_MDSS_PCLK0_CLK>, +< DISP_CC_MDSS_ESC0_CLK>, +< DISP_CC_MDSS_AHB_CLK>, +< GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", +
Re: [Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
On 05/12/2022 17:37, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++- > 1 file changed, 195 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi > b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 434f8e8b12c1..fb1c616c5e89 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include > #include > #include > #include > @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 { > }; > }; > > + mdss: mdss@ae0 { Based on bindings: display-subsystem > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae0 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <_noc MASTER_MDP0 0 _virt > SLAVE_EBI1 0>, > + <_noc MASTER_MDP1 0 _virt > SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = < MDSS_GDSC>; > + resets = < DISP_CC_MDSS_CORE_BCR>; > + > + clocks = < DISP_CC_MDSS_AHB_CLK>, > + < GCC_DISP_HF_AXI_CLK>, > + < GCC_DISP_SF_AXI_CLK>, > + < DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <_smmu 0x820 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = < GCC_DISP_HF_AXI_CLK>, > + < GCC_DISP_SF_AXI_CLK>, > + < DISP_CC_MDSS_AHB_CLK>, > + < DISP_CC_MDSS_MDP_LUT_CLK>, > + < DISP_CC_MDSS_MDP_CLK>, > + < DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = < > DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <1920>; > + > + operating-points-v2 = <_opp_table>; > + power-domains = < SM8350_MMCX>; > + > + interrupt-parent = <>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = > <_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <>; > + interrupts = <4>; > + > + clocks = < DISP_CC_MDSS_BYTE0_CLK>, > + < DISP_CC_MDSS_BYTE0_INTF_CLK>, > + < DISP_CC_MDSS_PCLK0_CLK>, > + < DISP_CC_MDSS_ESC0_CLK>, > + < DISP_CC_MDSS_AHB_CLK>, > + < GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > +
Re: [Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
On 05/12/2022 18:37, Robert Foss wrote: Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++- 1 file changed, 195 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 434f8e8b12c1..fb1c616c5e89 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include #include #include #include @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 { }; }; + mdss: mdss@ae0 { display-sybsystem@ I also had this issue in sm8450.dtsi (and I'm going to fix it in the next revision). + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae0 0 0x1000>; + reg-names = "mdss"; + + interconnects = <_noc MASTER_MDP0 0 _virt SLAVE_EBI1 0>, + <_noc MASTER_MDP1 0 _virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = < MDSS_GDSC>; + resets = < DISP_CC_MDSS_CORE_BCR>; + + clocks = < DISP_CC_MDSS_AHB_CLK>, +< GCC_DISP_HF_AXI_CLK>, +< GCC_DISP_SF_AXI_CLK>, +< DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = < GCC_DISP_HF_AXI_CLK>, + < GCC_DISP_SF_AXI_CLK>, + < DISP_CC_MDSS_AHB_CLK>, + < DISP_CC_MDSS_MDP_LUT_CLK>, + < DISP_CC_MDSS_MDP_CLK>, + < DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <1920>; + + operating-points-v2 = <_opp_table>; + power-domains = < SM8350_MMCX>; + + interrupt-parent = <>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <>; + interrupts = <4>; + + clocks = < DISP_CC_MDSS_BYTE0_CLK>, +< DISP_CC_MDSS_BYTE0_INTF_CLK>, +< DISP_CC_MDSS_PCLK0_CLK>, +< DISP_CC_MDSS_ESC0_CLK>, +< DISP_CC_MDSS_AHB_CLK>, +< GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", +
[Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++- 1 file changed, 195 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 434f8e8b12c1..fb1c616c5e89 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include #include #include #include @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 { }; }; + mdss: mdss@ae0 { + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae0 0 0x1000>; + reg-names = "mdss"; + + interconnects = <_noc MASTER_MDP0 0 _virt SLAVE_EBI1 0>, + <_noc MASTER_MDP1 0 _virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = < MDSS_GDSC>; + resets = < DISP_CC_MDSS_CORE_BCR>; + + clocks = < DISP_CC_MDSS_AHB_CLK>, +< GCC_DISP_HF_AXI_CLK>, +< GCC_DISP_SF_AXI_CLK>, +< DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = < GCC_DISP_HF_AXI_CLK>, + < GCC_DISP_SF_AXI_CLK>, + < DISP_CC_MDSS_AHB_CLK>, + < DISP_CC_MDSS_MDP_LUT_CLK>, + < DISP_CC_MDSS_MDP_CLK>, + < DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <1920>; + + operating-points-v2 = <_opp_table>; + power-domains = < SM8350_MMCX>; + + interrupt-parent = <>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <>; + interrupts = <4>; + + clocks = < DISP_CC_MDSS_BYTE0_CLK>, +< DISP_CC_MDSS_BYTE0_INTF_CLK>, +< DISP_CC_MDSS_PCLK0_CLK>, +< DISP_CC_MDSS_ESC0_CLK>, +< DISP_CC_MDSS_AHB_CLK>, +< GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus";