Re: [Freedreno] [PATCH v3 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2022-11-30 Thread Bjorn Andersson 
On Fri, Nov 18, 2022 at 03:15:25PM -0800, Kuogee Hsieh wrote:
> 
> On 10/25/2022 8:26 PM, Bjorn Andersson wrote:
[..]
> > +   mdss0: display-subsystem@ae0 {
[..]
> > +
> just curious, where are mdss0_dp0 and mdss0_dp1?. Are two dp/usb combo phys
> not going used?

They are, but at the time of posting this, the QMP nodes was still being
reworked to support expressing the DP-part of things.

Now that the rework is in place I will include them as I respin this
series.

Regards,
Bjorn

Re: [Freedreno] [PATCH v3 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2022-11-18 Thread Kuogee Hsieh 



On 10/25/2022 8:26 PM, Bjorn Andersson wrote:

From: Bjorn Andersson 

Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.

Signed-off-by: Bjorn Andersson 
Signed-off-by: Bjorn Andersson 
---

Changes since v2:
- New patch on list

  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
  1 file changed, 838 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi 
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index ed806a6e20f6..8526ed74b7be 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4,6 +4,7 @@
   * Copyright (c) 2022, Linaro Limited
   */
  
+#include 

  #include 
  #include 
  #include 
@@ -1245,6 +1246,44 @@ usb_1_ssphy: usb3-phy@8903400 {
};
};
  
+		mdss1_dp0_phy: phy@8909a00 {

+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x08909a00 0 0x19c>,
+ <0 0x08909200 0 0xec>,
+ <0 0x08909600 0 0xec>,
+ <0 0x08909000 0 0x1c8>;
+
+   clocks = < DISP_CC_MDSS_DPTX0_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = < SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
+   mdss1_dp1_phy: phy@890ca00 {
+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x0890ca00 0 0x19c>,
+ <0 0x0890c200 0 0xec>,
+ <0 0x0890c600 0 0xec>,
+ <0 0x0890c000 0 0x1c8>;
+
+   clocks = < DISP_CC_MDSS_DPTX1_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = < SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
system-cache-controller@920 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x0920 0 0x58000>, <0 0x0960 0 
0x58000>;
@@ -1360,6 +1399,326 @@ usb_1_dwc3: usb@a80 {
};
};
  
+		mdss0: display-subsystem@ae0 {

+   compatible = "qcom,sc8280xp-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   power-domains = < MDSS_GDSC>;
+
+   clocks = < GCC_DISP_AHB_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface",
+ "ahb",
+ "core";
+
+   resets = < DISP_CC_MDSS_CORE_BCR>;
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interconnects = <_noc MASTER_MDP0 0 _virt 
SLAVE_EBI1 0>,
+   <_noc MASTER_MDP1 0 _virt 
SLAVE_EBI1 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   iommus = <_smmu 0x1000 0x402>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss0_mdp: display-controller@ae01000 {
+   compatible = "qcom,sc8280xp-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = < GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_LUT_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+   assigned-clocks = < 
DISP_CC_MDSS_MDP_CLK>,
+ < 
DISP_CC_MDSS_VSYNC_CLK>;
+

Re: [Freedreno] [PATCH v3 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2022-10-26 Thread Johan Hovold 
On Tue, Oct 25, 2022 at 08:26:22PM -0700, Bjorn Andersson wrote:
> From: Bjorn Andersson 
> 
> Define the display clock controllers, the MDSS instances, the DP phys
> and connect these together.
> 
> Signed-off-by: Bjorn Andersson 
> Signed-off-by: Bjorn Andersson 
> ---
> 
> Changes since v2:
> - New patch on list
> 
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
>  1 file changed, 838 insertions(+)

> + mdss0_mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-2 {
> + opp-hz = /bits/ 64 <2>;
> + required-opps = 
> <_opp_low_svs>;
> + };
> +
> + opp-3 {
> + opp-hz = /bits/ 64 <3>;
> + required-opps = 
> <_opp_svs>;
> + };
> +
> + opp-37500 {
> + opp-hz = /bits/ 64 <37500>;
> + required-opps = 
> <_opp_svs_l1>;
> + };
> +
> + opp-5 {
> + opp-hz = /bits/ 64 <5>;
> + required-opps = 
> <_opp_nom>;
> + };
> + opp-6 {

Super nit: missing newline between entries (I only noticed when rebasing
the external DP support on top).

> + opp-hz = /bits/ 64 <6>;
> + required-opps = 
> <_opp_turbo_l1>;
> + };
> + };
> + };

> + mdss1_mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-2 {
> + opp-hz = /bits/ 64 <2>;
> + required-opps = 
> <_opp_low_svs>;
> + };
> +
> + opp-3 {
> + opp-hz = /bits/ 64 <3>;
> + required-opps = 
> <_opp_svs>;
> + };
> +
> + opp-37500 {
> + opp-hz = /bits/ 64 <37500>;
> + required-opps = 
> <_opp_svs_l1>;
> + };
> +
> + opp-5 {
> + opp-hz = /bits/ 64 <5>;
> + required-opps = 
> <_opp_nom>;
> + };
> + opp-6 {
> + opp-hz = /bits/ 64 <6>;
> + required-opps = 
> <_opp_turbo_l1>;
> + };

Ditto.

> + };
> + };

Johan

[Freedreno] [PATCH v3 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2022-10-25 Thread Bjorn Andersson 
From: Bjorn Andersson 

Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.

Signed-off-by: Bjorn Andersson 
Signed-off-by: Bjorn Andersson 
---

Changes since v2:
- New patch on list

 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
 1 file changed, 838 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi 
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index ed806a6e20f6..8526ed74b7be 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4,6 +4,7 @@
  * Copyright (c) 2022, Linaro Limited
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -1245,6 +1246,44 @@ usb_1_ssphy: usb3-phy@8903400 {
};
};
 
+   mdss1_dp0_phy: phy@8909a00 {
+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x08909a00 0 0x19c>,
+ <0 0x08909200 0 0xec>,
+ <0 0x08909600 0 0xec>,
+ <0 0x08909000 0 0x1c8>;
+
+   clocks = < DISP_CC_MDSS_DPTX0_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = < SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
+   mdss1_dp1_phy: phy@890ca00 {
+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x0890ca00 0 0x19c>,
+ <0 0x0890c200 0 0xec>,
+ <0 0x0890c600 0 0xec>,
+ <0 0x0890c000 0 0x1c8>;
+
+   clocks = < DISP_CC_MDSS_DPTX1_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = < SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
system-cache-controller@920 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x0920 0 0x58000>, <0 0x0960 0 
0x58000>;
@@ -1360,6 +1399,326 @@ usb_1_dwc3: usb@a80 {
};
};
 
+   mdss0: display-subsystem@ae0 {
+   compatible = "qcom,sc8280xp-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   power-domains = < MDSS_GDSC>;
+
+   clocks = < GCC_DISP_AHB_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface",
+ "ahb",
+ "core";
+
+   resets = < DISP_CC_MDSS_CORE_BCR>;
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interconnects = <_noc MASTER_MDP0 0 _virt 
SLAVE_EBI1 0>,
+   <_noc MASTER_MDP1 0 _virt 
SLAVE_EBI1 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   iommus = <_smmu 0x1000 0x402>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss0_mdp: display-controller@ae01000 {
+   compatible = "qcom,sc8280xp-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = < GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_LUT_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+   assigned-clocks = < 
DISP_CC_MDSS_MDP_CLK>,
+ < 
DISP_CC_MDSS_VSYNC_CLK>;
+   assigned-clock-rates = <46000>,
+