Re: [Freedreno] [RFC] drm/msm/disp/dpu1: add support for inline rotation in dpu driver
On 03/07/2021 14:32, Kalyan Thota wrote:
Add inline rotation support in dpu driver. This change adds
rotation config for SC7280 target.
Change-Id: I15861dc03422274ffd823fc0fc2c1e47909bb22c
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 93 --
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
4 files changed, 128 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..45e4e56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -25,6 +25,9 @@
#define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+#define VIG_SC7280_MASK \
+ (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+
#define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -102,6 +105,8 @@
#define MAX_DOWNSCALE_RATIO 4
#define SSPP_UNITY_SCALE 1
+#define INLINE_ROTATOR_V2 2
+
#define STRCAT(X, Y) (X Y)
static const uint32_t plane_formats[] = {
@@ -177,6 +182,11 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_YVU420,
};
+static const uint32_t rotation_formats[] = {
+ DRM_FORMAT_NV12,
+ /* TODO add formats after validation */
+};
+
/*
* DPU sub blocks config
*/
@@ -465,7 +475,16 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
/* SSPP common configuration */
-#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
+static const struct dpu_rotation_cfg dpu_rot_cfg = {
+ .version = INLINE_ROTATOR_V2,
+ .rot_maxdwnscale_ratio_num = 1,
+ .rot_maxdwnscale_ratio_dem = 1,
+ .rot_maxheight = 1088,
+ .rot_num_formats = ARRAY_SIZE(rotation_formats),
+ .rot_format_list = rotation_formats,
+};
+
+#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
@@ -482,6 +501,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
+ .rotation_cfg = rot_cfg, \
}
#define _DMA_SBLK(num, sdma_pri) \
@@ -498,13 +518,13 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
}
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
- _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
- _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
- _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
@@ -543,7 +563,10 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
};
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
- _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, 0);
+
+static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4,
&dpu_rot_cfg);
static const struct dpu_sspp_cfg sc7180_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
@@ -557,13 +580,13 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
};
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE,
0);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
- _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE,
0);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
- _VIG_SBLK("2",
Re: [Freedreno] [RFC] drm/msm/disp/dpu1: add support for inline rotation in dpu driver
Hi,
Something is wrong with the threading, since this patch does not contain
In-Reply-To header pointing to the cover letter? Could you please
correct that? Using git-send-email --compose would allow you to write
properly threaded cover letter.
On 03/07/2021 14:32, Kalyan Thota wrote:
Add inline rotation support in dpu driver. This change adds
rotation config for SC7280 target.
After spending some time reading display techpack, I think I'll ask you
to add some summary to the patch summary, describing some bits and
pieces. For example:
- Some DPU versions support inline rot90. It is supported only for
limited amount of UBWC formats.
- There are two versions of inline rotators, v1 (present on sm8250 and
sm7250) and v2 (sc7280). These versions differ in the list of supported
formats and in the scaler possibilities.
- rot90 options are common to the rotation block version and do not
depend on the SoC.
Change-Id: I15861dc03422274ffd823fc0fc2c1e47909bb22c
Please remove this
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 93 --
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
4 files changed, 128 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..45e4e56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -25,6 +25,9 @@
#define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+#define VIG_SC7280_MASK \
+ (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+
#define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -102,6 +105,8 @@
#define MAX_DOWNSCALE_RATIO 4
#define SSPP_UNITY_SCALE 1
+#define INLINE_ROTATOR_V2 2
+
#define STRCAT(X, Y) (X Y)
static const uint32_t plane_formats[] = {
@@ -177,6 +182,11 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_YVU420,
};
+static const uint32_t rotation_formats[] = {
rotation_v2_formats?
+ DRM_FORMAT_NV12,
+ /* TODO add formats after validation */
+};
+
/*
* DPU sub blocks config
*/
@@ -465,7 +475,16 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
/* SSPP common configuration */
-#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
+static const struct dpu_rotation_cfg dpu_rot_cfg = {
dpu_rot_cfg is a bit too broad. dpu_rot_cfg_v2 seem to be more appropriate.
+ .version = INLINE_ROTATOR_V2,
There are no check on the version, so you can drop this field.
+ .rot_maxdwnscale_ratio_num = 1,
+ .rot_maxdwnscale_ratio_dem = 1,
These don't seem to be used in your patch. Was the intent to avoid all
the pre-downscale and downscale options? If so I'd suggest just
enforcing the scale factor to 1 for now in the rot90 checking code.
From reading the code I had the impression that for v2 downscaling up
to 4:1 should be supported, so there is no need for special handling
(VIG_SBLK already declared downscaling up to 4:1). V1 is different and
will need limiting to 11:5. Is my understanding correct?
+ .rot_maxheight = 1088,
+ .rot_num_formats = ARRAY_SIZE(rotation_formats),
+ .rot_format_list = rotation_formats,
+};
+
+#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
@@ -482,6 +501,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
+ .rotation_cfg = rot_cfg, \
At some point I thought about moving rot_cfg contents directly into the
sblk config, but now I don't have a strong opinion on that. Let's keep
it in the current way for now.
}
#define _DMA_SBLK(num, sdma_pri) \
@@ -498,13 +518,13 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
}
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3, 0);
NULL, not 0.
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
- _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
- _VIG_SBLK("2", 7, DPU_SS
[Freedreno] [RFC] drm/msm/disp/dpu1: add support for inline rotation in dpu driver
Add inline rotation support in dpu driver. This change adds
rotation config for SC7280 target.
Change-Id: I15861dc03422274ffd823fc0fc2c1e47909bb22c
Signed-off-by: Kalyan Thota
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 93 --
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 +
4 files changed, 128 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..45e4e56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -25,6 +25,9 @@
#define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+#define VIG_SC7280_MASK \
+ (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+
#define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -102,6 +105,8 @@
#define MAX_DOWNSCALE_RATIO4
#define SSPP_UNITY_SCALE 1
+#define INLINE_ROTATOR_V2 2
+
#define STRCAT(X, Y) (X Y)
static const uint32_t plane_formats[] = {
@@ -177,6 +182,11 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_YVU420,
};
+static const uint32_t rotation_formats[] = {
+ DRM_FORMAT_NV12,
+ /* TODO add formats after validation */
+};
+
/*
* DPU sub blocks config
*/
@@ -465,7 +475,16 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
/* SSPP common configuration */
-#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
+static const struct dpu_rotation_cfg dpu_rot_cfg = {
+ .version = INLINE_ROTATOR_V2,
+ .rot_maxdwnscale_ratio_num = 1,
+ .rot_maxdwnscale_ratio_dem = 1,
+ .rot_maxheight = 1088,
+ .rot_num_formats = ARRAY_SIZE(rotation_formats),
+ .rot_format_list = rotation_formats,
+};
+
+#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
@@ -482,6 +501,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
+ .rotation_cfg = rot_cfg, \
}
#define _DMA_SBLK(num, sdma_pri) \
@@ -498,13 +518,13 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
}
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
- _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
- _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
- _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3, 0);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
@@ -543,7 +563,10 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
};
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
- _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, 0);
+
+static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
+ _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4,
&dpu_rot_cfg);
static const struct dpu_sspp_cfg sc7180_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
@@ -557,13 +580,13 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
};
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
- _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE,
0);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
- _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE,
0);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
- _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
+ _VIG_SBLK("2", 7, DPU_SS
