Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On 29/05/2023 12:08, Konrad Dybcio wrote: On 29.05.2023 10:47, Dmitry Baryshkov wrote: On 29/05/2023 10:42, Konrad Dybcio wrote: On 29.05.2023 04:42, Dmitry Baryshkov wrote: On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote: Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. This series tries to address the lack of that. Example path: interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; If we are going to touch the MDSS interconnects, could you please also add the rotator interconnect to the bindings? We do not need to touch it at this time, but let's not have to change bindings later again. Ack Also, several points noted from the mdss fbdev driver: - All possible clents vote for the low bw setting. This includes DSI, HDMI, MDSS itself and INTF As in, "you need NUM_CLIENTS * MIN_VOTE" or as in "any client necessitates a vote"? Each client has separate vote - SMMU also casts such vote, which I do not think should be necessary, unless there is a separate MDSS SMMU? There's one on 8996, pre-845 SoCs often have a MMSS MMU, 845 and later have a MMSS-specific TBU which (theoretically) requires a vote for access to 0x400-0x7ff SIDs Ack. - PINGPONG cacsts high bw setting for the sake of speeding up the LUT tables if required. Hm, I think is would be a separate topic. I think so. I'd do a single vote from mdp5/dpu1. Then we can cast higher vote from PP/DSPP/etc. -- With best wishes Dmitry
Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On 29.05.2023 10:47, Dmitry Baryshkov wrote: > On 29/05/2023 10:42, Konrad Dybcio wrote: >> >> >> On 29.05.2023 04:42, Dmitry Baryshkov wrote: >>> On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio >>> wrote: Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. This series tries to address the lack of that. Example path: interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; >>> >>> If we are going to touch the MDSS interconnects, could you please also >>> add the rotator interconnect to the bindings? >>> We do not need to touch it at this time, but let's not have to change >>> bindings later again. >>> >> Ack > > Also, several points noted from the mdss fbdev driver: > > - All possible clents vote for the low bw setting. This includes DSI, HDMI, > MDSS itself and INTF As in, "you need NUM_CLIENTS * MIN_VOTE" or as in "any client necessitates a vote"? > - SMMU also casts such vote, which I do not think should be necessary, unless > there is a separate MDSS SMMU? There's one on 8996, pre-845 SoCs often have a MMSS MMU, 845 and later have a MMSS-specific TBU which (theoretically) requires a vote for access to 0x400-0x7ff SIDs > - PINGPONG cacsts high bw setting for the sake of speeding up the LUT tables > if required. Hm, I think is would be a separate topic. Konrad >
Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On 29/05/2023 10:42, Konrad Dybcio wrote: On 29.05.2023 04:42, Dmitry Baryshkov wrote: On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote: Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. This series tries to address the lack of that. Example path: interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; If we are going to touch the MDSS interconnects, could you please also add the rotator interconnect to the bindings? We do not need to touch it at this time, but let's not have to change bindings later again. Ack Also, several points noted from the mdss fbdev driver: - All possible clents vote for the low bw setting. This includes DSI, HDMI, MDSS itself and INTF - SMMU also casts such vote, which I do not think should be necessary, unless there is a separate MDSS SMMU? - PINGPONG cacsts high bw setting for the sake of speeding up the LUT tables if required. -- With best wishes Dmitry
Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On 29.05.2023 04:42, Dmitry Baryshkov wrote: > On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote: >> >> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's >> another path that needs to be handled to ensure MDSS functions properly, >> namely the "reg bus", a.k.a the CPU-MDSS interconnect. >> >> Gating that path may have a variety of effects.. from none to otherwise >> inexplicable DSI timeouts.. >> >> This series tries to address the lack of that. >> >> Example path: >> >> interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; > > If we are going to touch the MDSS interconnects, could you please also > add the rotator interconnect to the bindings? > We do not need to touch it at this time, but let's not have to change > bindings later again. > Ack Konrad >> >> Signed-off-by: Konrad Dybcio >> --- >> Konrad Dybcio (5): >> dt-bindings: display/msm: Add reg bus interconnect >> drm/msm/dpu1: Rename path references to mdp_path >> drm/msm/mdss: Rename path references to mdp_path >> drm/msm/mdss: Handle the reg bus ICC path >> drm/msm/dpu1: Handle the reg bus ICC path >> >> .../bindings/display/msm/mdss-common.yaml | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 34 >> - >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 5 ++-- >> drivers/gpu/drm/msm/msm_mdss.c | 35 >> ++ >> 5 files changed, 57 insertions(+), 28 deletions(-) >> --- >> base-commit: d3f2cd24819158bb70701c3549e586f9df9cee67 >> change-id: 20230417-topic-dpu_regbus-abc94a770952 >> >> Best regards, >> -- >> Konrad Dybcio >> > >
Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On Wed, 19 Apr 2023 at 21:50, Jeykumar Sankaran wrote: > > > > On 4/17/2023 8:30 AM, Konrad Dybcio wrote: > > Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's > > another path that needs to be handled to ensure MDSS functions properly, > > namely the "reg bus", a.k.a the CPU-MDSS interconnect. > > > > Gating that path may have a variety of effects.. from none to otherwise > > inexplicable DSI timeouts.. > > > Current DPU driver already votes on the "reg bus" indirectly through the > display AHB clock handle[< DISP_CC_MDSS_AHB_CLK>] in DTSI. Can > you provide more details on the issues that warrants this patch series? Does that mean that if we cast a proper vote on the SLAVE_DISPLAY_CFG, we can drop the DISP_CC_MDSS_AHB_CLK clock? Also, I'd like to point out that SDE does both things: it casts the <1 590 xxx yyy> bus votes and enables the DISP_CC_MDSS_AHB_CLK clock. > > > This series tries to address the lack of that. > > > > Example path: > > > > interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; > > > > Signed-off-by: Konrad Dybcio > > --- > > Konrad Dybcio (5): > >dt-bindings: display/msm: Add reg bus interconnect > >drm/msm/dpu1: Rename path references to mdp_path > >drm/msm/mdss: Rename path references to mdp_path > >drm/msm/mdss: Handle the reg bus ICC path > >drm/msm/dpu1: Handle the reg bus ICC path > > > > .../bindings/display/msm/mdss-common.yaml | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 34 > > - > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 5 ++-- > > drivers/gpu/drm/msm/msm_mdss.c | 35 > > ++ > > 5 files changed, 57 insertions(+), 28 deletions(-) > > --- > > base-commit: d3f2cd24819158bb70701c3549e586f9df9cee67 > > change-id: 20230417-topic-dpu_regbus-abc94a770952 > > > > Best regards, -- With best wishes Dmitry
Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio wrote: > > Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's > another path that needs to be handled to ensure MDSS functions properly, > namely the "reg bus", a.k.a the CPU-MDSS interconnect. > > Gating that path may have a variety of effects.. from none to otherwise > inexplicable DSI timeouts.. > > This series tries to address the lack of that. > > Example path: > > interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; If we are going to touch the MDSS interconnects, could you please also add the rotator interconnect to the bindings? We do not need to touch it at this time, but let's not have to change bindings later again. > > Signed-off-by: Konrad Dybcio > --- > Konrad Dybcio (5): > dt-bindings: display/msm: Add reg bus interconnect > drm/msm/dpu1: Rename path references to mdp_path > drm/msm/mdss: Rename path references to mdp_path > drm/msm/mdss: Handle the reg bus ICC path > drm/msm/dpu1: Handle the reg bus ICC path > > .../bindings/display/msm/mdss-common.yaml | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++ > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 34 - > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 5 ++-- > drivers/gpu/drm/msm/msm_mdss.c | 35 > ++ > 5 files changed, 57 insertions(+), 28 deletions(-) > --- > base-commit: d3f2cd24819158bb70701c3549e586f9df9cee67 > change-id: 20230417-topic-dpu_regbus-abc94a770952 > > Best regards, > -- > Konrad Dybcio > -- With best wishes Dmitry
Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On 4/17/2023 8:30 AM, Konrad Dybcio wrote: Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. Current DPU driver already votes on the "reg bus" indirectly through the display AHB clock handle[< DISP_CC_MDSS_AHB_CLK>] in DTSI. Can you provide more details on the issues that warrants this patch series? Thanks Jeykumar S This series tries to address the lack of that. Example path: interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; Signed-off-by: Konrad Dybcio --- Konrad Dybcio (5): dt-bindings: display/msm: Add reg bus interconnect drm/msm/dpu1: Rename path references to mdp_path drm/msm/mdss: Rename path references to mdp_path drm/msm/mdss: Handle the reg bus ICC path drm/msm/dpu1: Handle the reg bus ICC path .../bindings/display/msm/mdss-common.yaml | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 34 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 5 ++-- drivers/gpu/drm/msm/msm_mdss.c | 35 ++ 5 files changed, 57 insertions(+), 28 deletions(-) --- base-commit: d3f2cd24819158bb70701c3549e586f9df9cee67 change-id: 20230417-topic-dpu_regbus-abc94a770952 Best regards,
Re: [Freedreno] [PATCH 0/5] MDSS reg bus interconnect
On 4/17/2023 8:30 AM, Konrad Dybcio wrote: Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts.. Current DPU driver already votes on the "reg bus" indirectly through the display AHB clock handle[< DISP_CC_MDSS_AHB_CLK>] in DTSI. Can you provide more details on the issues that warrants this patch series? This series tries to address the lack of that. Example path: interconnects = < MASTER_AMPSS_M0 0 _noc SLAVE_DISPLAY_CFG 0>; Signed-off-by: Konrad Dybcio --- Konrad Dybcio (5): dt-bindings: display/msm: Add reg bus interconnect drm/msm/dpu1: Rename path references to mdp_path drm/msm/mdss: Rename path references to mdp_path drm/msm/mdss: Handle the reg bus ICC path drm/msm/dpu1: Handle the reg bus ICC path .../bindings/display/msm/mdss-common.yaml | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 34 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 5 ++-- drivers/gpu/drm/msm/msm_mdss.c | 35 ++ 5 files changed, 57 insertions(+), 28 deletions(-) --- base-commit: d3f2cd24819158bb70701c3549e586f9df9cee67 change-id: 20230417-topic-dpu_regbus-abc94a770952 Best regards,
