Re: [Freedreno] [PATCH 1/5] dt-bindings: display/msm: Add reg bus interconnect

2023-04-19 Thread Dmitry Baryshkov

On 19/04/2023 23:05, Jeykumar Sankaran wrote:
Resending the question as the previous one was sent only to the 
freedreno list. Apologies for spamming!


On 4/17/2023 8:30 AM, Konrad Dybcio wrote:

Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.

Gating that path may have a variety of effects.. from none to otherwise
inexplicable DSI timeouts..

Describe it in bindings to allow for use in device trees.

Signed-off-by: Konrad Dybcio 
---
  Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 +
  1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml 
b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml

index ccd7d6417523..9eb5b6d3e0b9 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
@@ -72,6 +72,7 @@ properties:
  items:
    - const: mdp0-mem
    - const: mdp1-mem
+  - const: cpu-cfg

If posted already, please point to the DTSI patch for this ICC path.


Probably it's worth updating the example in one of mdss schemas.


    resets:
  items:



--
With best wishes
Dmitry



Re: [Freedreno] [PATCH 1/5] dt-bindings: display/msm: Add reg bus interconnect

2023-04-19 Thread Jeykumar Sankaran
Resending the question as the previous one was sent only to the 
freedreno list. Apologies for spamming!


On 4/17/2023 8:30 AM, Konrad Dybcio wrote:

Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.

Gating that path may have a variety of effects.. from none to otherwise
inexplicable DSI timeouts..

Describe it in bindings to allow for use in device trees.

Signed-off-by: Konrad Dybcio 
---
  Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 +
  1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml 
b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
index ccd7d6417523..9eb5b6d3e0b9 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
@@ -72,6 +72,7 @@ properties:
  items:
- const: mdp0-mem
- const: mdp1-mem
+  - const: cpu-cfg
  

If posted already, please point to the DTSI patch for this ICC path.

resets:
  items:



Re: [Freedreno] [PATCH 1/5] dt-bindings: display/msm: Add reg bus interconnect

2023-04-19 Thread Jeykumar Sankaran




On 4/17/2023 8:30 AM, Konrad Dybcio wrote:

Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.

Gating that path may have a variety of effects.. from none to otherwise
inexplicable DSI timeouts..

Describe it in bindings to allow for use in device trees.

Signed-off-by: Konrad Dybcio 
---
  Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 +
  1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml 
b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
index ccd7d6417523..9eb5b6d3e0b9 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
@@ -72,6 +72,7 @@ properties:
  items:
- const: mdp0-mem
- const: mdp1-mem
+  - const: cpu-cfg
  

If posted already, please point to the DTSI patch for this ICC path.

resets:
  items:



Re: [Freedreno] [PATCH 1/5] dt-bindings: display/msm: Add reg bus interconnect

2023-04-18 Thread Krzysztof Kozlowski
On 17/04/2023 17:30, Konrad Dybcio wrote:
> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
> another path that needs to be handled to ensure MDSS functions properly,
> namely the "reg bus", a.k.a the CPU-MDSS interconnect.
> 
> Gating that path may have a variety of effects.. from none to otherwise
> inexplicable DSI timeouts..
> 
> Describe it in bindings to allow for use in device trees.
> 
> Signed-off-by: Konrad Dybcio 
> ---
>  Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml 
> b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> index ccd7d6417523..9eb5b6d3e0b9 100644
> --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> @@ -72,6 +72,7 @@ properties:
>  items:
>- const: mdp0-mem
>- const: mdp1-mem
> +  - const: cpu-cfg

You added only interconnect-name, not actual interconnect.

Best regards,
Krzysztof