Re: [Freetel-codec2] STM32 freeDV cost benchmarks

2023-11-20 Thread glen english LIST 

Hi Mooneer

thanks for the comments. The FDIV on the ESP32-S3 is very slow I think 
80 cycles, but of course one should always use RECIPS  and a MUL. 
Integer div is a couple of cycles IIRC.


I'll start and see what jams it all up .

regards,

On 21/11/2023 4:01 pm, Mooneer Salem wrote:

Hi Glen,

I seem to remember that there was a previous project that implemented 
it on a FPGA, but I can't recall specifics at the moment. FWIW, on 
ezDV (ESP32-S3 but should perform similarly to the STM32F4 on the 
SM1000), 700D TX took something like ~90ms per 160ms frame while RX 
using real-only (vs. complex numbers) was something like 40ms per 
160ms frame. Unfortunately, I never did do a detailed accounting of 
what parts of encode and decode took the most time on the ESP32.


Thanks,



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Re: [Freetel-codec2] STM32 freeDV cost benchmarks

2023-11-20 Thread Mooneer Salem 
Hi Glen,

I seem to remember that there was a previous project that implemented it on
a FPGA, but I can't recall specifics at the moment. FWIW, on ezDV (ESP32-S3
but should perform similarly to the STM32F4 on the SM1000), 700D TX took
something like ~90ms per 160ms frame while RX using real-only (vs. complex
numbers) was something like 40ms per 160ms frame. Unfortunately, I never
did do a detailed accounting of what parts of encode and decode took the
most time on the ESP32.

Thanks,

-Mooneer K6AQ

On Mon, Nov 20, 2023 at 8:49 PM glen english LIST 
wrote:

> Hi Mooneer
>
> I am preparing to implement FreeDV on an FPGA.
>
> Is there a location in the repo somewhere, or does anyone have ,
> anecdotally a feeling of, the major workloads / major consumers of
> processor time on the STM32 FreeDV port.
>
> regards
>
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