Re: [PATCH v3, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

[Carl E. Love]

GCC Maintainers:

I have updated the define_expands for float2_v2di, uns_float2_v2di,
unsfloatev2di, floato, unsfloatov2di per the comments from Michael
Meissner.  

I retested the changes on powerpc64le-unknown-linux-gnu (Power 8 LE)
only. 

Please let me know if there are any additional issues that need fixing.
Thanks.

Carl Love


gcc/ChangeLog:

2017-06-12  Carl Love  

* config/rs6000/rs6000-c.c: Add definitions for the vec_float,
vec_float2, vec_floato, vec_floate built-ins.
* config/rs6000/vsx.md: Add RTL code for instructions vsx_xvcvsxws
vsx_xvcvuxwsp, float2, floato and floate.
* config/rs6000/rs6000-builtin.def: Add definitions for vsx_xvcvsxwsp,
vsx_xvcvuxwsp, float2, floato and floate.
* config/altivec.md: Add version of p8_vmrgew that takes V4SF args and
returns V4SF.
* config/rs6000/altivec.h: Add builtin defines for vec_float,
vec_float2, vec_floate and vec_floato.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.

gcc/testsuite/ChangeLog:

2017-06-12  Carl Love  

* gcc.target/powerpc/builtins-3-runnable.c: Add runnable tests for
vec_float, vec_float2, vec_floate and vec_floato builtins
built-ins.

Signed-off-by: Carl Love 
---
 gcc/config/rs6000/altivec.h|   4 +
 gcc/config/rs6000/altivec.md   |  14 +-
 gcc/config/rs6000/rs6000-builtin.def   |  19 ++-
 gcc/config/rs6000/rs6000-c.c   |  28 +++-
 gcc/config/rs6000/rs6000-protos.h  |   1 +
 gcc/config/rs6000/rs6000.c |  45 +-
 gcc/config/rs6000/vsx.md   | 166 +
 gcc/doc/extend.texi|  14 ++
 .../gcc.target/powerpc/builtins-3-runnable.c   |  82 ++
 9 files changed, 361 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 20050eb..d542315 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -133,6 +133,10 @@
 #define vec_doublel __builtin_vec_doublel
 #define vec_doubleh __builtin_vec_doubleh
 #define vec_expte __builtin_vec_expte
+#define vec_float __builtin_vec_float
+#define vec_float2 __builtin_vec_float2
+#define vec_floate __builtin_vec_floate
+#define vec_floato __builtin_vec_floato
 #define vec_floor __builtin_vec_floor
 #define vec_loge __builtin_vec_loge
 #define vec_madd __builtin_vec_madd
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 487b9a4..25b2768 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1316,13 +1316,13 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; Power8 vector merge even/odd
-(define_insn "p8_vmrgew"
-  [(set (match_operand:V4SI 0 "register_operand" "=v")
-   (vec_select:V4SI
- (vec_concat:V8SI
-   (match_operand:V4SI 1 "register_operand" "v")
-   (match_operand:V4SI 2 "register_operand" "v"))
+;; Power8 vector merge two V4SF/V4SI even words to V4SF
+(define_insn "p8_vmrgew_"
+  [(set (match_operand:VSX_W 0 "register_operand" "=v")
+   (vec_select:VSX_W
+ (vec_concat:
+   (match_operand:VSX_W 1 "register_operand" "v")
+   (match_operand:VSX_W 2 "register_operand" "v"))
  (parallel [(const_int 0) (const_int 4)
 (const_int 2) (const_int 6)])))]
   "TARGET_P8_VECTOR"
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 241c439..4682628 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1591,6 +1591,8 @@ BU_VSX_2 (CMPLE_U16QI,"cmple_u16qi",CONST,  
vector_ngtuv16qi)
 BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST,  vector_ngtuv8hi)
 BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST,  vector_ngtuv4si)
 BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST,  vector_ngtuv2di)
+BU_VSX_2 (FLOAT2_V2DI,"float2_v2di",CONST,  float2_v2di)
+BU_VSX_2 (UNS_FLOAT2_V2DI,"uns_float2_v2di",CONST,  uns_float2_v2di)
 
 /* VSX abs builtin functions.  */
 BU_VSX_A (XVABSDP,   "xvabsdp",CONST,  absv2df2)
@@ -1648,6 +1650,16 @@ BU_VSX_1 (XVCVSPSXDS,  "xvcvspsxds", CONST,  
vsx_xvcvspsxds)
 BU_VSX_1 (XVCVSPUXDS,"xvcvspuxds", CONST,  vsx_xvcvspuxds)
 BU_VSX_1 (XVCVSXDSP, "xvcvsxdsp",  CONST,  vsx_xvcvsxdsp)
 BU_VSX_1 (XVCVUXDSP, "xvcvuxdsp",  CONST,  vsx_xvcvuxdsp)
+
+BU_VSX_1 (XVCVSXWSP_V4SF,  "vsx_xvcvsxwsp",   CONST,   vsx_xvcvsxwsp)
+BU_VSX_1 (XVCVUXWSP_V4SF,  "vsx_xvcvuxwsp",   CONST,   vsx_xvcvuxwsp)
+BU_VSX_1 (FLOATE_V2DI, "floate_v2di", CONST,   floatev2di)
+BU_VSX_1 (FLOATE_V2DF, "floate_v2df", CONST,   

Re: [PATCH v2, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

[Carl E. Love]

On Mon, 2017-06-12 at 14:09 -0400, Michael Meissner wrote:

> > 
> > > > +(define_insn "vsx_xvcvsxwsp"
> > > > +  [(set (match_operand:V4SF 0 "vsx_register_operand" "=v")
> > > > +   (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "v")]
> > > > +   UNSPEC_VSX_CVSXWSP))]
> > > > +  "VECTOR_UNIT_VSX_P (V4SFmode)"
> > > > +  "xvcvsxwsp %x0,%x1"
> > > > +  [(set_attr "type" "vecdouble")])
> > > 
> > > "v" is only the VRs...  Do you want "wa" or similar instead?
> > > 
> > 
> > I went back and re-studied the Power register constrains.  I find them a
> > bit confusing, I am sure they are perfectly clear to everyone else.  So
> > the instructions all take VSX registers so "wa" should be fine if I
> > understand it correctly.  Not sure there is any need to further
> > constrain with "vs" for doubles or "ww" but I think you could.
> 
> Well in the power7 days, it wasn't clear whether we wanted to reduce the
> register set, so I added the general "wa", and then added the more specific
> changes ("ws", "wf", "wd").  In hindsight it probably wasn't a good idea.  But
> the trouble is we can't delete the old constraints, or we would break user asm
> code.
> 
> Over time, I have been deleting things where you have the specific constraint
> and the general one where I'm modifying code:
> 
>   (match_operand:V2DF 0 "=wd,?wa")
> 
> to
> 
>   (match_operand:V2DF 0 "=wa")
> 
> Now the second round of constraints are needed because of the
> -mupper-regs- debug switches.  You might/might not allow DFmode into the
> Altivec registers, and so you need several constraints:
> 
>   d   Just the traditional FPRs
>   ws  Any FPR/Altivec register DFmode can go in for ISA 2.06 insns
>   wk  Like ws, but only if 64-bit direct moves are supported
>   wv  Only altivec registers (used for 64-bit load/stores)
> 
> Note, you have to be careful not to allow a register constraint that the
> current type cannot go into.  This is due to a 'feature' in the LRA register
> allocator that it will trap if such a case occurs.  For example, for ISA 2.06,
> we do not have 32-bit floating point instructions in the Altivec registers.
> This means you can't use "v" (just the Altivec registers) on any code where
> -mcpu=power7 (or -mno-upper-regs-sf) is allowed.
> 

Michael:

OK, so sounds like I should stick to the general wa register constraint.
The third field of the define_expand I have what I believe is called the
"condition string" as "TARGET_VSX".  Is that the appropriate condition
string?  I see conditions string "VECTOR_UNIT_VSX_P (V4SFmode)" also
used.  Segher is thinking that this string would have the same effect as
"TARGET_VSX"??  How does one select the correct condition string based
on the register constraint?


Here is what I currently have for my define_expand. Is it correct?

;; Generate
float2  
;; convert two long long signed ints to float   
(define_expand "float2_v2di"
  [(match_operand:V4SF 0 "register_operand" "=wa")  
   (unspec:V4SI [(match_operand:V2DI 1 "register_operand" "wa") 
 (match_operand:V2DI 2 "register_operand" "wa")]
  UNSPEC_VSX_FLOAT2)]   

  "TARGET_VSX"  
{   
  rtx rtx_src1, rtx_src2, rtx_dst;  

  rtx_dst = operands[0];
  rtx_src1 = operands[1];   
  rtx_src2 = operands[2];   

  rs6000_generate_float2_code (true, rtx_dst, rtx_src1, rtx_src2);  
  DONE; 
})

Thanks for your help on this.

Re: [PATCH v2, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

[Carl E. Love]

GCC Maintainers:

On Fri, 2017-06-09 at 16:05 -0500, Segher Boessenkool wrote:

Fixed the various formatting (spaces) issues.  Been toying with how to
write a space checker for patches.  Have to take some time to really
think about how to do that

> > +
> > +  /* The vector merge instruction vmrgew swaps the 2nd and 3rd words,
> > + compensate by swapping the 64-bit elements around to negate the vmrgew
> > + swap. */
> 
> This comment isn't very clear to me...  Could you expand it a bit?

Reworked it, hopefully it explains things better

> > +;; Mode iterator and attribute for vector floate and floato conversions
> > +(define_mode_iterator VFC [V2DI V2DF])
> > +(define_mode_attr VFC_inst [(V2DI "sxd") (V2DF "dp")])
> 
> .._sxddp, like VS_sxswp in altivec.md?  The iterator is just VSX_D.
> 
> Maybe some or all of these iterators/attrs should live in vector.md?
> 
> Is it really useful to have separate files altivec.md and vsx.md anymore?
> Or should some things be moved?  This is a general question, not really
> something to be handled in this patch ;-)
> 

Yea, I find searching through all the files to rather hard.  Perhaps
putting all the definitions into a single "header" file?  That way it
could span across all of the .md files.  If you combined vsx.md and
altivec.md, you would have a really large file.  Big files can be
problematic in their own right.

> > +(define_insn "vsx_xvcvsxwsp"
> > +  [(set (match_operand:V4SF 0 "vsx_register_operand" "=v")
> > +   (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "v")]
> > +   UNSPEC_VSX_CVSXWSP))]
> > +  "VECTOR_UNIT_VSX_P (V4SFmode)"
> > +  "xvcvsxwsp %x0,%x1"
> > +  [(set_attr "type" "vecdouble")])
> 
> "v" is only the VRs...  Do you want "wa" or similar instead?
> 

I went back and re-studied the Power register constrains.  I find them a
bit confusing, I am sure they are perfectly clear to everyone else.  So
the instructions all take VSX registers so "wa" should be fine if I
understand it correctly.  Not sure there is any need to further
constrain with "vs" for doubles or "ww" but I think you could.

I retested the changes on powerpc64le-unknown-linux-gnu (Power 8 LE)
only. 

Please let me know if the updated patch is OK for gcc mainline?

 Carl Love
---
>From 3378d779286284183a4dc30a7a5dd10fa30671ff Mon Sep 17 00:00:00 2001
From: Carl Love 
Date: Fri, 9 Jun 2017 17:58:23 -0500
Subject: [PATCH] Add vec_float, vec_float2, vec_floate, vec_floate, builtin
 support.

gcc/ChangeLog:

2017-06-09  Carl Love  

* config/rs6000/rs6000-c.c: Add definitions for the vec_float,
vec_float2, vec_floato, vec_floate built-ins.
* config/rs6000/vsx.md: Add RTL code for instructions vsx_xvcvsxws
vsx_xvcvuxwsp, float2, floato and floate.
* config/rs6000/rs6000-builtin.def: Add definitions for vsx_xvcvsxwsp,
vsx_xvcvuxwsp, float2, floato and floate.
* config/altivec.md: Add version of p8_vmrgew that takes V4SF args and
returns V4SF.
* config/rs6000/altivec.h: Add builtin defines for vec_float,
vec_float2, vec_floate and vec_floato.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.

gcc/testsuite/ChangeLog:

2017-06-09  Carl Love  

* gcc.target/powerpc/builtins-3-runnable.c: Add runnable tests for
vec_float, vec_float2, vec_floate and vec_floato builtins
built-ins.

Signed-off-by: Carl Love 
---
 gcc/config/rs6000/altivec.h|   4 +
 gcc/config/rs6000/altivec.md   |  14 +-
 gcc/config/rs6000/rs6000-builtin.def   |  19 ++-
 gcc/config/rs6000/rs6000-c.c   |  28 +++-
 gcc/config/rs6000/rs6000-protos.h  |   1 +
 gcc/config/rs6000/rs6000.c |  45 +-
 gcc/config/rs6000/vsx.md   | 175 +
 gcc/doc/extend.texi|  14 ++
 .../gcc.target/powerpc/builtins-3-runnable.c   |  82 ++
 9 files changed, 370 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 20050eb..d542315 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -133,6 +133,10 @@
 #define vec_doublel __builtin_vec_doublel
 #define vec_doubleh __builtin_vec_doubleh
 #define vec_expte __builtin_vec_expte
+#define vec_float __builtin_vec_float
+#define vec_float2 __builtin_vec_float2
+#define vec_floate __builtin_vec_floate
+#define vec_floato __builtin_vec_floato
 #define vec_floor __builtin_vec_floor
 #define vec_loge __builtin_vec_loge
 #define vec_madd __builtin_vec_madd
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 487b9a4..25b2768 100644
--- 

[PATCH, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins

[Carl E. Love]

GCC Maintainers:

This patch adds support for the various vec_float, vec_float2,
vec_floate, vec_floate, builtins.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
and on powerpc64-unknown-linux-gnu (Power 8 BE) with no regressions.

Is the patch OK for gcc mainline?

  Carl Love
--

gcc/ChangeLog:

2017-06-09  Carl Love  

* config/rs6000/rs6000-c.c: Add definitions for the vec_float,
vec_float2, vec_floato, vec_floate built-ins.
* config/rs6000/vsx.md: Add RTL code for instructions vsx_xvcvsxws
vsx_xvcvuxwsp, float2, floato and floate.
* config/rs6000/rs6000-builtin.def: Add definitions for vsx_xvcvsxwsp,
vsx_xvcvuxwsp, float2, floato and floate.
* config/altivec.md: Add version of p8_vmrgew that takes V4SF args and
returns V4SF.
* config/rs6000/altivec.h: Add builtin defines for vec_float,
vec_float2, vec_floate and vec_floato.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.

gcc/testsuite/ChangeLog:

2017-06-09  Carl Love  

* gcc.target/powerpc/builtins-3-runnable.c: Add runnable tests for
vec_float, vec_float2, vec_floate and vec_floato builtins
built-ins.
---
 gcc/config/rs6000/altivec.h|   4 +
 gcc/config/rs6000/altivec.md   |  14 +-
 gcc/config/rs6000/rs6000-builtin.def   |  19 ++-
 gcc/config/rs6000/rs6000-c.c   |  28 +++-
 gcc/config/rs6000/rs6000-protos.h  |   1 +
 gcc/config/rs6000/rs6000.c |  44 -
 gcc/config/rs6000/vsx.md   | 177 +
 gcc/doc/extend.texi|  14 ++
 .../gcc.target/powerpc/builtins-3-runnable.c   |  82 ++
 9 files changed, 371 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 20050eb..d542315 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -133,6 +133,10 @@
 #define vec_doublel __builtin_vec_doublel
 #define vec_doubleh __builtin_vec_doubleh
 #define vec_expte __builtin_vec_expte
+#define vec_float __builtin_vec_float
+#define vec_float2 __builtin_vec_float2
+#define vec_floate __builtin_vec_floate
+#define vec_floato __builtin_vec_floato
 #define vec_floor __builtin_vec_floor
 #define vec_loge __builtin_vec_loge
 #define vec_madd __builtin_vec_madd
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 487b9a4..25b2768 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1316,13 +1316,13 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; Power8 vector merge even/odd
-(define_insn "p8_vmrgew"
-  [(set (match_operand:V4SI 0 "register_operand" "=v")
-   (vec_select:V4SI
- (vec_concat:V8SI
-   (match_operand:V4SI 1 "register_operand" "v")
-   (match_operand:V4SI 2 "register_operand" "v"))
+;; Power8 vector merge two V4SF/V4SI even words to V4SF
+(define_insn "p8_vmrgew_"
+  [(set (match_operand:VSX_W 0 "register_operand" "=v")
+   (vec_select:VSX_W
+ (vec_concat:
+   (match_operand:VSX_W 1 "register_operand" "v")
+   (match_operand:VSX_W 2 "register_operand" "v"))
  (parallel [(const_int 0) (const_int 4)
 (const_int 2) (const_int 6)])))]
   "TARGET_P8_VECTOR"
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 241c439..4682628 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1591,6 +1591,8 @@ BU_VSX_2 (CMPLE_U16QI,"cmple_u16qi",CONST,  
vector_ngtuv16qi)
 BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST,  vector_ngtuv8hi)
 BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST,  vector_ngtuv4si)
 BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST,  vector_ngtuv2di)
+BU_VSX_2 (FLOAT2_V2DI,"float2_v2di",CONST,  float2_v2di)
+BU_VSX_2 (UNS_FLOAT2_V2DI,"uns_float2_v2di",CONST,  uns_float2_v2di)
 
 /* VSX abs builtin functions.  */
 BU_VSX_A (XVABSDP,   "xvabsdp",CONST,  absv2df2)
@@ -1648,6 +1650,16 @@ BU_VSX_1 (XVCVSPSXDS,  "xvcvspsxds", CONST,  
vsx_xvcvspsxds)
 BU_VSX_1 (XVCVSPUXDS,"xvcvspuxds", CONST,  vsx_xvcvspuxds)
 BU_VSX_1 (XVCVSXDSP, "xvcvsxdsp",  CONST,  vsx_xvcvsxdsp)
 BU_VSX_1 (XVCVUXDSP, "xvcvuxdsp",  CONST,  vsx_xvcvuxdsp)
+
+BU_VSX_1 (XVCVSXWSP_V4SF,  "vsx_xvcvsxwsp",   CONST,   vsx_xvcvsxwsp)
+BU_VSX_1 (XVCVUXWSP_V4SF,  "vsx_xvcvuxwsp",   CONST,   vsx_xvcvuxwsp)
+BU_VSX_1 (FLOATE_V2DI, "floate_v2di", CONST,   floatev2di)
+BU_VSX_1 (FLOATE_V2DF, "floate_v2df", CONST,   floatev2df)
+BU_VSX_1 (FLOATO_V2DI, "floato_v2di", CONST,   floatov2di)

[PATCH, rs6000] PR 80982 gcc.target/powerpc/builtins-3-runnable.c fails starting with its introduction in r248846

[Carl E. Love]

GCC Maintainers:

The support for vec_doublel () builtin didn't get re-tested on BE before
submission.  The following buzilla was filed against the builtin
support.


Bug 80982 - gcc.target/powerpc/builtins-3-runnable.c fails starting with
its introduction in r248846. 

The failure was due to GEN_INT (8) being out of bounds.  Once that was
fixed, the order of the arguments also needed fixing to get the correct
result.  These changes only apply to the BE code.

The following patch has been tested on powerpc64le-unknown-linux-gnu
(Power 8 LE) and on powerpc64-unknown-linux-gnu (Power 8 BE) with no
regressions.

Is the patch OK for gcc mainline?

  Carl Love

-
PR 80982 gcc.target/powerpc/builtins-3-runnable.c fails
 starting   with its introduction in r248846.

gcc/ChangeLog:

2017-06-07  Carl Love  

PR target/80982
* config/rs6000/altivec.md: Fix the implementation of
(define_expand "doublel2" for BE.
---
 gcc/config/rs6000/altivec.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 9e592bc..487b9a4 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -3002,9 +3002,9 @@
   emit_insn (gen_vsx_xxsldwi_ (rtx_tmp, operands[1],
 operands[1], rtx_val));
 
-  rtx_val = GEN_INT (8);
-  emit_insn (gen_vsx_xxsldwi_ (rtx_tmp, rtx_tmp,
-operands[1],rtx_val));
+  rtx_val = GEN_INT (2);
+  emit_insn (gen_vsx_xxsldwi_ (rtx_tmp, operands[1],
+rtx_tmp, rtx_val));
   emit_insn (gen_vsx_xvcvdp (operands[0], rtx_tmp));
 }
   else
-- 
1.9.1

[PATCH, rs6000] Fix vec_mulo and vec_mule builtin implementations

[Carl E. Love]

GCC Maintainers:

The support for the vec_mulo and vec_mule that was recently submitted
has a couple of bugs.  Specifically, they were implemented with
int/unsigned int args and return int/unsigned int.  The return types
should have been long long/unsigned long long.  Additionally it was
noted that unsigned version returned a signed version by mistake.  

The following patch fixes these issues.  The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 8 LE) and on
powerpc64-unknown-linux-gnu (Power 8 BE) with no regressions.

Is the patch OK for gcc mainline?

  Carl Love
---

gcc/ChangeLog:

2017-06-08  Carl Love  

* config/rs6000/rs6000-c: The return type of the following
built-in functions was implemented as int not long long.  Fix sign
of return value for the unsigned version of vec_mulo and vec_mule.
vector unsigned long long vec_bperm (vector unsigned long long,
 vector unsigned char)
vector signed long long vec_mule (vector signed int,
  vector signed int)
vector unsigned long long vec_mule (vector unsigned int,
vector unsigned int)
vector signed long long vec_mulo (vector signed int,
  vector signed int)
vector unsigned long long vec_mulo (vector unsigned int,
vector unsigned int)
* doc/extend.texi: Fix the documentation for the
built-in functions.

gcc/testsuite/ChangeLog:

2017-06-08  Carl Love  

* gcc.target/powerpc/builtins-3.c: Fix vec_mule, vec_mulo test cases.
---
 gcc/config/rs6000/rs6000-c.c  | 12 +--
 gcc/doc/extend.texi   | 13 +++-
 gcc/testsuite/gcc.target/powerpc/builtins-3.c | 30 ++-
 3 files changed, 30 insertions(+), 25 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index b602dee..a917ea7 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2212,9 +2212,9 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
-RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
-RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
+RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
+RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
 RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 
RS6000_BTI_unsigned_V16QI, 0 },
@@ -2231,9 +2231,9 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 
RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
-RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
-RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
+RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
+RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
 RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index d147d5a..d467a16 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -16345,10 +16345,10 @@ vector signed short vec_mule (vector signed char,
 vector unsigned int vec_mule (vector unsigned short,
   vector unsigned short);
 vector signed int vec_mule (vector signed short, vector signed short);
-vector unsigned int vec_mule (vector unsigned int,
-  vector unsigned int);
-vector signed int vec_mule (vector signed int,
-vector signed int);
+vector unsigned long long vec_mule (vector unsigned int,
+vector unsigned int);
+vector signed long long vec_mule (vector signed int,
+  vector signed int);
 
 vector signed int vec_vmulesh (vector signed short,
vector signed short);
@@ -16368,7 +16368,10 @@ vector signed short vec_mulo (vector signed char, 
vector signed char);
 vector unsigned int vec_mulo (vector unsigned short,
   vector unsigned short);
 

[PATCH v3, rs6000] gcc mainline, add builtin support for vec_doublee, vec_doubleo, vec_doublel builtins

[Carl E. Love]

GCC Maintainers:

This is version 3 of the patch to add support for the various
vec_doublee, vec_doubleo, vec_doublel, vec_doubleh builtin-ins. I have
addressed the formatting comments from Segher on version 2.  I have run
the patch through contrib/check_GNU_style.sh to check for obvious
formatting errors.  

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc mainline?

  Carl Love


Add vec_doublee, vec_doubleo, vec_doublel, vec_doubleh builtin-ins

gcc/ChangeLog:

2017-06-01  Carl Love  

   * config/rs6000/rs6000-c: Add support for built-in functions
   vector double vec_doublee (vector signed int);
   vector double vec_doublee (vector unsigned int);
   vector double vec_doublee (vector float);
   vector double vec_doubleh (vector signed int);
   vector double vec_doubleh (vector unsigned int);
   vector double vec_doubleh (vector float);
   vector double vec_doublel (vector signed int);
   vector double vec_doublel (vector unsigned int);
   vector double vec_doublel (vector float);
   vector double vec_doubleo (vector signed int);
   vector double vec_doubleo (vector unsigned int);
   vector double vec_doubleo (vector float);.
   * config/rs6000/rs6000-builtin.def: Add definitions for DOUBLEE,
   DOUBLEO, DOUBLEH, DOUBLEL, UNS_DOUBLEO, UNS_DOUBLEE, UNS_DOUBLEH,
   UNS_DOUBLEL.
   * config/rs6000/altivec.md: Add code generator for doublee2,
   unsdoubleev4si2, doubleo2, unsdoubleov4si2, doubleh2,
   unsdoublehv4si2, doublel2, unsdoublelv4si2, add mode attribute
   VS_sxwsp.
   * config/rs6000/altivec.h: Add define for vec_doublee, vec_doubleo,
   vec_doublel, vec_doubleh.
   * doc/extend.texi: Update the built-in documentation file for the
   new built-in functions.

2017-06-01  Carl Love  

gcc/testsuite/ChangeLog:

   * gcc.target/powerpc/builtins-3-runnable.c: New file of runnable tests
   for the new built-ins.

Signed-off-by: Carl Love 
---
 gcc/config/rs6000/altivec.h|   4 +
 gcc/config/rs6000/altivec.md   | 337 +
 gcc/config/rs6000/rs6000-builtin.def   |  21 ++
 gcc/config/rs6000/rs6000-c.c   |  29 ++
 gcc/doc/extend.texi|  16 +
 .../gcc.target/powerpc/builtins-3-runnable.c   |  83 +
 6 files changed, 490 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index c92bcce..20050eb 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -128,6 +128,10 @@
 #define vec_ctu __builtin_vec_ctu
 #define vec_cpsgn __builtin_vec_copysign
 #define vec_double __builtin_vec_double
+#define vec_doublee __builtin_vec_doublee
+#define vec_doubleo __builtin_vec_doubleo
+#define vec_doublel __builtin_vec_doublel
+#define vec_doubleh __builtin_vec_doubleh
 #define vec_expte __builtin_vec_expte
 #define vec_floor __builtin_vec_floor
 #define vec_loge __builtin_vec_loge
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 649f181..af1fae3 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -203,6 +203,10 @@
   (KF "FLOAT128_VECTOR_P (KFmode)")
   (TF "FLOAT128_VECTOR_P (TFmode)")])
 
+;; Map the Vector convert single precision to double precision for integer
+;; versus floating point
+(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
+
 ;; Specific iterator for parity which does not have a byte/half-word form, but
 ;; does have a quad word form
 (define_mode_iterator VParity [V4SI
@@ -2739,6 +2743,339 @@
   "stvewx %1,%y0"
   [(set_attr "type" "vecstore")])
 
+;; Generate doublee
+;; signed int/float to double convert words 0 and 2
+(define_expand "doublee2"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+   (match_operand:VSX_W 1 "register_operand" "v"))]
+  "TARGET_VSX"
+{
+   machine_mode op_mode = GET_MODE (operands[1]);
+
+   if (VECTOR_ELT_ORDER_BIG)
+ {
+   /* Big endian word numbering for words in operand is 0 1 2 3.
+  Input words 0 and 2 are where they need to be.  */
+   emit_insn (gen_vsx_xvcvdp (operands[0], operands[1]));
+ }
+   else
+ {
+   /* Little endian word numbering for operand is 3 2 1 0.
+  take (operand[1] operand[1]) and shift left one word
+  3 2 1 03 2 1 0  =>  2 1 0 3
+  Input words 2 and 0 are now where they need to be for the
+  conversion.  */
+   rtx rtx_tmp;
+   rtx rtx_val = GEN_INT (1);
+
+   rtx_tmp = gen_reg_rtx (op_mode);
+   emit_insn (gen_vsx_xxsldwi_ (rtx_tmp, operands[1],
+  operands[1], rtx_val));
+   emit_insn (gen_vsx_xvcvdp (operands[0], rtx_tmp));
+ }
+   DONE;
+}
+  [(set_attr 

[PATCH v2, rs6000] gcc mainline, add builtin support for vec_doublee, vec_doubleo, vec_doublel builtins

[Carl E. Love]

GCC Maintainers:

This is version 2 of the patch to add support for the various
vec_doublee, vec_doubleo, vec_doublel, vec_doubleh builtin-ins. I have
addressed the various comments from Segher.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc mainline?

  Carl Love
---

gcc/ChangeLog:

2017-05-26  Carl Love  

   * config/rs6000/rs6000-c: Add support for built-in functions
   vector double vec_doublee (vector signed int);
   vector double vec_doublee (vector unsigned int);
   vector double vec_doublee (vector float);
   vector double vec_doubleh (vector signed int);
   vector double vec_doubleh (vector unsigned int);
   vector double vec_doubleh (vector float);
   vector double vec_doublel (vector signed int);
   vector double vec_doublel (vector unsigned int);
   vector double vec_doublel (vector float);
   vector double vec_doubleo (vector signed int);
   vector double vec_doubleo (vector unsigned int);
   vector double vec_doubleo (vector float);.
   * config/rs6000/rs6000-builtin.def: Add definitions for DOUBLEE,
   DOUBLEO, DOUBLEH, DOUBLEL, UNS_DOUBLEO, UNS_DOUBLEE, UNS_DOUBLEH,
   UNS_DOUBLEL.
   * config/rs6000/altivec.md: Add code generator for doublee, unsdoublee
   doubleov, unsdoubleov, doublehv, unsdoublehv, doublelv, unsdoublelv.
   * config/rs6000/altivec.h: Add define for vec_doublee, vec_doubleo,
   vec_doublel, vec_doubleh.
   * doc/extend.texi: Update the built-in documentation file for the
   new built-in functions.

2017-05-26  Carl Love  

gcc/testsuite/ChangeLog:

   * gcc.target/powerpc/builtins-3-runable.c: New file of runnable tests
   for the new built-ins.

Signed-off-by: Carl Love 
---
 gcc/config/rs6000/altivec.h|   4 +
 gcc/config/rs6000/altivec.md   | 338 +
 gcc/config/rs6000/rs6000-builtin.def   |  21 ++
 gcc/config/rs6000/rs6000-c.c   |  29 ++
 gcc/doc/extend.texi|  16 +
 .../gcc.target/powerpc/builtins-3-runnable.c   |  83 +
 6 files changed, 491 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index c92bcce..20050eb 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -128,6 +128,10 @@
 #define vec_ctu __builtin_vec_ctu
 #define vec_cpsgn __builtin_vec_copysign
 #define vec_double __builtin_vec_double
+#define vec_doublee __builtin_vec_doublee
+#define vec_doubleo __builtin_vec_doubleo
+#define vec_doublel __builtin_vec_doublel
+#define vec_doubleh __builtin_vec_doubleh
 #define vec_expte __builtin_vec_expte
 #define vec_floor __builtin_vec_floor
 #define vec_loge __builtin_vec_loge
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 649f181..dd08a90 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -203,6 +203,10 @@
   (KF "FLOAT128_VECTOR_P (KFmode)")
   (TF "FLOAT128_VECTOR_P (TFmode)")])
 
+;; Map the Vector convert single precision to double precision for integer
+;; versus floating point
+(define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")])
+
 ;; Specific iterator for parity which does not have a byte/half-word form, but
 ;; does have a quad word form
 (define_mode_iterator VParity [V4SI
@@ -2739,6 +2743,340 @@
   "stvewx %1,%y0"
   [(set_attr "type" "vecstore")])
 
+;; Generate doublee
+;;signed int/float to double convert words 0 and 2
+(define_expand "doublee2"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+(match_operand:VSX_W 1 "register_operand" "v"))]
+   "TARGET_VSX"
+{
+   machine_mode op_mode = GET_MODE (operands[1]);
+
+   if (VECTOR_ELT_ORDER_BIG)
+ {
+/* Big endian word numbering for words in operand is 0 1 2 3.
+   Input words 0 and 2 are where they need to be. */
+emit_insn (gen_vsx_xvcvdp (operands[0], operands[1]));
+ }
+   else
+ {
+/* Little endian word numbering for operand is 3 2 1 0.
+   take (operand[1] operand[1]) and shift left one word
+ 3 2 1 03 2 1 0  =>  2 1 0 3
+   Input words 2 and 0 are now where they need to be for the
+   conversion. */
+rtx rtx_tmp;
+rtx rtx_val = GEN_INT (1);
+
+rtx_tmp = gen_reg_rtx (op_mode);
+emit_insn (gen_vsx_xxsldwi_ (rtx_tmp,
+   operands[1], operands[1], rtx_val));
+emit_insn (gen_vsx_xvcvdp (operands[0], rtx_tmp));
+ }
+   DONE;
+}
+  [(set_attr "type" "veccomplex")])
+
+;; Generate unsdoublee
+;;unsigned int to double convert words 0 and 2
+(define_expand "unsdoubleev4si2"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+(match_operand:V4SI 1 

[PATCH, rs6000] gcc mainline, add builtin support for vec_doublee, vec_doubleo, vec_doublel builtins

[Carl E. Love]

GCC Maintainers:

This patch adds support for the various vec_doublee, vec_doubleo,
vec_doublel, vec_doubleh builtin-ins.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc mainline?

  Carl Love
--

gcc/ChangeLog:

2017-05-17  Carl Love  

   * config/rs6000/rs6000-c: Add support for built-in functions
   * config/rs6000/rs6000-builtin.def: Add definitions for
   * config/rs6000/altivec.h: Add define for
   * doc/extend.texi: Update the built-in documentation file for the
   new built-in functions.

gcc/testsuite/ChangeLog:

2017-05-17  Carl Love  

   * gcc.target/powerpc/builtins-3-runable.c: New file of runnable tests
   for the new built-ins.
---
 gcc/config/rs6000/altivec.h|   4 +
 gcc/config/rs6000/altivec.md   | 337 +
 gcc/config/rs6000/rs6000-builtin.def   |  20 ++
 gcc/config/rs6000/rs6000-c.c   |  29 ++
 gcc/doc/extend.texi|  16 +
 .../gcc.target/powerpc/builtins-3-runnable.c   |  84 +
 6 files changed, 490 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index c92bcce..20050eb 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -128,6 +128,10 @@
 #define vec_ctu __builtin_vec_ctu
 #define vec_cpsgn __builtin_vec_copysign
 #define vec_double __builtin_vec_double
+#define vec_doublee __builtin_vec_doublee
+#define vec_doubleo __builtin_vec_doubleo
+#define vec_doublel __builtin_vec_doublel
+#define vec_doubleh __builtin_vec_doubleh
 #define vec_expte __builtin_vec_expte
 #define vec_floor __builtin_vec_floor
 #define vec_loge __builtin_vec_loge
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 649f181..7d61641 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -203,6 +203,10 @@
   (KF "FLOAT128_VECTOR_P (KFmode)")
   (TF "FLOAT128_VECTOR_P (TFmode)")])
 
+(define_mode_iterator VM3 [V4SI V4SF])
+(define_mode_attr VM3_char [(V4SI "i")(V4SF "f")])
+(define_mode_attr VM3_x [(V4SI "xw")(V4SF "p")])
+
 ;; Specific iterator for parity which does not have a byte/half-word form, but
 ;; does have a quad word form
 (define_mode_iterator VParity [V4SI
@@ -2739,6 +2743,339 @@
   "stvewx %1,%y0"
   [(set_attr "type" "vecstore")])
 
+;; Generate doublee
+;;signed int/float to double convert words 0 and 2
+(define_expand "doublee2"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+(match_operand:VM3 1 "register_operand" "v"))]
+   "TARGET_VSX"
+{
+   machine_mode op_mode = GET_MODE (operands[1]);
+
+   if (VECTOR_ELT_ORDER_BIG)
+ {
+/* Big endian word numbering for words in operand is 0 1 2 3.
+   Input words 0 and 2 are where they need to be. */
+emit_insn (gen_vsx_xvcvsdp (operands[0], operands[1]));
+ }
+   else
+ {
+/* Little endian word numbering for operand is 3 2 1 0.
+   take (operand[1] operand[1]) and shift left one word
+ 3 2 1 03 2 1 0  =>  2 1 0 3
+   Input words 2 and 0 are now where they need to be for the
+   conversion. */
+rtx rtx_tmp;
+rtx rtx_val = GEN_INT (4);
+
+rtx_tmp = gen_reg_rtx (op_mode);
+emit_insn (gen_altivec_vsldoi_v4s (rtx_tmp,
+  operands[1], operands[1], rtx_val));
+emit_insn (gen_vsx_xvcvsdp (operands[0], rtx_tmp));
+ }
+   DONE;
+}
+  [(set_attr "type" "veccomplex")])
+
+;; Generate unsdoublee
+;;unsigned int to double convert words 0 and 2
+(define_expand "unsdoubleev4si2"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+(match_operand:V4SI 1 "register_operand" "v"))]
+   "TARGET_VSX"
+{
+   if (VECTOR_ELT_ORDER_BIG)
+ {
+/* Big endian word numbering for words in operand is 0 1 2 3.
+   Input words 0 and 2 are where they need to be. */
+emit_insn (gen_vsx_xvcvuxwdp (operands[0], operands[1]));
+ }
+   else
+ {
+/* Little endian word numbering for operand is 3 2 1 0.
+   take (operand[1] operand[1]) and shift left one word
+ 3 2 1 03 2 1 0  =>   2 1 0 3
+   Input words 2 and 0 are now where they need to be for the
+   conversion. */
+rtx rtx_tmp;
+rtx rtx_val = GEN_INT (4);
+
+rtx_tmp = gen_reg_rtx (V4SImode);
+emit_insn (gen_altivec_vsldoi_v4si (rtx_tmp,
+   operands[1], operands[1], rtx_val));
+emit_insn (gen_vsx_xvcvuxwdp (operands[0], rtx_tmp));
+ }
+   DONE;
+}
+  [(set_attr "type" "veccomplex")])
+
+;; Generate doubleov
+;;signed int/float to double convert words 1 and 3

[PATCH, rs6000] gcc mainline, add builtin support for vec_bperm(), vec_mule() and vec_mulo and vec_sldw() builtins

[Carl E. Love]

GCC Maintainers:

This patch adds support for the various vec_bperm(), vec_mule() and
vec_mulo and vec_sldw() builtins.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc mainline?

  Carl Love
--


gcc/ChangeLog:

2017-05-15  Carl Love  

   * config/rs6000/rs6000-c: Add support for built-in functions
   vector unsigned long long vec_bperm (vector unsigned long long,
vector unsigned char)
   vector signed long long vec_mule (vector signed int,
 vector signed int)
   vector unsigned long long vec_mule (vector unsigned int,
   vector unsigned int)
   vector signed long long vec_mulo (vector signed int,
 vector signed int)
   vector unsigned long long vec_mulo (vector unsigned int,
   vector unsigned int)
   vector signed char vec_sldw (vector signed char,
vector signed char,
const int)
   vector unsigned char vec_sldw (vector unsigned char,
  vector unsigned char,
  const int)
   vector signed short vec_sldw (vector signed short,
 vector signed short,
 const int)
   vector unsigned short vec_sldw (vector unsigned short,
   vector unsigned short,
   const int)
   vector signed int vec_sldw (vector signed int,
   vector signed int,
   const int)
   vector unsigned int vec_sldw (vector unsigned int,
 vector unsigned int,
 const int)
   vector signed long long vec_sldw (vector signed long long,
 vector signed long long,
 const int)
   vector unsigned long long vec_sldw (vector unsigned long long,
   vector unsigned long long,
   const int)
   * config/rs6000/rs6000-c: Add support for built-in functions
   * config/rs6000/rs6000-builtin.def: Add definition for SLDW.
   * config/rs6000/altivec.h: Add defintion for vec_sldw.
   * doc/extend.texi: Update the built-in documentation for the
 new built-in functions.

gcc/testsuite/ChangeLog:

2017-05-15  Carl Love  

   * gcc.target/powerpc/builtins-3.c: New vec_mule, vec_mulo test cases.
   * gcc.target/powerpc/builtins-3-p8.c: Add tests for the new Power 8
 built-ins to the test suite file.  Note, support for mradds exists
 but no test case exists.
   * gcc.target/powerpc/builtins-3-p9.c: Add tests for the new Power  9
 built-ins to the test suite file.
---
 gcc/config/rs6000/altivec.h  |  1 +
 gcc/config/rs6000/rs6000-builtin.def |  1 +
 gcc/config/rs6000/rs6000-c.c | 37 ++
 gcc/doc/extend.texi  | 32 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 37 +++---
 gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c | 31 +++-
 gcc/testsuite/gcc.target/powerpc/builtins-3.c| 93 +++-
 7 files changed, 204 insertions(+), 28 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index c334d9f..c92bcce 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -247,6 +247,7 @@
 #define vec_sel __builtin_vec_sel
 #define vec_sl __builtin_vec_sl
 #define vec_sld __builtin_vec_sld
+#define vec_sldw __builtin_vsx_xxsldwi
 #define vec_sll __builtin_vec_sll
 #define vec_slo __builtin_vec_slo
 #define vec_splat __builtin_vec_splat
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 41186b1..ebe005a 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1502,6 +1502,7 @@ BU_ALTIVEC_OVERLOAD_X (LVSR, "lvsr")
 BU_ALTIVEC_OVERLOAD_X (MUL,   "mul")
 BU_ALTIVEC_OVERLOAD_X (PROMOTE,   "promote")
 BU_ALTIVEC_OVERLOAD_X (SLD,   "sld")
+BU_ALTIVEC_OVERLOAD_X (SLDW,  "sldw")
 BU_ALTIVEC_OVERLOAD_X (SPLAT, "splat")
 BU_ALTIVEC_OVERLOAD_X (SPLATS,"splats")
 BU_ALTIVEC_OVERLOAD_X (ST,"st")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index a0536d6..8039814 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2182,6 +2182,11 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 
RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
 RS6000_BTI_V4SI, 

[PATCH, rs6000] gcc mainline, add builtin support for vec_popcnt() and vec_slo()

[Carl E. Love]

GCC Maintainers:

This patch adds support for the various vec_popcnt() and vec_slo()
builtins.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc mainline?

  Carl Love

---

2017-05-11  Carl Love  

* config/rs6000/rs6000-c: Add support for built-in functions
vector unsigned char vec_popcnt (vector signed char)
vector unsigned char vec_popcnt (vector unsigned char)
vector unsigned short vec_popcnt (vector signed short)
vector unsigned short vec_popcnt (vector unsigned short)
vector unsigned int vec_popcnt (vector signed int)
vector unsigned int vec_popcnt (vector unsigned int)
vector unsigned long long vec_popcnt (vector signed long long)
vector unsigned long long vec_popcnt (vector unsigned long long)
vector signed long long vec_slo (vector signed long long, vector signed 
char);
vector signed long long vec_slo (vector signed long long, vector 
unsigned char);
vector unsigned long long vec_slo (vector unsigned long long, vector 
signed char);
vector unsigned long long vec_slo (vector unsigned long long, vector 
unsigned char);
* config/rs6000/rs6000-builtin.def: Add definitions for VPOPCNTUB,
VPOPCNTUH, VPOPCNTUW, and VPOPCNTUD overloads.
* config/rs6000/altivec.h:  Add define for vec_popcnt, vec_popcntb,
vec_popth, vec_popcntw and vec_popcntd built-in functions.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.

gcc/testsuite/ChangeLog:

2017-05-11  Carl Love  

* gcc.target/powerpc/builtins-3-p8.c:  Add tests for the new built-ins
to the test suite file.
* gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins
to the test suite file.
---
 gcc/config/rs6000/altivec.h  |  5 ++
 gcc/config/rs6000/rs6000-builtin.def |  9 +++
 gcc/config/rs6000/rs6000-c.c | 28 +
 gcc/doc/extend.texi  | 13 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 76 ++--
 gcc/testsuite/gcc.target/powerpc/builtins-3.c| 31 +-
 6 files changed, 155 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 49b2a34..c334d9f 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -380,6 +380,11 @@
 #define vec_vpopcntd __builtin_vec_vpopcntd
 #define vec_vpopcnth __builtin_vec_vpopcnth
 #define vec_vpopcntw __builtin_vec_vpopcntw
+#define vec_popcnt __builtin_vec_vpopcntu
+#define vec_popcntb __builtin_vec_vpopcntub
+#define vec_popcnth __builtin_vec_vpopcntuh
+#define vec_popcntw __builtin_vec_vpopcntuw
+#define vec_popcntd __builtin_vec_vpopcntud
 #define vec_vrld __builtin_vec_vrld
 #define vec_vsld __builtin_vec_vsld
 #define vec_vsrad __builtin_vec_vsrad
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 50b1588..d292244 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1803,6 +1803,10 @@ BU_P8V_AV_1 (VPOPCNTB, "vpopcntb",   CONST,  
popcountv16qi2)
 BU_P8V_AV_1 (VPOPCNTH,   "vpopcnth",   CONST,  popcountv8hi2)
 BU_P8V_AV_1 (VPOPCNTW,   "vpopcntw",   CONST,  popcountv4si2)
 BU_P8V_AV_1 (VPOPCNTD,   "vpopcntd",   CONST,  popcountv2di2)
+BU_P8V_AV_1 (VPOPCNTUB,   "vpopcntub", CONST,  popcountv16qi2)
+BU_P8V_AV_1 (VPOPCNTUH,   "vpopcntuh", CONST,  popcountv8hi2)
+BU_P8V_AV_1 (VPOPCNTUW,   "vpopcntuw", CONST,  popcountv4si2)
+BU_P8V_AV_1 (VPOPCNTUD,   "vpopcntud", CONST,  popcountv2di2)
 BU_P8V_AV_1 (VGBBD,  "vgbbd",  CONST,  p8v_vgbbd)
 
 /* 2 argument altivec instructions added in ISA 2.07.  */
@@ -1886,6 +1890,11 @@ BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb")
 BU_P8V_OVERLOAD_1 (VPOPCNTH,   "vpopcnth")
 BU_P8V_OVERLOAD_1 (VPOPCNTW,   "vpopcntw")
 BU_P8V_OVERLOAD_1 (VPOPCNTD,   "vpopcntd")
+BU_P8V_OVERLOAD_1 (VPOPCNTU,   "vpopcntu")
+BU_P8V_OVERLOAD_1 (VPOPCNTUB,  "vpopcntub")
+BU_P8V_OVERLOAD_1 (VPOPCNTUH,  "vpopcntuh")
+BU_P8V_OVERLOAD_1 (VPOPCNTUW,  "vpopcntuw")
+BU_P8V_OVERLOAD_1 (VPOPCNTUD,  "vpopcntud")
 BU_P8V_OVERLOAD_1 (VGBBD,  "vgbbd")
 
 /* ISA 2.07 vector overloaded 2 argument functions.  */
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 3309f8d..6730f26 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2578,6 +2578,14 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 
},
   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
 RS6000_BTI_unsigned_V16QI, 

[PATCH, rs6000] gcc mainline, add builtin support for vec_neg()

[Carl E. Love]

GCC Maintainers:

This patch adds support for the various vec_neg() builtins.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc mainline?

  Carl Love

---

gcc/ChangeLog:

2017-04-05  Carl Love  

   * config/rs6000/rs6000-c: Add support for built-in functions
   vector signed charvec_neg (vector signed char)
   vector signed short int   vec_neg (vector short int)
   vector signed int vec_neg (vector signed int)
   vector signed long long   vec_neg (vector signed long long)
   vector float  vec_neg (vector float)
   vector double vec_neg (vector double)
   * config/rs6000/rs6000-builtin.def: Add definitions for NEG function
   overload.
   * config/rs6000/altivec.h: Add define for vec_neg
   * doc/extend.texi: Update the built-in documentation for the
   new built-in functions.

gcc/testsuite/ChangeLog:

2017-04-05  Carl Love  
   * gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins to
   to the test suite file.
   * gcc.target/powerpc/builtins-3-p8.c: Add tests for the new built-ins to
   to the test suite file.
---
 gcc/config/rs6000/altivec.h  |  1 +
 gcc/config/rs6000/rs6000-builtin.def |  9 +
 gcc/config/rs6000/rs6000-c.c | 14 +++
 gcc/doc/extend.texi  |  7 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 13 +--
 gcc/testsuite/gcc.target/powerpc/builtins-3.c| 47 +---
 6 files changed, 83 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index b9de05a..49b2a34 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -213,6 +213,7 @@
 #define vec_lvebx __builtin_vec_lvebx
 #define vec_lvehx __builtin_vec_lvehx
 #define vec_lvewx __builtin_vec_lvewx
+#define vec_neg __builtin_vec_neg
 #define vec_pmsum_be __builtin_vec_vpmsum
 #define vec_shasigma_be __builtin_crypto_vshasigma
 /* Cell only intrinsics.  */
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index a39f936..50b1588 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1133,6 +1133,14 @@ BU_ALTIVEC_A (NABS_V16QI, "nabs_v16qi",  CONST,  
nabsv16qi2)
 BU_ALTIVEC_A (NABS_V4SF,  "nabs_v4sf", CONST,  vsx_nabsv4sf2)
 BU_ALTIVEC_A (NABS_V2DF,  "nabs_v2df", CONST,  vsx_nabsv2df2)
 
+/* Altivec NEG functions.  */
+BU_ALTIVEC_A (NEG_V2DI,  "neg_v2di",   CONST,  negv2di2)
+BU_ALTIVEC_A (NEG_V4SI,  "neg_v4si",   CONST,  negv4si2)
+BU_ALTIVEC_A (NEG_V8HI,  "neg_v8hi",   CONST,  negv8hi2)
+BU_ALTIVEC_A (NEG_V16QI, "neg_v16qi",  CONST,  negv16qi2)
+BU_ALTIVEC_A (NEG_V4SF,  "neg_v4sf",   CONST,  negv4sf2)
+BU_ALTIVEC_A (NEG_V2DF,  "neg_v2df",   CONST,  negv2df2)
+
 /* 1 argument Altivec builtin functions.  */
 BU_ALTIVEC_1 (VEXPTEFP,  "vexptefp",   FP, 
altivec_vexptefp)
 BU_ALTIVEC_1 (VLOGEFP,   "vlogefp",FP, altivec_vlogefp)
@@ -1420,6 +1428,7 @@ BU_ALTIVEC_OVERLOAD_1 (FLOOR,"floor")
 BU_ALTIVEC_OVERLOAD_1 (LOGE,  "loge")
 BU_ALTIVEC_OVERLOAD_1 (MTVSCR,"mtvscr")
 BU_ALTIVEC_OVERLOAD_1 (NEARBYINT,  "nearbyint")
+BU_ALTIVEC_OVERLOAD_1 (NEG,   "neg")
 BU_ALTIVEC_OVERLOAD_1 (RE,"re")
 BU_ALTIVEC_OVERLOAD_1 (RINT,   "rint")
 BU_ALTIVEC_OVERLOAD_1 (ROUND, "round")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 80aab5f..3309f8d 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -,6 +,20 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
+
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V16QI,
+RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V8HI,
+RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SI,
+RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DI,
+RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SF,
+RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
+  { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DF,
+RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
+
   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 1255995..f2b3042 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -16343,6 +16343,13 @@ 

[PATCH, rs6000] gcc 6 back port of xvcvsxdsp and xvcvuxdsp RTL fixes

[Carl E. Love]

GCC Maintainers:

Here is the GCC 6 branch back port of the mainline fixes for the RTL
definitions for xvcvsxdsp and xvcvuxdsp instructions, commit r245460 on
2017-02-14.  The GCC 5 backport of these fixes have already been
approved and  committed.

The RTL defined the instructions with a V2DF argument and returning
V4SI. They should take a V2DI argument and return a V4SF based on the
Power ISA document. Additionally, the RTL define_insn for the xvcvuxdsp
was fixed to generate the correct xvcvuxdsp instruction instead of the
xvcvuxwdp instruction.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc 6 branch?  

   Carl Love
---

gcc/ChangeLog:

2017-02-17  Carl Love  

   Backport from mainline commit r245460 on 2017-02-14

   PR 79545
   * config/rs6000/rs6000.c: Add case statement entry to make the xvcvuxdsp
   built-in argument unsigned.
   * config/rs6000/vsx.md: Fix the source and return operand types so they
   match the instruction definitions from the ISA document.  Fix typo
   in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
   statement.

gcc/testsuite/ChangeLog:

2017-01-17  Carl Love  

   Backport from mainline commit r245460 on 2017-02-14

   PR 79545
   * gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
   xvcvsxdsp and xvcvuxdsp instructions.
---
 gcc/config/rs6000/rs6000.c   |  1 +
 gcc/config/rs6000/vsx.md | 10 +-
 gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 23 +++
 3 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7591e55..8661d4f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -17080,6 +17080,7 @@ builtin_function_type (machine_mode mode_ret, 
machine_mode mode_arg0,
   break;
 
   /* unsigned args, signed return.  */
+case VSX_BUILTIN_XVCVUXDSP:
 case VSX_BUILTIN_XVCVUXDDP_UNS:
 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
   h.uns_p[1] = 1;
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f9717f1..c7abb7b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1827,19 +1827,19 @@
   [(set_attr "type" "vecdouble")])
 
 (define_insn "vsx_xvcvsxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-   (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+   (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
 UNSPEC_VSX_CVSXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
   "xvcvsxdsp %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "vsx_xvcvuxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-   (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+   (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
 UNSPEC_VSX_CVUXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxwdp %x0,%x1"
+  "xvcvuxdsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
 ;; Convert from 32-bit to 64-bit types
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index f337c1c..ff5296c 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -35,6 +35,8 @@
 /* { dg-final { scan-assembler "xvcmpgesp" } } */
 /* { dg-final { scan-assembler "xxsldwi" } } */
 /* { dg-final { scan-assembler-not "call" } } */
+/* { dg-final { scan-assembler "xvcvsxdsp" } } */
+/* { dg-final { scan-assembler "xvcvuxdsp" } } */
 
 extern __vector int si[][4];
 extern __vector short ss[][4];
@@ -50,7 +52,9 @@ extern __vector __pixel p[][4];
 #ifdef __VSX__
 extern __vector double d[][4];
 extern __vector long sl[][4];
+extern __vector long long sll[][4];
 extern __vector unsigned long ul[][4];
+extern __vector unsigned long long ull[][4];
 extern __vector __bool long bl[][4];
 #endif
 
@@ -211,3 +215,22 @@ int do_xxsldwi (void)
   d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
   return i;
 }
+
+int do_xvcvsxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvsxdsp (sll[i][1]); i++;
+
+  return i;
+}
+
+int do_xvcvuxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvuxdsp (ull[i][1]); i++;
+
+  return i;
+}
+
-- 
1.9.1

[PATCH, rs6000] gcc 5 back port of xvcvsxdsp and xvcvuxdsp RTL fixes

[Carl E. Love]

GCC Maintainers:

I have backported the mainline fixes for the RTL definitions for
xvcvsxdsp and xvcvuxdsp instructions, commit r245460 on 2017-02-14 to
the GCC 5 branch.

The RTL defined the instructions with a V2DF argument and returning
V4SI. They should take a V2DI argument and return a V4SF based on the
Power ISA document. Additionally, the RTL define_insn for the xvcvuxdsp
was fixed to generate the correct xvcvuxdsp instruction instead of the
xvcvuxwdp instruction.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc 5 branch?  

   Carl Love

---
gcc/ChangeLog:

2017-02-16  Carl Love  

   Backport from mainline commit r245460 on 2017-02-14

   PR 79545
   * config/rs6000/rs6000.c: Add case statement entry to make the xvcvuxdsp
   built-in argument unsigned.
   * config/rs6000/vsx.md: Fix the source and return operand types so they
   match the instruction definitions from the ISA document.  Fix typo
   in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
   statement.


gcc/testsuite/ChangeLog:

2017-01-16  Carl Love  

   Backport from mainline commit r245460 on 2017-02-14

   PR 79545
   * gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
   xvcvsxdsp and xvcvuxdsp instructions.
---
 gcc/config/rs6000/rs6000.c   |  1 +
 gcc/config/rs6000/vsx.md | 10 +-
 gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 23 +++
 3 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 5bba64e..234d277 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15628,6 +15628,7 @@ builtin_function_type (machine_mode mode_ret, 
machine_mode mode_arg0,
   break;
 
   /* unsigned args, signed return.  */
+case VSX_BUILTIN_XVCVUXDSP:
 case VSX_BUILTIN_XVCVUXDDP_UNS:
 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
   h.uns_p[1] = 1;
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a689c2b..efbd3ec 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1501,19 +1501,19 @@
   [(set_attr "type" "vecdouble")])
 
 (define_insn "vsx_xvcvsxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-   (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+   (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
 UNSPEC_VSX_CVSXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
   "xvcvsxdsp %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "vsx_xvcvuxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-   (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+   (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
 UNSPEC_VSX_CVUXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxwdp %x0,%x1"
+  "xvcvuxdsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
 ;; Convert from 32-bit to 64-bit types
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index f337c1c..ff5296c 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -35,6 +35,8 @@
 /* { dg-final { scan-assembler "xvcmpgesp" } } */
 /* { dg-final { scan-assembler "xxsldwi" } } */
 /* { dg-final { scan-assembler-not "call" } } */
+/* { dg-final { scan-assembler "xvcvsxdsp" } } */
+/* { dg-final { scan-assembler "xvcvuxdsp" } } */
 
 extern __vector int si[][4];
 extern __vector short ss[][4];
@@ -50,7 +52,9 @@ extern __vector __pixel p[][4];
 #ifdef __VSX__
 extern __vector double d[][4];
 extern __vector long sl[][4];
+extern __vector long long sll[][4];
 extern __vector unsigned long ul[][4];
+extern __vector unsigned long long ull[][4];
 extern __vector __bool long bl[][4];
 #endif
 
@@ -211,3 +215,22 @@ int do_xxsldwi (void)
   d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
   return i;
 }
+
+int do_xvcvsxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvsxdsp (sll[i][1]); i++;
+
+  return i;
+}
+
+int do_xvcvuxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvuxdsp (ull[i][1]); i++;
+
+  return i;
+}
+
-- 
1.9.1

[PATCH, rs6000] Fix RTL definitions of the xvcvsxdsp and xvcvuxdsp instructions

[Carl E. Love]

GCC Maintainers:

The following patch addresses errors in the RTL define_insn statements
for the xvcvsxdsp and xvcvuxdsp instructions.  The RTL defined the
instructions with a V2DF argument and returning V4SI.  They should take
a V2DI argument and return a V4SF based on the Power ISA document. 

Additionally, the RTL define_insn for the xvcvuxdsp was fixed to
generate the correct xvcvuxdsp instruction instead of the xvcvuxwdp
instruction. Note, this is an additional fix added to the previously
reviewed patch.

A compile only test was added to test the argument and return types for
the RTL define_insn definitions.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc mainline?

   Carl Love



gcc/ChangeLog:

2017-02-14  Carl Love  

   * config/rs6000/rs6000.c: Add case statement entry to make the xvcvuxdsp
   built-in argument unsigned.
   * config/rs6000/vsx.md: Fix the source and return operand types so they
   match the instruction definitions from the ISA document.  Fix typo
   in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
   statement.

gcc/testsuite/ChangeLog:

2017-01-14  Carl Love  

   * gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
   xvcvsxdsp and xvcvuxdsp instructions.
---
 gcc/config/rs6000/rs6000.c   |  1 +
 gcc/config/rs6000/vsx.md | 10 +-
 gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 23 +++
 3 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index b1c9ef5..f752d1d 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -18594,6 +18594,7 @@ builtin_function_type (machine_mode mode_ret, 
machine_mode mode_arg0,
   break;
 
   /* unsigned args, signed return.  */
+case VSX_BUILTIN_XVCVUXDSP:
 case VSX_BUILTIN_XVCVUXDDP_UNS:
 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
   h.uns_p[1] = 1;
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b10ade4..9c3c07d 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1914,19 +1914,19 @@
   [(set_attr "type" "vecdouble")])
 
 (define_insn "vsx_xvcvsxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-   (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+   (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
 UNSPEC_VSX_CVSXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
   "xvcvsxdsp %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "vsx_xvcvuxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-   (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+   (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
 UNSPEC_VSX_CVUXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxwdp %x0,%x1"
+  "xvcvuxdsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
 ;; Convert from 32-bit to 64-bit types
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index f337c1c..ff5296c 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -35,6 +35,8 @@
 /* { dg-final { scan-assembler "xvcmpgesp" } } */
 /* { dg-final { scan-assembler "xxsldwi" } } */
 /* { dg-final { scan-assembler-not "call" } } */
+/* { dg-final { scan-assembler "xvcvsxdsp" } } */
+/* { dg-final { scan-assembler "xvcvuxdsp" } } */
 
 extern __vector int si[][4];
 extern __vector short ss[][4];
@@ -50,7 +52,9 @@ extern __vector __pixel p[][4];
 #ifdef __VSX__
 extern __vector double d[][4];
 extern __vector long sl[][4];
+extern __vector long long sll[][4];
 extern __vector unsigned long ul[][4];
+extern __vector unsigned long long ull[][4];
 extern __vector __bool long bl[][4];
 #endif
 
@@ -211,3 +215,22 @@ int do_xxsldwi (void)
   d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
   return i;
 }
+
+int do_xvcvsxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvsxdsp (sll[i][1]); i++;
+
+  return i;
+}
+
+int do_xvcvuxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvuxdsp (ull[i][1]); i++;
+
+  return i;
+}
+
-- 
1.9.1

[PATCH, rs6000] gcc 5 back port of vec_packs and vec_vgbbd builtin table entry fixes

[Carl E. Love]

GCC Maintainers:

The GCC 6 branch for the back port of the following two mainline commits
was approved and committed to GCC 6.  The following patch is the back
port for the two commits for the GCC 5 branch.  The only difference
relative to the GCC 6 patch is the line numbers.

mainline commits.
commit r244943  Remove bogus entries for the P8V_BUILTIN_VEC_VGBBD   
built-ins
commit r244904  Fix order of entries for ALTIVEC_BUILTIN_VEC_PACKS
and P8V_BUILTIN_VEC_VGBBD.

The patch fixes the issue of the vec_packs built-in entries not being
contiguous and removes the bogus entries for the vec_vgbbd built-in.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc 5 branch?  

   Carl Love
\

gcc/ChangeLog:

2017-02-03  Carl Love  

Backport of two commits from mainline, r244943 and r244904,
dated 017-01-26 and 2017-01-25 respectively

* config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order
of entries for ALTIVEC_BUILTIN_VEC_PACKS.  Remove bogus entries
for P8V_BUILTIN_VEC_VGBBD.

gcc/testsuite/ChangeLog:

2017-02-03  Carl Love  
* gcc.target/powerpc/builtins-3-p8.c:  Add new testfile for missing
vec_packs built-in tests.
---
 gcc/config/rs6000/rs6000-c.c | 13 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 26 
 2 files changed, 30 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index fbb8e2d..33cb27f 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2065,14 +2065,14 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
-RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
-RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, 
RS6000_BTI_unsigned_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+  { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
+RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
+RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
@@ -4196,11 +4196,6 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_V16QI, 0, 0, 0 },
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
-
   /* Crypto builtins.  */
   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
new file mode 100644
index 000..2c06ea7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8" } */
+
+#include 
+
+vector signed int
+test_vsi_packs_vsll_vsll (vector signed long long x,
+  vector signed long long y)
+{
+  return vec_packs (x, y);
+}
+
+vector unsigned int
+test_vui_packs_vull_vull (vector unsigned long long x,
+  vector unsigned long long y)
+{
+  return vec_packs (x, y);
+}
+
+/* Expected test results:
+ test_vsi_packs_vsll_vsll  1 vpksdss
+ test_vui_packs_vull_vull  1 vpkudus */
+
+/* { dg-final { scan-assembler-times "vpksdss"  1 } } */
+/* { dg-final { scan-assembler-times "vpkudus"  1 } } */
-- 
1.9.1

[PATCH, rs6000] gcc 6 back port of vec_packs and vec_vgbbd builtin table entry fixes

[Carl E. Love]

GCC Maintainers:

I have squashed the following two patches from mainline 

commit r244943  Remove bogus entries for the P8V_BUILTIN_VEC_VGBBD   
built-ins
commit r244904  Fix order of entries for ALTIVEC_BUILTIN_VEC_PACKS
and P8V_BUILTIN_VEC_VGBBD.

and back ported them to the GCC 6 branch.  The patch fixes the issue
of the vec_packs built-in entries not being contiguous and removes the
bogus entries for the vec_vgbbd built-in.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for gcc 6 branch?  

   Carl Love
-
gcc/ChangeLog:

2017-02-03  Carl Love  

* config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order
of entries for ALTIVEC_BUILTIN_VEC_PACKS.  Remove bogus entries
for P8V_BUILTIN_VEC_VGBBD.

gcc/testsuite/ChangeLog:

2017-02-03  Carl Love  
* gcc.target/powerpc/builtins-3-p8.c:  Add new testfile for missing
vec_packs built-in tests.
---
 gcc/config/rs6000/rs6000-c.c | 13 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 26 
 2 files changed, 30 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 9eb6d54..474b48c 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2133,14 +2133,14 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
-RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
-RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, 
RS6000_BTI_unsigned_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+  { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
+RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
+RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
@@ -4550,11 +4550,6 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_V16QI, 0, 0, 0 },
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
-
   { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
 RS6000_BTI_unsigned_V16QI, 0 },
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
new file mode 100644
index 000..2c06ea7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8" } */
+
+#include 
+
+vector signed int
+test_vsi_packs_vsll_vsll (vector signed long long x,
+  vector signed long long y)
+{
+  return vec_packs (x, y);
+}
+
+vector unsigned int
+test_vui_packs_vull_vull (vector unsigned long long x,
+  vector unsigned long long y)
+{
+  return vec_packs (x, y);
+}
+
+/* Expected test results:
+ test_vsi_packs_vsll_vsll  1 vpksdss
+ test_vui_packs_vull_vull  1 vpkudus */
+
+/* { dg-final { scan-assembler-times "vpksdss"  1 } } */
+/* { dg-final { scan-assembler-times "vpkudus"  1 } } */
-- 
1.9.1

[PATCH,rs6000] Remove invalid P8V_BUILTIN_VEC_VGBBD entries

[Carl E. Love]

GCC Maintainers:

After further discussion of the two P8V_BUILTIN_VGBBD built-ins that do
not take any arguments, it was determined they should just be removed as
they are not valid.

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for trunk?  

   Carl Love
-

gcc/ChangeLog:

2017-01-24  Carl Love  

* config/rs6000/rs6000-c (altivec_overloaded_builtins): Remove
bogus entries for the P8V_BUILTIN_VEC_VGBBD built-ins
---
 gcc/config/rs6000/rs6000-c.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 1466c0c..cda0da8 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -4789,10 +4789,6 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_V16QI, 0, 0, 0 },
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
   
   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
 RS6000_BTI_V16QI, RS6000_BTI_V4SI,
-- 
1.9.1

Re: [PATCH, rs6000] Fix for entries in table of overloaded built-in functions

[Carl E. Love]

Bill:


> >   
> > I don't see any tests for the two built-in entries in rs6000-c.c which the 
> > patch moves, i.e.
> > 
> >   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,   
> >   
> > RS6000_BTI_V16QI, 0, 0, 0 },
> >   
> >   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,   
> >   
> > RS6000_BTI_unsigned_V16QI, 0, 0, 0 },  
> > 

> 
> Those two entries look bogus to me, and they should just be removed, not
> moved.  I have no idea where they came from.  I suspect they were
> place-holders at one time that snuck into the code by accident.
> 
> The relevant API interface listed in the ELFv2 ABI is vec_gb, which
> should support only one interface:
> 
> vector unsigned char vec_gb (vector unsigned char);
> 
> So please remove the two bogus interfaces, and make sure we have support
> for the vec_gb interface in your GCC 8 patch list.  Thanks!

Taking this off list.

Bill sorry I missed your email this morning before I committed the patch
that moved the vec_vgbbd.  I agree the two vec_gbbd entries look bogus
to me.  There is a test in 
gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
for the vec_gb() interface you mentioned from the ABI that covers this
case.

I will create and test a patch to remove the bogus entries.  I will then
roll it into a single patch that fixes the vex_packs entries and adds
the missing vex_packs tests.  I will then back port the single patch to
GCC-5 and GCC-6.  I will post the back ported patches to the list in a
week or so assuming no issues arise with the changes to mainline. 

Does that all sound reasonable?

   Carl Love 

Re: [PATCH, rs6000] Fix for entries in table of overloaded built-in functions

[Carl E. Love]

On Tue, 2017-01-24 at 11:08 -0600, Segher Boessenkool wrote:
> On Tue, Jan 24, 2017 at 08:28:37AM -0800, Carl E. Love wrote:
> > The following patch fixes an issue with the entries in the table of
> > built-in functions.  All of the entries for a given built-in, must occur
> > in the table as a single block of entries.  Otherwise the code that
> > searches the table for a given built-in definition will stop looking
> > once it reaches the end of the initial block of definitions for that
> > built-in function and subsequent definitions for that built-in will
> > never be checked.  This issue currently occurs with the
> > ALTIVEC_BUILTIN_VEC_PACKS and P8V_BUILTIN_VEC_VGBBD built-ins.  The
> > patch simply moves the existing entries so the definition for a given
> > built-in are all together in the same block of entries.
> 
> Do we need a separate testcase to check for this?  Or do those specific
> builtins need better testcases?  Or was the bug obvious already?

I have a list of built-ins that need to have support and test cases
added.  I found the issue with the ALTIVEC_BUILTIN_VEC_PACKS when I
tried to add support for the built-ins:

  vector signed int vec_packs (vector signed long long x, vector signed long 
long y);
  vector unsigned int vec_packs (vector unsigned long long x, vector unsigned 
long long y);

which were in my to do list.  What I found was the support for vec_packs
is all there but I don't find any test cases for these built-ins.  At
this point, I do plan to add the vec_pack test cases as part of my work
to add the support for the other built-ins on my list.  I have the patch
in my patch series with the others that need adding.  Currently holding
off on posting patches since we are only supposed to be posting bug
fixes at the moment.

Once the bug for the ALTIVEC_BUILTIN_VEC_PACKS built-in was found, I
wrote a perl script to scan through the entire table looking for the
issue with any other built-in functions.  The script found the issue
with the P8V_BUILTIN_VEC_VGBBD built-in.  My list of built-ins to add
doesn't include anything for vec_vgbbd.  

It would be easy for my to add the test cases for the vec_packs()
built-ins to this patch if you would like?  

I just took a look at the vec_vgbbd() built-in.  I grep'd for vgbbd and
found the followint two testcases in
gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c:

typedef vector signed charvc_sign;  

typedef vector unsigned char  vc_uns;
 
vc_sign vc_gbb_2 (vc_sign a)

{   

  return vec_vgbbd (a); 

}   



vc_uns vc_gbb_3 (vc_uns a)  

{   

  return vec_vgbbd (a); 

}   


which correspond to the built-in entries in rs6000-c.c which I didn't move

  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,   
  
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 
  
  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,   
  
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
  
I don't see any tests for the two built-in entries in rs6000-c.c which the 
patch moves, i.e.

  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,   
  
RS6000_BTI_V16QI, 0, 0, 0 },
  
  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,   
  
RS6000_BTI_unsigned_V16QI, 0, 0, 0 },  

I tried a quick test of adding the following to the test file  
p8vector-builtin-4.c for these entries:
  
vc_sign vc_gbb_4 (void) 

{   

[PATCH, rs6000] Fix for entries in table of overloaded built-in functions

[Carl E. Love]

GCC maintainers:

The following patch fixes an issue with the entries in the table of
built-in functions.  All of the entries for a given built-in, must occur
in the table as a single block of entries.  Otherwise the code that
searches the table for a given built-in definition will stop looking
once it reaches the end of the initial block of definitions for that
built-in function and subsequent definitions for that built-in will
never be checked.  This issue currently occurs with the
ALTIVEC_BUILTIN_VEC_PACKS and P8V_BUILTIN_VEC_VGBBD built-ins.  The
patch simply moves the existing entries so the definition for a given
built-in are all together in the same block of entries.

Note this issue also exists with the GCC-5 and GCC-6 branches.  

The patch has been tested on powerpc64le-unknown-linux-gnu (Power 8 LE)
with no regressions.

Is the patch OK for trunk?  

Assuming this patch is OK, would it be acceptable to post a back port of
the patch for GCC 5 and GCC 6 branches after the patch is in mainline as
long as no issues are seen with this version in the mainline code base?


Carl Love


gcc/ChangeLog:

2017-01-23  Carl Love  

* config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order
of entries for ALTIVEC_BUILTIN_VEC_PACKS and P8V_BUILTIN_VEC_VGBBD.
---
 gcc/config/rs6000/rs6000-c.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 8b87a0a..92e9849 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2154,14 +2154,14 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
-RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
-RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, 
RS6000_BTI_unsigned_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+  { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
+RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
+RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 
RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
@@ -4777,6 +4777,10 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
+  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+RS6000_BTI_V16QI, 0, 0, 0 },
+  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
 
   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
 RS6000_BTI_V16QI, RS6000_BTI_V4SI,
@@ -5038,11 +5042,6 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_V16QI, 0, 0, 0 },
-  { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
-
   { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
 RS6000_BTI_unsigned_V16QI, 0 },
-- 
1.9.1

[PATCH, rs6000] Fix for test_ne_int() built-in test case.

[Carl E. Love]

GCC maintainers:

The following patch fixes an issue with the builtin test test_ne_long().
The issue is the arguments need to be "bool long long" not "bool long"
to get the correct 64-bit value when running in 32-bit mode.

The patch has been tested on:
powerpc64-unknown-linux-gnu (Power 7 64-bit, 32-bit) with no
regressions.

Is this OK for trunk?

Carl Love

--

gcc/testsuite/ChangeLog:

2017-01-13 Carl Love  

* gcc.target/powerpc/builtins-3-p9.c (test_ne_long()):
Test fails in 32-bit mode because the arguments are of type
"bool long" not "bool long long".  The arguments need to be
"bool long long" to get a correct 64-bit value in 32-bit mode.
---
 gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
index d846e29..e3db2da 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
@@ -22,8 +22,8 @@ test_ne_int (vector bool int x, vector bool int y)
return vec_cmpne (x, y);
 }
 
-vector bool long
-test_ne_long (vector bool long x, vector bool long y)
+vector bool long long
+test_ne_long (vector bool long long x, vector bool long long y)
 {
return vec_cmpne (x, y);
 }
-- 
1.8.3.1

Re: [PATCH, rs6000] Add vec_nabs builtin support

[Carl E. Love]

Segar:

The issues you pointed out below have been addressed in the following
updated patch.  Please let me know if the changes are acceptable.
Thanks for your help and feedback.

   Carl Love
> rs6000-c.c
> 
> > vector signed char vec_nabs (vector signed char)
> > vector signed short vec_nabs (vector signed short)
> > vector signed int vec_nabs (vector signed int)
> > vector signed long long vec_nabs (vector signed long long)
> > vector float vec_nabs (vector float)
> > vector double vec_nabs (vector double)
> 
> You should mention the name of the function or data etc. you modified here:

>   rs6000-c.c (altivec_overloaded_builtins): Blabla.
> 
> or something like that.
> 
> > * config/rs6000/rs6000-builtin.def: Add definitions for NABS functions
> > and NABS overload.
> > * config/rs6000/altivec.md: Add define to expand nabs2 types
> > * config/rs6000/altivec.h: Add define for vec_nabs built-in function.
> > * doc/extend.texi: Update the built-in documentation file for the
> > new built-in functions.
> 
> Here, too.
> 
> > +  int i, n_elt = GET_MODE_NUNITS (mode);
> 
> Two lines for this please, two separate declarations.  I realise you just
> copied this code ;-)
--

gcc/ChangeLog:

2017-01-08  Carl Love  

* config/rs6000/rs6000-c (altivec_overloaded_builtins): Add support
for built-in functions
vector signed char vec_nabs (vector signed char)
vector signed short vec_nabs (vector signed short)
vector signed int vec_nabs (vector signed int)
vector signed long long vec_nabs (vector signed long long)
vector float vec_nabs (vector float)
vector double vec_nabs (vector double)
* config/rs6000/rs6000-builtin.def: Add definitions for NABS functions
and NABS overload.
* config/rs6000/altivec.md: Add define to expand nabs2 types
* config/rs6000/altivec.h: Add define for vec_nabs built-in function.
* doc/extend.texi (section 6.60.22 PowerPC AltiVec Built-in Functions):
Update the documentation file for the new built-in functions.

gcc/testsuite/ChangeLog:

2017-01-08  Carl Love  

* gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins
to the test suite file.
* gcc.target/powerpc/builtins-3-p8.c: Add tests for the new built-ins
to the test suite file.
---
 gcc/config/rs6000/altivec.h  |  1 +
 gcc/config/rs6000/altivec.md | 27 ++
 gcc/config/rs6000/rs6000-builtin.def |  9 +
 gcc/config/rs6000/rs6000-c.c | 12 ++
 gcc/doc/extend.texi  |  8 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 12 +-
 gcc/testsuite/gcc.target/powerpc/builtins-3.c| 47 +++-
 7 files changed, 114 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 73567ff..17bc33e 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -189,6 +189,7 @@
 #define vec_vupklsh __builtin_vec_vupklsh
 #define vec_vupklsb __builtin_vec_vupklsb
 #define vec_abs __builtin_vec_abs
+#define vec_nabs __builtin_vec_nabs
 #define vec_abss __builtin_vec_abss
 #define vec_add __builtin_vec_add
 #define vec_adds __builtin_vec_adds
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index c2063d5..2a26007 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2741,6 +2741,33 @@
 })
 
 ;; Generate
+;;vspltisw SCRATCH1,0
+;;vsubu?m SCRATCH2,SCRATCH1,%1
+;;vmins? %0,%1,SCRATCH2"
+(define_expand "nabs2"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4)
+(minus:VI2 (match_dup 2)
+  (match_operand:VI2 1 "register_operand" "v")))
+   (set (match_operand:VI2 0 "register_operand" "=v")
+(smin:VI2 (match_dup 1) (match_dup 4)))]
+  ""
+{
+  int i;
+  int n_elt = GET_MODE_NUNITS (mode);
+
+  rtvec v = rtvec_alloc (n_elt);
+
+  /* Create an all 0 constant.  */
+  for (i = 0; i < n_elt; ++i)
+RTVEC_ELT (v, i) = const0_rtx;
+
+  operands[2] = gen_reg_rtx (mode);
+  operands[3] = gen_rtx_CONST_VECTOR (mode, v);
+  operands[4] = gen_reg_rtx (mode);
+})
+
+;; Generate
 ;;vspltisw SCRATCH1,-1
 ;;vslw SCRATCH2,SCRATCH1,SCRATCH1
 ;;vandc %0,%1,SCRATCH2
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 2329c1f..1cdf9a8 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1129,6 +1129,14 @@ BU_ALTIVEC_A (ABSS_V4SI,  "abss_v4si",   SAT,
altivec_abss_v4si)
 BU_ALTIVEC_A (ABSS_V8HI,  "abss_v8hi", SAT,altivec_abss_v8hi)
 BU_ALTIVEC_A (ABSS_V16QI, "abss_v16qi",SAT,altivec_abss_v16qi)
 
+/* 

Re: [PATCH, rs6000] Add vec_nabs builtin support

[Carl E. Love]

Oops, accidentally  hit send.  Was trying to insert file.

On Mon, 2017-01-09 at 09:58 -0800, Carl E. Love wrote:
> GCC maintainers:
> 
> The following patch adds two more built-ins that are missing.
> Specifically:
> 
> vector signed char vec_nabs (vector signed char)
>   vector signed short vec_nabs (vector signed short)
>   vector signed int vec_nabs (vector signed int)
>   vector signed long long vec_nabs (vector signed long long)
>   vector float vec_nabs (vector float)
>   vector double vec_nabs (vector double)
>  
> 
> The patch has been boot strapped and tested on
> powerpc64le-unknown-linux-gnu (Power 8 LE) and on 
> powerpc64-unknown-linux-gnu (Power 8 BE 64-bit, 32-bit) and on 
> powerpc64-unknown-linux-gnu (Power 7 64-bit, 32-bit) with no
> regressions.
> 
> Is this OK for trunk?
> 
> Carl Love
> 
> 
> ---

gcc/ChangeLog:

2017-01-09  Carl Love  <c...@us.ibm.com>

* config/rs6000/rs6000-c: Add support for built-in functions
vector signed char vec_nabs (vector signed char)
vector signed short vec_nabs (vector signed short)
vector signed int vec_nabs (vector signed int)
vector signed long long vec_nabs (vector signed long long)
vector float vec_nabs (vector float)
vector double vec_nabs (vector double)
* config/rs6000/rs6000-builtin.def: Add definitions for NABS functions
and NABS overload.
* config/rs6000/altivec.md: Add define to expand nabs2 types
* config/rs6000/altivec.h: Add define for vec_nabs built-in function.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.

gcc/testsuite/ChangeLog:

2017-01-09  Carl Love  <c...@us.ibm.com>

* gcc.target/powerpc/builtins-3.c: Add tests for the new built-ins
to the test suite file.
* gcc.target/powerpc/builtins-3-p8.c: Add tests for the new built-ins
to the test suite file.
---
 gcc/config/rs6000/altivec.h  |  1 +
 gcc/config/rs6000/altivec.md | 25 +
 gcc/config/rs6000/rs6000-builtin.def |  9 +
 gcc/config/rs6000/rs6000-c.c | 12 ++
 gcc/doc/extend.texi  |  8 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 12 +-
 gcc/testsuite/gcc.target/powerpc/builtins-3.c| 47 +++-
 7 files changed, 112 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 73567ff..17bc33e 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -189,6 +189,7 @@
 #define vec_vupklsh __builtin_vec_vupklsh
 #define vec_vupklsb __builtin_vec_vupklsb
 #define vec_abs __builtin_vec_abs
+#define vec_nabs __builtin_vec_nabs
 #define vec_abss __builtin_vec_abss
 #define vec_add __builtin_vec_add
 #define vec_adds __builtin_vec_adds
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index c2063d5..2c8d20b 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2741,6 +2741,31 @@
 })
 
 ;; Generate
+;;vspltisw SCRATCH1,0
+;;vsubu?m SCRATCH2,SCRATCH1,%1
+;;vmins? %0,%1,SCRATCH2"
+(define_expand "nabs2"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4)
+(minus:VI2 (match_dup 2)
+  (match_operand:VI2 1 "register_operand" "v")))
+   (set (match_operand:VI2 0 "register_operand" "=v")
+(smin:VI2 (match_dup 1) (match_dup 4)))]
+  ""
+{
+  int i, n_elt = GET_MODE_NUNITS (mode);
+  rtvec v = rtvec_alloc (n_elt);
+
+  /* Create an all 0 constant.  */
+  for (i = 0; i < n_elt; ++i)
+RTVEC_ELT (v, i) = const0_rtx;
+
+  operands[2] = gen_reg_rtx (mode);
+  operands[3] = gen_rtx_CONST_VECTOR (mode, v);
+  operands[4] = gen_reg_rtx (mode);
+})
+
+;; Generate
 ;;vspltisw SCRATCH1,-1
 ;;vslw SCRATCH2,SCRATCH1,SCRATCH1
 ;;vandc %0,%1,SCRATCH2
diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index 2329c1f..1cdf9a8 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1129,6 +1129,14 @@ BU_ALTIVEC_A (ABSS_V4SI,  "abss_v4si",   SAT,
altivec_abss_v4si)
 BU_ALTIVEC_A (ABSS_V8HI,  "abss_v8hi", SAT,altivec_abss_v8hi)
 BU_ALTIVEC_A (ABSS_V16QI, "abss_v16qi",SAT,altivec_abss_v16qi)
 
+/* Altivec NABS functions.  */
+BU_ALTIVEC_A (NABS_V2DI,  "nabs_v2di", CONST,  nabsv2di2)
+BU_ALTIVEC_A (NABS_V4SI,  "nabs_v4si", CONST,  nabsv4si2)
+BU_ALTIVEC_A (NABS_V8HI,  "nabs_v8hi", CONST,  nabsv8hi2)
+BU_ALTIVEC_A (NABS_V16QI, 

[PATCH, rs6000] Add vec_nabs builtin support

[Carl E. Love]

GCC maintainers:

The following patch adds two more built-ins that are missing.
Specifically:

vector signed char vec_nabs (vector signed char)
vector signed short vec_nabs (vector signed short)
vector signed int vec_nabs (vector signed int)
vector signed long long vec_nabs (vector signed long long)
vector float vec_nabs (vector float)
vector double vec_nabs (vector double)
 

The patch has been boot strapped and tested on
powerpc64le-unknown-linux-gnu (Power 8 LE) and on 
powerpc64-unknown-linux-gnu (Power 8 BE 64-bit, 32-bit) and on 
powerpc64-unknown-linux-gnu (Power 7 64-bit, 32-bit) with no
regressions.

Is this OK for trunk?

Carl Love


---

Re: [PATCH, rs6000] Add support for vec_pack and vec_sld built-ins

[Carl E. Love]

On Thu, 2016-12-08 at 21:03 -0600, Segher Boessenkool wrote:
> On Thu, Dec 08, 2016 at 08:28:22AM -0800, Carl E. Love wrote:
> > The following patch adds two more built-ins that are missing.
> > Specifically:
> > 
> > vector floatvec_packvector doublevector double
> > vector double   vec_sld vector doublevector double
> > 
> > The patch has been boot strapped and tested on
> > powerpc64le-unknown-linux-gnu (Power 8) and on 
> > powerpc64-unknown-linux-gnu (Power 7) with no regressions.
> 
> > 2016-12-08  Carl Love  <c...@us.ibm.com>
> > 
> >* config/rs6000/rs6000-c.c: Add built-in support for
> >vector float  vec_pack  vector double  vector double
> >vector double  vec_sld  vector double  vector double
> 
> Add some parens and commas here?
> 
> >* config/rs6000/rs6000.c: Add icode check for vsldoi_v2df to allow
> >4-bit unsigned literal.
> >* config/rs6000/rs6000-builtin.def: Add definition for VSLDOI_2DF
> >* doc/extend.texi: Update the built-in documentation file for the
> >new powerpc vec_pack and vec_sld built-ins.
> 
> Okay for trunk with that.  Thanks,

Segher:

The patch has been committed with the requested changes to the ChangeLog
message.

Revision 243612 - Directory Listing
Modified Tue Dec 13 16:18:36 2016 UTC (77 seconds ago) by carll

gcc/ChangeLog:

2016-12-13  Carl Love  <c...@us.ibm.com>

   * config/rs6000/rs6000-c.c: Add built-in support for
   vector float vec_pack (vector double, vector double)
   vector double vec_sld (vector double, vector double)
   * config/rs6000/rs6000.c: Add icode check for vsldoi_v2df to allow
   4-bit unsigned literal.
   * config/rs6000/rs6000-builtin.def: Add definition for VSLDOI_2DF
   * doc/extend.texi: Update the built-in documentation file for the
   new powerpc vec_pack and vec_sld built-ins.

gcc/testsuite/ChangeLog:

2016-12-13 Carl Love  <c...@us.ibm.com>

* gcc.target/powerpc/builtins-3.c: Add new test of the test suite
file.
* gcc.target/powerpc/builtins-3-p8.c: Add new test of the test suite
file.


  Carl Love

[PATCH, rs6000] Add support for vec_pack and vec_sld built-ins

[Carl E. Love]

GCC maintainers:

The following patch adds two more built-ins that are missing.
Specifically:

vector floatvec_packvector doublevector double
vector double   vec_sld vector doublevector double

The patch has been boot strapped and tested on
powerpc64le-unknown-linux-gnu (Power 8) and on 
powerpc64-unknown-linux-gnu (Power 7) with no regressions.

Is this OK for trunk?

Carl Love

2016-12-08  Carl Love  

   * config/rs6000/rs6000-c.c: Add built-in support for
   vector float  vec_pack  vector double  vector double
   vector double  vec_sld  vector double  vector double
   * config/rs6000/rs6000.c: Add icode check for vsldoi_v2df to allow
   4-bit unsigned literal.
   * config/rs6000/rs6000-builtin.def: Add definition for VSLDOI_2DF
   * doc/extend.texi: Update the built-in documentation file for the
   new powerpc vec_pack and vec_sld built-ins.

gcc/testsuite/ChangeLog:

2016-12-08 Carl Love  

* gcc.target/powerpc/builtins-3.c: Add new test of the test suite
file.
* gcc.target/powerpc/builtins-3.c: Add new test of the test suite
file.
---
 gcc/config/rs6000/rs6000-builtin.def |  1 +
 gcc/config/rs6000/rs6000-c.c |  4 
 gcc/config/rs6000/rs6000.c   |  1 +
 gcc/doc/extend.texi  |  3 +++
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 10 +-
 gcc/testsuite/gcc.target/powerpc/builtins-3.c|  9 -
 6 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.def 
b/gcc/config/rs6000/rs6000-builtin.def
index d21f275..68f0936 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -958,6 +958,7 @@ BU_ALTIVEC_3 (VSLDOI_16QI,"vsldoi_16qi",CONST,  
altivec_vsldoi_v16qi)
 BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, 
altivec_vsldoi_v8hi)
 BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, 
altivec_vsldoi_v4si)
 BU_ALTIVEC_3 (VSLDOI_4SF, "vsldoi_4sf", CONST, 
altivec_vsldoi_v4sf)
+BU_ALTIVEC_3 (VSLDOI_2DF, "vsldoi_2df", CONST, 
altivec_vsldoi_v2df)
 
 /* Altivec DST builtins.  */
 BU_ALTIVEC_D (DST,   "dst",MISC,   altivec_dst)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 4f332d7..bf01a11 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2118,6 +2118,8 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, 
RS6000_BTI_unsigned_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
+  { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
+RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
@@ -3193,6 +3195,8 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 
RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 
RS6000_BTI_NOT_OPAQUE },
+  { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
+RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 59bd3fe..228a6e2 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15096,6 +15096,7 @@ rs6000_expand_ternop_builtin (enum insn_code icode, 
tree exp, rtx target)
  with identical values.  We'd never reach here at runtime in
  this case.  */
   if (icode == CODE_FOR_altivec_vsldoi_v4sf
+  || icode == CODE_FOR_altivec_vsldoi_v2df
   || icode == CODE_FOR_altivec_vsldoi_v4si
   || icode == CODE_FOR_altivec_vsldoi_v8hi
   || icode == CODE_FOR_altivec_vsldoi_v16qi)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index a8402e1..9477446 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -16513,6 +16513,8 @@ vector unsigned char vec_vslb (vector unsigned char,
vector unsigned char);
 
 vector float vec_sld (vector float, vector float, const int);
+vector double vec_sld (vector double, vector double, const int);
+
 vector signed int vec_sld (vector signed int,
vector signed int,
const int);
@@ -17745,6 +17747,7 @@ vector int vec_pack 

Re: [PATCH v3, rs6000] Add built-in support for vector compare listed in the ABI

[Carl E. Love]

On Tue, 2016-12-06 at 15:59 -0600, Segher Boessenkool wrote:
> On Tue, Dec 06, 2016 at 01:23:24PM -0800, Carl E. Love wrote:
> > Per the feedback I received on the first and second versions of the
> > patch I have created the following patch to modify the original commit
> > for the vector compare built-in support.  Specifically, the tests were
> > broken into files for the processors that supports them.  This allows
> > for specific control over specifying the effective targets and compiler
> > options.
> > 
> > The patch has been boot strapped and tested on
> > powerpc64le-unknown-linux-gnu (Power 8) and on 
> > powerpc64-unknown-linux-gnu (Power 7).  
> > 
> > 
> > Is this ok for trunk?
> 
> This looks good, please apply.  Thanks,
> 
> 
> Segher

Segher:

Thanks, patch applied


Revision 243370 - Directory Listing
Modified Wed Dec 7 16:21:16 2016 UTC (68 seconds ago) by carll

2016-12-07  Carl Love  <c...@us.ibm.com>

* gcc.target/powerpc/builtins-3.c: Move built-in tests for P8 and
P9 to their own test file.  This allows precise constraints on the
effective target and compile options.
* gcc.target/powerpc/builtins-3-p8.c: New file for the vector
compare P8 built-in tests.
* gcc.target/powerpc/builtins-3-p9.c: New file for the vector
compare P9 built-in tests.

[PATCH v3, rs6000] Add built-in support for vector compare listed in the ABI

[Carl E. Love]

GCC maintainers:

Per the feedback I received on the first and second versions of the
patch I have created the following patch to modify the original commit
for the vector compare built-in support.  Specifically, the tests were
broken into files for the processors that supports them.  This allows
for specific control over specifying the effective targets and compiler
options.

The patch has been boot strapped and tested on
powerpc64le-unknown-linux-gnu (Power 8) and on 
powerpc64-unknown-linux-gnu (Power 7).  


Is this ok for trunk?

 Carl Love

gcc/testsuite/ChangeLog:

2016-12-06  Carl Love  

* gcc.target/powerpc/builtins-3.c: Move built-in tests for P8 and
P9 to their own test file.  This allows precise constraints on the
effective target and compile options.
* gcc.target/powerpc/builtins-3-p8.c: New file for the vector
compare P8 built-in tests.
* gcc.target/powerpc/builtins-3-p9.c: New file for the vector
compare P9 built-in tests.
---
 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 17 
 gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c | 42 +++
 gcc/testsuite/gcc.target/powerpc/builtins-3.c| 51 
 3 files changed, 67 insertions(+), 43 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c

diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
new file mode 100644
index 000..e52795c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8" } */
+
+#include 
+
+vector bool long long
+test_eq_long_long (vector bool long long x, vector bool long long y)
+{
+   return vec_cmpeq (x, y);
+}
+
+/* Expected test results:
+
+ test_eq_long_long  1 vcmpequd inst */
+
+/* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
new file mode 100644
index 000..d846e29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9" } */
+
+#include 
+
+vector bool char
+test_ne_char (vector bool char x, vector bool char y)
+{
+   return vec_cmpne (x, y);
+}
+
+vector bool short
+test_ne_short (vector bool short x, vector bool short y)
+{
+   return vec_cmpne (x, y);
+}
+
+vector bool int
+test_ne_int (vector bool int x, vector bool int y)
+{
+   return vec_cmpne (x, y);
+}
+
+vector bool long
+test_ne_long (vector bool long x, vector bool long y)
+{
+   return vec_cmpne (x, y);
+}
+
+/* Expected test results:
+
+ test_ne_char  1 vcmpneb
+ test_ne_short 1 vcmpneh
+ test_ne_int   1 vcmpnew
+ test_ne_long  1 vcmpequd, 1 xxlnor inst */
+
+/* { dg-final { scan-assembler-times "vcmpneb"  1 } } */
+/* { dg-final { scan-assembler-times "vcmpneh"  1 } } */
+/* { dg-final { scan-assembler-times "vcmpnew"  1 } } */
+/* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor"   1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index 1a09654..1d243ce 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-options "-maltivec -mvsx" } */
 
 #include 
@@ -22,48 +22,13 @@ test_eq_int (vector bool int x, vector bool int y)
return vec_cmpeq (x, y);
 }
 
-vector bool long
-test_eq_long (vector bool long x, vector bool long y)
-{
-   return vec_cmpeq (x, y);
-}
-
-vector bool char
-test_ne_char (vector bool char x, vector bool char y)
-{
-   return vec_cmpne (x, y);
-}
-
-vector bool short
-test_ne_short (vector bool short x, vector bool short y)
-{
-   return vec_cmpne (x, y);
-}
-
-vector bool int
-test_ne_int (vector bool int x, vector bool int y)
-{
-   return vec_cmpne (x, y);
-}
-
-vector bool long
-test_ne_long (vector bool long x, vector bool long y)
-{
-   return vec_cmpne (x, y);
-}
 
-/* Note: vec_cmpne is implemented as vcmpeq and then NOT'ed
-   using the xxlnor instruction.
+/* Expected test results:
 
-   Expected test results:
-   test_eq_char  1 vcmpeq inst
-   test_eq_short 1 vcmpeq inst
-   test_eq_int   1 vcmpeq inst
-   test_eq_long  1 vcmpeq inst
-   test_ne_char  1 vcmpeq, 1 xxlnor inst
-   test_ne_short 1 vcmpeq, 

[PATCH v2, rs6000] Add built-in support for vector compare

[Carl E. Love]

Segher:

I realized over the weekend that I forgot to update the built-in documentation
file, doc/extend.texi.  I have updated the patch with these additions and fixed
the issues you mentioned before.

The Power ABI document lists a number of built-ins that it is supposed
to support.  There are still some missing.  This patch adds the built-in
support for the following built-ins:

vector bool char  vec_cmpeq vector bool char   vector bool char
vector bool int   vec_cmpeq vector bool intvector bool int
vector bool long long vec_cmpeq vector bool long long  vector bool long long
vector bool short vec_cmpeq vector bool short  vector bool short
vector bool char  vec_cmpne vector bool char   vector bool char
vector bool int   vec_cmpne vector bool intvector bool int
vector bool long long vec_cmpne vector bool long long  vector bool long long
vector bool short vec_cmpne vector bool short  vector bool short

Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. 

Is this ok for trunk?

Carl Love


gcc/ChangeLog:

2016-11-21  Carl Love  

* config/rs6000/rs6000-c.c: Add built-in support for vector compare
equal and vector compare not equal.  The vector compares take two
arguments of type vector bool char, vector bool short, vector bool int,
vector bool long long with the same return type.
* doc/extend.texi: Update built-in documentation file for the new
powerpc built-ins.

gcc/testsuite/ChangeLog:

2016-11-21  Carl Love  

* gcc.target/powerpc/builtins-3.c: New file to test the new
built-ins for vector compare equal and vector compare not equal.
---
 gcc/config/rs6000/rs6000-c.c  | 17 ++-
 gcc/doc/extend.texi   | 10 
 gcc/testsuite/gcc.target/powerpc/builtins-3.c | 68 +++
 3 files changed, 94 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3.c

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 4bba293..4f332d7 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1107,15 +1107,23 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 
RS6000_BTI_unsigned_V16QI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
+RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
+RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 
0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
+RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 
0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
+RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 
0 },
@@ -4486,6 +4494,9 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
 RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
+RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
+RS6000_BTI_bool_V16QI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
 RS6000_BTI_unsigned_V16QI, 0 },
 
@@ -4508,7 +4519,11 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
 RS6000_BTI_unsigned_V4SI, 0 },
-
+  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
+RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
+RS6000_BTI_bool_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED,
+RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEF,
 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPNE, 

[PATCH, rs6000] Add built-in support for vector compare listed in the ABI

[Carl E. Love]

GCC maintainers:

The Power ABI document lists a number of built-ins that it is supposed
to support.  There are still some missing.  This patch adds the built-in
support for the following built-ins:

vector bool char  vec_cmpeq vector bool char   vector bool char
vector bool int   vec_cmpeq vector bool intvector bool int
vector bool long long vec_cmpeq vector bool long long  vector bool long long
vector bool short vec_cmpeq vector bool short  vector bool short
vector bool char  vec_cmpne vector bool char   vector bool char
vector bool int   vec_cmpne vector bool intvector bool int
vector bool long long vec_cmpne vector bool long long  vector bool long long
vector bool short vec_cmpne vector bool short  vector bool short

Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. 

Is this ok for trunk?

 Carl Love

gcc/ChangeLog:

2016-11-15  Carl Love 

* config/rs6000/rs6000-c.c : Add built-in support for vector compare
equal and vector compare not equal.  The vector compares take two
arguments of type vector bool char, vector bool short, vector bool int,
vector bool long long with the same return type.

gcc/testsuite/ChangeLog:

2016-11-15  Carl Love 

* gcc.target/powerpc/builtins-3.c : New file to test the new
built-ins for vecotr compare equal and vector compare not equal.
---
 gcc/config/rs6000/rs6000-c.c  | 19 +++-
 gcc/testsuite/gcc.target/powerpc/builtins-3.c | 68 +++
 2 files changed, 85 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-3.c

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 4bba293..6566279 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1107,15 +1107,24 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 
RS6000_BTI_unsigned_V16QI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
+RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
+RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 
0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
+RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 
0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
+RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
+
+  { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 
0 },
@@ -4486,9 +4495,11 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
 RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
+RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
+RS6000_BTI_bool_V16QI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
 RS6000_BTI_unsigned_V16QI, 0 },
-
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
 RS6000_BTI_bool_V8HI, 0 },
@@ -4508,7 +4519,11 @@ const struct altivec_builtin_types 
altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
 RS6000_BTI_unsigned_V4SI, 0 },
-
+  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
+RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
+RS6000_BTI_bool_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED,
+RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEF,
 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED,
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c 
b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
new file mode 100644
index 000..8d4b63d
--- /dev/null
+++ 

Re: MAINTAINERS update

[Carl E. Love]

On Sat, 2016-10-29 at 12:10 -0500, Segher Boessenkool wrote:
Hi Carl,
> 
> On Fri, Oct 28, 2016 at 08:11:11AM -0700, Carl E. Love wrote:
> >  Manuel López-Ibáñez  <m...@gcc.gnu.org>
> >  Martin v. Löwis
<loe...@informatik.hu-berlin.de>
> >  H.J. Lu
<hjl.to...@gmail.com>
> > +Carl Love<c...@us.ibm.com>
> >  Christophe Lyon
<christophe.l...@st.com>
> >  Luis Machado <luis...@br.ibm.com>
> >  Ziga Mahkovec
<ziga.mahko...@klika.si>
> 
> That is not alphabetical...  Move it two up?
> 
> Segher

Seger:

Yup, it is in the wrong order.  I have updated the MAINTAINERS file and
the ChangeLog.

  Carl Love

-

Index: ChangeLog
===
--- ChangeLog   (revision 241702)
+++ ChangeLog   (working copy)
@@ -1,5 +1,10 @@
 2016-10-27  Carl Love  <c...@us.ibm.com>
 
+   * MAINTAINERS (Write After Approval): Fix my entry in the Write After
+   Approval list to make it alphabetical.
+
+2016-10-27  Carl Love  <c...@us.ibm.com>
+
* MAINTAINERS (Write After Approval): Add myself.
 
 2016-10-27  Andrew Burgess  <andrew.burg...@embecosm.com>
Index: MAINTAINERS
===
--- MAINTAINERS (revision 241702)
+++ MAINTAINERS (working copy)
@@ -477,9 +477,9 @@
 Gabor Loki <l...@inf.u-szeged.hu>
 Sandra Loosemore   <san...@codesourcery.com>
 Manuel López-Ibáñez<m...@gcc.gnu.org>
+Carl Love  <c...@us.ibm.com>
 Martin v. Löwis
<loe...@informatik.hu-berlin.de>
 H.J. Lu<hjl.to...@gmail.com>
-Carl Love  <c...@us.ibm.com>
 Christophe Lyon<christophe.l...@st.com>
 Luis Machado   <luis...@br.ibm.com>
 Ziga Mahkovec  <ziga.mahko...@klika.si>

Re: MAINTAINERS update

[Carl E. Love]

Hi, 

I added myself to the MAINTAINERS file (Write After Approval) on
10/27/2016.  The commit was r241636.

Sorry, forgot the patch the first time.
 
  Carl Love


Index: ChangeLog
===
--- ChangeLog   (revision 241636)
+++ ChangeLog   (working copy)
@@ -1,3 +1,7 @@
+2016-10-27  Carl Love  
+
+   * MAINTAINERS (Write After Approval): Add myself.
+
 2016-10-27  Andrew Burgess  
 
* MAINTAINERS (Reviewers): Add myself.
Index: MAINTAINERS
===
--- MAINTAINERS (revision 241636)
+++ MAINTAINERS (working copy)
@@ -479,6 +479,7 @@
 Manuel López-Ibáñez
 Martin v. Löwis

 H.J. Lu
+Carl Love  
 Christophe Lyon
 Luis Machado   
 Ziga Mahkovec  

MAINTAINERS update

[Carl E. Love]

Hi,

I added myself to the MAINTAINERS file (Write After Approval) on
10/27/2016.  The commit was r241636.

 Carl Love