[PATCH] RISC-V: Fix testcases renamed test flag options

[Edwin Lu]

Some testcases still had --param=riscv-autovec-preference=_,
update to use -mrvv-vector-bits=_. Also add missing period
in riscv.opt which caused a compiler driver error.

gcc/ChangeLog:

* config/riscv/riscv.opt: Add missing period

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/no-segment.c: Update dejagnu flags
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c: 
Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c: Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c:
  Ditto
* gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c:
  Ditto
---
 gcc/config/riscv/riscv.opt| 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c   | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c  | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c  | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c  | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c  | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c  | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c  | 2 +-
 .../riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c  | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c| 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c   | 4 ++--
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c   | 2 +-
 .../riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c| 2 +-
 

Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode switch

[Edwin Lu]

On 4/11/2024 5:45 AM, Li, Pan2 wrote:

Thanks for reporting this. Just take a look from my test log that 930623-1.c is 
all pass.

Thus I bet this difference comes from the build option --with-arch=rv32imac but 
my test script take rv64gcv.


I've built the git revision f3fdcf4a37a with
../gcc-trunk/configure --target=riscv-unknown-elf 
--prefix=/home/ed/gnu/riscv-unknown-elf --enable-languages=c,c++ 
--disable-multilib --with-arch=rv32imac --with-abi=ilp32



I am a bit surprised since the target is not supposed to support floating point
or vector instructions AFAIK.


Because you specify rv32imac, with doesn't include f/d/v extension, aka 
single/double floating point and vector extension. Thus, related functionality 
are disabled.


The issue does not happen with gcc-trunk from yesterday.


Ack, will look into it.

Pan
 

Hi Pan,

Our postcommit-ci found that it breaks for non-vector targets on rv32/64 
newlib/linux https://github.com/patrick-rivos/gcc-postcommit-ci/issues/757.


The patchwork precommit-ci also appeared to have flagged it 
https://github.com/ewlu/gcc-precommit-ci/issues/1417#issuecomment-2048846532


Edwin

Re: [gcc-13 backport Committed] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]

[Edwin Lu]

On 4/4/2024 7:40 AM, Palmer Dabbelt wrote:

On Thu, 04 Apr 2024 07:37:56 PDT (-0700), ja...@redhat.com wrote:

On Thu, Apr 04, 2024 at 07:28:40AM -0700, Palmer Dabbelt wrote:

I'm not sure if we need release maintainer approval,


For cherry-picking one's own non-risky bugfixes for regression or
documentation bugs from trunk to release branches no special approval
is needed, or maintainer of the corresponding code can approve that,
release manager approval is only needed when a branch is frozen before a
release.


Ya, I'm just never sure when the branch is frozen...


all I can find is the
13.2.1 status report saying 13.3 is expected in the spring
.  My 
allergies
certainly indicate it's spring, but that's kind of a wide time 
window...


Maybe Jakub knows?


Most likely some short time after 14.1 is released, so that one can 
still
cherry-pick whatever was fixed on the 14 branch and there is time for 
those

cherry-picks and testing.
https://gcc.gnu.org/releases.html#timeline gives some hints...


OK, so sounds like it's not frozen now and Edwin's OK to commit this 
on the 13 branch.  Thanks.




Jakub


Thanks for the clarifications! Committed!

Edwin

[gcc-13 backport PATCH] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]

[Edwin Lu]

We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and
there is nothing to advance, but that is not the case for (...) functions
returning by hidden reference which have one such artificial argument.
This causes gcc.dg/c23-stdarg-[68].c to fail

Fix the issue by checking if arg.type is NULL as r14-9503-g218d1749612
explains

Tested on linux rv64gcv.

gcc/ChangeLog:

PR target/114175
* config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
if arg.type is NULL

(cherry picked from commit 60586710b0646efdbbd77a7f53b93fb5edb87a61)
---
 gcc/config/riscv/riscv.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 01eebc83cc5..cefd3b7b2b2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3961,7 +3961,8 @@ riscv_setup_incoming_varargs (cumulative_args_t cum,
  argument.  Advance a local copy of CUM past the last "real" named
  argument, to find out how many registers are left over.  */
   local_cum = *get_cumulative_args (cum);
-  if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)))
+  if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
+  || arg.type != NULL_TREE)
 riscv_function_arg_advance (pack_cumulative_args (_cum), arg);
 
   /* Found out how many registers we need to save.  */
-- 
2.34.1

Re: [Committed] RISC-V: Update test expectancies with recent scheduler change

[Edwin Lu]

On 3/18/2024 8:14 PM, Jeff Law wrote:



On 3/12/24 3:56 PM, Edwin Lu wrote:

Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Disable 
scheduling

* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: Update test expectancies
* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
* gcc.target/riscv/rvv/base/vcreate.c: Disable scheduling and update
test expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Disable 
scheduling

* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Update test
expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
As we discussed last week.  This should go forward as it brings a 
better degree of stability to these tests.  Looking forward to cleaner 
testresults as my tester has been complaining about this stuff for a 
month now :(



And a note for the future.  Let's take this one:

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c

index 4c6e88e7eed..46d3b5e98d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -60,11 +60,11 @@ test_vbool1_then_vbool64(int8_t * restrict in, 
int8_t * restrict out) {

  }
    /* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 2 } } */
  /* { dg-final { scan-assembler-times 
{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
  /* { dg-final { scan-assembler-times 
{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */


This shows an example of how uarch information such as instruction 
latency will affect vset counts.  If someone wanted to test that 
pr108185-1 can drive the counts of each of those vsets to since 
instance, they can certainly #include pr108185-1 and provide suitable 
dg directives to set a specific uarch tuning and appropriate dg-final 
directives to ensure just a single instance of each vset occurs.


I'm not expecting you do to this.  Just making a note if someone 
really wants to use those tests to verify a specific set of vsets on a 
particular uarch.



Jeff


Committed!

Edwin

Re: [Committed] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]

[Edwin Lu]

On 3/18/2024 8:07 PM, Jeff Law wrote:



On 3/18/24 12:54 PM, Edwin Lu wrote:
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named 
arguments and
there is nothing to advance, but that is not the case for (...) 
functions

returning by hidden reference which have one such artificial argument.
This causes gcc.dg/c23-stdarg-[68].c to fail

Fix the issue by checking if arg.type is NULL as r14-9503-g218d1749612
explains

Tested on linux rv64gcv.

gcc/ChangeLog:

PR target/114175
* config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
if arg.type is NULL

OK.  Thanks for taking care of this.

Jeff


Committed!

Edwin

[PATCH] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]

[Edwin Lu]

We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and
there is nothing to advance, but that is not the case for (...) functions
returning by hidden reference which have one such artificial argument.
This causes gcc.dg/c23-stdarg-[68].c to fail

Fix the issue by checking if arg.type is NULL as r14-9503-g218d1749612
explains

Tested on linux rv64gcv.

gcc/ChangeLog:

PR target/114175
* config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
if arg.type is NULL
---
 gcc/config/riscv/riscv.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 680c4a728e9..1f5dc33796b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5378,7 +5378,8 @@ riscv_setup_incoming_varargs (cumulative_args_t cum,
  argument.  Advance a local copy of CUM past the last "real" named
  argument, to find out how many registers are left over.  */
   local_cum = *get_cumulative_args (cum);
-  if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl)))
+  if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))
+  || arg.type != NULL_TREE)
 riscv_function_arg_advance (pack_cumulative_args (_cum), arg);
 
   /* Found out how many registers we need to save.  */
-- 
2.34.1

[PATCH V2] RISC-V: Update test expectancies with recent scheduler change

[Edwin Lu]

Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Disable scheduling
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: Update test expectancies
* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
* gcc.target/riscv/rvv/base/vcreate.c: Disable scheduling and update
test expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Disable scheduling
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Update test
expectancies
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto

Signed-off-by: Edwin Lu 
---
V1: Change tests to scan for range of vsetvls instead of specific number

V2: Add -fno-schedule-insns and -fno-schedule-insns2 to testcases that
were missing them. Those that had disabled insn scheduling, update
testcases to match current outputs to pass tests
---
 .../vect/costmodel/riscv/rvv/dynamic-lmul4-6.c   |  1 +
 .../vect/costmodel/riscv/rvv/dynamic-lmul4-8.c   |  1 +
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c|  6 --
 .../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c |  1 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c |  1 +
 .../riscv/rvv/vsetvl/vlmax_single_block-17.c | 12 ++--
 .../riscv/rvv/vsetvl/vlmax_single_block-18.c |  6 +++---
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c  |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c  |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c  |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c  |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c  |  4 ++--
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c  |  4 ++--
 23 files changed, 75 insertions(+), 69 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index bd7ce23f6b8..b23acebc916 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling 
-fdump-tree-vect-details" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include 
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 61619a0c879..ef719ee8445 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling 
-fdump-tree-vect-details" } */
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 

[PATCH] middle-end: Fix dominator information with loop duplication PR114197

[Edwin Lu]

When adding the new_preheader to the cfg, only the new_preheader's dominator
information is updated. If one of the new basic block's children was part
of the original cfg and adding new_preheader to the cfg introduces another path
to that child, the child's dominator information will not be updated. This may
cause verify_dominator's assertion to fail.

Force recalculating dominators for all duplicated basic blocks and their
successors when updating new_preheader's dominator information.

PR 114197

gcc/ChangeLog:

* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
Recalculate dominator info when adding new_preheader to cfg

gcc/testsuite/ChangeLog:

* gcc.dg/vect/pr114197.c: New test.

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/gcc.dg/vect/pr114197.c | 18 ++
 gcc/tree-vect-loop-manip.cc  | 17 -
 2 files changed, 34 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.dg/vect/pr114197.c

diff --git a/gcc/testsuite/gcc.dg/vect/pr114197.c 
b/gcc/testsuite/gcc.dg/vect/pr114197.c
new file mode 100644
index 000..b1fb807729c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr114197.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O3" } */
+
+
+#pragma pack(push)
+struct a {
+  volatile signed b : 8;
+};
+#pragma pack(pop)
+int c;
+static struct a d = {5};
+void e() {
+f:
+  for (c = 8; c < 55; ++c)
+if (!d.b)
+  goto f;
+}
+
diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc
index f72da915103..0f3a489e78c 100644
--- a/gcc/tree-vect-loop-manip.cc
+++ b/gcc/tree-vect-loop-manip.cc
@@ -1840,7 +1840,22 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop 
*loop, edge loop_exit,
}
 
   if (was_imm_dom || duplicate_outer_loop)
-   set_immediate_dominator (CDI_DOMINATORS, exit_dest, new_exit->src);
+   {
+ set_immediate_dominator (CDI_DOMINATORS, exit_dest, new_exit->src);
+
+ /* Update the dominator info for children of duplicated bbs.  */
+ for (unsigned i = 0; i < scalar_loop->num_nodes; i++)
+   {
+ basic_block dom_bb = NULL;
+ edge e;
+ edge_iterator ei;
+ FOR_EACH_EDGE (e, ei, new_bbs[i]->succs)
+   {
+ dom_bb = recompute_dominator (CDI_DOMINATORS, e->dest);
+ set_immediate_dominator (CDI_DOMINATORS, e->dest, dom_bb);
+   }
+   }
+   }
 
   /* And remove the non-necessary forwarder again.  Keep the other
  one so we have a proper pre-header for the loop at the exit edge.  */
-- 
2.34.1

[PATCH] RISC-V: Update test expectancies with recent scheduler change

[Edwin Lu]

Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Bound testcase
assembly matching
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
* gcc.target/riscv/rvv/base/vcreate.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto

Signed-off-by: Edwin Lu 
---
 .../costmodel/riscv/rvv/dynamic-lmul4-6.c |  3 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-8.c |  3 +-
 .../gcc.target/riscv/rvv/base/pr108185-1.c| 25 +
 .../gcc.target/riscv/rvv/base/pr108185-2.c| 25 +
 .../gcc.target/riscv/rvv/base/pr108185-3.c| 25 +
 .../gcc.target/riscv/rvv/base/pr108185-4.c| 25 +
 .../gcc.target/riscv/rvv/base/pr108185-5.c| 25 +
 .../gcc.target/riscv/rvv/base/pr108185-6.c| 25 +
 .../gcc.target/riscv/rvv/base/pr108185-7.c| 25 +
 .../gcc.target/riscv/rvv/base/vcreate.c   | 13 +++--
 .../riscv/rvv/vsetvl/vlmax_back_prop-30.c |  8 --
 .../riscv/rvv/vsetvl/vlmax_back_prop-31.c |  8 --
 .../riscv/rvv/vsetvl/vlmax_single_block-17.c  | 28 ++-
 .../riscv/rvv/vsetvl/vlmax_single_block-18.c  | 14 --
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |  9 --
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |  3 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |  3 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |  8 --
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |  8 --
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |  8 --
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |  8 --
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |  8 --
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |  8 --
 23 files changed, 238 insertions(+), 77 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index d2766f5984c..1cb0888f9d8 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -20,7 +20,8 @@ foo (uint8_t *restrict a, uint8_t *restrict b, int n)
 }
 
 /* { dg-final { scan-assembler {e8,m4} } } */
-/* { dg-final { scan-assembler-times {csrr} 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} >= 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} <= 3 } } */
 /* Since we don't support VLA SLP for LMUL = 8, dynamic LMUL cost model start 
from LMUL = 4.  */
 /* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it 
has unexpected spills" "vect" } } */
 /* { dg-final { scan-tree-dump-not "Maximum lmul = 8" "vect" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 362c49f1411..0d644fc69bf 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -29,7 +29,8 @@ foo (uint8_t *restrict a, uint8_t *restrict b, int n)
 }
 
 /* { dg-final { scan-assembler {e8,m4} } } */
-/* { dg-final { scan-assembler-times {csrr} 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} >= 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} <= 3 } } */
 /* Since we don't support VLA SLP for LMUL = 8, dynamic LMUL cost model start 
from LMUL = 4.  */
 /* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it 
has unexpec

Re: [Committed V4 4/5] RISC-V: Quick and simple fixes to testcases that break due to reordering

[Edwin Lu]

On 2/21/2024 10:57 AM, Robin Dapp wrote:



For calling-convention-*.c, LGTM but one nit about change log. Take
**Update** here may make others not easy to learn what you did about
the file. You can say similar to "Rearrange and adjust the
asm-checker times" or likewise. Of course, you can refine the
changelog when commit.

* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: update




Yes, agreed,  changes LGTM but please refine the commit message
slightly.  The first letter should also be capitalized I believe.

The rest of the is already ACK'ed so I believe it's good to go now.
I didn't pay a lot of attention to the other commit messages.
In case they need refining you can do that still.



Thanks! I updated the changelogs and committed.

Edwin

Re: [Committed V2] RISC-V: Specify mtune and march for PR113742

[Edwin Lu]

Committed

Edwin

On 2/20/2024 5:36 PM, Kito Cheng wrote:

LGTM, thanks for fixing that issue :)

On Wed, Feb 21, 2024 at 6:03 AM Edwin Lu  wrote:

The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'

Specify '-march=rv64gc' with '-mtune=sifive-p600-series'

V1: https://gcc.gnu.org/pipermail/gcc-patches/2024-February/645609.html

 PR target/113742

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/pr113742.c: change mcpu to mtune and add march

Signed-off-by: Edwin Lu 
---
V1: use require-effective-target
V2: switch to specifying march and mtune
---
  gcc/testsuite/gcc.target/riscv/pr113742.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c 
b/gcc/testsuite/gcc.target/riscv/pr113742.c
index ab8934c2a8a..573afd6f0ad 100644
--- a/gcc/testsuite/gcc.target/riscv/pr113742.c
+++ b/gcc/testsuite/gcc.target/riscv/pr113742.c
@@ -1,4 +1,4 @@
-//* { dg-do compile } */
-/* { dg-options "-O2 -finstrument-functions -mabi=lp64d -mcpu=sifive-p670" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -finstrument-functions -march=rv64gc -mabi=lp64d 
-mtune=sifive-p600-series" } */

  void foo(void) {}
--
2.34.1

[PATCH V2] RISC-V: Specify mtune and march for PR113742

[Edwin Lu]

The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'

Specify '-march=rv64gc' with '-mtune=sifive-p600-series'

V1: https://gcc.gnu.org/pipermail/gcc-patches/2024-February/645609.html

PR target/113742

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr113742.c: change mcpu to mtune and add march

Signed-off-by: Edwin Lu 
---
V1: use require-effective-target
V2: switch to specifying march and mtune
---
 gcc/testsuite/gcc.target/riscv/pr113742.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c 
b/gcc/testsuite/gcc.target/riscv/pr113742.c
index ab8934c2a8a..573afd6f0ad 100644
--- a/gcc/testsuite/gcc.target/riscv/pr113742.c
+++ b/gcc/testsuite/gcc.target/riscv/pr113742.c
@@ -1,4 +1,4 @@
-//* { dg-do compile } */
-/* { dg-options "-O2 -finstrument-functions -mabi=lp64d -mcpu=sifive-p670" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -finstrument-functions -march=rv64gc -mabi=lp64d 
-mtune=sifive-p600-series" } */
 
 void foo(void) {}
-- 
2.34.1

Re: [Committed] testsuite: Add support for scanning assembly with comparitor

[Edwin Lu]

Thanks! Committed

Edwin

On 2/15/2024 9:27 AM, Mike Stump wrote:

On Feb 12, 2024, at 11:38 AM, Edwin Lu  wrote:

There is currently no support for matching at least x lines of assembly
(only scan-assembler-times). This patch would allow setting upper or lower
bounds.

Use case: using different scheduler descriptions and/or cost models will change
assembler output. Testing common functionality across tunes would require a
separate testcase per tune since each assembly output would be different. If we
know a base number of lines should appear across all tunes (i.e. testing return
values: we expect at minimum n stores into register x), we can lower-bound the
test to search for scan-assembler-bound {RE for storing into register x} >= n.
This avoids artificially inflating the scan-assembler-times expected count due
to the assembler choosing to perform extra stores into register x (using it as
a temporary register).

The testcase would be more robust to cpu/tune changes at the cost of not being
as granular towards specific cpu tuning.

I didn't see an Ok?  Just in case you forgot, yes, this is ok.

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

On 2/15/2024 1:25 AM, Li, Pan2 wrote:


Sorry for late reply due to holiday. I double-checked the 
calling-convernsion-*.c dump, it is safe to adjust the asm check to the number 
as you mentioned.


Hi Pan,

I hope you had a good holiday! I already changed the numbers and added a 
bit more checks and documentation to the calling-convention-*.c files in 
this patch 
https://gcc.gnu.org/pipermail/gcc-patches/2024-February/645638.html.


If you have the time, it'd be great if you can take a look at it.

Thanks!
Edwin

[PATCH V4 4/5] RISC-V: Quick and simple fixes to testcases that break due to reordering

[Edwin Lu]

The following test cases are easily fixed with small updates to the expected
assembly order. Additionally make calling-convention testcases more robust

PR target/113249

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: update
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: ditto
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: reorder assembly
* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: change expected vsetvl

Signed-off-by: Edwin Lu 
---
V1-3:
- Patch did not exist
V4: 
- New patch
- improve calling-convention testcases (calling-conventions)
- reorder expected function body assembly (binop/shift_vx_constraint)
- change expected value (avl_single)
---
 .../rvv/autovec/vls/calling-convention-1.c| 27 ---
 .../rvv/autovec/vls/calling-convention-2.c| 23 ++--
 .../rvv/autovec/vls/calling-convention-3.c| 18 -
 .../rvv/autovec/vls/calling-convention-4.c| 12 -
 .../rvv/autovec/vls/calling-convention-5.c| 22 ++-
 .../rvv/autovec/vls/calling-convention-6.c| 17 
 .../rvv/autovec/vls/calling-convention-7.c| 12 -
 .../riscv/rvv/base/binop_vx_constraint-12.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-16.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-17.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-19.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-21.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-23.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-25.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-27.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-29.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-31.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-33.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-35.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-4.c|  4 +--
 .../riscv/rvv/base/binop_vx_constraint-40.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-44.c   |  4 +--
 .../riscv/rvv/base/binop_vx_constraint-8.c|  4 +--
 .../riscv/rvv/base/shift_vx_constraint-1.c|  5 +---
 .../riscv/rvv/vsetvl/avl_single-107.c |  2 +-
 25 files changed, 140 insertions(+), 62 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
index 41e31c258f8..217885c2d67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
@@ -143,12 +143,33 @@ DEF_RET1_ARG9 (v1024qi)
 DEF_RET1_ARG9 (v2048qi)
 DEF_RET1_ARG9 (v4096qi)
 
+// RET1_ARG0 tests
 /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 9 } } */
+/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 
3 } } */
+
+// v1qi tests: return value (lbu) and function prologue (sb)
+// 1 lbu per test, argnum sb's when args > 1
 /* { dg-final { scan-assembler-times {lbu\s+a0,\s*[0-9]+\(sp\)} 8 } } */
-/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */
-/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */
-/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 35 } } */
 /* { dg-final { scan-assembler-times {sb\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */
+
+// v2qi test: return value (lhu) and function prologue (sh)
+// 1 lhu per test, argnum sh's when args > 1
+/* { dg-final { scan-assembler-times {lh

[PATCH V4 3/5] RISC-V: Use default cost model for insn scheduling

[Edwin Lu]

Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series.

PR target/113249

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/bug-1.C: use default scheduling
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: ditto
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: ditto
* gcc.target/riscv/rvv/base/pr108185-2.c: ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto

Signed-off-by: Edwin Lu 
---
V2: 
- New patch
V3/V4:
- No change
---
 gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-12.c  | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-16.c  | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-17.c  | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-19.c  | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-21.c

[PATCH V4 2/5] RISC-V: Add vector related pipelines

[Edwin Lu]

Creates new generic vector pipeline file common to all cpu tunes.
Moves all vector related pipelines from generic-ooo to generic-vector-ooo.
Creates new vector crypto related insn reservations.

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo): Move reservation
(generic_ooo_vec_load): ditto
(generic_ooo_vec_store): ditto
(generic_ooo_vec_loadstore_seg): ditto
(generic_ooo_vec_alu): ditto
(generic_ooo_vec_fcmp): ditto
(generic_ooo_vec_imul): ditto
(generic_ooo_vec_fadd): ditto
(generic_ooo_vec_fmul): ditto
(generic_ooo_crypto): ditto
(generic_ooo_perm): ditto
(generic_ooo_vec_reduction): ditto
(generic_ooo_vec_ordered_reduction): ditto
(generic_ooo_vec_idiv): ditto
(generic_ooo_vec_float_divsqrt): ditto
(generic_ooo_vec_mask): ditto
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_setrm): ditto
(generic_ooo_vec_readlen): ditto
* config/riscv/riscv.md: include generic-vector-ooo
* config/riscv/generic-vector-ooo.md: New file. to here

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 
---
V2:
- Remove unnecessary syntax changes in generic-ooo
- Add new vector crypto reservations and types to
  pipelines
V3:
- Move all vector pipelines into separate file which defines all ooo vector
  reservations.
- Add temporary attribute while cost model changes.
V4:
- No change
---
 gcc/config/riscv/generic-ooo.md| 127 +-
 gcc/config/riscv/generic-vector-ooo.md | 143 +
 gcc/config/riscv/riscv.md  |   1 +
 3 files changed, 145 insertions(+), 126 deletions(-)
 create mode 100644 gcc/config/riscv/generic-vector-ooo.md

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 83cd06234b3..e70df63d91f 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -1,5 +1,5 @@
 ;; RISC-V generic out-of-order core scheduling model.
-;; Copyright (C) 2017-2024 Free Software Foundation, Inc.
+;; Copyright (C) 2023-2024 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -48,9 +48,6 @@ (define_automaton "generic_ooo")
 ;; Integer/float issue queues.
 (define_cpu_unit "issue0,issue1,issue2,issue3,issue4" "generic_ooo")
 
-;; Separate issue queue for vector instructions.
-(define_cpu_unit "generic_ooo_vxu_issue" "generic_ooo")
-
 ;; Integer/float execution units.
 (define_cpu_unit "ixu0,ixu1,ixu2,ixu3" "generic_ooo")
 (define_cpu_unit "fxu0,fxu1" "generic_ooo")
@@ -58,12 +55,6 @@ (define_cpu_unit "fxu0,fxu1" "generic_ooo")
 ;; Integer subunit for division.
 (define_cpu_unit "generic_ooo_div" "generic_ooo")
 
-;; Vector execution unit.
-(define_cpu_unit "generic_ooo_vxu_alu" "generic_ooo")
-
-;; Vector subunit that does mult/div/sqrt.
-(define_cpu_unit "generic_ooo_vxu_multicycle" "generic_ooo")
-
 ;; Shortcuts
 (define_reservation "generic_ooo_issue" "issue0|issue1|issue2|issue3|issue4")
 (define_reservation "generic_ooo_ixu_alu" "ixu0|ixu1|ixu2|ixu3")
@@ -92,25 +83,6 @@ (define_insn_reservation "generic_ooo_float_store" 6
(eq_attr "type" "fpstore"))
   "generic_ooo_issue,generic_ooo_fxu")
 
-;; Vector load/store
-(define_insn_reservation "generic_ooo_vec_load" 6
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-(define_insn_reservation "generic_ooo_vec_store" 6
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector segment loads/stores.
-(define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
-   vssegte,vssegts,vssegtux,vssegtox"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-
 ;; Generic integer instructions.
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
@@ -191,103 +163,6 @@ (define_insn_reservation "generic_ooo_popcount" 2
(eq_attr "type" "cpop,clmul"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
-;; Regular vector operations and integer comparisons.
-(define_insn_reservation "generic_ooo_vec_alu" 3
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" 
"via

[PATCH V4 5/5] RISC-V: Enable assert for insn_has_dfa_reservation

[Edwin Lu]

Enables assert that every typed instruction is associated with a
dfa reservation

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

Signed-off-by: Edwin Lu 
---
V2:
- No changes
V3: 
- Remove debug statements
V4: 
- no changes
---
 gcc/config/riscv/riscv.cc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4100abc9dd1..5e984ee2a55 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8269,9 +8269,7 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, 
int more)
 
   /* If we ever encounter an insn without an insn reservation, trip
  an assert so we can find and fix this problem.  */
-#if 0
   gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
 
   return more - 1;
 }
-- 
2.34.1

[PATCH V4 1/5] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

This patch adds non-vector related insn reservations and updates/creates
new insn reservations so all non-vector typed instructions have a reservation.

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
(generic_ooo_branch): ditto
* config/riscv/generic.md (generic_sfb_alu): ditto
(generic_fmul_half): ditto
* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
* config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
(sifive_7_popcount): ditto
* config/riscv/sifive-p400.md (sifive_p400_clmul): ditto
* config/riscv/sifive-p600.md (sifive_p600_clmul): ditto
* config/riscv/vector.md: change rdfrm to fmove
* config/riscv/zc.md: change pushpop to load/store

Signed-off-by: Edwin Lu 
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
V3:
- No changes
V4:
- Update sifive-p400 and sifive-p600 series
---
 gcc/config/riscv/generic-ooo.md | 15 +-
 gcc/config/riscv/generic.md | 20 +--
 gcc/config/riscv/riscv.md   | 16 +++---
 gcc/config/riscv/sifive-7.md| 17 +-
 gcc/config/riscv/sifive-p400.md | 10 +++-
 gcc/config/riscv/sifive-p600.md | 10 +++-
 gcc/config/riscv/vector.md  |  2 +-
 gcc/config/riscv/zc.md  | 96 -
 8 files changed, 117 insertions(+), 69 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index a22f8a3e079..83cd06234b3 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
-   move,bitmanip,min,max,minu,maxu,clz,ctz"))
+   move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
+   condmove,mvpair,zicond"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
+(define_insn_reservation "generic_ooo_sfb_alu" 2
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "sfb_alu"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
+
+;; Branch instructions
+(define_insn_reservation "generic_ooo_branch" 1
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
 
 ;; Float move, convert and compare.
 (define_insn_reservation "generic_ooo_float_move" 3
@@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_popcount" 2
 (define_insn_reservation "generic_ooo_vec_alu" 3
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov"))
+   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float comparison, conversion etc.
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index 3f0eaa2ea08..4f6e63bff57 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,9 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+   (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
+   move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\
+   condmove,crypto,mvpair,zicond"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
@@ -47,12 +49,17 @@ (define_insn_reservation "generic_xfer" 3
 
 (define_insn_reservation "generic_branch" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "branch,jump,call,jalr"))
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "alu")
+
+(define_insn_reservation "generic_sfb_alu" 2
+  (and (eq_attr "tune" "generic")
+   (eq_attr "type" "sfb_alu"))
   "alu")
 
 (define_insn_reservation "generic_imul" 10
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "imul,clmul"))
+   (eq_attr "type" "imul,clmul,cpop"))
   "imuldiv*10")
 
 (define_insn_reservation "generic_idivsi&qu

[PATCH V4 0/5] RISC-V: Associate typed insns to dfa reservation

[Edwin Lu]

Previous version (V3 23cd2961bd2ff63583f46e3499a07bd54491d45c) was reverted. 

Updates all tune insn reservation pipelines to cover all types defined by
define_attr "type" in riscv.md.

Creates new vector insn reservation pipelines in new file generic-vector-ooo.md
which has separate automaton vector_ooo where all reservations are mapped to.
This allows all tunes to share a common vector model for now as we make 
large changes to the vector cost model. 
(https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642511.html)

Disables pipeline scheduling for some tests with scan dump failures when using
-mtune=generic-ooo. 

Updates test cases that were failing due to simple insn reordering to match new
code generation

Enables assert that all insn types must be associated with a dfa pipeline
reservation

---
V2:
- Update non-vector insn types and add new pipelines
- Add -fno-schedule-insn -fno-schedule-insn2 to some test cases

V3:
- Separate vector pipelines to separate file which all tunes have access to

V4:
- Add insn reservations to sifive-p400 and sifive-p600 series
- Update test cases with new code generation
---

Edwin Lu (5):
  RISC-V: Add non-vector types to dfa pipelines
  RISC-V: Add vector related pipelines
  RISC-V: Use default cost model for insn scheduling
  RISC-V: Quick and simple fixes to testcases that break due to
reordering
  RISC-V: Enable assert for insn_has_dfa_reservation

 gcc/config/riscv/generic-ooo.md   | 140 ++---
 gcc/config/riscv/generic-vector-ooo.md| 143 ++
 gcc/config/riscv/generic.md   |  20 ++-
 gcc/config/riscv/riscv.cc |   2 -
 gcc/config/riscv/riscv.md |  17 +--
 gcc/config/riscv/sifive-7.md  |  17 ++-
 gcc/config/riscv/sifive-p400.md   |  10 +-
 gcc/config/riscv/sifive-p600.md   |  10 +-
 gcc/config/riscv/vector.md|   2 +-
 gcc/config/riscv/zc.md|  96 ++--
 .../g++.target/riscv/rvv/base/bug-1.C |   2 +
 .../riscv/rvv/autovec/reduc/reduc_call-2.c|   2 +
 .../rvv/autovec/vls/calling-convention-1.c|  27 +++-
 .../rvv/autovec/vls/calling-convention-2.c|  23 ++-
 .../rvv/autovec/vls/calling-convention-3.c|  18 ++-
 .../rvv/autovec/vls/calling-convention-4.c|  12 +-
 .../rvv/autovec/vls/calling-convention-5.c|  22 ++-
 .../rvv/autovec/vls/calling-convention-6.c|  17 +++
 .../rvv/autovec/vls/calling-convention-7.c|  12 +-
 .../riscv/rvv/base/binop_vx_constraint-102.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-108.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-114.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-119.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-12.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-16.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-17.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-19.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-21.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-23.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-25.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-27.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-29.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-31.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-33.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-35.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-4.c|   2 +-
 .../riscv/rvv/base/binop_vx_constraint-40.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-44.c   |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-50.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-56.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-62.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-68.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-74.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-79.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-8.c|   2 +-
 .../riscv/rvv/base/binop_vx_constraint-84.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-90.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-96.c   |   2 +
 .../rvv/base/float-point-dynamic-frm-30.c |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-1.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-2.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-3.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-4.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-5.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-6.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-7.c|   2 +
 .../riscv/rvv/base/shift_vx_constraint-1.c|   3 +-
 .../riscv/rvv/vsetvl/avl_single-107.c |   2 +-
 .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-29.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-32.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-33.c |   2 +
 .../riscv/

Re: [PATCH] RISC-V: Set require-effective-target rv64 for PR113742

[Edwin Lu]

On 2/14/2024 12:09 PM, Robin Dapp wrote:

On 2/14/24 20:46, Edwin Lu wrote:

The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'

I think we usually just add exactly this to the test options (so
it is always run rather than just on a 64-bit target.

Regards
  Robin


Ah oops I glanced over the /* { dg-do compile } */part. It should be 
fine to add '-march=rv64gc' instead then?


Edwin

[PATCH] RISC-V: Set require-effective-target rv64 for PR113742

[Edwin Lu]

The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'

Disable testing on rv32 targets

PR target/113742

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr113742.c: add require-effective-target

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/gcc.target/riscv/pr113742.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c 
b/gcc/testsuite/gcc.target/riscv/pr113742.c
index ab8934c2a8a..9cea92ed97c 100644
--- a/gcc/testsuite/gcc.target/riscv/pr113742.c
+++ b/gcc/testsuite/gcc.target/riscv/pr113742.c
@@ -1,4 +1,5 @@
 //* { dg-do compile } */
 /* { dg-options "-O2 -finstrument-functions -mabi=lp64d -mcpu=sifive-p670" } */
+/* { dg-require-effective-target rv64 } */
 
 void foo(void) {}
-- 
2.34.1

[PATCH] testsuite: Add support for scanning assembly with comparitor

[Edwin Lu]

There is currently no support for matching at least x lines of assembly
(only scan-assembler-times). This patch would allow setting upper or lower
bounds.

Use case: using different scheduler descriptions and/or cost models will change
assembler output. Testing common functionality across tunes would require a
separate testcase per tune since each assembly output would be different. If we
know a base number of lines should appear across all tunes (i.e. testing return
values: we expect at minimum n stores into register x), we can lower-bound the
test to search for scan-assembler-bound {RE for storing into register x} >= n.
This avoids artificially inflating the scan-assembler-times expected count due
to the assembler choosing to perform extra stores into register x (using it as
a temporary register).

The testcase would be more robust to cpu/tune changes at the cost of not being
as granular towards specific cpu tuning.

gcc/ChangeLog:

* doc/sourcebuild.texi: add scan-assembler-bound

gcc/testsuite/ChangeLog:

* lib/scanasm.exp: add scan-assembler-bound

Signed-off-by: Edwin Lu 
---
 gcc/doc/sourcebuild.texi  |  4 +++
 gcc/testsuite/lib/scanasm.exp | 64 +++
 2 files changed, 68 insertions(+)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 193be19767f..4a8c672c9fd 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -3396,6 +3396,10 @@ excluding LTO sections.
 Passes if @var{regex} is matched exactly @var{num} times in the test's
 assembler output, excluding LTO sections.
 
+@item scan-assembler-bound @var{regex} @var{cmp} @var{num} [@{ target/xfail 
@var{selector} @}]
+Passes if @var{regex} is matched @var{cmp} @var{num} times in the test's
+assembler output, excluding LTO sections. @var{cmp} is a comparitor.
+
 @item scan-assembler-dem @var{regex} [@{ target/xfail @var{selector} @}]
 Passes if @var{regex} matches text in the test's demangled assembler output,
 excluding LTO sections.
diff --git a/gcc/testsuite/lib/scanasm.exp b/gcc/testsuite/lib/scanasm.exp
index 165890eb976..741a5a048b8 100644
--- a/gcc/testsuite/lib/scanasm.exp
+++ b/gcc/testsuite/lib/scanasm.exp
@@ -516,6 +516,70 @@ proc scan-assembler-times { args } {
 
 set_required_options_for scan-assembler-times
 
+# Call pass if pattern is present within a lower or upper bound, 
+# otherwise fail.
+# ex /* { dg-final { scan-assembler-bound {RE} > 3 } }
+proc scan-assembler-bound { args } {
+if { [llength $args] < 3 } {
+   error "scan-assembler-bound: too few arguments"
+return
+}
+if { [llength $args] > 4 } {
+   error "scan-assembler-bound: too many arguments"
+   return
+}
+if { [llength $args] >= 4 } {
+   switch [dg-process-target [lindex $args 3]] {
+   "S" { }
+   "N" { return }
+   "F" { setup_xfail "*-*-*" }
+   "P" { }
+   }
+}
+
+set testcase [testname-for-summary]
+# The name might include a list of options; extract the file name.
+set filename [lindex $testcase 0]
+set pattern [lindex $args 0]
+set cmp [lindex $args 1]
+set bound [lindex $args 2]
+set pp_pattern [make_pattern_printable $pattern]
+
+# This must match the rule in gcc-dg.exp.
+set output_file "[file rootname [file tail $filename]].s"
+
+set files [glob -nocomplain $output_file]
+if { $files == "" } {
+   verbose -log "$testcase: output file does not exist"
+   unresolved "$testcase scan-assembler-bound $pp_pattern $min $max"
+   return
+}
+
+if { [lsearch { < > <= >= } $cmp] == -1 } {
+error "scan-assembler-bound: illegal argument: $cmp"
+return
+}
+if ![string is integer $bound ] {
+error "scan-assembler-bound: illegal argument: $bound"
+return
+}
+
+set fd [open $output_file r]
+set text [read $fd]
+close $fd
+regsub -all 
{(^|\n)[[:space:]]*\.section[[:space:]]*"?\.gnu\.lto_(?:[^\n]*\n(?![[:space:]]*\.(section|text|data|bss)))*[^\n]*\n}
 $text {\1} text
+
+set result_count [regexp -all -- $pattern $text]
+if [expr $result_count $cmp $bound] {
+   pass "$testcase scan-assembler-bound $pp_pattern $cmp $bound"
+} else {
+   verbose -log "$testcase: $pp_pattern found $result_count times"
+   fail "$testcase scan-assembler-bound $pp_pattern $cmp $bound"
+}
+}
+
+set_required_options_for scan-assembler-bound
+
 # Utility for scanning demangled compiler result, invoked via dg-final.
 # Call pass if pattern is present, otherwise fail.
 proc scan-assembler-dem { args } {
-- 
2.34.1

Re: [Committed] RISC-V: Fix rvv intrinsic pragma tests dejagnu selector

[Edwin Lu]

Committed

On 1/30/2024 9:51 AM, Palmer Dabbelt wrote:

On Mon, 29 Jan 2024 11:38:12 PST (-0800), e...@rivosinc.com wrote:

Adding rvv related flags (i.e. --param=riscv-autovec-preference) to
non vector targets bypassed the dejagnu skip test directive. Change the
target selector to skip if rvv is enabled

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/abi-1.c: change selector
* gcc.target/riscv/rvv/base/pragma-2.c: ditto
* gcc.target/riscv/rvv/base/pragma-3.c: ditto

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c    | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c

index 2eef9e1e1a8..a072bdd47bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! riscv_xtheadvector } } } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { 
"-march=rv*v*" } } */

+/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } } */

 void foo0 () {__rvv_bool64_t t;}
 void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c

index fd2aa3066cd..fc1bb13c53d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { 
"-march=rv*v*" } } */

+/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } } */

 #pragma riscv intrinsic "vector"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c

index 96a0e051a29..45580bb2faa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { 
"-march=rv*v*" } } */

+/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } */

 #pragma riscv intrinsic "report-error" /* { dg-error {unknown 
'#pragma riscv intrinsic' option 'report-error'} } */


Reviewed-by: Palmer Dabbelt 

[PATCH] RISC-V: Add support for B standard extension

[Edwin Lu]

This patch adds support for recognizing the B standard extension to be the
collection of Zba, Zbb, Zbs extensions for consistency and conciseness across
toolchains

* https://github.com/riscv/riscv-b/tags

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add imply rules for B extension
* config/riscv/arch-canonicalize: ditto

Signed-off-by: Edwin Lu 
---
 gcc/common/config/riscv/riscv-common.cc | 7 +++
 gcc/config/riscv/arch-canonicalize  | 1 +
 2 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 631ce8309a0..31117a7b0fd 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -77,6 +77,10 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"f", "zicsr"},
   {"d", "zicsr"},
 
+  {"b", "zba"},
+  {"b", "zbb"},
+  {"b", "zbs"},
+
   {"zdinx", "zfinx"},
   {"zfinx", "zicsr"},
   {"zdinx", "zicsr"},
@@ -235,6 +239,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"c", ISA_SPEC_CLASS_20190608, 2, 0},
   {"c", ISA_SPEC_CLASS_2P2,  2, 0},
 
+  {"b",   ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"h",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"v",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -388,6 +394,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 /* Combine extensions defined in this table  */
 static const struct riscv_ext_version riscv_combine_info[] =
 {
+  {"b",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zk",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkn",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zks",  ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index 629bed85347..dcfae732714 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -41,6 +41,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 IMPLIED_EXT = {
   "d" : ["f", "zicsr"],
   "f" : ["zicsr"],
+  "b" : ["zba", "zbb", "zbs"],
   "zdinx" : ["zfinx", "zicsr"],
   "zfinx" : ["zicsr"],
   "zhinx" : ["zhinxmin", "zfinx", "zicsr"],
-- 
2.34.1

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

On 2/2/2024 11:10 PM, Li, Pan2 wrote:

Hi Edwin


I believe the only problematic failures are the 5 vls calling convention
ones where only 24 ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) are found.


Does this "only 24" comes from calling-convention-1.c?


Oops sorry about that. I said I would include all the 7 failures and 
ended up not doing that. The failures are here
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 35
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 33
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 31
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 29
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 29


These all have the problem of only 24 ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 
being found. So that is calling-conventions 1, 2, 3, 4, 7 with only 24 
matching RE.


FAIL: gcc.target/riscv/rvv/base/vcreate.c scan-assembler-times 
vmv1r.v\\s+v[0-9]+,\\s*v[0-9]+ 24 <-- found 36 times
FAIL: gcc.target/riscv/rvv/base/vcreate.c scan-assembler-times 
vmv2r.v\\s+v[0-9]+,\\s*v[0-9]+ 12 <-- found 28 times
FAIL: gcc.target/riscv/rvv/base/vcreate.c scan-assembler-times 
vmv4r.v\\s+v[0-9]+,\\s*v[0-9]+ 16 <-- found 19 times


These find more vmv's than expected

FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-107.c   -O2 
scan-assembler-times vsetvli\\tzero,zero,e32,m1,t[au],m[au] 1 <-- found 
0 times
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-107.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none   scan-assembler-times 
vsetvli\\tzero,zero,e32,m1,t[au],m[au] 1 <-- found 0 times
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-107.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times 
vsetvli\\tzero,zero,e32,m1,t[au],m[au] 1 <-- found 0 times


These failures are from vsetvli zero,a0,e2,m1,ta,ma being found instead. 
I believe these should be fine.





This is what I'm getting locally (first instance of wrong match):
v32qi_RET1_ARG8:
.LFB109:


V32qi will pass the args by reference instead of GPR(s), thus It is expected. I 
think we need to diff the asm code before and after the patch for the whole 
test-file.
The RE "ld\\s+a[0-1],\\s*[0-9]+\\(sp\\)" would like to check vls mode values 
are returned by a[0-1].



I've been using this https://godbolt.org/z/vdxTY3rc7 (calling convention 
1) as my comparison to what I have compiled locally (included as 
attachment). From what I see, the differences, aside from reordering due 
to latency, are that the ld insns use a5 (for 32-512) or t4 (for 
1024-2048) or t5 (for 4096) for ARG8 and ARG9. Is there something else 
that I might be missing?


Edwin

.file   "calling-convention-1.c"
.option nopic
.attribute arch, 
"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.align  1
.globl  v1qi_RET1_ARG0
.type   v1qi_RET1_ARG0, @function
v1qi_RET1_ARG0:
.LFB0:
.cfi_startproc
li  a0,0
ret
.cfi_endproc
.LFE0:
.size   v1qi_RET1_ARG0, .-v1qi_RET1_ARG0
.align  1
.globl  v2qi_RET1_ARG0
.type   v2qi_RET1_ARG0, @function
v2qi_RET1_ARG0:
.LFB1:
.cfi_startproc
li  a0,0
ret
.cfi_endproc
.LFE1:
.size   v2qi_RET1_ARG0, .-v2qi_RET1_ARG0
.align  1
.globl  v4qi_RET1_ARG0
.type   v4qi_RET1_ARG0, @function
v4qi_RET1_ARG0:
.LFB2:
.cfi_startproc
li  a0,0
ret
.cfi_endproc
.LFE2:
.size   v4qi_RET1_ARG0, .-v4qi_RET1_ARG0
.align  1
.globl  v8qi_RET1_ARG0
.type   v8qi_RET1_ARG0, @function
v8qi_RET1_ARG0:
.LFB3:
.cfi_startproc
li  a0,0
ret
.cfi_endproc
.LFE3:
.size   v8qi_RET1_ARG0, .-v8qi_RET1_ARG0
.align  1
.globl  v16qi_RET1_ARG0
.type   v16qi_RET1_ARG0, @function
v16qi_RET1_ARG0:
.LFB4:
.cfi_startproc
li  a0,0
li  a1,0
ret
.cfi_endproc
.LFE4:
.size   v16qi_RET1_ARG0, .-v16qi_RET1_ARG0
.align  1
.globl  v32qi_RET1_ARG0
.type   v32qi_RET1_ARG0, @function
v32qi_RET1_ARG0:
.LFB5:
.cfi_startproc

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

On 2/1/2024 8:28 PM, Li, Pan2 wrote:

Hi Edwin,

Just rerun the newlib and there is no ICE but still 160 dump failures as below.

Pan



Hi Pan,

Thanks for confirming! Having dump failures is expected. There are 
around 7 more unique failures than I expected 
(https://github.com/patrick-rivos/gcc-postcommit-ci/issues/473 <-- 
postcommit found 46 while I expected 39 
https://inbox.sourceware.org/gcc-patches/12d205cd-3177-48ea-a54e-c2052fdde...@gmail.com/ 
https://github.com/ewlu/gcc-precommit-ci/issues/1178#issuecomment-1889782987) 



I included the 7 failed tests below and what was found instead.

I believe the only problematic failures are the 5 vls calling convention 
ones where only 24 ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) are found.


FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 35
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 33
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 31
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 29
FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c -O3 
-ftree-vectorize --param riscv-autovec-preference=scalable 
scan-assembler-times ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) 29


This is what I'm getting locally (first instance of wrong match):
v32qi_RET1_ARG8:
.LFB109:
.cfi_startproc
li  t1,32
vsetvli zero,t1,e8,mf8,ta,ma
vle8.v  v1,0(a1)
vle8.v  v4,0(a2)
vle8.v  v3,0(a3)
vle8.v  v2,0(a4)
vadd.vv v1,v1,v4
vadd.vv v1,v1,v3
vle8.v  v3,0(a5)
ld  a5,0(sp)  <-- used a5 instead of a1
vadd.vv v1,v1,v2
vle8.v  v2,0(a6)
vadd.vv v1,v1,v3
vle8.v  v3,0(a7)
vadd.vv v1,v1,v2
vle8.v  v2,0(a5)
vadd.vv v1,v1,v3
vadd.vv v1,v1,v2
vse8.v  v1,0(a0)
ret
.cfi_endproc

If I understand correctly, this is wrong since we aren't returning 
anything (nothing gets stored in a[0-1])?


Edwin

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

On 1/31/2024 11:05 PM, juzhe.zh...@rivai.ai wrote:
Sorry again. I just realized you have reverted your patches that's why I 
can pass the testing now.


I checkout your latest patch commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c>

Then I can reproduce the ICE now:

bug.c: In function 'popcount32_uint64_tuint64_t':
bug.c:20:3: internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972

    20 |   }
       |   ^
bug.c:123:3: note: in expansion of macro 'DEF32'
   123 |   DEF32 (uint64_t, uint64_t)   
                 \

       |   ^
bug.c:444:1: note: in expansion of macro 'DEF_ALL'
   444 | DEF_ALL ()
       | ^~~
0x1fbf06f riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**, 
rtx_def*, bool)

         ../../../../gcc/gcc/config/riscv/riscv-v.cc:4972
0x1fe2c60 simplify_replace_vlmax_avl
         ../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:200
0x1fe3b05 pass_avlprop::execute(function*)
         ../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:506

Would you mind taking a look at it ?


juzhe.zh...@rivai.ai


Hi Juzhe,

I ran the following configs on both linux and newlib locally (at hash 
23cd2961bd2ff63583f46e3499a07bd54491d45c mtune=rocket) and did not find 
the ice, only additional scan dump failures.

rv32gc/ilp32d
rv32gc_zba_zbb_zbc_zbs/ilp32d
rv32gcv/ilp32d
rv64gc/lp64d
rv64gc_zba_zbb_zbc_zbs/lp64d
rv64gcv/lp64d
rv64gcv_zvbb_zvbc_zvkg_zvkn_zvknc_zvkned_zvkng_zvknha_zvknhb_zvks_zvksc_zvksed_zvksg_zvksh_zvkt/lp64d
rv64imafdcv_zicond_zawrs_zbc_zvkng_zvksg_zvbb_zvbc_zicsr_zba_zbb_zbs_zicbom_zicbop_zicboz_zfhmin_zkt/lp64d/

Can you send me what configuration you are using to get the ice? Is it 
appearing on other tunes? Nothing in my patch should affect anything in 
riscv-v.cc. I'll look into the problem if I'm able to reproduce the error.


The new scan dump failures are a result of now having a vector 
scheduling pipeline.


Edwin


*From:* Edwin Lu <mailto:e...@rivosinc.com>
*Date:* 2024-02-01 14:13
*To:* juzhe.zh...@rivai.ai <mailto:juzhe.zh...@rivai.ai>;
gcc-patches <mailto:gcc-patches@gcc.gnu.org>
*CC:* Robin Dapp <mailto:rdapp@gmail.com>; kito.cheng
<mailto:kito.ch...@gmail.com>; jeffreyalaw
<mailto:jeffreya...@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
vineetg <mailto:vine...@rivosinc.com>; Patrick O'Neill
<mailto:patr...@rivosinc.com>
*Subject:* Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to
dfa pipelines
 From what I know, if it was a problem with my dfa reservation assert,
it would have ICEd in riscv.cc and not riscv-v.cc. For now I reverted
the changes since I don't want to leave things possibly broken
overnight
and not knowing which patch is the root cause. I kicked off another set
of test runs using our full gcc postcommit testing configurations and
should have those results in tomorrow. Hopefully it was just a missed
config target I didn't test and wasn't tested on the precommit ci.
Edwin
On 1/31/2024 9:42 PM, Edwin Lu wrote:
 > Hi Juzhe,
 >
 > I didn't see any ICEs when I tested locally (tested on
 >

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8123f3ca3fd891034a8366518e756f161c4ff40d).
 Can you tell me what config you're using?
 >
 > Edwin
 >
 > On 1/31/2024 6:57 PM, juzhe.zh...@rivai.ai wrote:
 >> Hi, all.
 >>
 >>

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8>
 >>

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8>
 >>

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4b799a16ae59fc0f508c5931ebf1851a3446b707
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4b799a16ae59fc0f508c5931ebf1851a3446b707>
 >>

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c>
 >>
 >> These 4 commits cause all testcases failed (ICE and dump FAILs).
 >>
 >> FAIL:
gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c
 >> scan-tree-dump-times vect "vectorized 1 loops in function" 11
 >> FAIL:
 >>
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c
 >> (internal compiler error: in validate_change_or_fail, at
 

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

On 1/31/2024 11:29 PM, Li, Pan2 wrote:
I can somehow reproduce the failures on commit id 
23cd2961bd2ff63583f46e3499a07bd54491d45c, configurations as below.


./configure --prefix=${install_dir} \

--with-arch=rv64imafdcv \

--with-abi=lp64d \

--with-isa-spec=20191213 \

--with-sim=qemu

make -j $(nproc) build-sim SIM=qemu

make report -j $(nproc) RUNTESTFLAGS=rvv.exp

= Summary of gcc testsuite =

| # of unexpected case / # of unique unexpected case

|gcc |g++ |gfortran |

rv64imafdcv/lp64d/ medlow |160 /47 |0 /0 |- |

make: *** [Makefile:1067: report-gcc-newlib] Error 1

Pan


Hi Pan,

I'm getting similar numbers as well using your steps but I also want to 
confirm whether you are also getting the ICEs or are just getting 
additional scan dump failures. The scan dump failures are a result of 
adding the new scheduling pipelines. I skimmed through them and didn't 
find anything unexpected.


Edwin



*From:*juzhe.zh...@rivai.ai 
*Sent:* Thursday, February 1, 2024 3:06 PM
*To:* Edwin Lu ; gcc-patches 
*Cc:* Robin Dapp ; kito.cheng 
; jeffreyalaw ; palmer 
; vineetg ; Patrick O'Neill 

*Subject:* Re: Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to 
dfa pipelines


Sorry again. I just realized you have reverted your patches that's why I 
can pass the testing now.


I checkout your latest patch commit:

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c>



Then I can reproduce the ICE now:



bug.c: In function 'popcount32_uint64_tuint64_t':

bug.c:20:3: internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972


    20 |   }

       |   ^

bug.c:123:3: note: in expansion of macro 'DEF32'

   123 |   DEF32 (uint64_t, uint64_t)   
                 \


       |   ^

bug.c:444:1: note: in expansion of macro 'DEF_ALL'

   444 | DEF_ALL ()

       | ^~~

0x1fbf06f riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**, 
rtx_def*, bool)


         ../../../../gcc/gcc/config/riscv/riscv-v.cc:4972

0x1fe2c60 simplify_replace_vlmax_avl

         ../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:200

0x1fe3b05 pass_avlprop::execute(function*)

         ../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:506

Would you mind taking a look at it ?



juzhe.zh...@rivai.ai <mailto:juzhe.zh...@rivai.ai>

*From:*Edwin Lu <mailto:e...@rivosinc.com>

*Date:* 2024-02-01 14:13

*To:*juzhe.zh...@rivai.ai <mailto:juzhe.zh...@rivai.ai>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>

*CC:*Robin Dapp <mailto:rdapp@gmail.com>; kito.cheng
<mailto:kito.ch...@gmail.com>; jeffreyalaw
<mailto:jeffreya...@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
vineetg <mailto:vine...@rivosinc.com>; Patrick O'Neill
<mailto:patr...@rivosinc.com>

*Subject:* Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to
dfa pipelines

 From what I know, if it was a problem with my dfa reservation assert,

it would have ICEd in riscv.cc and not riscv-v.cc. For now I reverted

the changes since I don't want to leave things possibly broken
overnight

and not knowing which patch is the root cause. I kicked off another set

of test runs using our full gcc postcommit testing configurations and

should have those results in tomorrow. Hopefully it was just a missed

config target I didn't test and wasn't tested on the precommit ci.

Edwin

On 1/31/2024 9:42 PM, Edwin Lu wrote:

> Hi Juzhe,

>

> I didn't see any ICEs when I tested locally (tested on

>

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8123f3ca3fd891034a8366518e756f161c4ff40d
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8123f3ca3fd891034a8366518e756f161c4ff40d>).
 Can you tell me what config you're using?

>

> Edwin

>

> On 1/31/2024 6:57 PM,  juzhe.zh...@rivai.ai <mailto:juzhe.zh...@rivai.ai> 
wrote:

>> Hi, all.

>>

>>
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8> 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8>>

>>
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8> 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e72

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

From what I know, if it was a problem with my dfa reservation assert, 
it would have ICEd in riscv.cc and not riscv-v.cc. For now I reverted 
the changes since I don't want to leave things possibly broken overnight 
and not knowing which patch is the root cause. I kicked off another set 
of test runs using our full gcc postcommit testing configurations and 
should have those results in tomorrow. Hopefully it was just a missed 
config target I didn't test and wasn't tested on the precommit ci.


Edwin

On 1/31/2024 9:42 PM, Edwin Lu wrote:

Hi Juzhe,

I didn't see any ICEs when I tested locally (tested on 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8123f3ca3fd891034a8366518e756f161c4ff40d). Can you tell me what config you're using?


Edwin

On 1/31/2024 6:57 PM, juzhe.zh...@rivai.ai wrote:

Hi, all.

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8>
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8>
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4b799a16ae59fc0f508c5931ebf1851a3446b707
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4b799a16ae59fc0f508c5931ebf1851a3446b707>
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c
 
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c>

These 4 commits cause all testcases failed (ICE and dump FAILs).

FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c 
(internal compiler error: in valid

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

Hi Juzhe,

I didn't see any ICEs when I tested locally (tested on 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8123f3ca3fd891034a8366518e756f161c4ff40d). 
Can you tell me what config you're using?


Edwin

On 1/31/2024 6:57 PM, juzhe.zh...@rivai.ai wrote:

Hi, all.

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=26c34b809cd1a6249027730a8b52bbf6a1c0f4a8
 

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e56fb037d9d265682f5e7217d8a4c12a8d3fddf8
 

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4b799a16ae59fc0f508c5931ebf1851a3446b707
 

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=23cd2961bd2ff63583f46e3499a07bd54491d45c
 


These 4 commits cause all testcases failed (ICE and dump FAILs).

FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c 
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c 
(internal compiler error: in validate_change_or_fail, at 
config/riscv/riscv-v.cc:4972)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c 
(test for excess errors)
FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c 
scan-tree-dump-times vect "vectorized 1 loops in function" 11
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c 
(internal compiler error: 

Re: [PATCH] RISC-V: Support scheduling for sifive p600 series

[Edwin Lu]

I recently committed changes modifying the scheduling reservations. Some 
things may need to be retested with the newly enabled asserts.


Edwin

On 1/31/2024 1:40 AM, Monk Chiang wrote:

Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.

gcc/ChangeLog:
* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
attribute, and include sifive-p600.md.
* config/riscv/generic-ooo.md: Update type attribute.
* config/riscv/sifive-7.md: Update type attribute.
* config/riscv/sifive-p600.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add sifive_p600.
* config/riscv/riscv.c (sifive_p600_tune_info): New.
* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
* doc/invoke.texi (RISC-V Options): Add sifive-p600-series
---
  gcc/config/riscv/generic-ooo.md  |   2 +-
  gcc/config/riscv/generic.md  |   2 +-
  gcc/config/riscv/riscv-cores.def |   1 +
  gcc/config/riscv/riscv-opts.h|   1 +
  gcc/config/riscv/riscv.cc|  17 +++
  gcc/config/riscv/riscv.h |   4 +-
  gcc/config/riscv/riscv.md|  19 ++--
  gcc/config/riscv/sifive-7.md |   2 +-
  gcc/config/riscv/sifive-p600.md  | 174 +++
  gcc/doc/invoke.texi  |   3 +-
  10 files changed, 212 insertions(+), 13 deletions(-)
  create mode 100644 gcc/config/riscv/sifive-p600.md

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 421a7bb929d..a22f8a3e079 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -127,7 +127,7 @@
  
  (define_insn_reservation "generic_ooo_fcvt" 3

(and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "fcvt"))
+   (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
"generic_ooo_issue,generic_ooo_fxu")
  
  (define_insn_reservation "generic_ooo_fcmp" 2

diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b99ae345bb3..3f0eaa2ea08 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -42,7 +42,7 @@
  
  (define_insn_reservation "generic_xfer" 3

(and (eq_attr "tune" "generic")
-   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
+   (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
"alu")
  
  (define_insn_reservation "generic_branch" 1

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index b30f4dfb08e..a07a79e2cb7 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
  RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
  RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
  RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
+RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
  RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
  RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
  RISCV_TUNE("size", generic, optimize_size_tune_info)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1500f8811ef..25951665b13 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
  enum riscv_microarchitecture_type {
generic,
sifive_7,
+  sifive_p600,
generic_ooo
  };
  extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7b6111aa545..92d6fd5cf47 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -447,6 +447,23 @@ static const struct riscv_tune_param sifive_7_tune_info = {
NULL,   /* vector cost */
  };
  
+/* Costs to use when optimizing for Sifive p600 Series.  */

+static const struct riscv_tune_param sifive_p600_tune_info = {
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_add */
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_mul */
+  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},/* fp_div */
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* int_mul */
+  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},  /* int_div */
+  4,   /* issue_rate */
+  4,   /* branch_cost */
+  3,   /* memory_cost */
+  4,   /* fmv_cost */
+  true,/* 
slow_unaligned_access */
+  false,   /* use_divmod_expansion */
+  RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI,  /* fusible_ops */
+  NULL,/* vector cost */
+};

Re: [COMMITTED V4 2/4] RISC-V: Add vector related pipelines

[Edwin Lu]

On 1/31/2024 12:28 PM, Robin Dapp wrote:

LGTM, thanks.

Regards
  Robin



Committed!

Edwin

Re: [COMMITTED V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation

[Edwin Lu]

On 1/25/2024 9:06 AM, Robin Dapp wrote:

/* If we ever encounter an insn without an insn reservation, trip
   an assert so we can find and fix this problem.  */
-#if 0
+  if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type (insn));
+  }
gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
  
return more - 1;

  }


I was thinking about make the gcc_assert a gcc_checking_assert so,
in case we accidentally forget something at any point, it would
only gracefully degrade in a release build.  As we already have
a hard assert for the type the patch (and not many test with
enable checking anyway) this is OK IMHO.

I suppose you tested with all available -mtune options?

Regards
  Robin




Committed without the debugging stuff!

Edwin

Re: [COMMITTED V3 3/4] RISC-V: Use default cost model for insn scheduling

[Edwin Lu]

On 1/25/2024 9:06 AM, Robin Dapp wrote:

Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series.


This is OK, thanks.


39 additional unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?


Currently, without vector op latency, the output should come close
to what's normally considered "good" (i.e. minimal number of vsetvls
and so on).  Therefore I'd suggest not to change the scan dumps to
much except when there is a real problem.  If you have a specific
example that you're unsure about we can discuss this on or off list.

Regards
  Robin




Committed!

Edwin

Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

On 1/25/2024 9:06 AM, Robin Dapp wrote:

LGTM, thanks.

Regards
  Robin



Committed!

Edwin

[PATCH V4 2/4] RISC-V: Add vector related pipelines

[Edwin Lu]

Creates new generic vector pipeline file common to all cpu tunes.
Moves all vector related pipelines from generic-ooo to generic-vector-ooo.
Creates new vector crypto related insn reservations.

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo): Move reservation
(generic_ooo_vec_load): ditto
(generic_ooo_vec_store): ditto
(generic_ooo_vec_loadstore_seg): ditto
(generic_ooo_vec_alu): ditto
(generic_ooo_vec_fcmp): ditto
(generic_ooo_vec_imul): ditto
(generic_ooo_vec_fadd): ditto
(generic_ooo_vec_fmul): ditto
(generic_ooo_crypto): ditto
(generic_ooo_perm): ditto
(generic_ooo_vec_reduction): ditto
(generic_ooo_vec_ordered_reduction): ditto
(generic_ooo_vec_idiv): ditto
(generic_ooo_vec_float_divsqrt): ditto
(generic_ooo_vec_mask): ditto
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_setrm): ditto
(generic_ooo_vec_readlen): ditto
* config/riscv/riscv.md: include generic-vector-ooo
* config/riscv/generic-vector-ooo.md: New file. to here

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 
---
V2:
- Remove unnecessary syntax changes in generic-ooo
- Add new vector crypto reservations and types to
  pipelines
V3:
- Move all vector pipelines into separate file which defines all ooo vector
  reservations.
- Add temporary attribute while cost model changes.
V4:
- Remove temporary attribute
---
 gcc/config/riscv/generic-ooo.md| 127 +-
 gcc/config/riscv/generic-vector-ooo.md | 143 +
 gcc/config/riscv/riscv.md  |   1 +
 3 files changed, 145 insertions(+), 126 deletions(-)
 create mode 100644 gcc/config/riscv/generic-vector-ooo.md

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index ef8cb96daf4..4e8297bf96f 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -1,5 +1,5 @@
 ;; RISC-V generic out-of-order core scheduling model.
-;; Copyright (C) 2017-2024 Free Software Foundation, Inc.
+;; Copyright (C) 2023-2024 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -48,9 +48,6 @@ (define_automaton "generic_ooo")
 ;; Integer/float issue queues.
 (define_cpu_unit "issue0,issue1,issue2,issue3,issue4" "generic_ooo")
 
-;; Separate issue queue for vector instructions.
-(define_cpu_unit "generic_ooo_vxu_issue" "generic_ooo")
-
 ;; Integer/float execution units.
 (define_cpu_unit "ixu0,ixu1,ixu2,ixu3" "generic_ooo")
 (define_cpu_unit "fxu0,fxu1" "generic_ooo")
@@ -58,12 +55,6 @@ (define_cpu_unit "fxu0,fxu1" "generic_ooo")
 ;; Integer subunit for division.
 (define_cpu_unit "generic_ooo_div" "generic_ooo")
 
-;; Vector execution unit.
-(define_cpu_unit "generic_ooo_vxu_alu" "generic_ooo")
-
-;; Vector subunit that does mult/div/sqrt.
-(define_cpu_unit "generic_ooo_vxu_multicycle" "generic_ooo")
-
 ;; Shortcuts
 (define_reservation "generic_ooo_issue" "issue0|issue1|issue2|issue3|issue4")
 (define_reservation "generic_ooo_ixu_alu" "ixu0|ixu1|ixu2|ixu3")
@@ -92,25 +83,6 @@ (define_insn_reservation "generic_ooo_float_store" 6
(eq_attr "type" "fpstore"))
   "generic_ooo_issue,generic_ooo_fxu")
 
-;; Vector load/store
-(define_insn_reservation "generic_ooo_vec_load" 6
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-(define_insn_reservation "generic_ooo_vec_store" 6
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector segment loads/stores.
-(define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
-   vssegte,vssegts,vssegtux,vssegtox"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-
 ;; Generic integer instructions.
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
@@ -191,103 +163,6 @@ (define_insn_reservation "generic_ooo_popcount" 2
(eq_attr "type" "cpop,clmul"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
-;; Regular vector operations and integer comparisons.
-(define_insn_reservation "generic_ooo_vec_alu" 3
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" 
"via

[PATCH] RISC-V: Fix rvv intrinsic pragma tests dejagnu selector

[Edwin Lu]

Adding rvv related flags (i.e. --param=riscv-autovec-preference) to
non vector targets bypassed the dejagnu skip test directive. Change the
target selector to skip if rvv is enabled

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/abi-1.c: change selector
* gcc.target/riscv/rvv/base/pragma-2.c: ditto
* gcc.target/riscv/rvv/base/pragma-3.c: ditto

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c| 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c
index 2eef9e1e1a8..a072bdd47bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! riscv_xtheadvector } } } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } } */
 
 void foo0 () {__rvv_bool64_t t;}
 void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
index fd2aa3066cd..fc1bb13c53d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } } */
 
 #pragma riscv intrinsic "vector"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
index 96a0e051a29..45580bb2faa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+/* { dg-skip-if "test rvv intrinsic" { ! riscv_v } */
 
 #pragma riscv intrinsic "report-error" /* { dg-error {unknown '#pragma riscv 
intrinsic' option 'report-error'} } */
-- 
2.34.1

Re: [PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation

[Edwin Lu]

On 1/25/2024 9:06 AM, Robin Dapp wrote:

/* If we ever encounter an insn without an insn reservation, trip
   an assert so we can find and fix this problem.  */
-#if 0
+  if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type (insn));
+  }
gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
  
return more - 1;

  }


Oops accidentally left my debugging statements in the patch.



I was thinking about make the gcc_assert a gcc_checking_assert so,
in case we accidentally forget something at any point, it would
only gracefully degrade in a release build.  As we already have
a hard assert for the type the patch (and not many test with
enable checking anyway) this is OK IMHO.

I suppose you tested with all available -mtune options?



I ran the testsuite on all three tunes using linux rv64gcv. generic-ooo 
had some bugs fixed while rocket and sifive-7-series had around 37 new 
scan dump failures which I think is to be expected. No ICE's from the 
hard gcc_assert on any of the tunes so I think it should be fine as is.


Edwin

Re: [PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling

[Edwin Lu]

On 1/25/2024 9:06 AM, Robin Dapp wrote:


39 additional unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?


Currently, without vector op latency, the output should come close
to what's normally considered "good" (i.e. minimal number of vsetvls
and so on).  Therefore I'd suggest not to change the scan dumps to
much except when there is a real problem.  If you have a specific
example that you're unsure about we can discuss this on or off list.



That sounds good to me! I don't have a specific example that stands out. 
It's mostly just not finding the expected number of vsetvls or the 
vector insns have been moved earlier or something like that.


Edwin

Re: [PATCH V3 2/4] RISC-V: Add vector related pipelines

[Edwin Lu]

On 1/25/2024 9:06 AM, Robin Dapp wrote:

Thanks, that looks better IMHO.


+;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
+;; Contributed by Andrew Waterman (and...@sifive.com).
+;; Based on MIPS target for GNU compiler.

You might want to change that, as well as the date.  While at
it you can also fix the broken date in my original file ;)



Completely forgot about this. I'll update it :)


+(define_insn_reservation "vec_load" 6
+  (and (eq_attr "is_inorder" "no")
+   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
+  "vxu_ooo_issue,vxu_ooo_alu")

I would rather ditch the is_inorder attribute for now and define
"low" latencies as well as reservations explicitly once we're
sure rather than falling back to scheduler defaults.



I think removing the is_inorder attribute should be ok. I added it 
because I wanted to avoid having two matching insn reservations defined 
since matching solely on the type attribute should also match on all 
subsets as well (i.e. if eventually we add an insn reservation checking 
for type "vlde" and tune "generic-ooo", any "vlde" insn would map to 
both reservations)


For now I should just remove the is_inorder attribute. We will update 
the latencies and add new reservations after we know what they should 
be. Is that correct?



OK with those changes.

Regards
  Robin

Re: [Committed V2] RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark-pro

[Edwin Lu]

On 1/16/2024 5:41 PM, juzhe.zh...@rivai.ai wrote:
Are you saying using glibc lib ? I do the testing with newlib, I didn't 
anything wrong.


Yes, I'm seeing the problem using glibc. Looking at our postcommit ci 
reports, it appears to only affect linux rv32gcv.
It seems that this patch triggers latent bug of VSETVL PASS (Even though 
this patch doesn't change anything related to VSETVL PASS).


I will investigate it.

Thanks.


Thanks!

Edwin

Re: [Committed V2] RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark-pro

[Edwin Lu]

Hi Juzhe,

I'm seeing that this patch introduces failures with rv32gcv-ilp32d as 
seen here https://github.com/ewlu/gcc-precommit-ci/issues/1194. Digging 
a little deeper, it appears that there's an illegal instruction in a 
shared library which (at least for FAIL: 
gcc.c-torture/execute/920501-8.c   -O2  execution test) is using vmv.v.i 
without a prior vsetvl. I believe the other failures may be similar.


Logs:
spawn -ignore SIGHUP 
/scratch/ewlu/ci/triage/compare/build-407-errors/build-gcc-linux-stage2/gcc/xgcc 
-B/scratch/ewlu/ci/triage/compare/build-407-errors/build-gcc-linux-stage2/gcc/ 
/scratch/ewlu/ci/triage/compare/gcc/gcc/testsuite/gcc.c-torture/execute/920501-8.c 
-march=rv32gcv -mabi=ilp32d -mtune=rocket -mcmodel=medlow 
-fdiagnostics-plain-output -O2 -w -lm -o ./920501-8.exe

PASS: gcc.c-torture/execute/920501-8.c   -O2  (test for excess errors)
spawn riscv64-unknown-linux-gnu-run ./920501-8.exe
/scratch/ewlu/ci/triage/compare/build-407-errors/../scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run: 
line 15: 584664 Illegal instruction (core dumped) 
QEMU_CPU="$(march-to-cpu-opt --get-riscv-tag $1)" qemu-riscv$xlen -r 
5.10 "${qemu_args[@]}" -L ${RISC_V_SYSROOT} "$@"

FAIL: gcc.c-torture/execute/920501-8.c   -O2  execution test

Execution:
QEMU_CPU="rv32,vlen=128,v=true,vext_spec=v1.0,Zve32f=true,Zve64f=true" 
./bin/qemu-riscv32 ./920501-8.exe


GDB output:
Program received signal SIGILL, Illegal instruction.
0x2b3d0f3e in __printf_buffer () from 
/scratch/ewlu/ci/triage/compare/build-407-errors/sysroot/lib32/ilp32d/libc.so.6

1: x/i $pc
=> 0x2b3d0f3e <__printf_buffer+410>:vmv.v.i v1,0

I've included the first 150ish lines of the function's objdump below.

Edwin

$ ./bin/riscv64-unknown-linux-gnu-objdump -d 
sysroot/lib32/ilp32d/libc.so.6 > dump


00046da4 <__printf_buffer>:
   46da4:   000f8797auipc   a5,0xf8
   46da8:   1ac7a783lw  a5,428(a5) # 13ef50 
<_GLOBAL_OFFSET_TABLE_+0x64>

   46dac:   b3010113addisp,sp,-1232
   46db0:   4c812423sw  s0,1224(sp)
   46db4:   c6besw  a5,76(sp)
   46db6:   9792add a5,a5,tp
   46db8:   439clw  a5,0(a5)
   46dba:   842amv  s0,a0
   46dbc:   4d212023sw  s2,1216(sp)
   46dc0:   c2aesw  a1,68(sp)
   46dc2:   892emv  s2,a1
   46dc4:   852emv  a0,a1
   46dc6:   02500593li  a1,37
   46dca:   de3esw  a5,60(sp)
   46dcc:   4c112623sw  ra,1228(sp)
   46dd0:   4c912223sw  s1,1220(sp)
   46dd4:   4b312e23sw  s3,1212(sp)
   46dd8:   4b812423sw  s8,1192(sp)
   46ddc:   84b2mv  s1,a2
   46dde:   dcb2sw  a2,120(sp)
   46de0:   89b6mv  s3,a3
   46de2:   c0b6sw  a3,64(sp)
   46de4:   60a300efjal 773ee 
   46de8:   c4aasw  a0,72(sp)
   46dea:   41250633sub a2,a0,s2
   46dee:   8c2amv  s8,a0
   46df0:   85camv  a1,s2
   46df2:   8522mv  a0,s0
   46df4:   933f90efjal 40726 
<__printf_buffer_write>

   46df8:   4c1clw  a5,24(s0)
   46dfa:   c3ddbeqza5,46ea0 
<__printf_buffer+0xfc>

   46dfc:   000c4783lbu a5,0(s8)
   46e00:   c3c5beqza5,46ea0 
<__printf_buffer+0xfc>

   46e02:   000fa797auipc   a5,0xfa
   46e06:   85a7a783lw  a5,-1958(a5) # 14065c 
<__printf_function_table>

   46e0a:   4b512a23sw  s5,1204(sp)
   46e0e:   da3esw  a5,52(sp)
   46e10:   c399beqza5,46e16 
<__printf_buffer+0x72>
   46e12:   2680106fj   4807a 
<__printf_buffer+0x12d6>

   46e16:   000fa797auipc   a5,0xfa
   46e1a:   8367a783lw  a5,-1994(a5) # 14064c 
<__printf_modifier_table>
   46e1e:   740797e3bneza5,47d6c 
<__printf_buffer+0xfc8>

   46e22:   000f9797auipc   a5,0xf9
   46e26:   e927a783lw  a5,-366(a5) # 13fcb4 
<__printf_va_arg_table>
   46e2a:   740791e3bneza5,47d6c 
<__printf_buffer+0xfc8>

   46e2e:   57fdli  a5,-1
   46e30:   d0besw  a5,96(sp)
   46e32:   0019f793andia5,s3,1
   46e36:   d4besw  a5,104(sp)
   46e38:   111caddi  

[PATCH V3 3/4] RISC-V: Use default cost model for insn scheduling

[Edwin Lu]

Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series.

39 additional unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?

PR target/113249

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/bug-1.C: use default scheduling
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: ditto
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: ditto
* gcc.target/riscv/rvv/base/pr108185-2.c: ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-12.c  | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-16.c  | 2 ++
 .../gcc.target/riscv/rvv/base

[PATCH V3 4/4] RISC-V: Enable assert for insn_has_dfa_reservation

[Edwin Lu]

Enables assert that every typed instruction is associated with a
dfa reservation

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

Signed-off-by: Edwin Lu 
---
V2:
- No changes
V3:
- No changes
---
 gcc/config/riscv/riscv.cc | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee1a57b321d..c428d3e4e58 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8215,9 +8215,11 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, 
int more)
 
   /* If we ever encounter an insn without an insn reservation, trip
  an assert so we can find and fix this problem.  */
-#if 0
+  if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type (insn));
+  }
   gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
 
   return more - 1;
 }
-- 
2.34.1

[PATCH V3 2/4] RISC-V: Add vector related pipelines

[Edwin Lu]

Creates new generic vector pipeline file common to all cpu tunes.
Moves all vector related pipelines from generic-ooo to generic-vector-ooo.
Creates new vector crypto related insn reservations. Add temporary attribute
for making changes to the vector cost model

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo): Move reservation
(generic_ooo_vec_load): ditto
(generic_ooo_vec_store): ditto
(generic_ooo_vec_loadstore_seg): ditto
(generic_ooo_vec_alu): ditto
(generic_ooo_vec_fcmp): ditto
(generic_ooo_vec_imul): ditto
(generic_ooo_vec_fadd): ditto
(generic_ooo_vec_fmul): ditto
(generic_ooo_crypto): ditto
(generic_ooo_perm): ditto
(generic_ooo_vec_reduction): ditto
(generic_ooo_vec_ordered_reduction): ditto
(generic_ooo_vec_idiv): ditto
(generic_ooo_vec_float_divsqrt): ditto
(generic_ooo_vec_mask): ditto
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_setrm): ditto
(generic_ooo_vec_readlen): ditto
* config/riscv/riscv.md (no): add temporary attribute
* config/riscv/generic-vector-ooo.md: to here

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 
---
V2:
- Remove unnecessary syntax changes in generic-ooo
- Add new vector crypto reservations and types to
  pipelines
V3:
- Move all vector pipelines into separate file which defines all ooo vector
  reservations.
- Add temporary attribute while cost model changes.
---
 gcc/config/riscv/generic-ooo.md| 125 ---
 gcc/config/riscv/generic-vector-ooo.md | 165 +
 gcc/config/riscv/riscv.md  |   5 +
 3 files changed, 170 insertions(+), 125 deletions(-)
 create mode 100644 gcc/config/riscv/generic-vector-ooo.md

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index ef8cb96daf4..40e5104cde1 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -48,9 +48,6 @@ (define_automaton "generic_ooo")
 ;; Integer/float issue queues.
 (define_cpu_unit "issue0,issue1,issue2,issue3,issue4" "generic_ooo")
 
-;; Separate issue queue for vector instructions.
-(define_cpu_unit "generic_ooo_vxu_issue" "generic_ooo")
-
 ;; Integer/float execution units.
 (define_cpu_unit "ixu0,ixu1,ixu2,ixu3" "generic_ooo")
 (define_cpu_unit "fxu0,fxu1" "generic_ooo")
@@ -58,12 +55,6 @@ (define_cpu_unit "fxu0,fxu1" "generic_ooo")
 ;; Integer subunit for division.
 (define_cpu_unit "generic_ooo_div" "generic_ooo")
 
-;; Vector execution unit.
-(define_cpu_unit "generic_ooo_vxu_alu" "generic_ooo")
-
-;; Vector subunit that does mult/div/sqrt.
-(define_cpu_unit "generic_ooo_vxu_multicycle" "generic_ooo")
-
 ;; Shortcuts
 (define_reservation "generic_ooo_issue" "issue0|issue1|issue2|issue3|issue4")
 (define_reservation "generic_ooo_ixu_alu" "ixu0|ixu1|ixu2|ixu3")
@@ -92,25 +83,6 @@ (define_insn_reservation "generic_ooo_float_store" 6
(eq_attr "type" "fpstore"))
   "generic_ooo_issue,generic_ooo_fxu")
 
-;; Vector load/store
-(define_insn_reservation "generic_ooo_vec_load" 6
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-(define_insn_reservation "generic_ooo_vec_store" 6
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-;; Vector segment loads/stores.
-(define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
-   vssegte,vssegts,vssegtux,vssegtox"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-
-
 ;; Generic integer instructions.
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
@@ -191,103 +163,6 @@ (define_insn_reservation "generic_ooo_popcount" 2
(eq_attr "type" "cpop,clmul"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
-;; Regular vector operations and integer comparisons.
-(define_insn_reservation "generic_ooo_vec_alu" 3
-  (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
-  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
-

[PATCH V3 1/4] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

This patch adds non-vector related insn reservations and updates/creates
new insn reservations so all non-vector typed instructions have a reservation.

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
(generic_ooo_branch): ditto
* config/riscv/generic.md ( dittogeneric_sfb_alu):
(generic_fmul_half): ditto
* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
* config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
(sifive_7_popcount): ditto
* config/riscv/vector.md: change rdfrm to fmove
* config/riscv/zc.md: change pushpop to load/store

Signed-off-by: Edwin Lu 
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
V3:
- No changes
---
 gcc/config/riscv/generic-ooo.md | 15 +-
 gcc/config/riscv/generic.md | 20 +--
 gcc/config/riscv/riscv.md   | 18 +++
 gcc/config/riscv/sifive-7.md| 17 +-
 gcc/config/riscv/vector.md  |  2 +-
 gcc/config/riscv/zc.md  | 96 -
 6 files changed, 102 insertions(+), 66 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 421a7bb929d..ef8cb96daf4 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
-   move,bitmanip,min,max,minu,maxu,clz,ctz"))
+   move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
+   condmove,mvpair,zicond"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
+(define_insn_reservation "generic_ooo_sfb_alu" 2
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "sfb_alu"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
+
+;; Branch instructions
+(define_insn_reservation "generic_ooo_branch" 1
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
 
 ;; Float move, convert and compare.
 (define_insn_reservation "generic_ooo_float_move" 3
@@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_popcount" 2
 (define_insn_reservation "generic_ooo_vec_alu" 3
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov"))
+   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float comparison, conversion etc.
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b99ae345bb3..45986cfea89 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,9 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+   (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
+   move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\
+   condmove,crypto,mvpair,zicond"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
@@ -47,12 +49,17 @@ (define_insn_reservation "generic_xfer" 3
 
 (define_insn_reservation "generic_branch" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "branch,jump,call,jalr"))
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "alu")
+
+(define_insn_reservation "generic_sfb_alu" 2
+  (and (eq_attr "tune" "generic")
+   (eq_attr "type" "sfb_alu"))
   "alu")
 
 (define_insn_reservation "generic_imul" 10
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "imul,clmul"))
+   (eq_attr "type" "imul,clmul,cpop"))
   "imuldiv*10")
 
 (define_insn_reservation "generic_idivsi" 34
@@ -67,6 +74,12 @@ (define_insn_reservation "generic_idivdi" 66
(eq_attr "mode" "DI")))
   "imuldiv*66")
 
+(define_insn_reservation "generic_fmul_half" 5
+  (and (eq_attr "tune&

[PATCH V3 0/4] RISC-V: Associate typed insns to dfa reservation

[Edwin Lu]

Updates all tune insn reservation pipelines to cover all types defined by
define_attr "type" in riscv.md.

Creates new vector insn reservation pipelines in new file generic-vector-ooo.md
which has separate automaton vector_ooo where all reservations are mapped to.
This allows all tunes to share a common vector model for now as we make 
large changes to the vector cost model. 
(https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642511.html)

Disables pipeline scheduling for some tests with scan dump failures when using
-mtune=generic-ooo. 

Enables assert that all insn types must be associated with a dfa pipeline
reservation

Edwin Lu (4):
  RISC-V: Add non-vector types to dfa pipelines
  RISC-V: Add vector related pipelines
  RISC-V: Use default cost model for insn scheduling
  RISC-V: Enable assert for insn_has_dfa_reservation

---
V2:
- Update non-vector insn types and add new pipelines
- Add -fno-schedule-insn -fno-schedule-insn2 to some test cases

V3:
- Separate vector pipelines to separate file which all tunes have access to
---

 gcc/config/riscv/generic-ooo.md   | 138 ++-
 gcc/config/riscv/generic-vector-ooo.md| 165 ++
 gcc/config/riscv/generic.md   |  20 ++-
 gcc/config/riscv/riscv.cc |   6 +-
 gcc/config/riscv/riscv.md |  23 +--
 gcc/config/riscv/sifive-7.md  |  17 +-
 gcc/config/riscv/vector.md|   2 +-
 gcc/config/riscv/zc.md|  96 +-
 .../g++.target/riscv/rvv/base/bug-1.C |   2 +
 .../riscv/rvv/autovec/reduc/reduc_call-2.c|   2 +
 .../riscv/rvv/base/binop_vx_constraint-102.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-108.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-114.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-119.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-12.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-16.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-17.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-19.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-21.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-23.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-25.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-27.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-29.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-31.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-33.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-35.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-4.c|   2 +
 .../riscv/rvv/base/binop_vx_constraint-40.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-44.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-50.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-56.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-62.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-68.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-74.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-79.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-8.c|   2 +
 .../riscv/rvv/base/binop_vx_constraint-84.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-90.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-96.c   |   2 +
 .../rvv/base/float-point-dynamic-frm-30.c |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-1.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-2.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-3.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-4.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-5.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-6.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-7.c|   2 +
 .../riscv/rvv/base/shift_vx_constraint-1.c|   2 +
 .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-29.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-32.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-33.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-17.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-18.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-19.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |   2 +
 gcc/testsuite/gfortran.dg/vect/vect-8.f90 |   2 +
 66 files changed, 391 insertions(+), 192 deletions(-)
 create mode 100644 gcc/config/riscv/generic-vector-ooo.md

-- 
2.34.1

Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations

[Edwin Lu]

Since all the pipelines should be tuned to their cost model, they
would be different anyway. If it would be simpler for now, I could
separate the files out.
I think I'm getting a bit confused. Is there a reason why we would
want to exchange scheduler descriptions like the example you
provided? I'm just thinking why a in-order model would want to use an
ooo vector model and vice versa. Please correct me if I got the wrong
idea.


Yeah, the confusion is understandable as it's all in flow and several
things I mentioned are artifacts of us not yet being stabilized (or
actually having hard data to base our decisions on).

Usually, once a uarch has settled there is no reason to exchange
anything, just smaller tweaks might be done.  I was more thinking of
the near to mid-term future where larger changes like ripping out
one thing and using another one altogether might still happen.

Regarding out of order vs in order - for in-order pipelines we will
always want to get latencies right.  For out of order it is a balancing
act (proper latencies often mean more spilling and the processor will
reorder correctly anyway).

So you're mostly right that the argument is not very strong as soon
as we really know what to do and not to do.


That makes sense to me!

I also want to double check, isn't forcing all typed instructions to
be part of a dfa pipeline in effect removing a situation where a tune
model does not specify a "vector tune model"? At least from my
testing with the assert statement, I get ICEs when trying to run the
testsuite without the vector tune model even on gc.


There are (at least) three parts of the "tune model":
  - vector cost model, specifying the cost of generic vector operations,
not necessarily corresponding to an insn
  - insn cost, specifying the cost of an individual insn, usually close
to latency but sometimes also "complexity" or other things.
  - insn latency and other hardware scheduler properties.

We can leave out any of those which will make us fall back to default
values.  Even if we forced a scheduler description we could still have
the default fallback for the other two and generate unfavorable code
as a result.

So if I'm understanding things correctly, the costs the Juzhe is working 
on in riscv.cc would be part of the vector cost model since they don't 
correspond to individual instructions and only target vector code. These 
costs would be the default fallback in the event of having no scheduler 
descriptions for the insn.


The vector pipelines I'm working describes the insn latency categorized 
by the insn type. The scheduler will attempt to generate favorable code 
by this description but also consider the vector cost model. That is, 
it's possible for an insn with a latency of 1 and cost of 10 to be 
replaced by an insn with a latency of 2 and cost of 3.


The insn cost is the cost of every insn which can be specified 
elsewhere. These override the values in the vector cost model for vector 
insns? Where are these specified?


Then, all of these combined form a tune model like generic-ooo or rocket.

However, this is of course not desirable and we will soon have a
reasonable vector cost model that corresponds to the non-uarch
specific properties of the vector spec.  Once this is in place
we will also want a somewhat generic vector scheduler description
that goes hand in hand with that.  Despite the name, the vector
part of generic-ooo could be used for in-order vector uarchs and
we might want to define a different description for out-of-order
uarchs.  That's a separate discussion but at least for that
contingency it would make sense to easily interchange the scheduler
description ;)

I think I understand everything. I'm currently testing a run with a 
generic-vector-ooo file and I'm a little unsure how we would create a 
second generic-vector-in-order file such that each insn maps only to one 
reservation without using tune attributes but I guess that will be an 
implementation detail for later :)


Edwin

Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations

[Edwin Lu]

Hi Robin,
On 1/10/2024 8:00 AM, Robin Dapp wrote:

Hi Edwin,


This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. Creates new vector crypto related
insn reservations.


In principle, the changes look good to me but I wonder if we could
split off the vector parts from generic-ooo into their own md file
(generic-vector-ooo or so?) and include this in the others?  Or is
there a reason why you decided against this?

I forgot we could include other md files into another file (I'll double 
check that there isn't anything fancy for including other pipelines), 
but I also thought that eventually all the tunes would have their own 
vector cost pipelines. Since all the pipelines should be tuned to their 
cost model, they would be different anyway. If it would be simpler for 
now, I could separate the files out.



A recurring question in vector cost model discussions seems to be how
to handle the situation when a tune model does not specify a "vector tune
model".  The problem exists for the scheduler descriptions and the
normal vector cost model (and possibly insn_costs as well).

Juzhe just implemented a fallback so we always use the "generic rvv" cost
model.  Your changes would be in the same vein and if we could split
them off then we'd be able to easier exchange one scheduler descriptions
for another one (say if one tune model wants to use an in-order vector
model).

I think I'm getting a bit confused. Is there a reason why we would want 
to exchange scheduler descriptions like the example you provided? I'm 
just thinking why a in-order model would want to use an ooo vector model 
and vice versa. Please correct me if I got the wrong idea.


I also want to double check, isn't forcing all typed instructions to be 
part of a dfa pipeline in effect removing a situation where a tune model 
does not specify a "vector tune model"? At least from my testing with 
the assert statement, I get ICEs when trying to run the testsuite 
without the vector tune model even on gc.



There is also still the question of whether to set all latencies
to 1 for an OOO core but this question should be settled separately
as soon as we have proper hardware benchmark results.  If so we
would probably rename generic-vector-ooo into
generic-vector-in-order ;)

Regards
  Robin



I agree the latencies can be tweaked after we get those benchmarks :)

Edwin

[PATCH V2 3/4][RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249

[Edwin Lu]

Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series.

Unfortunately, 40 unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?

PR target/113249

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/bug-1.C: use default tune scheduling
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: ditto
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: ditto
* gcc.target/riscv/rvv/base/pr108185-2.c: ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto

Signed-off-by: Edwin Lu 
---
V2: 
- New patch
---
 gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-12.c  | 2 ++
 .../gcc.target/riscv/rvv/base/binop_vx_constraint-16.c  | 2

[PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines

[Edwin Lu]

This patch adds non-vector related insn reservations and updates/creates
new insn reservations so all non-vector typed instructions have a reservation.

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
(generic_ooo_branch): ditto
* config/riscv/generic.md (generic_sfb_alu): ditto
(generic_fmul_half): ditto
* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
* config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
(sifive_7_popcount): ditto
* config/riscv/vector.md: change rdfrm to fmove
* config/riscv/zc.md: change pushpop to load/store

Signed-off-by: Edwin Lu 
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
---
 gcc/config/riscv/generic-ooo.md | 15 +-
 gcc/config/riscv/generic.md | 20 +--
 gcc/config/riscv/riscv.md   | 18 +++
 gcc/config/riscv/sifive-7.md| 17 +-
 gcc/config/riscv/vector.md  |  2 +-
 gcc/config/riscv/zc.md  | 96 -
 6 files changed, 102 insertions(+), 66 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 421a7bb929d..ef8cb96daf4 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
-   move,bitmanip,min,max,minu,maxu,clz,ctz"))
+   move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
+   condmove,mvpair,zicond"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
+(define_insn_reservation "generic_ooo_sfb_alu" 2
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "sfb_alu"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
+
+;; Branch instructions
+(define_insn_reservation "generic_ooo_branch" 1
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
 
 ;; Float move, convert and compare.
 (define_insn_reservation "generic_ooo_float_move" 3
@@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_popcount" 2
 (define_insn_reservation "generic_ooo_vec_alu" 3
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov"))
+   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float comparison, conversion etc.
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b99ae345bb3..45986cfea89 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,9 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+   (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
+   move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\
+   condmove,crypto,mvpair,zicond"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
@@ -47,12 +49,17 @@ (define_insn_reservation "generic_xfer" 3
 
 (define_insn_reservation "generic_branch" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "branch,jump,call,jalr"))
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "alu")
+
+(define_insn_reservation "generic_sfb_alu" 2
+  (and (eq_attr "tune" "generic")
+   (eq_attr "type" "sfb_alu"))
   "alu")
 
 (define_insn_reservation "generic_imul" 10
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "imul,clmul"))
+   (eq_attr "type" "imul,clmul,cpop"))
   "imuldiv*10")
 
 (define_insn_reservation "generic_idivsi" 34
@@ -67,6 +74,12 @@ (define_insn_reservation "generic_idivdi" 66
(eq_attr "mode" "DI")))
   "imuldiv*66")
 
+(define_insn_reservation "generic_fmul_half" 5
+  (and (eq_attr "tune" "generic")
+

[PATCH V2 4/4][RFC] RISC-V: Enable assert for insn_has_dfa_reservation

[Edwin Lu]

Enables assert that every typed instruction is associated with a
dfa reservation

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

Signed-off-by: Edwin Lu 
---
V2:
- No changes
---
 gcc/config/riscv/riscv.cc | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e275fcc2245 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8150,9 +8150,11 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, 
int more)
 
   /* If we ever encounter an insn without an insn reservation, trip
  an assert so we can find and fix this problem.  */
-#if 0
+  if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type (insn));
+  }
   gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
 
   return more - 1;
 }
-- 
2.34.1

[PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation

[Edwin Lu]

This series is a prototype for adding all typed instructions to a dfa 
scheduling pipeline.

This is what I currently have for cleaning up the cost models. Adding the 
vector insns to the dfa pipelines changes the expected output of a lot of test
cases as expected. Should I update the expected output of the test cases to
the output of the new cost model? I'm not fully sure which codegen is more
optimal. Please let me know if I should do so and I'll add a patch adjusting
the expected testcase output.

Edwin Lu (4):
  RISC-V: Add non-vector types to dfa pipelines
  RISC-V: Add vector related reservations
  RISC-V: Use default cost model for insn scheduling for tests affected
in PR113249
  RISC-V: Enable assert for insn_has_dfa_reservation

---
V2:
- Update non-vector insn types and add new pipelines
- Add -fno-schedule-insn -fno-schedule-insn2 to some test cases
---

 gcc/config/riscv/generic-ooo.md   |  40 -
 gcc/config/riscv/generic.md   | 163 +-
 gcc/config/riscv/riscv.cc |   6 +-
 gcc/config/riscv/riscv.md |  18 +-
 gcc/config/riscv/sifive-7.md  | 161 -
 gcc/config/riscv/vector.md|   2 +-
 gcc/config/riscv/zc.md|  96 +--
 .../g++.target/riscv/rvv/base/bug-1.C |   2 +
 .../riscv/rvv/autovec/reduc/reduc_call-2.c|   2 +
 .../riscv/rvv/base/binop_vx_constraint-102.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-108.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-114.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-119.c  |   2 +
 .../riscv/rvv/base/binop_vx_constraint-12.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-16.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-17.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-19.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-21.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-23.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-25.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-27.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-29.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-31.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-33.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-35.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-4.c|   2 +
 .../riscv/rvv/base/binop_vx_constraint-40.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-44.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-50.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-56.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-62.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-68.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-74.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-79.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-8.c|   2 +
 .../riscv/rvv/base/binop_vx_constraint-84.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-90.c   |   2 +
 .../riscv/rvv/base/binop_vx_constraint-96.c   |   2 +
 .../rvv/base/float-point-dynamic-frm-30.c |   2 +
 .../gcc.target/riscv/rvv/base/pr108185-1.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-2.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-3.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-4.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-5.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-6.c|   2 +
 .../gcc.target/riscv/rvv/base/pr108185-7.c|   2 +
 .../riscv/rvv/base/shift_vx_constraint-1.c|   2 +
 .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-28.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-29.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-32.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-33.c |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-17.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-18.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_single_block-19.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |   2 +
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |   2 +
 gcc/testsuite/gfortran.dg/vect/vect-8.f90 |   2 +
 65 files changed, 532 insertions(+), 70 deletions(-)

-- 
2.34.1

[PATCH V2 2/4][RFC] RISC-V: Add vector related reservations

[Edwin Lu]

This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. Creates new vector crypto related
insn reservations.

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo_crypto_aes): create 
reservation
(generic_ooo_crypto_sha): ditto
(generic_ooo_crypto_sm): ditto
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_vsetvl): ditto
* config/riscv/generic.md (pipe0): ditto
(generic_vec_load): ditto
(generic_vec_store): ditto
(generic_vec_loadstore_seg): ditto
(generic_vec_alu): ditto
(generic_vec_fcmp): ditto
(generic_vec_imul): ditto
(generic_vec_fadd): ditto
(generic_vec_fmul): ditto
(generic_crypto): ditto
(generic_crypto_aes): ditto
(generic_crypto_sha): ditto
(generic_crypto_sm): ditto
(generic_perm): ditto
(generic_vec_reduction): ditto
(generic_vec_ordered_reduction): ditto
(generic_vec_idiv): ditto
(generic_vec_float_divsqrt): ditto
(generic_vec_mask): ditto
(generic_vec_vesetvl): ditto
(generic_vec_setrm): ditto
(generic_vec_readlen): ditto
* config/riscv/sifive-7.md (sifive_7): ditto
(sifive_7_vec_load): ditto
(sifive_7_vec_store): ditto
(sifive_7_vec_loadstore_seg): ditto
(sifive_7_vec_alu): ditto
(sifive_7_vec_fcmp): ditto
(sifive_7_vec_imul): ditto
(sifive_7_vec_fadd): ditto
(sifive_7_vec_fmul): ditto
(sifive_7_crypto): ditto
(sifive_7_crypto_aes): ditto
(sifive_7_crypto_sha): ditto
(sifive_7_crypto_sm): ditto
(sifive_7_perm): ditto
(sifive_7_vec_reduction): ditto
(sifive_7_vec_ordered_reduction): ditto
(sifive_7_vec_idiv): ditto
(sifive_7_vec_float_divsqrt): ditto
(sifive_7_vec_mask): ditto
(sifive_7_vec_vesetvl): ditto
(sifive_7_vec_setrm): ditto
(sifive_7_vec_readlen): ditto

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 
---
V2:
- Remove unnecessary syntax changes in generic-ooo
- Add new vector crypto reservations and types to
  pipelines
---
 gcc/config/riscv/generic-ooo.md |  27 +-
 gcc/config/riscv/generic.md | 143 +++
 gcc/config/riscv/sifive-7.md| 144 
 3 files changed, 311 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index ef8cb96daf4..fb5f34c0ef2 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -195,7 +195,8 @@ (define_insn_reservation "generic_ooo_popcount" 2
 (define_insn_reservation "generic_ooo_vec_alu" 3
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
+   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\
+   vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float comparison, conversion etc.
@@ -209,7 +210,8 @@ (define_insn_reservation "generic_ooo_vec_fcmp" 3
 ;; Vector integer multiplication.
 (define_insn_reservation "generic_ooo_vec_imul" 4
   (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul"))
+   (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
+   vghsh,vgmul"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float addition.
@@ -230,6 +232,25 @@ (define_insn_reservation "generic_ooo_crypto" 4
(eq_attr "type" "crypto"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
+;; Vector crypto, AES
+(define_insn_reservation "generic_ooo_crypto_aes" 4
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
+  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
+
+;; Vector crypto, sha
+(define_insn_reservation "generic_ooo_crypto_sha" 4
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
+  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
+
+;; Vector crypto, SM3/4
+(define_insn_reservation "generic_ooo_crypto_sm" 4
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c"))
+  "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
+
+
 ;; Vector permute.
 (define_insn_reservation "generic_ooo_perm" 3

Re: [PATCH 2/3][RFC] RISC-V: Add vector related reservations

[Edwin Lu]

On 12/20/2023 2:55 PM, Edwin Lu wrote:

On 12/20/2023 10:57 AM, Jeff Law wrote:



On 12/15/23 11:53, Edwin Lu wrote:

This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. The vector pipelines are
necessary to avoid an ICE from the assert


I forgot to get clarification earlier but this patch would introduce 
many scan-dump failures for both vector and non-vector targets 
(https://github.com/ewlu/gcc-precommit-ci/issues/950#issuecomment-1858392181). 
I haven't identified any execution errors that would be introduced on 
mtune=rocket aside from one ICE which I'm currently working on fixing.


Additionally, as mentioned in PR113035, there are significant testsuite 
differences between mtune=rocket and mtune=sifive-7-series. I haven't 
gone through all of the differences and I don't know if they are a 
problem with the patch or a result of the cost modeling assumptions.


Is there a problem with the current way mtune=rocket is modeled with 
generic.md?


Edwin

Re: [PATCH 2/3][RFC] RISC-V: Add vector related reservations

[Edwin Lu]

On 12/20/2023 10:57 AM, Jeff Law wrote:



On 12/15/23 11:53, Edwin Lu wrote:

This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. The vector pipelines are
necessary to avoid an ICE from the assert




gcc/ChangeLog:

* config/riscv/generic-ooo.md: syntax
* config/riscv/generic.md (pipe0): new reservation
(generic_vec_load): ditto
(generic_vec_store): ditto
(generic_vec_loadstore_seg): ditto
(generic_generic_vec_alu): ditto
(generic_vec_fcmp): ditto
(generic_vec_imul): ditto
(generic_vec_fadd): ditto
(generic_vec_fmul): ditto
(generic_crypto): ditto
(generic_vec_perm): ditto
(generic_vec_reduction): ditto
(generic_vec_ordered_reduction): ditto
(generic_vec_idiv): ditto
(generic_vec_float_divsqrt): ditto
(generic_vec_mask): ditto
(generic_vec_vesetvl): ditto
(generic_vec_setrm): ditto
(generic_vec_readlen): ditto
* config/riscv/sifive-7.md (sifive_7): new reservation
(sifive_7_vec_load): ditto
(sifive_7_vec_store): ditto
(sifive_7_vec_loadstore_seg): ditto
(sifive_7_sifive_7_vec_alu): ditto
(sifive_7_vec_fcmp): ditto
(sifive_7_vec_imul): ditto
(sifive_7_vec_fadd): ditto
(sifive_7_vec_fmul): ditto
(sifive_7_crypto): ditto
(sifive_7_vec_perm): ditto
(sifive_7_vec_reduction): ditto
(sifive_7_vec_ordered_reduction): ditto
(sifive_7_vec_idiv): ditto
(sifive_7_vec_float_divsqrt): ditto
(sifive_7_vec_mask): ditto
(sifive_7_vec_vesetvl): ditto
(sifive_7_vec_setrm): ditto
(sifive_7_vec_readlen): ditto

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 
---
  gcc/config/riscv/generic-ooo.md |  19 ++---
  gcc/config/riscv/generic.md | 118 
  gcc/config/riscv/sifive-7.md    | 118 
  3 files changed, 242 insertions(+), 13 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md 
b/gcc/config/riscv/generic-ooo.md

index de93245f965..18b606bb981 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
I'm not sure why you changed these.  In general we try to keep lines 
under 80 columns in the source.  Things like insn reservations are in a 
grey area as the lists sometimes get very long.  In general I'd leave 
this stuff alone if it doesn't have a function change.


Hmm when I was testing things before, I encountered an error where the 
scheduler had a problem with "\ " with the assert enabled, but now 
I can't reproduce it. I'll revert it back to what it originally was and 
experiment some more.


index 3e49d942495..7ac974ad634 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
Note that some of the stuff pointed out on patch #1 applies here to, 
like rdfrm not being a vector load/store.  So as you clean up patch #1, 
make sure to mirror the cleanups in patch #2 of the series.



Will do!

Edwin

Re: [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines

[Edwin Lu]

On 12/20/2023 10:50 AM, Jeff Law wrote:



On 12/15/23 11:53, Edwin Lu wrote:

This patch does not create vector related insn reservations for
generic.md and sifive-7.md. It updates/creates insn reservations
for all non-vector typed insns

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): create/update 
reservation

(generic_ooo_branch): ditto
* config/riscv/generic.md (generic_sfb_alu): ditto
* config/riscv/sifive-7.md (sifive_7_popcount): ditto

Signed-off-by: Edwin Lu 
---
  gcc/config/riscv/generic-ooo.md | 16 +---
  gcc/config/riscv/generic.md | 13 +
  gcc/config/riscv/sifive-7.md    | 12 +---
  3 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md 
b/gcc/config/riscv/generic-ooo.md

index 78b9e48f935..de93245f965 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -95,7 +95,7 @@ (define_insn_reservation "generic_ooo_float_store" 6
  ;; Vector load/store
  (define_insn_reservation "generic_ooo_vec_load" 6
    (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
+   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,rdfrm"))
    "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
Hmm, I don't think "rdfrm" is really a vector load.  It's really a read 
of some bits in the fpcsr which elsewhere is handled as type fmove.  I'd 
actually suggest fixing vector.md to use fmove on the appropriate insn, 
then dropping rdfrm entirely.

Sounds good!



  (define_insn_reservation "generic_xfer" 3
    (and (eq_attr "tune" "generic")
-   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
+   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp,cbo"))
    "alu")

cbo is probably closer to a load/store than it is a transfer operation.

That makes sense. I wasn't sure where exactly to put it since we have 
two separate insn reservations for load and store and from my 
understanding, the same type cannot be in two separate insn 
reservations. Would a new insn reservation like

(define_insn_reservation "generic_load_store" 2 ...) work?


  (define_insn_reservation "generic_branch" 1
    (and (eq_attr "tune" "generic")
-   (eq_attr "type" "branch,jump,call,jalr"))
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap,pushpop"))
+  "alu")
pushpop are a mix of some pure memory operations and some mixed memory + 
branch.


However, from a scheduling standpoint the branch isn't particularly 
interesting.  So I'd have pushpop as a load/store.



Same as above

Edwin

[PATCH 3/3][RFC] RISC-V: Enable assert for insn_has_dfa_reservation

[Edwin Lu]

Enables assert that every typed instruction is associated with a
dfa reservation

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv.cc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ab0f95e5fe9..3adeb415bec 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8048,9 +8048,7 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, 
int more)
 
   /* If we ever encounter an insn without an insn reservation, trip
  an assert so we can find and fix this problem.  */
-#if 0
   gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
 
   return more - 1;
 }
-- 
2.34.1

[PATCH 2/3][RFC] RISC-V: Add vector related reservations

[Edwin Lu]

This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. The vector pipelines are
necessary to avoid an ICE from the assert

gcc/ChangeLog:

* config/riscv/generic-ooo.md: syntax
* config/riscv/generic.md (pipe0): new reservation
(generic_vec_load): ditto
(generic_vec_store): ditto
(generic_vec_loadstore_seg): ditto
(generic_generic_vec_alu): ditto
(generic_vec_fcmp): ditto
(generic_vec_imul): ditto
(generic_vec_fadd): ditto
(generic_vec_fmul): ditto
(generic_crypto): ditto
(generic_vec_perm): ditto
(generic_vec_reduction): ditto
(generic_vec_ordered_reduction): ditto
(generic_vec_idiv): ditto
(generic_vec_float_divsqrt): ditto
(generic_vec_mask): ditto
(generic_vec_vesetvl): ditto
(generic_vec_setrm): ditto
(generic_vec_readlen): ditto
* config/riscv/sifive-7.md (sifive_7): new reservation
(sifive_7_vec_load): ditto
(sifive_7_vec_store): ditto
(sifive_7_vec_loadstore_seg): ditto
(sifive_7_sifive_7_vec_alu): ditto
(sifive_7_vec_fcmp): ditto
(sifive_7_vec_imul): ditto
(sifive_7_vec_fadd): ditto
(sifive_7_vec_fmul): ditto
(sifive_7_crypto): ditto
(sifive_7_vec_perm): ditto
(sifive_7_vec_reduction): ditto
(sifive_7_vec_ordered_reduction): ditto
(sifive_7_vec_idiv): ditto
(sifive_7_vec_float_divsqrt): ditto
(sifive_7_vec_mask): ditto
(sifive_7_vec_vesetvl): ditto
(sifive_7_vec_setrm): ditto
(sifive_7_vec_readlen): ditto

Signed-off-by: Edwin Lu 
Co-authored-by: Robin Dapp 
---
 gcc/config/riscv/generic-ooo.md |  19 ++---
 gcc/config/riscv/generic.md | 118 
 gcc/config/riscv/sifive-7.md| 118 
 3 files changed, 242 insertions(+), 13 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index de93245f965..18b606bb981 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -106,16 +106,14 @@ (define_insn_reservation "generic_ooo_vec_store" 6
 ;; Vector segment loads/stores.
 (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
   (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
-   vssegte,vssegts,vssegtux,vssegtox"))
+   (eq_attr "type" 
"vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vssegte,vssegts,vssegtux,vssegtox"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 
 ;; Generic integer instructions.
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
-   
move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,cbo,mvpair,zicond"))
+   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,cbo,mvpair,zicond"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
 (define_insn_reservation "generic_ooo_sfb_alu" 2
@@ -193,16 +191,13 @@ (define_insn_reservation "generic_ooo_popcount" 2
 ;; Regular vector operations and integer comparisons.
 (define_insn_reservation "generic_ooo_vec_alu" 3
   (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
+   (eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float comparison, conversion etc.
 (define_insn_reservation "generic_ooo_vec_fcmp" 3
   (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
-   vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
-   vfncvtftoi,vfncvtftof"))
+   (eq_attr "type" 
"vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector integer multiplication.
@@ -232,8 +227,7 @@ (define_insn_reservation "generic_ooo_crypto" 4
 ;; Vector permute.
 (define_insn_reservation "generic_ooo_perm" 3
   (and (eq_attr "tune" "generic_ooo")
-   (eq_at

[PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines

[Edwin Lu]

This patch does not create vector related insn reservations for
generic.md and sifive-7.md. It updates/creates insn reservations
for all non-vector typed insns

gcc/ChangeLog:

* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): create/update 
reservation
(generic_ooo_branch): ditto
* config/riscv/generic.md (generic_sfb_alu): ditto
* config/riscv/sifive-7.md (sifive_7_popcount): ditto

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/generic-ooo.md | 16 +---
 gcc/config/riscv/generic.md | 13 +
 gcc/config/riscv/sifive-7.md| 12 +---
 3 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 78b9e48f935..de93245f965 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -95,7 +95,7 @@ (define_insn_reservation "generic_ooo_float_store" 6
 ;; Vector load/store
 (define_insn_reservation "generic_ooo_vec_load" 6
   (and (eq_attr "tune" "generic_ooo")
-   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
+   (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,rdfrm"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 (define_insn_reservation "generic_ooo_vec_store" 6
@@ -115,9 +115,19 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
 (define_insn_reservation "generic_ooo_alu" 1
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
-   move,bitmanip,min,max,minu,maxu,clz,ctz"))
+   
move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,cbo,mvpair,zicond"))
   "generic_ooo_issue,generic_ooo_ixu_alu")
 
+(define_insn_reservation "generic_ooo_sfb_alu" 2
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "sfb_alu"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
+
+;; Branch instructions
+(define_insn_reservation "generic_ooo_branch" 1
+  (and (eq_attr "tune" "generic_ooo")
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap,pushpop"))
+  "generic_ooo_issue,generic_ooo_ixu_alu")
 
 ;; Float move, convert and compare.
 (define_insn_reservation "generic_ooo_float_move" 3
@@ -184,7 +194,7 @@ (define_insn_reservation "generic_ooo_popcount" 2
 (define_insn_reservation "generic_ooo_vec_alu" 3
   (and (eq_attr "tune" "generic_ooo")
(eq_attr "type" 
"vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
-   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov"))
+   vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
   "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
 
 ;; Vector float comparison, conversion etc.
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index 88940483829..3e49d942495 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,7 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,condmove,crypto,mvpair,zicond"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
@@ -42,17 +42,22 @@ (define_insn_reservation "generic_store" 1
 
 (define_insn_reservation "generic_xfer" 3
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
+   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp,cbo"))
   "alu")
 
 (define_insn_reservation "generic_branch" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "branch,jump,call,jalr"))
+   (eq_attr "type" "branch,jump,call,jalr,ret,trap,pushpop"))
+  "alu")
+
+(define_insn_reservation "generic_sfb_alu" 2
+  (and (eq_attr "tune" "generic")
+   (eq_attr "type" "sfb_alu"))
   "alu")
 
 (define_insn_reservation "generic_imul" 10
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" "imul,clmul"))
+   (eq_attr "type" "imul,clmul,cpop"))
   "imuldiv*10")
 
 (define_insn_reservation &quo

[PATCH 0/3][RFC] RISC-V: Associate typed insns to dfa reservation

[Edwin Lu]

This series is a prototype for adding all typed instructions to a dfa 
scheduling pipeline.

I've been working on adding insn reservations for all typed instructions
to ensure all instructions are part of a dfa pipeline. I don't have a good 
understanding of vector instruction latency, so I have been struggling
with what I should do for those. 

As of right now, I have copied the insn reservations from generic-ooo.md 
for vector instructions into the generic.md and sifive-7.md files. This 
prevents ICEs from enabling the assert but introduces numerous scan
dump failures (when tested in linux rv64gcv and rv64gc_zba_zbb_zbc_zbs).

Currently, only patch 1/3 RISC-V: Add non-vector types to pipelines does
not introduce regressions (when tested against linux rv32/64 gc/gcv
on rocket).  I hope that the locations I added the insn types make sense. 
Please let me know if they should change.

The final patch enables the assert for insn_has_dfa_reservation. 

I tested the full patch series on both rocket and sifive-7-series. The 
series does introduce additional scan dump failures compared to their
respective baselines, however, I'm not sure how many failures were
due to the patch vs incorrect modeling assumptions. I created
PR113035 which has the full testsuite failures I saw (without the patches
applied).

Edwin Lu (3):
  RISC-V: Add non-vector types to pipelines
  RISC-V: Add vector related reservations
  RISC-V: Enable assert for insn_has_dfa_reservation

 gcc/config/riscv/generic-ooo.md |  31 
 gcc/config/riscv/generic.md | 131 +++-
 gcc/config/riscv/riscv.cc   |   2 -
 gcc/config/riscv/sifive-7.md| 130 ++-
 4 files changed, 271 insertions(+), 23 deletions(-)

-- 
2.34.1

[PATCH V3] RISC-V: XFAIL scan dump fails for autovec PR111311

[Edwin Lu]

Clean up scan dump failures on linux rv64 vector targets Juzhe mentioned
could be ignored for now. This will help reduce noise and make it more obvious
if a bug or regression is introduced. The failures that are still reported
are either execution failures or failures that are also present on armv8-a+sve

gcc/testsuite/ChangeLog:

* c-c++-common/vector-subscript-4.c: xfail testcase
* g++.dg/tree-ssa/pr83518.C: ditto
* gcc.dg/attr-alloc_size-11.c: remove xfail
* gcc.dg/signbit-2.c: xfail testcase
* gcc.dg/signbit-5.c: ditto
* gcc.dg/tree-ssa/cunroll-16.c: ditto
* gcc.dg/tree-ssa/gen-vect-34.c: ditto
* gcc.dg/tree-ssa/loop-bound-1.c: ditto
* gcc.dg/tree-ssa/loop-bound-2.c: ditto
* gcc.dg/tree-ssa/pr84512.c: remove xfail
* gcc.dg/tree-ssa/predcom-4.c: xfail testcase
* gcc.dg/tree-ssa/predcom-5.c: ditto
* gcc.dg/tree-ssa/predcom-9.c: ditto
* gcc.dg/tree-ssa/reassoc-46.c: ditto
* gcc.dg/tree-ssa/scev-10.c: ditto
* gcc.dg/tree-ssa/scev-11.c: ditto
* gcc.dg/tree-ssa/scev-14.c: ditto
* gcc.dg/tree-ssa/scev-9.c: ditto
* gcc.dg/tree-ssa/split-path-11.c: ditto
* gcc.dg/tree-ssa/ssa-dom-cse-2.c: ditto
* gcc.dg/tree-ssa/update-threading.c: ditto
* gcc.dg/unroll-8.c: ditto
* gcc.dg/var-expand1.c: ditto
* gcc.dg/vect/pr103116-1.c: ditto
* gcc.dg/vect/pr103116-2.c: ditto
* gcc.dg/vect/pr65310.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto

Signed-off-by: Edwin Lu 
---
V2 changes:
- added attr-alloc_size-11.c and update-threading.c which were missed in
  previous patch
- remove pr83232.f90 xfail since it was fixed in a recent trunk update
- adjust xfail on split-path-11.c to only apply to rv64

V3 changes:
- swapped to only xfailing riscv specifically (pr84512.c and pr83518.c)
- removed modifications to target-supports.exp as it was accidentally added
---
 gcc/testsuite/c-c++-common/vector-subscript-4.c  | 3 ++-
 gcc/testsuite/g++.dg/tree-ssa/pr83518.C  | 2 +-
 gcc/testsuite/gcc.dg/attr-alloc_size-11.c| 4 ++--
 gcc/testsuite/gcc.dg/signbit-2.c | 5 +++--
 gcc/testsuite/gcc.dg/signbit-5.c | 1 +
 gcc/testsuite/gcc.dg/tree-ssa/cunroll-16.c   | 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/loop-bound-1.c | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/loop-bound-2.c | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/pr84512.c  | 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/predcom-4.c| 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/predcom-5.c| 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/predcom-9.c| 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c   | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-10.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-11.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-14.c  | 4 +++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-9.c   | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/split-path-11.c| 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c| 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/update-threading.c | 2 +-
 gcc/testsuite/gcc.dg/unroll-8.c  | 8 +---
 gcc/testsuite/gcc.dg/var-expand1.c   | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr103116-1.c   | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr103116-2.c   | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr65310.c  | 4 ++--
 gcc/testsuite/gfortran.dg/vect/vect-8.f90| 3 ++-
 27 files changed, 56 insertions(+), 34 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/vector-subscript-4.c 
b/gcc/testsuite/c-c++-common/vector-subscript-4.c
index 2c2481f88b7..eb0bca1c19e 100644
--- a/gcc/testsuite/c-c++-common/vector-subscript-4.c
+++ b/gcc/testsuite/c-c++-common/vector-subscript-4.c
@@ -25,5 +25,6 @@ foobar(16)
 foobar(32)
 foobar(64)
 
+/* Xfail riscv PR112531.  */
 /* Verify we don't have any vector temporaries in the IL.  */
-/* { dg-final { scan-tree-dump-not "vector" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "vector" "optimized" { xfail { riscv_v && 
vect_variable_length } } } } */
diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C 
b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
index b8a2bd1ebbd..dcb9279abc2 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
@@ -24,4 +24,4 @@ unsigned test()
   return sum;
 }
 
-/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail 
vect_variable_length } } } */
+/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail { 
vect_variable_length && { ! riscv_v } } } } */
diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c 
b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
index a2efe128915..2828db12e05 100644
--- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
+++ b/gcc/testsuite/gcc.dg/a

Re: [PATCH V2] RISC-V: XFAIL scan dump fails for autovec PR111311

[Edwin Lu]

On 12/10/2023 9:37 PM, Kito Cheng wrote:

diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C 
b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
index b8a2bd1ebbd..6f2fc56c82c 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
@@ -24,4 +24,4 @@ unsigned test()
return sum;
  }

-/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail 
vect_variable_length } } } */
+/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail { vect_variable_length 
&& aarch64*-*-* } } } } */

aarch64?


I found the patch which added the xfail vect_variable_length originating 
from https://inbox.sourceware.org/gcc-patches/mptfszz8vxw@arm.com/. 
The patch mentioned how it was tested on aarch64 which is why I added 
it. Should I change it to ! riscv_v?


Edwin

[PATCH V2] RISC-V: XFAIL scan dump fails for autovec PR111311

[Edwin Lu]

Clean up scan dump failures on linux rv64 vector targets Juzhe mentioned 
could be ignored for now. This will help reduce noise and make it more obvious
if a bug or regression is introduced. The failures that are still reported
are either execution failures or failures that are also present on armv8-a+sve

gcc/testsuite/ChangeLog:

* c-c++-common/vector-subscript-4.c: xfail testcase
* g++.dg/tree-ssa/pr83518.C: ditto
* gcc.dg/attr-alloc_size-11.c: remove xfail
* gcc.dg/signbit-2.c: xfail testcase
* gcc.dg/signbit-5.c: ditto
* gcc.dg/tree-ssa/cunroll-16.c: ditto
* gcc.dg/tree-ssa/gen-vect-34.c: ditto
* gcc.dg/tree-ssa/loop-bound-1.c: ditto
* gcc.dg/tree-ssa/loop-bound-2.c: ditto
* gcc.dg/tree-ssa/pr84512.c: remove xfail
* gcc.dg/tree-ssa/predcom-4.c: xfail testcase
* gcc.dg/tree-ssa/predcom-5.c: ditto
* gcc.dg/tree-ssa/predcom-9.c: ditto
* gcc.dg/tree-ssa/reassoc-46.c: ditto
* gcc.dg/tree-ssa/scev-10.c: ditto
* gcc.dg/tree-ssa/scev-11.c: ditto
* gcc.dg/tree-ssa/scev-14.c: ditto
* gcc.dg/tree-ssa/scev-9.c: ditto
* gcc.dg/tree-ssa/split-path-11.c: ditto
* gcc.dg/tree-ssa/ssa-dom-cse-2.c: ditto
* gcc.dg/tree-ssa/update-threading.c: ditto
* gcc.dg/unroll-8.c: ditto
* gcc.dg/var-expand1.c: ditto
* gcc.dg/vect/pr103116-1.c: ditto
* gcc.dg/vect/pr103116-2.c: ditto
* gcc.dg/vect/pr65310.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
* lib/target-supports.exp: ditto

Signed-off-by: Edwin Lu 
---
V2 changes:
- added attr-alloc_size-11.c and update-threading.c which were missed in
  previous patch
- remove pr83232.f90 xfail since it was fixed in a recent trunk update
- adjust xfail on split-path-11.c to only apply to rv64
---
 gcc/testsuite/c-c++-common/vector-subscript-4.c  | 3 ++-
 gcc/testsuite/g++.dg/tree-ssa/pr83518.C  | 2 +-
 gcc/testsuite/gcc.dg/attr-alloc_size-11.c| 4 ++--
 gcc/testsuite/gcc.dg/signbit-2.c | 5 +++--
 gcc/testsuite/gcc.dg/signbit-5.c | 1 +
 gcc/testsuite/gcc.dg/tree-ssa/cunroll-16.c   | 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/loop-bound-1.c | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/loop-bound-2.c | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/pr84512.c  | 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/predcom-4.c| 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/predcom-5.c| 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/predcom-9.c| 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c   | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-10.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-11.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-14.c  | 4 +++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-9.c   | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/split-path-11.c| 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c| 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/update-threading.c | 2 +-
 gcc/testsuite/gcc.dg/unroll-8.c  | 8 +---
 gcc/testsuite/gcc.dg/var-expand1.c   | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr103116-1.c   | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr103116-2.c   | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr65310.c  | 4 ++--
 gcc/testsuite/gfortran.dg/vect/vect-8.f90| 3 ++-
 gcc/testsuite/lib/target-supports.exp| 3 +++
 28 files changed, 59 insertions(+), 34 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/vector-subscript-4.c 
b/gcc/testsuite/c-c++-common/vector-subscript-4.c
index 2c2481f88b7..eb0bca1c19e 100644
--- a/gcc/testsuite/c-c++-common/vector-subscript-4.c
+++ b/gcc/testsuite/c-c++-common/vector-subscript-4.c
@@ -25,5 +25,6 @@ foobar(16)
 foobar(32)
 foobar(64)
 
+/* Xfail riscv PR112531.  */
 /* Verify we don't have any vector temporaries in the IL.  */
-/* { dg-final { scan-tree-dump-not "vector" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "vector" "optimized" { xfail { riscv_v && 
vect_variable_length } } } } */
diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C 
b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
index b8a2bd1ebbd..6f2fc56c82c 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
@@ -24,4 +24,4 @@ unsigned test()
   return sum;
 }
 
-/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail 
vect_variable_length } } } */
+/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail { 
vect_variable_length && aarch64*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c 
b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
index a2efe128915..2828db12e05 100644
--- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
+++ b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
@@ -47,8 +47,8 @@ typedef __SIZE_T

[PATCH] RISC-V: XFAIL scan dump fails for autovec PR111311

[Edwin Lu]

Clean up scan dump failures Juzhe mentioned could be ignored for now
with vector enabled. This will help reduce noise and make it more obvious
if a bug or regression is introduced. The failures that are still reported
are either execution failures or failures that are also present on armv8-a+sve

gcc/testsuite/ChangeLog:

* c-c++-common/vector-subscript-4.c: xfail testcase
* g++.dg/tree-ssa/pr83518.C: ditto
* gcc.dg/signbit-2.c: ditto
* gcc.dg/tree-ssa/cunroll-16.c: ditto
* gcc.dg/tree-ssa/gen-vect-34.c: ditto
* gcc.dg/tree-ssa/loop-bound-1.c: ditto
* gcc.dg/tree-ssa/loop-bound-2.c: ditto
* gcc.dg/tree-ssa/pr84512.c: remove xfail
* gcc.dg/tree-ssa/predcom-4.c: xfail testcase
* gcc.dg/tree-ssa/predcom-5.c: ditto
* gcc.dg/tree-ssa/predcom-9.c: ditto
* gcc.dg/tree-ssa/reassoc-46.c: ditto
* gcc.dg/tree-ssa/scev-10.c: ditto
* gcc.dg/tree-ssa/scev-11.c: ditto
* gcc.dg/tree-ssa/scev-14.c: ditto
* gcc.dg/tree-ssa/scev-9.c: ditto
* gcc.dg/tree-ssa/split-path-11.c: ditto
* gcc.dg/unroll-8.c: ditto
* gcc.dg/var-expand1.c: ditto
* gcc.dg/vect/pr103116-1.c: ditto
* gcc.dg/vect/pr103116-2.c: ditto
* gfortran.dg/vect/pr83232.f90: ditto
* gfortran.dg/vect/vect-8.f90: ditto

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/c-c++-common/vector-subscript-4.c | 3 ++-
 gcc/testsuite/g++.dg/tree-ssa/pr83518.C | 2 +-
 gcc/testsuite/gcc.dg/signbit-2.c| 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/cunroll-16.c  | 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/loop-bound-1.c| 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/loop-bound-2.c| 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/pr84512.c | 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/predcom-4.c   | 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/predcom-5.c   | 5 +++--
 gcc/testsuite/gcc.dg/tree-ssa/predcom-9.c   | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/reassoc-46.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-10.c | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-11.c | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-14.c | 4 +++-
 gcc/testsuite/gcc.dg/tree-ssa/scev-9.c  | 3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/split-path-11.c   | 3 ++-
 gcc/testsuite/gcc.dg/unroll-8.c | 8 +---
 gcc/testsuite/gcc.dg/var-expand1.c  | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr103116-1.c  | 3 ++-
 gcc/testsuite/gcc.dg/vect/pr103116-2.c  | 3 ++-
 gcc/testsuite/gfortran.dg/vect/pr83232.f90  | 3 ++-
 gcc/testsuite/gfortran.dg/vect/vect-8.f90   | 3 ++-
 23 files changed, 52 insertions(+), 29 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/vector-subscript-4.c 
b/gcc/testsuite/c-c++-common/vector-subscript-4.c
index 2c2481f88b7..eb0bca1c19e 100644
--- a/gcc/testsuite/c-c++-common/vector-subscript-4.c
+++ b/gcc/testsuite/c-c++-common/vector-subscript-4.c
@@ -25,5 +25,6 @@ foobar(16)
 foobar(32)
 foobar(64)
 
+/* Xfail riscv PR112531.  */
 /* Verify we don't have any vector temporaries in the IL.  */
-/* { dg-final { scan-tree-dump-not "vector" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "vector" "optimized" { xfail { riscv_v && 
vect_variable_length } } } } */
diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C 
b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
index b8a2bd1ebbd..6f2fc56c82c 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
@@ -24,4 +24,4 @@ unsigned test()
   return sum;
 }
 
-/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail 
vect_variable_length } } } */
+/* { dg-final { scan-tree-dump "return 15;" "optimized" { xfail { 
vect_variable_length && aarch64*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.dg/signbit-2.c b/gcc/testsuite/gcc.dg/signbit-2.c
index 62bb4047d74..2a32568de9e 100644
--- a/gcc/testsuite/gcc.dg/signbit-2.c
+++ b/gcc/testsuite/gcc.dg/signbit-2.c
@@ -22,6 +22,7 @@ void fun2(int32_t *x, int n)
 }
 
 /* Xfail amdgcn where vector truth type is not integer type.  */
-/* { dg-final { scan-tree-dump {\s+>\s+\{ 0(, 0)+ \}} optimized { target 
vect_shift xfail amdgcn-*-* } } } */
+/* Xfail riscv PR111311.  */
+/* { dg-final { scan-tree-dump {\s+>\s+\{ 0(, 0)+ \}} optimized { target 
vect_shift xfail { amdgcn-*-* || { riscv_v && vect_variable_length } } } } } */
 /* { dg-final { scan-tree-dump {\s+>\s+0} optimized { target { ! vect_shift } 
} } } */
-/* { dg-final { scan-tree-dump-not {\s+>>\s+31} optimized { xfail amdgcn-*-* } 
} } */
+/* { dg-final { scan-tree-dump-not {\s+>>\s+31} optimized { xfail { amdgcn-*-* 
|| { riscv_v && vect_variable_length } } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/cunroll-16.c 
b/gcc/testsuite/gcc.dg/tree-ssa/cunroll-16.c
in

Re: [Committed] RISC-V: Remove xfail from ssa-fre-3.c testcase

[Edwin Lu]

Committed!

On 12/6/2023 8:22 AM, Palmer Dabbelt wrote:

On Tue, 05 Dec 2023 16:39:06 PST (-0800), e...@rivosinc.com wrote:
Ran the test case at 122e7b4f9d0c2d54d865272463a1d812002d0a5c where 
the xfail


That's the original port submission, I'm actually kind of surprised it 
still builds/works at all.


was introduced. The test did pass at that hash and has continued to 
pass since

then. Remove the xfail

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/ssa-fre-3.c: Remove xfail

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c 
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c

index 224dd4f72ef..b2924837a22 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
@@ -18,4 +18,4 @@ foo (int a, int b)
   return aa + bb;
 }

-/* { dg-final { scan-tree-dump "Replaced \\\(int\\\) aa_.*with a_" 
"fre1" { xfail { riscv*-*-* && lp64 } } } } */
+/* { dg-final { scan-tree-dump "Replaced \\\(int\\\) aa_.*with a_" 
"fre1" } } */


Reviewed-by: Palmer Dabbelt 

Though Kito did all the test suite stuff back then, so not sure if he 
happens to remember anything specific about what was going on.


Thanks!

[PATCH] RISC-V: Remove xfail from ssa-fre-3.c testcase

[Edwin Lu]

Ran the test case at 122e7b4f9d0c2d54d865272463a1d812002d0a5c where the xfail 
was introduced. The test did pass at that hash and has continued to pass since
then. Remove the xfail

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/ssa-fre-3.c: Remove xfail

Signed-off-by: Edwin Lu 
---
 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c 
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
index 224dd4f72ef..b2924837a22 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
@@ -18,4 +18,4 @@ foo (int a, int b)
   return aa + bb;
 }
 
-/* { dg-final { scan-tree-dump "Replaced \\\(int\\\) aa_.*with a_" "fre1" { 
xfail { riscv*-*-* && lp64 } } } } */
+/* { dg-final { scan-tree-dump "Replaced \\\(int\\\) aa_.*with a_" "fre1" } } 
*/
-- 
2.34.1

Re: [Committed] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]

[Edwin Lu]

Committed!

On 11/15/2023 11:34 PM, Kito Cheng wrote:

ohhh, thanks for fixing that, LGTM!

On Thu, Nov 16, 2023 at 7:31 AM Edwin Lu  wrote:

Fix __riscv_unaligned_fast/slow/avoid macro name to
__riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec

gcc/ChangeLog:

 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/attribute-1.c: update macro name
 * gcc.target/riscv/attribute-4.c: ditto
 * gcc.target/riscv/attribute-5.c: ditto
 * gcc.target/riscv/predef-align-1.c: ditto
 * gcc.target/riscv/predef-align-2.c: ditto
 * gcc.target/riscv/predef-align-3.c: ditto
 * gcc.target/riscv/predef-align-4.c: ditto
 * gcc.target/riscv/predef-align-5.c: ditto
 * gcc.target/riscv/predef-align-6.c: ditto

Signed-off-by: Edwin Lu 
---
  gcc/config/riscv/riscv-c.cc |  6 +++---
  gcc/testsuite/gcc.target/riscv/attribute-1.c| 10 +-
  gcc/testsuite/gcc.target/riscv/attribute-4.c|  8 
  gcc/testsuite/gcc.target/riscv/attribute-5.c| 10 +-
  gcc/testsuite/gcc.target/riscv/predef-align-1.c | 10 +-
  gcc/testsuite/gcc.target/riscv/predef-align-2.c |  8 
  gcc/testsuite/gcc.target/riscv/predef-align-3.c | 10 +-
  gcc/testsuite/gcc.target/riscv/predef-align-4.c | 10 +-
  gcc/testsuite/gcc.target/riscv/predef-align-5.c |  8 
  gcc/testsuite/gcc.target/riscv/predef-align-6.c | 10 +-
  10 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index b7f9ba204f7..dd1bd0596fc 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -109,11 +109,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
  }

if (riscv_user_wants_strict_align)
-builtin_define_with_int_value ("__riscv_unaligned_avoid", 1);
+builtin_define_with_int_value ("__riscv_misaligned_avoid", 1);
else if (riscv_slow_unaligned_access_p)
-builtin_define_with_int_value ("__riscv_unaligned_slow", 1);
+builtin_define_with_int_value ("__riscv_misaligned_slow", 1);
else
-builtin_define_with_int_value ("__riscv_unaligned_fast", 1);
+builtin_define_with_int_value ("__riscv_misaligned_fast", 1);

if (TARGET_MIN_VLEN != 0)
  builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c 
b/gcc/testsuite/gcc.target/riscv/attribute-1.c
index abfb0b498e0..a39efb3e6ff 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-1.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c
@@ -4,13 +4,13 @@ int foo()
  {

  /* In absence of -m[no-]strict-align, default mcpu is currently
-   set to rocket.  rocket has slow_unaligned_access=true.  */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+   set to rocket.  rocket has slow_misaligned_access=true.  */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
  #endif

-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly 
set"
  #endif

  return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c 
b/gcc/testsuite/gcc.target/riscv/attribute-4.c
index 545f87cb899..a5a95042a31 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-4.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c
@@ -3,12 +3,12 @@
  int foo()
  {

-#if !defined(__riscv_unaligned_avoid)
-#error "__riscv_unaligned_avoid is not set"
+#if !defined(__riscv_misaligned_avoid)
+#error "__riscv_misaligned_avoid is not set"
  #endif

-#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set"
  #endif

return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c 
b/gcc/testsuite/gcc.target/riscv/attribute-5.c
index 753043c31e9..ad1a1811fa3 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-5.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c
@@ -3,13 +3,13 @@
  int foo()
  {

-/* Default mcpu is rocket which has slow_unaligned_access=true.  */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+/* Default mcpu is rocket which has slow_misaligned_access=true.  */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
  #en

[PATCH] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]

[Edwin Lu]

Fix __riscv_unaligned_fast/slow/avoid macro name to
__riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec

gcc/ChangeLog:

* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-1.c: update macro name
* gcc.target/riscv/attribute-4.c: ditto
* gcc.target/riscv/attribute-5.c: ditto
* gcc.target/riscv/predef-align-1.c: ditto
* gcc.target/riscv/predef-align-2.c: ditto
* gcc.target/riscv/predef-align-3.c: ditto
* gcc.target/riscv/predef-align-4.c: ditto
* gcc.target/riscv/predef-align-5.c: ditto
* gcc.target/riscv/predef-align-6.c: ditto

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv-c.cc |  6 +++---
 gcc/testsuite/gcc.target/riscv/attribute-1.c| 10 +-
 gcc/testsuite/gcc.target/riscv/attribute-4.c|  8 
 gcc/testsuite/gcc.target/riscv/attribute-5.c| 10 +-
 gcc/testsuite/gcc.target/riscv/predef-align-1.c | 10 +-
 gcc/testsuite/gcc.target/riscv/predef-align-2.c |  8 
 gcc/testsuite/gcc.target/riscv/predef-align-3.c | 10 +-
 gcc/testsuite/gcc.target/riscv/predef-align-4.c | 10 +-
 gcc/testsuite/gcc.target/riscv/predef-align-5.c |  8 
 gcc/testsuite/gcc.target/riscv/predef-align-6.c | 10 +-
 10 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index b7f9ba204f7..dd1bd0596fc 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -109,11 +109,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 }
 
   if (riscv_user_wants_strict_align)
-builtin_define_with_int_value ("__riscv_unaligned_avoid", 1);
+builtin_define_with_int_value ("__riscv_misaligned_avoid", 1);
   else if (riscv_slow_unaligned_access_p)
-builtin_define_with_int_value ("__riscv_unaligned_slow", 1);
+builtin_define_with_int_value ("__riscv_misaligned_slow", 1);
   else
-builtin_define_with_int_value ("__riscv_unaligned_fast", 1);
+builtin_define_with_int_value ("__riscv_misaligned_fast", 1);
 
   if (TARGET_MIN_VLEN != 0)
 builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c 
b/gcc/testsuite/gcc.target/riscv/attribute-1.c
index abfb0b498e0..a39efb3e6ff 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-1.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c
@@ -4,13 +4,13 @@ int foo()
 {
 
 /* In absence of -m[no-]strict-align, default mcpu is currently 
-   set to rocket.  rocket has slow_unaligned_access=true.  */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+   set to rocket.  rocket has slow_misaligned_access=true.  */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast)
+#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly 
set"
 #endif
 
 return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c 
b/gcc/testsuite/gcc.target/riscv/attribute-4.c
index 545f87cb899..a5a95042a31 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-4.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c
@@ -3,12 +3,12 @@
 int foo()
 {
 
-#if !defined(__riscv_unaligned_avoid)
-#error "__riscv_unaligned_avoid is not set"
+#if !defined(__riscv_misaligned_avoid)
+#error "__riscv_misaligned_avoid is not set"
 #endif
 
-#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c 
b/gcc/testsuite/gcc.target/riscv/attribute-5.c
index 753043c31e9..ad1a1811fa3 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-5.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c
@@ -3,13 +3,13 @@
 int foo()
 {
 
-/* Default mcpu is rocket which has slow_unaligned_access=true.  */
-#if !defined(__riscv_unaligned_slow)
-#error "__riscv_unaligned_slow is not set"
+/* Default mcpu is rocket which has slow_misaligned_access=true.  */
+#if !defined(__riscv_misaligned_slow)
+#error "__riscv_misaligned_slow is not set"
 #endif
 
-#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
-#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#if defined(__

Re: [Committed] RISC-V: Add check for types without insn reservations

[Edwin Lu]

On 11/1/2023 11:53 AM, Jeff Law wrote:



On 11/1/23 12:17, Edwin Lu wrote:

Now that all insns are guaranteed to have a type, ensure every insn
is associated with a cpu unit/insn reservation.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled 
assert
OK.  Really interested to see how often this trips in practice.  I 
suspect often right now ;-)


Committed! On a local test with just rv64gc, actually not that many 
types were tripped. I think there were around 13 that weren't part of 
any reservation


Edwin

jeff

[PATCH] RISC-V: Add check for types without insn reservations

[Edwin Lu]

Now that all insns are guaranteed to have a type, ensure every insn
is associated with a cpu unit/insn reservation.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled 
assert

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv.cc | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0148a4f2e43..0bfd06902e5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7751,6 +7751,12 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, 
int more)
  an assert so we can find and fix this problem.  */
   gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN);
 
+  /* If we ever encounter an insn without an insn reservation, trip
+ an assert so we can find and fix this problem.  */
+#if 0
+  gcc_assert (insn_has_dfa_reservation_p (insn));
+#endif
+
   return more - 1;
 }
 
-- 
2.34.1

Re: [Committed] Make genautomata.cc output reflect insn-attr.h expectation:

[Edwin Lu]

On 11/1/2023 8:07 AM, Vladimir Makarov wrote:


On 10/31/23 18:51, Edwin Lu wrote:

genattr.cc currently generates insn-attr.h with the following structure:

#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool insn_has_dfa_reservation_p (rtx_insn *);

however genautomata.cc generates insn-automata.cc with the following 
structure:

#if CPU_UNITS_QUERY
int get_cpu_unit_code (const char * ) { ... }
int cpu_unit_reservation_p (state_t, int) { ... }
bool insn_has_dfa_reservation_p (rtx_insn *) { ... }
#endif

I'm not sure if insn_has_dfa_reservation_p is supposed to be a part of 
the
CPU_UNITS_QUERY conditional group or not. For consistency, I would 
like to

move it outside of the group.


No, it should  be not considered a part of cpu unit query group. The 
function just says that there is any cpu reservation by insns.


Two other functions say that the state is still reserving a particular 
cpu unit.  Using these 2 functions requires a lot of memory for their 
implementation and prevent further dfa minimizations.  The functions 
should be used mostly for VLIW CPUs when we need this information to 
generate machine insns (e.g, ia64 VLIW insn template).



Thanks for the clarification!


This would move insn_has_dfa_reservation_p out of the #if CPU_UNITS_QUERY
conditional inside of insn-automata.cc. This would allow us to see if the
scheduler is trying to schedule an insn with a type which is not 
associated
with a cpu unit or insn reservation through the 
TARGET_SCHED_VARIABLE_ISSUE

hook.

If there is a reason for insn_has_dfa_reservation_p being within the
conditional, please let me know!


It seems a typo.

The patch is ok for me.  Thank you for finding this out.


Committed!

Edwin

gcc/Changelog:

* genautomata.cc (write_automata): move endif

Signed-off-by: Edwin Lu 
---
  gcc/genautomata.cc | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/genautomata.cc b/gcc/genautomata.cc
index 72f01686d6b..9dda25e5ba2 100644
--- a/gcc/genautomata.cc
+++ b/gcc/genautomata.cc
@@ -9503,9 +9503,9 @@ write_automata (void)
    fprintf (output_file, "\n#if %s\n\n", CPU_UNITS_QUERY_MACRO_NAME);
    output_get_cpu_unit_code_func ();
    output_cpu_unit_reservation_p ();
-  output_insn_has_dfa_reservation_p ();
    fprintf (output_file, "\n#endif /* #if %s */\n\n",
 CPU_UNITS_QUERY_MACRO_NAME);
+  output_insn_has_dfa_reservation_p ();
    output_dfa_clean_insn_cache_func ();
    output_dfa_start_func ();
    output_dfa_finish_func ();

[RFC] Make genautomata.cc output reflect insn-attr.h expectation:

[Edwin Lu]

genattr.cc currently generates insn-attr.h with the following structure:

#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool insn_has_dfa_reservation_p (rtx_insn *);

however genautomata.cc generates insn-automata.cc with the following structure:
#if CPU_UNITS_QUERY
int get_cpu_unit_code (const char * ) { ... }
int cpu_unit_reservation_p (state_t, int) { ... }
bool insn_has_dfa_reservation_p (rtx_insn *) { ... }
#endif

I'm not sure if insn_has_dfa_reservation_p is supposed to be a part of the 
CPU_UNITS_QUERY conditional group or not. For consistency, I would like to 
move it outside of the group. 

This would move insn_has_dfa_reservation_p out of the #if CPU_UNITS_QUERY 
conditional inside of insn-automata.cc. This would allow us to see if the 
scheduler is trying to schedule an insn with a type which is not associated 
with a cpu unit or insn reservation through the TARGET_SCHED_VARIABLE_ISSUE 
hook.

If there is a reason for insn_has_dfa_reservation_p being within the 
conditional, please let me know!

gcc/Changelog:

* genautomata.cc (write_automata): move endif

Signed-off-by: Edwin Lu 
---
 gcc/genautomata.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/genautomata.cc b/gcc/genautomata.cc
index 72f01686d6b..9dda25e5ba2 100644
--- a/gcc/genautomata.cc
+++ b/gcc/genautomata.cc
@@ -9503,9 +9503,9 @@ write_automata (void)
   fprintf (output_file, "\n#if %s\n\n", CPU_UNITS_QUERY_MACRO_NAME);
   output_get_cpu_unit_code_func ();
   output_cpu_unit_reservation_p ();
-  output_insn_has_dfa_reservation_p ();
   fprintf (output_file, "\n#endif /* #if %s */\n\n",
   CPU_UNITS_QUERY_MACRO_NAME);
+  output_insn_has_dfa_reservation_p ();
   output_dfa_clean_insn_cache_func ();
   output_dfa_start_func ();
   output_dfa_finish_func ();
-- 
2.34.1

Re: [RFC] RISC-V: Handle new types in scheduling descriptions

[Edwin Lu]

On 10/10/2023 10:11 AM, Jeff Law wrote:



On 10/9/23 15:02, Edwin Lu wrote:

Now that every insn is guaranteed a type, we want to ensure the types are
handled by the existing scheduling descriptions.

There are 2 approaches I see:
1. Create a new pipeline intended to eventually abort (sifive-7.md)
2. Add the types to an existing pipeline (generic.md)

Which approach do we want to go with? If there is a different approach we
want to take instead, please let me know as well.

Additionally, should types associated with specific extensions
(vector, crypto, etc) have specific pipelines dedicated to them?

* config/riscv/generic.md: update pipeline
* config/riscv/sifive-7.md (sifive_7): update pipeline
(sifive_7_other):
I'd largely expect that we look at an unhandled type and first look to 
see if its properties roughly fit into an existing define_insn_unit.  If 
so, just add it to the existing unit.  Otherwise we end up needing to 
create another unit.


The main types that were added that are not associated with any 
extension would be "trap" type and the "cbo" (cache block operation) 
type. I have added these types to an existing pipeline in the generic.md 
file.


For the vector extension, I don't believe the existing pipelines would 
support those operations. Should I create the pipelines for now?


What would be really interesting would be to see if we can get the 
scheduler to indicate that it's trying to schedule an insn that doesn't 
have a reservation.    ie, our backend tells us if we have an insn with 
no type, the next step is to see if we have a type with no 
units/reservations.



Jeff

Do you happen to have any idea on how to do this or if there are any 
existing mechanisms I should look at? I have been searching around the 
docs to see if there was any way to tell which pipeline (if any) an 
instruction is using when it is not included under a reservation without 
any luck.


Edwin

[RFC] RISC-V: Handle new types in scheduling descriptions

[Edwin Lu]

Now that every insn is guaranteed a type, we want to ensure the types are 
handled by the existing scheduling descriptions. 

There are 2 approaches I see:
1. Create a new pipeline intended to eventually abort (sifive-7.md) 
2. Add the types to an existing pipeline (generic.md)

Which approach do we want to go with? If there is a different approach we
want to take instead, please let me know as well.

Additionally, should types associated with specific extensions 
(vector, crypto, etc) have specific pipelines dedicated to them? 

* config/riscv/generic.md: update pipeline
* config/riscv/sifive-7.md (sifive_7): update pipeline
(sifive_7_other):

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/generic.md  | 3 ++-
 gcc/config/riscv/sifive-7.md | 7 +++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index 57d3c3b4adc..338d2e85b77 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,8 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+   (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,
+ logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop,trap,cbo"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index 526278e46d4..e76d82614d6 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -12,6 +12,8 @@ (define_cpu_unit "sifive_7_B" "sifive_7")
 (define_cpu_unit "sifive_7_idiv" "sifive_7")
 (define_cpu_unit "sifive_7_fpu" "sifive_7")
 
+(define_cpu_unit "sifive_7_abort" "sifive_7")
+
 (define_insn_reservation "sifive_7_load" 3
   (and (eq_attr "tune" "sifive_7")
(eq_attr "type" "load"))
@@ -106,6 +108,11 @@ (define_insn_reservation "sifive_7_f2i" 3
(eq_attr "type" "mfc"))
   "sifive_7_A")
 
+(define_insn_reservation "sifive_7_other" 3
+  (and (eq_attr "tune" "sifive_7")
+   (eq_attr "type" "trap,cbo"))
+  "sifive_7_abort")
+
 (define_bypass 1 
"sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
   "sifive_7_alu,sifive_7_branch")
 
-- 
2.34.1

Re: [Committed] RISC-V: Support VLS INT <-> FP conversions

[Edwin Lu]

Hi Juzhe,

I was testing this patch and found it introduced a gfortran regression 
in gfortran.dg/host_assoc_function_7.f90. More info here: 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545


Edwin

On 9/20/2023 7:17 PM, Juzhe-Zhong wrote:

Support INT <-> FP VLS auto-vectorization patterns.

Regression passed.
Committed.

gcc/ChangeLog:

* config/riscv/autovec.md: Extend VLS modes.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/convert-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/convert-9.c: New test.

---
  gcc/config/riscv/autovec.md   |  12 +-
  gcc/config/riscv/vector-iterators.md  | 202 ++
  gcc/config/riscv/vector.md|  20 +-
  .../riscv/rvv/autovec/vls/convert-1.c |  74 +++
  .../riscv/rvv/autovec/vls/convert-10.c|  80 +++
  .../riscv/rvv/autovec/vls/convert-11.c|  54 +
  .../riscv/rvv/autovec/vls/convert-12.c|  36 
  .../riscv/rvv/autovec/vls/convert-2.c |  74 +++
  .../riscv/rvv/autovec/vls/convert-3.c |  58 +
  .../riscv/rvv/autovec/vls/convert-4.c |  36 
  .../riscv/rvv/autovec/vls/convert-5.c |  80 +++
  .../riscv/rvv/autovec/vls/convert-6.c |  55 +
  .../riscv/rvv/autovec/vls/convert-7.c |  37 
  .../riscv/rvv/autovec/vls/convert-8.c |  58 +
  .../riscv/rvv/autovec/vls/convert-9.c |  22 ++
  15 files changed, 882 insertions(+), 16 deletions(-)
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 75ed7ae4f2e..55c0a04df3b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -847,7 +847,7 @@
  (define_insn_and_split "2"
[(set (match_operand: 0 "register_operand")
(any_fix:
- (match_operand:VF 1 "register_operand")))]
+ (match_operand:V_VLSF 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -868,8 +868,8 @@
  ;; -
  
  (define_insn_and_split "2"

-  [(set (match_operand:VF 0 "register_operand")
-   (any_float:VF
+  [(set (match_operand:V_VLSF 0 "register_operand")
+   (any_float:V_VLSF
  (match_operand: 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -916,8 +916,8 @@
  ;; - vfwcvt.f.x.v
  ;; -
  (define_insn_and_split "2"
-  [(set (match_operand:VF 0 "register_operand")
-   (any_float:VF
+  [(set (match_operand:V_VLSF 0 "register_operand")
+   (any_float:V_VLSF
  (match_operand: 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
@@ -940,7 +940,7 @@
  (define_insn_and_split "2"
[(set (match_operand: 0 "register_operand")
(any_fix:
- (match_operand:VF 1 "register_operand")))]
+ (match_operand:V_VLSF 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 053d84c0c7d..19f3ec3ef74 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ 

Re: [Committed] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Edwin Lu]

On 9/11/2023 5:49 PM, Jeff Law via Gcc-patches wrote:



On 9/11/23 16:52, Edwin Lu wrote:
Updates autovec instruction that was added after last patch and turns 
on the

assert statement to ensure all new instructions have a type.

* config/riscv/autovec-opt.md: Update type
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
"Remove assert" -> "Enable assert."  We're removing the #if 0 guard, not 
the assert itself :-)


OK with the ChangeLog fixed.
jeff


Forgot to update but committed.

Edwin

[PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Edwin Lu]

Updates autovec instruction that was added after last patch and turns on the
assert statement to ensure all new instructions have a type.

* config/riscv/autovec-opt.md: Update type
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/autovec-opt.md | 3 ++-
 gcc/config/riscv/riscv.cc   | 2 --
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 58e80044f1e..f1d058ce911 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -649,7 +649,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine vlmax neg and UNSPEC_VCOPYSIGN
 (define_insn_and_split "*copysign_neg"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 12926b206ac..d3b09543ba0 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7708,11 +7708,9 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, 
int more)
   if (get_attr_type (insn) == TYPE_GHOST)
 return 0;
 
-#if 0
   /* If we ever encounter an insn with an unknown type, trip
  an assert so we can find and fix this problem.  */
   gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN);
-#endif
 
   return more - 1;
 }
-- 
2.34.1

Re: [PATCH 4/5][Committed] RISC-V: Update Types for RISC-V Instructions

[Edwin Lu]

On 9/6/2023 4:23 PM, Kito Cheng via Gcc-patches wrote:

LGTM

Edwin Lu  於 2023年9月7日 週四 01:52 寫道：


This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html

gcc/ChangeLog:

 * config/riscv/riscv.md: Update types

Signed-off-by: Edwin Lu 
---
  gcc/config/riscv/riscv.md | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c329f55db43..c1cecd27815 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmv.x.w\t%0,%1"
[(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
 (set_attr "mode" "DF")])


@@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmvh.x.d\t%0,%1"
[(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
 (set_attr "mode" "DF")])

  (define_insn "movdfsisi3_rv32"
@@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmvp.d.x\t%0,%2,%1"
[(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
 (set_attr "mode" "DF")])

  (define_split
--
2.34.1





Committed!

Edwin

Re: [PATCH 3/5][Committed] RISC-V: Add Types to Un-Typed Zicond Instructions

[Edwin Lu]

On 9/7/2023 6:17 AM, Jeff Law via Gcc-patches wrote:



On 9/6/23 18:42, Tsukasa OI via Gcc-patches wrote:



Looks okay to me but will need to resolve merge conflicts after commit
af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
'Zicond' support").
Sure.  We allow trival updates to resolve merge conflicts without 
needing another round of review.


Jeff


Committed!

Edwin

Re: [PATCH v2 1/5][Committed] RISC-V: Update Types for Vector Instructions

[Edwin Lu]

On 9/8/2023 4:56 PM, Jeff Law via Gcc-patches wrote:



On 9/8/23 12:16, Edwin Lu wrote:
This patch adds types to vector instructions that were added after or 
were

missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Update types
* config/riscv/autovec.md: likewise
I think these were all define_insn_and_splits, so just about anything 
will do.  OK.


jeff


Committed!

Edwin

Re: [PATCH] RISC-V Add Types to Un-Typed Thead Instructions:

[Edwin Lu]

On 9/10/2023 8:37 AM, Jeff Law via Gcc-patches wrote:



On 8/31/23 11:36, Edwin Lu wrote:

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/

This patch updates the THEAD instructions to ensure that no insn is left
without a type attribute.

Tested for regressions using rv32/64 multilib for linux/newlib.

gcc/Changelog:

* config/riscv/thead.md: Update types
OK.  THe first could arguably be "multi", but both instructions it 
generates appear to be move/conversions, so "fmove" is reasonable as well.


Ok for the trunk.  And I think that's should allow us to turn on the 
assertion, right?


jeff

I just did one final check, there's one insn in autovec-opt.md that was 
added (line 635) but otherwise I think that should be it. I've typed it 
"vector" for now and am currently running a test to make sure nothing 
breaks. Would you like me to send another patch for it?


Edwin

[PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions

[Edwin Lu]

This patch adds types to the untyped zc instructions. Creates a new
types "pushpop" and "mvpair" for now

gcc/ChangeLog:

* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types

Signed-off-by: Edwin Lu 
---
Changes in V2:
  - Change "csr" type to "pushpop" and "mvpair"
---
 gcc/config/riscv/riscv.md |   6 ++-
 gcc/config/riscv/zc.md| 102 +++---
 2 files changed, 56 insertions(+), 52 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b630b51ee50..a6046c17fc3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -316,6 +316,8 @@ (define_attr "ext_enabled" "no,yes"
 ;; condmoveconditional moves
 ;; cbocache block instructions
 ;; crypto cryptography instructions
+;; pushpopzc push and pop instructions
+;; mvpairzc move pair instructions
 ;; Classification of RVV instructions which will be added to each RVV .md 
pattern and used by scheduler.
 ;; rdvlenb vector byte length vlenb csrr read
 ;; rdvlvector length vl csrr read
@@ -425,8 +427,8 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
-   atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
-   vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,condmove,cbo,crypto,pushpop,mvpair,rdvlenb,rdvl,wrvxrm,wrfrm,
+   rdfrm,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,

vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 77b28adde95..18b3c30c342 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s0_"
   [(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s1_"
   [(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s1}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s2_"
   [(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s2}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s3_"
   [(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s3}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s4_"
   [(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s4}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s5_"
   [(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s5}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s6_"
   [(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s6}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s7_"
   [(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_"
   (const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s7}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s8_"
   [(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s8}, %0&q

[PATCH v2 1/5] RISC-V: Update Types for Vector Instructions

[Edwin Lu]

This patch adds types to vector instructions that were added after or were
missed by the original patch 
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Update types
* config/riscv/autovec.md: likewise

Signed-off-by: Edwin Lu 
---
Changes in V2:
  - Add types to insns missed by prev version
---
 gcc/config/riscv/autovec-opt.md | 72 ++---
 gcc/config/riscv/autovec.md | 52 
 2 files changed, 83 insertions(+), 41 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 3aaee54f02a..58e80044f1e 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -628,7 +628,8 @@ (define_insn_and_split "*cond_abs"
 gen_int_mode (GET_MODE_NUNITS 
(mode), Pmode),
 const0_rtx));
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine vfsqrt.v and cond_mask
 (define_insn_and_split "*cond_"
@@ -666,7 +667,8 @@ (define_insn_and_split "*copysign_neg"
   riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode),
   riscv_vector::BINARY_OP, operands);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine sign_extend/zero_extend(vf2) and vcond_mask
 (define_insn_and_split "*cond_"
@@ -685,7 +687,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine sign_extend/zero_extend(vf4) and vcond_mask
 (define_insn_and_split "*cond_"
@@ -704,7 +707,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine sign_extend/zero_extend(vf8) and vcond_mask
 (define_insn_and_split "*cond_"
@@ -723,7 +727,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine trunc(vf2) + vcond_mask
 (define_insn_and_split "*cond_trunc"
@@ -743,7 +748,8 @@ (define_insn_and_split "*cond_trunc"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine FP extend(vf2) and vcond_mask
 (define_insn_and_split "*cond_extend"
@@ -762,7 +768,8 @@ (define_insn_and_split "*cond_extend"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine FP trunc(vf2) + vcond_mask
 (define_insn_and_split "*cond_trunc"
@@ -782,7 +789,8 @@ (define_insn_and_split "*cond_trunc"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(FP->INT) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -802,7 +810,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(INT->FP) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -822,7 +831,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(FP->2xINT) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -842,7 +852,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(INT->2xFP) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -862,7 +873,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(2xFP->INT) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -882,7 +894,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};

[PATCH v2 0/5] RISC-V: Add Types to Untyped Instructions

[Edwin Lu]

This series adds types to the remaining untyped instructions.

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/

Also enables assert which checks to make sure every instruction has a type

All patches were tested with rv32/rv64 linux/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs

Edwin Lu (5):
  RISC-V: Update Types for Vector Instructions
  RISC-V: Add Types for Un-Typed zc Instructions
  RISC-V: Add Types to Un-Typed Zicond Instructions
  RISC-V: Add Types to Un-Typed Zicond Instructions
  RISC-V: Remove Assert Protecting Types

 gcc/config/riscv/autovec-opt.md |  72 ++
 gcc/config/riscv/autovec.md |  52 ++--
 gcc/config/riscv/riscv.cc   |   2 -
 gcc/config/riscv/riscv.md   |  10 +++-
 gcc/config/riscv/zc.md  | 102 
 gcc/config/riscv/zicond.md  |   8 +--
 6 files changed, 147 insertions(+), 99 deletions(-)

-- 
2.42.0

Re: [PATCH 5/5] RISC-V: Remove Assert Protecting Types

[Edwin Lu]

On 9/7/2023 6:19 AM, Jeff Law wrote:



On 9/6/23 11:50, Edwin Lu wrote:

This patch turns on the assert which ensures every instruction has type
that is not TYPE_UNKNOWN.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
And this is fine.  But hold off committing until all the dependencies 
are also committed.  I think there's still one earlier patch that I 
wanted to look at again.


jeff


Sounds good to me. The thead instructions were the ones that haven't 
been checked in yet.


Edwin

Re: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

[Edwin Lu]

On 9/6/2023 4:33 PM, Kito Cheng wrote:
csr is kind of confusing, I would suggest something like `pushpop` and 
`mvpair`.



Sounds good! I'll make the update.

Edwin

Re: [PATCH 1/5] RISC-V: Update Types for Vector Instructions

[Edwin Lu]

On 9/6/2023 4:23 PM, Kito Cheng wrote:

LGTM

Edwin Lu  於 2023年9月7日 週四 01:51 寫道：

This patch adds types to vector instructions that were added after
or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html

gcc/ChangeLog:

        * config/riscv/autovec-opt.md: Update types
        * config/riscv/autovec.md: likewise

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/autovec-opt.md | 42
++---
 gcc/config/riscv/autovec.md     | 28 +++---
 2 files changed, 47 insertions(+), 23 deletions(-)

There seems to be around 9 new instructions that were added since this 
patch. I have tested them for the same extensions but only for linux so 
far. I'll submit a new patch later today with those changes


Edwin

[PATCH 5/5] RISC-V: Remove Assert Protecting Types

[Edwin Lu]

This patch turns on the assert which ensures every instruction has type
that is not TYPE_UNKNOWN.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv.cc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ef63079de8e..f0576351cda 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7330,11 +7330,9 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, 
int more)
   if (get_attr_type (insn) == TYPE_GHOST)
 return 0;
 
-#if 0
   /* If we ever encounter an insn with an unknown type, trip
  an assert so we can find and fix this problem.  */
   gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN);
-#endif
 
   return more - 1;
 }
-- 
2.34.1

[PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions

[Edwin Lu]

This patch creates a new "zicond" type and updates all zicond instructions
with that type.

gcc/ChangeLog:

* config/riscv/riscv.md: Add "zicond" type
* config/riscv/zicond.md: Update types

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv.md  | 5 +++--
 gcc/config/riscv/zicond.md | 8 
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6684ad89cff..c329f55db43 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes"
 ;; cbocache block instructions
 ;; crypto cryptography instructions
 ;; csrcode size reduction instructions
+;; zicondzicond instructions
 ;; Classification of RVV instructions which will be added to each RVV .md 
pattern and used by scheduler.
 ;; rdvlenb vector byte length vlenb csrr read
 ;; rdvlvector length vl csrr read
@@ -422,8 +423,8 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
-   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
-   vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,
+   vsetvl, vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,

vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 1721e1011ea..0269bd14399 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -30,7 +30,7 @@ (define_insn "*czero.."
   (const_int 0)))]
   "TARGET_ZICOND"
   "czero.\t%0,%2,%1"
-)
+[(set_attr "type" "zicond")])
 
 (define_insn "*czero.."
   [(set (match_operand:GPR 0 "register_operand" "=r")
@@ -40,7 +40,7 @@ (define_insn "*czero.."
   (match_operand:GPR 2 "register_operand"   "r")))]
   "TARGET_ZICOND"
   "czero.\t%0,%2,%1"
-)
+[(set_attr "type" "zicond")])
 
 ;; Special optimization under eq/ne in primitive semantics
 (define_insn "*czero.eqz..opt1"
@@ -51,7 +51,7 @@ (define_insn "*czero.eqz..opt1"
   (match_operand:GPR 3 "register_operand" "r")))]
   "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
   "czero.eqz\t%0,%3,%1"
-)
+[(set_attr "type" "zicond")])
 
 (define_insn "*czero.nez..opt2"
   [(set (match_operand:GPR 0 "register_operand"   "=r")
@@ -61,7 +61,7 @@ (define_insn "*czero.nez..opt2"
   (match_operand:GPR 3 "register_operand" "1")))]
   "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
   "czero.eqz\t%0,%2,%1"
-)
+[(set_attr "type" "zicond")])
 
 ;; Combine creates this form in some cases (particularly the coremark
 ;; CRC loop.
-- 
2.34.1

[PATCH 4/5] RISC-V: Update Types for RISC-V Instructions

[Edwin Lu]

This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html

gcc/ChangeLog:

* config/riscv/riscv.md: Update types

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c329f55db43..c1cecd27815 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmv.x.w\t%0,%1"
   [(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
(set_attr "mode" "DF")])
 
 
@@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmvh.x.d\t%0,%1"
   [(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
(set_attr "mode" "DF")])
 
 (define_insn "movdfsisi3_rv32"
@@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmvp.d.x\t%0,%2,%1"
   [(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
(set_attr "mode" "DF")])
 
 (define_split
-- 
2.34.1

[PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

[Edwin Lu]

This patch adds types to the untyped zc instructions. Creates a new
type "csr" for these instructions for now.

gcc/ChangeLog:

* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv.md |   3 +-
 gcc/config/riscv/zc.md| 102 +++---
 2 files changed, 54 insertions(+), 51 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d80b6938f84..6684ad89cff 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -312,6 +312,7 @@ (define_attr "ext_enabled" "no,yes"
 ;; condmoveconditional moves
 ;; cbocache block instructions
 ;; crypto cryptography instructions
+;; csrcode size reduction instructions
 ;; Classification of RVV instructions which will be added to each RVV .md 
pattern and used by scheduler.
 ;; rdvlenb vector byte length vlenb csrr read
 ;; rdvlvector length vl csrr read
@@ -421,7 +422,7 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
-   atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
+   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,

vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 77b28adde95..86f1afd66cb 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s0_"
   [(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s1_"
   [(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s1}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s2_"
   [(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s2}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s3_"
   [(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s3}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s4_"
   [(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s4}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s5_"
   [(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s5}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s6_"
   [(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s6}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s7_"
   [(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_"
   (const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s7}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s8_"
   [(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s8}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s9_"
   [(set (reg:X SP_REGNUM)
@@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_"
(const_int ]
   "TARGET_ZCMP"
   

[PATCH 1/5] RISC-V: Update Types for Vector Instructions

[Edwin Lu]

This patch adds types to vector instructions that were added after or were
missed by the original patch 
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Update types
* config/riscv/autovec.md: likewise

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/autovec-opt.md | 42 ++---
 gcc/config/riscv/autovec.md | 28 +++---
 2 files changed, 47 insertions(+), 23 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 1ca5ce97193..6cc1a01629c 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs"
 gen_int_mode (GET_MODE_NUNITS 
(mode), Pmode),
 const0_rtx));
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine vlmax neg and UNSPEC_VCOPYSIGN
 (define_insn_and_split "*copysign_neg"
@@ -746,7 +747,8 @@ (define_insn_and_split "*copysign_neg"
   riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode),
   riscv_vector::BINARY_OP, operands);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine sign_extend/zero_extend(vf2) and vcond_mask
 (define_insn_and_split "*cond_"
@@ -765,7 +767,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine sign_extend/zero_extend(vf4) and vcond_mask
 (define_insn_and_split "*cond_"
@@ -784,7 +787,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine sign_extend/zero_extend(vf8) and vcond_mask
 (define_insn_and_split "*cond_"
@@ -803,7 +807,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine trunc(vf2) + vcond_mask
 (define_insn_and_split "*cond_trunc"
@@ -823,7 +828,8 @@ (define_insn_and_split "*cond_trunc"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask
 (define_insn_and_split "*cond_extend"
@@ -842,7 +848,8 @@ (define_insn_and_split "*cond_extend"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine FP trunc(vf2) + vcond_mask
 (define_insn_and_split "*cond_trunc"
@@ -862,7 +869,8 @@ (define_insn_and_split "*cond_trunc"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(FP->INT) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -882,7 +890,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(INT->FP) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -902,7 +911,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(FP->2xINT) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -922,7 +932,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(INT->2xFP) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -942,7 +953,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine convert(2xFP->INT) + vcond_mask
 (define_insn_and_split "*cond_"
@@ -962,7 +974,8 @@ (define_insn_and_split "*cond_"
gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
   riscv_vector::expand_cond_len_unop (ic

[PATCH 0/5] RISC-V: Add Types to Untyped Instructions

[Edwin Lu]

This series adds types to the remaining untyped instructions.

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/

Also enables assert which checks to make sure every instruction has a type

All patches were tested with rv32/rv64 linux/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs

Edwin Lu (5):
  RISC-V: Update Types for Vector Instructions
  RISC-V: Add Types for Un-Typed zc Instructions
  RISC-V: Add Types to Un-Typed Zicond Instructions
  RISC-V: Add Types to Un-Typed Zicond Instructions
  RISC-V: Remove Assert Protecting Types

 gcc/config/riscv/autovec-opt.md |  42 -
 gcc/config/riscv/autovec.md |  28 ++---
 gcc/config/riscv/riscv.cc   |   2 -
 gcc/config/riscv/riscv.md   |   9 ++-
 gcc/config/riscv/zc.md  | 102 
 gcc/config/riscv/zicond.md  |   8 +--
 6 files changed, 110 insertions(+), 81 deletions(-)

-- 
2.34.1

Re: [Committed] RISC-V: Add Types to Un-Typed Risc-v Instructions:

[Edwin Lu]

On 9/1/2023 11:02 AM, Jeff Law wrote:



On 8/31/23 11:32, Edwin Lu wrote:

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/ 



This patch updates the riscv instructions to ensure that no insn is left
without a type attribute. Added new types: "trap" (self explanatory) 
and "cbo"

(for cache related instructions)

Tested for regressions using rv32/64 multilib for linux/newlib. Also 
tested

rv32/64 gcv for linux.

gcc/Changelog:

* config/riscv/riscv.md: Update/Add types

OK.

jeff


Committed!

Edwin

Re: [Committed] Add Types to Un-Typed Pic Instructions:

[Edwin Lu]

On 9/1/2023 6:15 AM, Jeff Law wrote:



On 8/31/23 17:01, Edwin Lu wrote:

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/ 



This patch updates the pic instructions to ensure that no insn is left
without a type attribute.

Tested for regressions using rv32/64 multilib with newlib/linux.

gcc/Changelog:

* config/riscv/pic.md: Update types

OK.  THanks.
jeff


Committed!

Edwin

[PATCH] Add Types to Un-Typed Pic Instructions:

[Edwin Lu]

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/

This patch updates the pic instructions to ensure that no insn is left
without a type attribute.

Tested for regressions using rv32/64 multilib with newlib/linux. 

gcc/Changelog:

* config/riscv/pic.md: Update types

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/pic.md | 30 --
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md
index da636e31619..cfaa670caf0 100644
--- a/gcc/config/riscv/pic.md
+++ b/gcc/config/riscv/pic.md
@@ -27,21 +27,24 @@ (define_insn "*local_pic_load"
(mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
   "USE_LOAD_ADDRESS_MACRO (operands[1])"
   "\t%0,%1"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "load")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "*local_pic_load_s"
   [(set (match_operand:SUPERQI 0 "register_operand" "=r")
(sign_extend:SUPERQI (mem:SUBX (match_operand 1 
"absolute_symbolic_operand" ""]
   "USE_LOAD_ADDRESS_MACRO (operands[1])"
   "\t%0,%1"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "load")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "*local_pic_load_u"
   [(set (match_operand:SUPERQI 0 "register_operand" "=r")
(zero_extend:SUPERQI (mem:SUBX (match_operand 1 
"absolute_symbolic_operand" ""]
   "USE_LOAD_ADDRESS_MACRO (operands[1])"
   "u\t%0,%1"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "load")
+   (set (attr "length") (const_int 8))])
 
 ;; We can support ANYLSF loads into X register if there is no double support
 ;; or if the target is 64-bit.
@@ -55,7 +58,8 @@ (define_insn "*local_pic_load"
   "@
\t%0,%1,%2
\t%0,%1"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "fpload")
+   (set (attr "length") (const_int 8))])
 
 ;; ??? For a 32-bit target with double float, a DF load into a X reg isn't
 ;; supported.  ld is not valid in that case.  Punt for now.  Maybe add a split
@@ -68,14 +72,16 @@ (define_insn "*local_pic_load_32d"
   "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
&& (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)"
   "\t%0,%1,%2"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "fpload")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "*local_pic_load_sf"
   [(set (match_operand:SOFTF 0 "register_operand" "=r")
(mem:SOFTF (match_operand 1 "absolute_symbolic_operand" "")))]
   "!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])"
   "\t%0,%1"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "fpload")
+   (set (attr "length") (const_int 8))])
 
 ;; Simplify PIC stores to static variables.
 ;; These should go away once we figure out how to emit auipc discretely.
@@ -86,7 +92,8 @@ (define_insn "*local_pic_store"
(clobber (match_scratch:P 2 "="))]
   "USE_LOAD_ADDRESS_MACRO (operands[0])"
   "\t%z1,%0,%2"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "store")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "*local_pic_store"
   [(set (mem:ANYLSF (match_operand 0 "absolute_symbolic_operand" ""))
@@ -97,7 +104,8 @@ (define_insn "*local_pic_store"
   "@
\t%1,%0,%2
\t%1,%0,%2"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "fpstore")
+   (set (attr "length") (const_int 8))])
 
 ;; ??? For a 32-bit target with double float, a DF store from a X reg isn't
 ;; supported.  sd is not valid in that case.  Punt for now.  Maybe add a split
@@ -110,7 +118,8 @@ (define_insn "*local_pic_store_32d"
   "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
&& (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)"
   "\t%1,%0,%2"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "fpstore")
+   (set (attr "length") (const_int 8))])
 
 (define_insn "*local_pic_store_sf"
   [(set (mem:SOFTF (match_operand 0 "absolute_symbolic_operand" ""))
@@ -118,4 +127,5 @@ (define_insn "*local_pic_store_sf"
(clobber (match_scratch:P 2 "="))]
   "!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])"
   "\t%1,%0,%2"
-  [(set (attr "length") (const_int 8))])
+  [(set_attr "type" "fpstore")
+   (set (attr "length") (const_int 8))])
-- 
2.34.1

[PATCH] RISC-V Add Types to Un-Typed Thead Instructions:

[Edwin Lu]

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/

This patch updates the THEAD instructions to ensure that no insn is left
without a type attribute. 

Tested for regressions using rv32/64 multilib for linux/newlib. 

gcc/Changelog:

* config/riscv/thead.md: Update types

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/thead.md | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 29f98dec3a8..6e63cb946e4 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -169,6 +169,7 @@ (define_insn "th_fmv_hw_w_x"
   "!TARGET_64BIT && TARGET_XTHEADFMV"
   "fmv.w.x\t%0,%2\n\tth.fmv.hw.x\t%0,%1"
   [(set_attr "move_type" "move")
+   (set_attr "type" "fmove")
(set_attr "mode" "DF")])
 
 (define_insn "th_fmv_x_w"
@@ -178,6 +179,7 @@ (define_insn "th_fmv_x_w"
   "!TARGET_64BIT && TARGET_XTHEADFMV"
   "fmv.x.w\t%0,%1"
   [(set_attr "move_type" "move")
+   (set_attr "type" "fmove")
(set_attr "mode" "DF")])
 
 (define_insn "th_fmv_x_hw"
@@ -187,6 +189,7 @@ (define_insn "th_fmv_x_hw"
   "!TARGET_64BIT && TARGET_XTHEADFMV"
   "th.fmv.x.hw\t%0,%1"
   [(set_attr "move_type" "move")
+   (set_attr "type" "fmove")
(set_attr "mode" "DF")])
 
 ;; XTheadMac
@@ -322,6 +325,7 @@ (define_insn "*th_mempair_load_2"
&& th_mempair_operands_p (operands, true, mode)"
   { return th_mempair_output_move (operands, true, mode, UNKNOWN); }
   [(set_attr "move_type" "load")
+   (set_attr "type" "load")
(set_attr "mode" "")])
 
 ;; MEMPAIR store 64/32 bit
@@ -334,6 +338,7 @@ (define_insn "*th_mempair_store_2"
&& th_mempair_operands_p (operands, false, mode)"
   { return th_mempair_output_move (operands, false, mode, UNKNOWN); }
   [(set_attr "move_type" "store")
+   (set_attr "type" "store")
(set_attr "mode" "")])
 
 ;; MEMPAIR load DI extended signed SI
@@ -346,6 +351,7 @@ (define_insn "*th_mempair_load_extendsidi2"
&& th_mempair_operands_p (operands, true, SImode)"
   { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
   [(set_attr "move_type" "load")
+   (set_attr "type" "load")
(set_attr "mode" "DI")
(set_attr "length" "8")])
 
@@ -359,6 +365,7 @@ (define_insn "*th_mempair_load_zero_extendsidi2"
&& th_mempair_operands_p (operands, true, SImode)"
   { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
   [(set_attr "move_type" "load")
+   (set_attr "type" "load")
(set_attr "mode" "DI")
(set_attr "length" "8")])
 
-- 
2.34.1