Re: Re: [PATCH] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c
Committed, thanks. xu...@eswincomputing.com From: Robin Dapp Date: 2024-05-21 22:58 To: juzhe.zh...@rivai.ai; Li Xu; gcc-patches CC: rdapp.gcc; kito.cheng; palmer; tamar.christina; Richard Biener; richard.sandiford; zhengyu; pan2.li Subject: Re: [PATCH] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c The patch is OK from the riscv side. generic-ooo includes fast unaligned access. Regards Robin
[PATCH] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c
From: xuli
Because "targetm.slow_unaligned_access" is set to true by default
(aka -mtune=rocket) for RISC-V, it causes the __builtin_memcpy with
8 bytes failed to folded into int64 assignment during ccp1.
So adding "-mtune=generic-ooo" to the RISC-V target can vectorize
vect-early-break_124-pr114403.c.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-early-break_124-pr114403.c: Enable vectrization for
RISC-V target.
---
gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c
b/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c
index 101ae1e0eaa..610b951b262 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c
@@ -1,8 +1,9 @@
/* { dg-add-options vect_early_break } */
/* { dg-require-effective-target vect_early_break_hw } */
/* { dg-require-effective-target vect_long_long } */
+/* { dg-additional-options "-mtune=generic-ooo" { target riscv*-*-* } } */
-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { xfail riscv*-*-* } }
} */
+/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */
#include "tree-vect.h"
@@ -74,4 +75,3 @@ int main ()
return 0;
}
-
--
2.17.1
[PATCH v2] RISC-V: Add riscv_vector_cc function attribute
From: xuli
Standard vector calling convention variant will only enabled when function
has vector argument or returning value by default, however user may also
want to invoke function without that during a vectorized loop at some situation,
but it will cause a huge performance penalty due to vector register
store/restore.
So user can declare function with this riscv_vector_cc attribute like below,
that could enforce
function will use standard vector calling convention variant.
void foo() __attribute__((riscv_vector_cc));
[[riscv::vector_cc]] void foo(); // For C++11 and C23
For more details please reference the below link.
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67
gcc/ChangeLog:
* config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
attribute to riscv_attribute_table.
(riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc
function.
(riscv_fntype_abi): Add riscv_vector_cc attribute check.
* doc/extend.texi: Add riscv_vector_cc attribute description.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test.
* gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c:
New test.
* gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test.
---
gcc/config/riscv/riscv.cc | 55 ---
gcc/doc/extend.texi | 10
.../base/attribute-riscv_vector_cc-error.C| 21 +++
.../attribute-riscv_vector_cc-callee-saved.c | 30 ++
.../base/attribute-riscv_vector_cc-error.c| 11
5 files changed, 119 insertions(+), 8 deletions(-)
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4100abc9dd1..7f37f231796 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -537,24 +537,52 @@ static tree riscv_handle_fndecl_attribute (tree *, tree,
tree, int, bool *);
static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
/* Defining target-specific uses of __attribute__. */
-TARGET_GNU_ATTRIBUTES (riscv_attribute_table,
+static const attribute_spec riscv_gnu_attributes[] =
{
/* Syntax: { name, min_len, max_len, decl_required, type_required,
function_type_required, affects_type_identity, handler,
exclude } */
/* The attribute telling no prologue/epilogue. */
- { "naked", 0, 0, true, false, false, false,
-riscv_handle_fndecl_attribute, NULL },
+ {"naked", 0, 0, true, false, false, false, riscv_handle_fndecl_attribute,
+ NULL},
/* This attribute generates prologue/epilogue for interrupt handlers. */
- { "interrupt", 0, 1, false, true, true, false,
-riscv_handle_type_attribute, NULL },
+ {"interrupt", 0, 1, false, true, true, false, riscv_handle_type_attribute,
+ NULL},
/* The following two are used for the built-in properties of the Vector type
and are not used externally */
{"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL},
- {"RVV type", 0, 0, false, true, false, true, NULL, NULL}
-});
+ {"RVV type", 0, 0, false, true, false, true, NULL, NULL},
+ /* This attribute is used to declare a function, forcing it to use the
+standard vector calling convention variant. Syntax:
+__attribute__((riscv_vector_cc)). */
+ {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL}
+};
+
+static const scoped_attribute_specs riscv_gnu_attribute_table =
+{
+ "gnu", {riscv_gnu_attributes}
+};
+
+static const attribute_spec riscv_attributes[] =
+{
+ /* This attribute is used to declare a function, forcing it to use the
+ standard vector calling convention variant. Syntax:
+ [[riscv::vector_cc]]. */
+ {"vector_cc", 0, 0, false, true, true, true, NULL, NULL}
+};
+
+static const scoped_attribute_specs riscv_nongnu_attribute_table =
+{
+ "riscv", {riscv_attributes}
+};
+
+static const scoped_attribute_specs *const riscv_attribute_table[] =
+{
+ _gnu_attribute_table,
+ _nongnu_attribute_table
+};
/* Order for the CLOBBERs/USEs of gpr_save. */
static const unsigned gpr_save_reg_order[] = {
@@ -5425,6 +5453,16 @@ riscv_arguments_is_vector_type_p (const_tree fntype)
return false;
}
+/* Return true if FUNC is a riscv_vector_cc function.
+ For more details please reference the below link.
+ https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
+static bool
+riscv_vector_cc_function_p (const_tree fntype)
+{
+ return lookup_attribute ("vector_cc", TYPE_ATTRIBUTES (fntype)) != NULL_TREE
+|| lookup_attribute ("riscv_vector_cc", TYPE_ATTRIBUTES (fntype)) !=
NULL_TREE;
+}
+
/* Implement TARGET_FNTYPE_ABI. */
Re: [PATCH] RISC-V: Add riscv_vector_cc function attribute
Ping.
xu...@eswincomputing.com
From: Li Xu
Date: 2024-02-27 09:17
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; xuli
Subject: [PATCH] RISC-V: Add riscv_vector_cc function attribute
From: xuli
Standard vector calling convention variant will only enabled when function
has vector argument or returning value by default, however user may also
want to invoke function without that during a vectorized loop at some situation,
but it will cause a huge performance penalty due to vector register
store/restore.
So user can declare function with this riscv_vector_cc attribute like below,
that could enforce
function will use standard vector calling convention variant.
void foo() __attribute__((riscv_vector_cc));
[[riscv::vector_cc]] void foo(); // For C++11 and C23
For more details please reference the below link.
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67
gcc/ChangeLog:
* config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
attribute to riscv_attribute_table.
(riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
(riscv_fntype_abi): Add riscv_vector_cc attribute check.
* doc/extend.texi: Add riscv_vector_cc attribute description.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test.
* gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c: New test.
* gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test.
---
gcc/config/riscv/riscv.cc | 55 ++--
gcc/doc/extend.texi | 12 ++
.../base/attribute-riscv_vector_cc-error.C| 22
.../attribute-riscv_vector_cc-callee-saved.c | 117 ++
.../base/attribute-riscv_vector_cc-error.c| 11 ++
5 files changed, 209 insertions(+), 8 deletions(-)
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4100abc9dd1..7f37f231796 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -537,24 +537,52 @@ static tree riscv_handle_fndecl_attribute (tree *, tree,
tree, int, bool *);
static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
/* Defining target-specific uses of __attribute__. */
-TARGET_GNU_ATTRIBUTES (riscv_attribute_table,
+static const attribute_spec riscv_gnu_attributes[] =
{
/* Syntax: { name, min_len, max_len, decl_required, type_required,
function_type_required, affects_type_identity, handler,
exclude } */
/* The attribute telling no prologue/epilogue. */
- { "naked", 0, 0, true, false, false, false,
-riscv_handle_fndecl_attribute, NULL },
+ {"naked", 0, 0, true, false, false, false, riscv_handle_fndecl_attribute,
+ NULL},
/* This attribute generates prologue/epilogue for interrupt handlers. */
- { "interrupt", 0, 1, false, true, true, false,
-riscv_handle_type_attribute, NULL },
+ {"interrupt", 0, 1, false, true, true, false, riscv_handle_type_attribute,
+ NULL},
/* The following two are used for the built-in properties of the Vector type
and are not used externally */
{"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL},
- {"RVV type", 0, 0, false, true, false, true, NULL, NULL}
-});
+ {"RVV type", 0, 0, false, true, false, true, NULL, NULL},
+ /* This attribute is used to declare a function, forcing it to use the
+standard vector calling convention variant. Syntax:
+__attribute__((riscv_vector_cc)). */
+ {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL}
+};
+
+static const scoped_attribute_specs riscv_gnu_attribute_table =
+{
+ "gnu", {riscv_gnu_attributes}
+};
+
+static const attribute_spec riscv_attributes[] =
+{
+ /* This attribute is used to declare a function, forcing it to use the
+ standard vector calling convention variant. Syntax:
+ [[riscv::vector_cc]]. */
+ {"vector_cc", 0, 0, false, true, true, true, NULL, NULL}
+};
+
+static const scoped_attribute_specs riscv_nongnu_attribute_table =
+{
+ "riscv", {riscv_attributes}
+};
+
+static const scoped_attribute_specs *const riscv_attribute_table[] =
+{
+ _gnu_attribute_table,
+ _nongnu_attribute_table
+};
/* Order for the CLOBBERs/USEs of gpr_save. */
static const unsigned gpr_save_reg_order[] = {
@@ -5425,6 +5453,16 @@ riscv_arguments_is_vector_type_p (const_tree fntype)
return false;
}
+/* Return true if FUNC is a riscv_vector_cc function.
+ For more details please reference the below link.
+ https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
+static bool
+riscv_vector_cc_function_p (const_tree fn
[PATCH] RISC-V: Add riscv_vector_cc function attribute
From: xuli
Standard vector calling convention variant will only enabled when function
has vector argument or returning value by default, however user may also
want to invoke function without that during a vectorized loop at some situation,
but it will cause a huge performance penalty due to vector register
store/restore.
So user can declare function with this riscv_vector_cc attribute like below,
that could enforce
function will use standard vector calling convention variant.
void foo() __attribute__((riscv_vector_cc));
[[riscv::vector_cc]] void foo(); // For C++11 and C23
For more details please reference the below link.
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67
gcc/ChangeLog:
* config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
attribute to riscv_attribute_table.
(riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc
function.
(riscv_fntype_abi): Add riscv_vector_cc attribute check.
* doc/extend.texi: Add riscv_vector_cc attribute description.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test.
* gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c:
New test.
* gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test.
---
gcc/config/riscv/riscv.cc | 55 ++--
gcc/doc/extend.texi | 12 ++
.../base/attribute-riscv_vector_cc-error.C| 22
.../attribute-riscv_vector_cc-callee-saved.c | 117 ++
.../base/attribute-riscv_vector_cc-error.c| 11 ++
5 files changed, 209 insertions(+), 8 deletions(-)
create mode 100644
gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4100abc9dd1..7f37f231796 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -537,24 +537,52 @@ static tree riscv_handle_fndecl_attribute (tree *, tree,
tree, int, bool *);
static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
/* Defining target-specific uses of __attribute__. */
-TARGET_GNU_ATTRIBUTES (riscv_attribute_table,
+static const attribute_spec riscv_gnu_attributes[] =
{
/* Syntax: { name, min_len, max_len, decl_required, type_required,
function_type_required, affects_type_identity, handler,
exclude } */
/* The attribute telling no prologue/epilogue. */
- { "naked", 0, 0, true, false, false, false,
-riscv_handle_fndecl_attribute, NULL },
+ {"naked", 0, 0, true, false, false, false, riscv_handle_fndecl_attribute,
+ NULL},
/* This attribute generates prologue/epilogue for interrupt handlers. */
- { "interrupt", 0, 1, false, true, true, false,
-riscv_handle_type_attribute, NULL },
+ {"interrupt", 0, 1, false, true, true, false, riscv_handle_type_attribute,
+ NULL},
/* The following two are used for the built-in properties of the Vector type
and are not used externally */
{"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL},
- {"RVV type", 0, 0, false, true, false, true, NULL, NULL}
-});
+ {"RVV type", 0, 0, false, true, false, true, NULL, NULL},
+ /* This attribute is used to declare a function, forcing it to use the
+standard vector calling convention variant. Syntax:
+__attribute__((riscv_vector_cc)). */
+ {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL}
+};
+
+static const scoped_attribute_specs riscv_gnu_attribute_table =
+{
+ "gnu", {riscv_gnu_attributes}
+};
+
+static const attribute_spec riscv_attributes[] =
+{
+ /* This attribute is used to declare a function, forcing it to use the
+ standard vector calling convention variant. Syntax:
+ [[riscv::vector_cc]]. */
+ {"vector_cc", 0, 0, false, true, true, true, NULL, NULL}
+};
+
+static const scoped_attribute_specs riscv_nongnu_attribute_table =
+{
+ "riscv", {riscv_attributes}
+};
+
+static const scoped_attribute_specs *const riscv_attribute_table[] =
+{
+ _gnu_attribute_table,
+ _nongnu_attribute_table
+};
/* Order for the CLOBBERs/USEs of gpr_save. */
static const unsigned gpr_save_reg_order[] = {
@@ -5425,6 +5453,16 @@ riscv_arguments_is_vector_type_p (const_tree fntype)
return false;
}
+/* Return true if FUNC is a riscv_vector_cc function.
+ For more details please reference the below link.
+ https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
+static bool
+riscv_vector_cc_function_p (const_tree fntype)
+{
+ return lookup_attribute ("vector_cc", TYPE_ATTRIBUTES (fntype)) != NULL_TREE
+|| lookup_attribute ("riscv_vector_cc", TYPE_ATTRIBUTES (fntype)) !=
NULL_TREE;
+}
+
/* Implement TARGET_FNTYPE_ABI. */
Re: Re: [PATCH v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
Committed, thanks
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2024-01-22 14:40
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-22 12:11
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
From: xuli
v2:
Avoid internal ICE for the case below.
vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t vm, const int32_t *rs1, size_t vl) {
return __riscv_vle8(vm, rs1, vl);
}
v1:
Change the hash value of overloaded intrinsic from considering
all parameter types to:
1. Encoding vector data type
2. In order to distinguish vle8_v_i8mf8_m(vbool64_t vm, const int8_t *rs1,
size_t vl)
and vle8_v_u8mf8_m(vbool64_t vm, const uint8_t *rs1, size_t vl), encode the
pointer type
3. In order to distinguish vfadd_vv_f32mf2_rm(vfloat32mf2_t vs2, vfloat32mf2_t
vs1, size_t vl)
and vfadd_vv_f32mf2(vfloat32mf2_t vs2, vfloat32mf2_t vs1, size_t vl), encode
the number of
parameters. The same goes for the vxrm intrinsics.
PR target/113420
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
(registered_function::overloaded_hash):refacotr.
(resolve_overloaded_builtin):avoid interal ICE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113420-1.c: New test.
* gcc.target/riscv/rvv/base/pr113420-2.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.cc | 93 ---
.../gcc.target/riscv/rvv/base/pr113420-1.c| 30 ++
.../gcc.target/riscv/rvv/base/pr113420-2.c| 31 +++
3 files changed, 77 insertions(+), 77 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr113420-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr113420-2.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 25e0b6e56de..c0e7af482da 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4271,24 +4271,22 @@ registered_function::overloaded_hash () const
: TYPE_UNSIGNED (type);
mode_p = POINTER_TYPE_P (type) ? TYPE_MODE (TREE_TYPE (type))
: TYPE_MODE (type);
- h.add_int (unsigned_p);
- h.add_int (mode_p);
+ if (POINTER_TYPE_P (type) || lookup_vector_type_attribute (type))
+ {
+ h.add_int (unsigned_p);
+ h.add_int (mode_p);
+ }
+ else if (instance.base->may_require_vxrm_p ()
+|| instance.base->may_require_frm_p ())
+ {
+ h.add_int (argument_types.length ());
+ break;
+ }
}
return h.end ();
}
-bool
-has_vxrm_or_frm_p (function_instance , const vec
)
-{
- if (instance.base->may_require_vxrm_p ()
- || (instance.base->may_require_frm_p ()
- && (TREE_CODE (TREE_TYPE (arglist[arglist.length () - 2]))
- == INTEGER_TYPE)))
-return true;
- return false;
-}
-
hashval_t
registered_function::overloaded_hash (const vec )
{
@@ -4296,68 +4294,8 @@ registered_function::overloaded_hash (const vec )
unsigned int len = arglist.length ();
for (unsigned int i = 0; i < len; i++)
-{
- /* vint8m1_t __riscv_vget_i8m1(vint8m2_t src, size_t index);
- When the user calls vget intrinsic, the __riscv_vget_i8m1(src, 1)
- form is used. The compiler recognizes that the parameter index is signed
- int, which is inconsistent with size_t, so the index is converted to
- size_t type in order to get correct hash value. vint8m2_t
- __riscv_vset(vint8m2_t dest, size_t index, vint8m1_t value); The reason
- is the same as above. */
- if ((instance.base == bases::vget && (i == (len - 1)))
- || ((instance.base == bases::vset
- || instance.shape == shapes::crypto_vi)
- && (i == (len - 2
- argument_types.safe_push (size_type_node);
- /* Vector fixed-point arithmetic instructions requiring argument vxrm.
- For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2,
- vuint32m4_t vs1, unsigned int vxrm, size_t vl); The user calls vaaddu
- intrinsic in the form of __riscv_vaaddu(vs2, vs1, 2, vl). The compiler
- recognizes that the parameter vxrm is a signed int, which is inconsistent
- with the parameter unsigned int vxrm declared by intrinsic, so the
- parameter vxrm is converted to an unsigned int type in order to get
- correct hash value.
-
- Vector Floating-Point Instructions requiring argument frm.
- DEF_RVV_FUNCTION (vfadd, alu, full_preds, f_vvv_ops)
- DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops)
- Taking vfadd as an example, theoretically we can add base or shape to the
- hash value to distinguish whether the frm parameter is required.
- vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, float32_t rs1, size_t vl);
- vflo
[PATCH v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
From: xuli
v2:
Avoid internal ICE for the case below.
vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t vm, const int32_t *rs1, size_t vl) {
return __riscv_vle8(vm, rs1, vl);
}
v1:
Change the hash value of overloaded intrinsic from considering
all parameter types to:
1. Encoding vector data type
2. In order to distinguish vle8_v_i8mf8_m(vbool64_t vm, const int8_t *rs1,
size_t vl)
and vle8_v_u8mf8_m(vbool64_t vm, const uint8_t *rs1, size_t vl), encode the
pointer type
3. In order to distinguish vfadd_vv_f32mf2_rm(vfloat32mf2_t vs2, vfloat32mf2_t
vs1, size_t vl)
and vfadd_vv_f32mf2(vfloat32mf2_t vs2, vfloat32mf2_t vs1, size_t vl), encode
the number of
parameters. The same goes for the vxrm intrinsics.
PR target/113420
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
(registered_function::overloaded_hash):refacotr.
(resolve_overloaded_builtin):avoid interal ICE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113420-1.c: New test.
* gcc.target/riscv/rvv/base/pr113420-2.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.cc | 93 ---
.../gcc.target/riscv/rvv/base/pr113420-1.c| 30 ++
.../gcc.target/riscv/rvv/base/pr113420-2.c| 31 +++
3 files changed, 77 insertions(+), 77 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr113420-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr113420-2.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 25e0b6e56de..c0e7af482da 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4271,24 +4271,22 @@ registered_function::overloaded_hash () const
: TYPE_UNSIGNED (type);
mode_p = POINTER_TYPE_P (type) ? TYPE_MODE (TREE_TYPE (type))
: TYPE_MODE (type);
- h.add_int (unsigned_p);
- h.add_int (mode_p);
+ if (POINTER_TYPE_P (type) || lookup_vector_type_attribute (type))
+ {
+ h.add_int (unsigned_p);
+ h.add_int (mode_p);
+ }
+ else if (instance.base->may_require_vxrm_p ()
+ || instance.base->may_require_frm_p ())
+ {
+ h.add_int (argument_types.length ());
+ break;
+ }
}
return h.end ();
}
-bool
-has_vxrm_or_frm_p (function_instance , const vec
)
-{
- if (instance.base->may_require_vxrm_p ()
- || (instance.base->may_require_frm_p ()
- && (TREE_CODE (TREE_TYPE (arglist[arglist.length () - 2]))
- == INTEGER_TYPE)))
-return true;
- return false;
-}
-
hashval_t
registered_function::overloaded_hash (const vec )
{
@@ -4296,68 +4294,8 @@ registered_function::overloaded_hash (const vec )
unsigned int len = arglist.length ();
for (unsigned int i = 0; i < len; i++)
-{
- /* vint8m1_t __riscv_vget_i8m1(vint8m2_t src, size_t index);
-When the user calls vget intrinsic, the __riscv_vget_i8m1(src, 1)
- form is used. The compiler recognizes that the parameter index is signed
- int, which is inconsistent with size_t, so the index is converted to
- size_t type in order to get correct hash value. vint8m2_t
- __riscv_vset(vint8m2_t dest, size_t index, vint8m1_t value); The reason
- is the same as above. */
- if ((instance.base == bases::vget && (i == (len - 1)))
- || ((instance.base == bases::vset
- || instance.shape == shapes::crypto_vi)
- && (i == (len - 2
- argument_types.safe_push (size_type_node);
- /* Vector fixed-point arithmetic instructions requiring argument vxrm.
-For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2,
- vuint32m4_t vs1, unsigned int vxrm, size_t vl); The user calls vaaddu
- intrinsic in the form of __riscv_vaaddu(vs2, vs1, 2, vl). The compiler
- recognizes that the parameter vxrm is a signed int, which is inconsistent
- with the parameter unsigned int vxrm declared by intrinsic, so the
- parameter vxrm is converted to an unsigned int type in order to get
- correct hash value.
-
- Vector Floating-Point Instructions requiring argument frm.
- DEF_RVV_FUNCTION (vfadd, alu, full_preds, f_vvv_ops)
- DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops)
- Taking vfadd as an example, theoretically we can add base or shape to the
- hash value to distinguish whether the frm parameter is required.
- vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, float32_t rs1, size_t vl);
- vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, vfloat32m1_t vs1, unsigned
int
- frm, size_t vl);
-
- However, the current registration mechanism of overloaded intinsic
for gcc
- limits the intrinsic obtained by entering the hook to always be vfadd,
not
- vfadd_frm. Therefore, the correct
Re: Re: [PATCH] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
you are right.
vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t vm, const int32_t *rs1, size_t vl) {
return __riscv_vle8(vm, rs1, vl);
}
This will cause ICE. I tried clang and it will also cause ICE.
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2024-01-19 15:53
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; zhengyu; pan2.li; Li Xu
Subject: Re: [PATCH] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
Could you add a test for vle with mask?
For example:
__riscv_vle8 which overload __riscv_vle8_v_i8mf8_m and __riscv_vle8_v_u8mf8_m
You are using pointer type and mask type to resolve it.
So this pointer type is expecting const int8_t or const uint8_t.
Could you add test:
1.__riscv_vle8 (const int8_t *...)
2. __riscv_vle8 (const uint8_t *...)
3. __riscv_vle8 (const int32_t *...) ---> I worry this will cause ICE since
pointer type doesn't match the expecting type,
I wonder whether it will cause ICE while resolving API.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-19 15:44
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; pan2.li; xuli
Subject: [PATCH] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
From: xuli
Change the hash value of overloaded intrinsic from considering
all parameter types to:
1. Encoding vector data type
2. In order to distinguish vle8_v_i8mf8_m(vbool64_t vm, const int8_t *rs1,
size_t vl)
and vle8_v_u8mf8_m(vbool64_t vm, const uint8_t *rs1, size_t vl), encode the
pointer type
3. In order to distinguish vfadd_vv_f32mf2_rm(vfloat32mf2_t vs2, vfloat32mf2_t
vs1, size_t vl)
and vfadd_vv_f32mf2(vfloat32mf2_t vs2, vfloat32mf2_t vs1, size_t vl), encode
the number of
parameters. The same goes for the vxrm intrinsics.
PR target/113420
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p): remove.
(registered_function::overloaded_hash): refactor.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113420.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.cc | 88 +++
.../gcc.target/riscv/rvv/base/pr113420.c | 30 +++
2 files changed, 43 insertions(+), 75 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr113420.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 25e0b6e56de..5240f9e1f02 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4271,24 +4271,22 @@ registered_function::overloaded_hash () const
: TYPE_UNSIGNED (type);
mode_p = POINTER_TYPE_P (type) ? TYPE_MODE (TREE_TYPE (type))
: TYPE_MODE (type);
- h.add_int (unsigned_p);
- h.add_int (mode_p);
+ if (POINTER_TYPE_P (type) || lookup_vector_type_attribute (type))
+ {
+ h.add_int (unsigned_p);
+ h.add_int (mode_p);
+ }
+ else if (instance.base->may_require_vxrm_p ()
+|| instance.base->may_require_frm_p ())
+ {
+ h.add_int (argument_types.length ());
+ break;
+ }
}
return h.end ();
}
-bool
-has_vxrm_or_frm_p (function_instance , const vec
)
-{
- if (instance.base->may_require_vxrm_p ()
- || (instance.base->may_require_frm_p ()
- && (TREE_CODE (TREE_TYPE (arglist[arglist.length () - 2]))
- == INTEGER_TYPE)))
-return true;
- return false;
-}
-
hashval_t
registered_function::overloaded_hash (const vec )
{
@@ -4296,68 +4294,8 @@ registered_function::overloaded_hash (const vec )
unsigned int len = arglist.length ();
for (unsigned int i = 0; i < len; i++)
-{
- /* vint8m1_t __riscv_vget_i8m1(vint8m2_t src, size_t index);
- When the user calls vget intrinsic, the __riscv_vget_i8m1(src, 1)
- form is used. The compiler recognizes that the parameter index is signed
- int, which is inconsistent with size_t, so the index is converted to
- size_t type in order to get correct hash value. vint8m2_t
- __riscv_vset(vint8m2_t dest, size_t index, vint8m1_t value); The reason
- is the same as above. */
- if ((instance.base == bases::vget && (i == (len - 1)))
- || ((instance.base == bases::vset
- || instance.shape == shapes::crypto_vi)
- && (i == (len - 2
- argument_types.safe_push (size_type_node);
- /* Vector fixed-point arithmetic instructions requiring argument vxrm.
- For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2,
- vuint32m4_t vs1, unsigned int vxrm, size_t vl); The user calls vaaddu
- intrinsic in the form of __riscv_vaaddu(vs2, vs1, 2, vl). The compiler
- recognizes that the parameter vxrm is a signed int, which is inconsistent
- with the parameter unsigned int vxrm declared by intrinsic, so the
- parameter vxrm is converted to an unsigned int type in order to get
- correct hash value.
-
- Vector Floating-Point Instructions requiring argument frm.
- DEF_RVV_FUNCTION (vfadd, alu, full_preds, f_v
[PATCH] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
From: xuli
Change the hash value of overloaded intrinsic from considering
all parameter types to:
1. Encoding vector data type
2. In order to distinguish vle8_v_i8mf8_m(vbool64_t vm, const int8_t *rs1,
size_t vl)
and vle8_v_u8mf8_m(vbool64_t vm, const uint8_t *rs1, size_t vl), encode the
pointer type
3. In order to distinguish vfadd_vv_f32mf2_rm(vfloat32mf2_t vs2, vfloat32mf2_t
vs1, size_t vl)
and vfadd_vv_f32mf2(vfloat32mf2_t vs2, vfloat32mf2_t vs1, size_t vl), encode
the number of
parameters. The same goes for the vxrm intrinsics.
PR target/113420
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p): remove.
(registered_function::overloaded_hash): refactor.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113420.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.cc | 88 +++
.../gcc.target/riscv/rvv/base/pr113420.c | 30 +++
2 files changed, 43 insertions(+), 75 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr113420.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 25e0b6e56de..5240f9e1f02 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4271,24 +4271,22 @@ registered_function::overloaded_hash () const
: TYPE_UNSIGNED (type);
mode_p = POINTER_TYPE_P (type) ? TYPE_MODE (TREE_TYPE (type))
: TYPE_MODE (type);
- h.add_int (unsigned_p);
- h.add_int (mode_p);
+ if (POINTER_TYPE_P (type) || lookup_vector_type_attribute (type))
+ {
+ h.add_int (unsigned_p);
+ h.add_int (mode_p);
+ }
+ else if (instance.base->may_require_vxrm_p ()
+ || instance.base->may_require_frm_p ())
+ {
+ h.add_int (argument_types.length ());
+ break;
+ }
}
return h.end ();
}
-bool
-has_vxrm_or_frm_p (function_instance , const vec
)
-{
- if (instance.base->may_require_vxrm_p ()
- || (instance.base->may_require_frm_p ()
- && (TREE_CODE (TREE_TYPE (arglist[arglist.length () - 2]))
- == INTEGER_TYPE)))
-return true;
- return false;
-}
-
hashval_t
registered_function::overloaded_hash (const vec )
{
@@ -4296,68 +4294,8 @@ registered_function::overloaded_hash (const vec )
unsigned int len = arglist.length ();
for (unsigned int i = 0; i < len; i++)
-{
- /* vint8m1_t __riscv_vget_i8m1(vint8m2_t src, size_t index);
-When the user calls vget intrinsic, the __riscv_vget_i8m1(src, 1)
- form is used. The compiler recognizes that the parameter index is signed
- int, which is inconsistent with size_t, so the index is converted to
- size_t type in order to get correct hash value. vint8m2_t
- __riscv_vset(vint8m2_t dest, size_t index, vint8m1_t value); The reason
- is the same as above. */
- if ((instance.base == bases::vget && (i == (len - 1)))
- || ((instance.base == bases::vset
- || instance.shape == shapes::crypto_vi)
- && (i == (len - 2
- argument_types.safe_push (size_type_node);
- /* Vector fixed-point arithmetic instructions requiring argument vxrm.
-For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2,
- vuint32m4_t vs1, unsigned int vxrm, size_t vl); The user calls vaaddu
- intrinsic in the form of __riscv_vaaddu(vs2, vs1, 2, vl). The compiler
- recognizes that the parameter vxrm is a signed int, which is inconsistent
- with the parameter unsigned int vxrm declared by intrinsic, so the
- parameter vxrm is converted to an unsigned int type in order to get
- correct hash value.
-
- Vector Floating-Point Instructions requiring argument frm.
- DEF_RVV_FUNCTION (vfadd, alu, full_preds, f_vvv_ops)
- DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops)
- Taking vfadd as an example, theoretically we can add base or shape to the
- hash value to distinguish whether the frm parameter is required.
- vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, float32_t rs1, size_t vl);
- vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, vfloat32m1_t vs1, unsigned
int
- frm, size_t vl);
-
- However, the current registration mechanism of overloaded intinsic
for gcc
- limits the intrinsic obtained by entering the hook to always be vfadd,
not
- vfadd_frm. Therefore, the correct hash value cannot be obtained through
the
- parameter list and overload name, base or shape.
- ++---+---+
- | index | name | kind |
- ++---+---+
- | 124733 | __riscv_vfadd | Overloaded| <- Hook fun
code
-
Re: Re: [PATCH] testsuite: Fix dump checks under different riscv-sim for RVV.
Committed, thanks juzhe. xu...@eswincomputing.com From: juzhe.zhong Date: 2023-12-19 14:01 To: Li Xu CC: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com; xuli Subject: Re: [PATCH] testsuite: Fix dump checks under different riscv-sim for RVV. ok Replied Message FromLi Xu Date12/19/2023 13:31 togcc-patc...@gcc.gnu.org cckito.ch...@gmail.com, pal...@dabbelt.com, juzhe.zh...@rivai.ai, xuli Subject[PATCH] testsuite: Fix dump checks under different riscv-sim for RVV.
[PATCH] testsuite: Fix dump checks under different riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks under medany.
* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Fix checks.
* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Ditto.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 23 +--
.../riscv/rvv/base/cpymem-strategy-3.c| 3 ++-
.../riscv/rvv/base/cpymem-strategy-4.c| 3 ++-
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index ccde7575051..9efe258c99a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -85,15 +85,34 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
*/
/*
-** f3: { target { any-opts "-mcmodel=medany" } }
+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts
"-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b"
"--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8"
"--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-preference=fixed-vlmax"
} } }
+**lla\s+[ta][0-7],a_a
**lla\s+[ta][0-7],a_b
-**vsetivli\s+zero,16,e32,m4,ta,ma
+**vsetivli\s+zero,16,e32,m8,ta,ma
+**vle32.v\s+v\d+,0\([ta][0-7]\)
+**vse32\.v\s+v\d+,0\([ta][0-7]\)
+**ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts
"-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv"
"-march=rv64gc_zve64d" "-march=rv64gc_zve32f" } } }
+**lla\s+[ta][0-7],a_b
+**vsetivli\s+zero,16,e32,m(f2|1|4),ta,ma
**vle32.v\s+v\d+,0\([ta][0-7]\)
**lla\s+[ta][0-7],a_a
**vse32\.v\s+v\d+,0\([ta][0-7]\)
**ret
*/
+/*
+** f3: { target { { any-opts "-mcmodel=medany
--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts
"-march=rv64gcv_zvl1024b" } } }
+**lla\s+[ta][0-7],a_a
+**lla\s+[ta][0-7],a_b
+**vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\)
+**vs(1|2|4)r\.v\s+v\d+,0\([ta][0-7]\)
+**ret
+*/
+
extern struct { __INT32_TYPE__ a[16]; } a_a, a_b;
void f3 ()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
index 83e5a837730..1e11ac0759f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
@@ -3,4 +3,5 @@
#include "cpymem-strategy.h"
-/* { dg-final { scan-assembler-times
{v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 } } */
+/* { dg-final { scan-assembler-times
{v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts
"--param=riscv-autovec-preference=fixed-vlmax" } } } } */
+/* { dg-final { scan-assembler-times
{v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts
"--param=riscv-autovec-preference=fixed-vlmax" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
index 800549c8556..6bbcb54dec1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
@@ -3,4 +3,5 @@
#include "cpymem-strategy.h"
-/* { dg-final { scan-assembler-times
{v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 } } */
+/* { dg-final { scan-assembler-times
{v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts
"--param=riscv-autovec-preference=fixed-vlmax" } } } } */
+/* { dg-final { scan-assembler-times
{v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts
"--param=riscv-autovec-preference=fixed-vlmax" } } } } */
--
2.17.1
[PATCH] testsuite: Fix cpymem-2.c dump checks under different riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-2.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-2.c | 44 ++-
1 file changed, 33 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index 7b706b6ef52..f1914a36161 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O1" } */
+/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */
@@ -8,23 +8,38 @@ typedef struct { char c[32]; } c32;
typedef struct { short s; char c[30]; } s16;
/* A short struct copy can use vsetivli.
-** f1:
-** vsetivli\s+zero,16,e8,m1,ta,ma
+** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }
+** vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma
** vle8.v\s+v1,0\(a1\)
** vse8.v\s+v1,0\(a0\)
** ret
*/
+
+/*
+** f1: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" }
&& { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b"
"-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** vl1re8.v\s+v1,0\(a1\)
+** vs1r.v\s+v1,0\(a0\)
+** ret
+*/
+
void f1 (c16 *a, c16* b)
{
*a = *b;
}
/* A longer one needs li.
-** f2:
+** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }
** li\s+[ta][0-7],32
-** vsetvli\s+zero,[ta][0-7],e8,m2,ta,ma
-** vle8.v\s+v2,0\(a1\)
-** vse8.v\s+v2,0\(a0\)
+** vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma
+** vle8.v\s+v(1|2|8),0\(a1\)
+** vse8.v\s+v(1|2|8),0\(a0\)
+** ret
+*/
+
+/*
+** f2: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" }
&& { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b"
"-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** vl2re8.v\s+v2,0\(a1\)
+** vs2r.v\s+v2,0\(a0\)
** ret
*/
void f2 (c32 *a, c32* b)
@@ -34,10 +49,17 @@ void f2 (c32 *a, c32* b)
/* A 32 byte struct is still short enough for vsetivli
if we can use an element width larger than 8.
-** f3:
-** vsetivli\s+zero,16,e16,m2,ta,ma
-** vle16.v\s+v2,0\(a1\)
-** vse16.v\s+v2,0\(a0\)
+** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }
+** vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma
+** vle16.v\s+v(1|2|8),0\(a1\)
+** vse16.v\s+v(1|2|8),0\(a0\)
+** ret
+*/
+
+/*
+** f3: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" }
&& { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b"
"-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** vl2re16.v\s+v2,0\(a1\)
+** vs2r.v\s+v2,0\(a0\)
** ret
*/
void f3 (s16 *a, s16* b)
--
2.17.1
[PATCH v2] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 29 +--
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 549d6648104..ccde7575051 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-O1" } */
+/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-add-options riscv_v } */
/* { dg-final { check-function-bodies "**" "" } } */
@@ -50,11 +50,34 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
Use extern here so that we get a known alignment, lest
DATA_ALIGNMENT force us to make the scan pattern accomodate
code for different alignments depending on word size.
-** f3: { target { any-opts "-mcmodel=medlow" } }
+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts
"-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b"
"--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2"
"--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8"
"--param=riscv-autovec-preference=fixed-vlmax" } } }
**lui\s+[ta][0-7],%hi\(a_a\)
+**addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
**lui\s+[ta][0-7],%hi\(a_b\)
**addi\s+a4,[ta][0-7],%lo\(a_b\)
-**vsetivli\s+zero,16,e32,m4,ta,ma
+**vsetivli\s+zero,16,e32,m8,ta,ma
+**vle32.v\s+v\d+,0\([ta][0-7]\)
+**vse32\.v\s+v\d+,0\([ta][0-7]\)
+**ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medlow
--param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow
-march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && {
no-opts "-march=rv64gcv_zvl1024b" } } }
+**lui\s+[ta][0-7],%hi\(a_a\)
+**lui\s+[ta][0-7],%hi\(a_b\)
+**addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
+**addi\s+a4,[ta][0-7],%lo\(a_b\)
+**vl(1|4|2)re32\.v\s+v\d+,0\([ta][0-7]\)
+**vs(1|4|2)r\.v\s+v\d+,0\([ta][0-7]\)
+**ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b"
"-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts
"--param=riscv-autovec-preference=fixed-vlmax" } } }
+**lui\s+[ta][0-7],%hi\(a_a\)
+**lui\s+[ta][0-7],%hi\(a_b\)
+**addi\s+a4,[ta][0-7],%lo\(a_b\)
+**vsetivli\s+zero,16,e32,(m1|m4|mf2),ta,ma
**vle32.v\s+v\d+,0\([ta][0-7]\)
**addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
**vse32\.v\s+v\d+,0\([ta][0-7]\)
--
2.17.1
[PATCH] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV.
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks.
---
.../gcc.target/riscv/rvv/base/cpymem-1.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 549d6648104..aac81079650 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -50,11 +50,34 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
Use extern here so that we get a known alignment, lest
DATA_ALIGNMENT force us to make the scan pattern accomodate
code for different alignments depending on word size.
-** f3: { target { any-opts "-mcmodel=medlow" } }
+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts
"-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b"
"--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2"
"--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8"
"--param=riscv-autovec-preference=fixed-vlmax" } } }
**lui\s+[ta][0-7],%hi\(a_a\)
+**addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
**lui\s+[ta][0-7],%hi\(a_b\)
**addi\s+a4,[ta][0-7],%lo\(a_b\)
-**vsetivli\s+zero,16,e32,m4,ta,ma
+**vsetivli\s+zero,16,e32,m8,ta,ma
+**vle32.v\s+v\d+,0\([ta][0-7]\)
+**vse32\.v\s+v\d+,0\([ta][0-7]\)
+**ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medlow
--param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow
-march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && {
no-opts "-march=rv64gcv_zvl1024b" } } }
+**lui\s+[ta][0-7],%hi\(a_a\)
+**lui\s+[ta][0-7],%hi\(a_b\)
+**addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
+**addi\s+a4,[ta][0-7],%lo\(a_b\)
+**vl(1|4|2)re32\.v\s+v\d+,0\([ta][0-7]\)
+**vs(1|4|2)r\.v\s+v\d+,0\([ta][0-7]\)
+**ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b"
"-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts
"--param=riscv-autovec-preference=fixed-vlmax" } } }
+**lui\s+[ta][0-7],%hi\(a_a\)
+**lui\s+[ta][0-7],%hi\(a_b\)
+**addi\s+a4,[ta][0-7],%lo\(a_b\)
+**vsetivli\s+zero,16,e32,(m1|m4|mf2),ta,ma
**vle32.v\s+v\d+,0\([ta][0-7]\)
**addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
**vse32\.v\s+v\d+,0\([ta][0-7]\)
--
2.17.1
Re: Re: [PATCH] RISC-V: Add viota missed avl_type attribute
Committed, thanks juzhe. xu...@eswincomputing.com From: juzhe.zhong Date: 2023-12-18 09:08 To: Li Xu CC: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com Subject: Re: [PATCH] RISC-V: Add viota missed avl_type attribute lgtm Replied Message FromLi Xu Date12/18/2023 09:04 togcc-patc...@gcc.gnu.org cckito.ch...@gmail.com, pal...@dabbelt.com, juzhe.zh...@rivai.ai Subject[PATCH] RISC-V: Add viota missed avl_type attribute
[PATCH] RISC-V: Add viota missed avl_type attribute
From: Juzhe-Zhong
This patch fixes the following FAIL when LMUL = 8:
riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medany/--param=riscv-autovec-lmul=m8/--param=riscv-autovec-preference=scalable
FAIL: gcc.dg/vect/slp-multitypes-2.c execution test
The rootcause is we missed viota avl_type, so we end up with incorrect vsetvl
configuration:
vsetvli zero,a2,e64,m8,ta,ma
viota.m v16,v0
'a2' value is a garbage value.
After this patch:
vsetvli a4,zero,e64,m8,ta,ma
viota.m v16,v0
gcc/ChangeLog:
* config/riscv/vector.md: Add viota avl_type attribute.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/bug-2.c: New test.
---
gcc/config/riscv/vector.md| 2 +-
.../gcc.target/riscv/rvv/autovec/bug-2.c | 75 +++
2 files changed, 76 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index a1284fd3251..7646615b12a 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -831,7 +831,7 @@
vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
- vimovxv,vfmovfv,vlsegde,vlsegdff")
+ vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota")
(const_int 7)
(eq_attr "type" "vldm,vstm,vmalu,vmalu")
(const_int 5)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
new file mode 100644
index 000..9ff93d3b163
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options "--param=riscv-autovec-lmul=m8
--param=riscv-autovec-preference=scalable -ftree-vectorize
-fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
+
+#define N 128
+
+__attribute__ ((noinline)) int
+main1 (unsigned short a0, unsigned short a1, unsigned short a2,
+ unsigned short a3, unsigned short a4, unsigned short a5,
+ unsigned short a6, unsigned short a7, unsigned short a8,
+ unsigned short a9, unsigned short a10, unsigned short a11,
+ unsigned short a12, unsigned short a13, unsigned short a14,
+ unsigned short a15, unsigned char b0, unsigned char b1)
+{
+ int i;
+ unsigned short out[N*16];
+ unsigned char out2[N*16];
+
+ for (i = 0; i < N; i++)
+{
+ out[i*16] = a8;
+ out[i*16 + 1] = a7;
+ out[i*16 + 2] = a1;
+ out[i*16 + 3] = a2;
+ out[i*16 + 4] = a8;
+ out[i*16 + 5] = a5;
+ out[i*16 + 6] = a5;
+ out[i*16 + 7] = a4;
+ out[i*16 + 8] = a12;
+ out[i*16 + 9] = a13;
+ out[i*16 + 10] = a14;
+ out[i*16 + 11] = a15;
+ out[i*16 + 12] = a6;
+ out[i*16 + 13] = a9;
+ out[i*16 + 14] = a0;
+ out[i*16 + 15] = a7;
+
+ out2[i*2] = b1;
+ out2[i*2+1] = b0;
+}
+
+ /* check results: */
+#pragma GCC novector
+ for (i = 0; i < N; i++)
+{
+ if (out[i*16] != a8
+ || out[i*16 + 1] != a7
+ || out[i*16 + 2] != a1
+ || out[i*16 + 3] != a2
+ || out[i*16 + 4] != a8
+ || out[i*16 + 5] != a5
+ || out[i*16 + 6] != a5
+ || out[i*16 + 7] != a4
+ || out[i*16 + 8] != a12
+ || out[i*16 + 9] != a13
+ || out[i*16 + 10] != a14
+ || out[i*16 + 11] != a15
+ || out[i*16 + 12] != a6
+ || out[i*16 + 13] != a9
+ || out[i*16 + 14] != a0
+ || out[i*16 + 15] != a7
+ || out2[i*2] != b1
+ || out2[i*2 + 1] != b0)
+__builtin_abort ();
+}
+
+ return 0;
+}
+
+int main (void)
+{
+ main1 (15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,20,21);
+
+ return 0;
+}
--
2.36.3
Re: Re: [PATCH] RISC-V: Remove useless modes
Got it. Committed, thanks juzhe and kito. xu...@eswincomputing.com From: Kito Cheng Date: 2023-12-06 14:45 To: Li Xu CC: gcc-patches; palmer; juzhe.zhong Subject: Re: [PATCH] RISC-V: Remove useless modes You could add [NFC] to the title for this kind of patch to declare its clean up or refactor patch without change any function or feature, that would be easier for reviewer, anyway LGTM as well On Wed, Dec 6, 2023 at 12:50 PM Li Xu wrote: > > From: xuli > > gcc/ChangeLog: > > * config/riscv/riscv.md: Remove. > --- > gcc/config/riscv/riscv.md | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index a98918dfd43..0db659acfbe 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -235,7 +235,6 @@ >RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,RVVM2x4DF, >RVVM1x4DF,RVVM2x3DF,RVVM1x3DF,RVVM4x2DF, >RVVM2x2DF,RVVM1x2DF, > - VNx2x1DF,VNx3x1DF,VNx4x1DF,VNx5x1DF,VNx6x1DF,VNx7x1DF,VNx8x1DF, > > V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI, >V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI, >V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI, > -- > 2.17.1 >
[PATCH] RISC-V: Remove useless modes
From: xuli gcc/ChangeLog: * config/riscv/riscv.md: Remove. --- gcc/config/riscv/riscv.md | 1 - 1 file changed, 1 deletion(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index a98918dfd43..0db659acfbe 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -235,7 +235,6 @@ RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,RVVM2x4DF, RVVM1x4DF,RVVM2x3DF,RVVM1x3DF,RVVM4x2DF, RVVM2x2DF,RVVM1x2DF, - VNx2x1DF,VNx3x1DF,VNx4x1DF,VNx5x1DF,VNx6x1DF,VNx7x1DF,VNx8x1DF, V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI, V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI, V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI, -- 2.17.1
Re: Re: [PATCH v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution test) on RV32
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2023-12-05 16:41
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os
(execution test) on RV32
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-12-05 16:38
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution
test) on RV32
From: xuli
This patch fixs the issue of g++.dg/torture/vshuf-v2di.C
and g++.dg/torture/vshuf-v4di.C -Os execution failure with
-march=rv32gcv -mabi=ilp32d.
Consider the following code:
typedef unsigned long long V __attribute__((vector_size(16)));
.LC0: 0xc1c2c3c4c5c6c7c8
before this patch:
lui a5,%hi(.LC0)
addi a5,a5,%lo(.LC0)
lw a6,4(a5)//0xc1c2c3c4
lw a5,0(a5)//0xc5c6c7c8
vsetivli zero,2,e64,m1,ta,mu
vmv.v.x v2,a5//v2 is {0xc5c6c7c8, 0xc5c6c7c8}
after this patch:
lui a5,%hi(.LC0)
addi a5,a5,%lo(.LC0)
vsetivli zero,2,e64,m1,ta,mu
vlse64.v v2,0(a5),zero//v2 is {0xc1c2c3c4c5c6c7c8, 0xc1c2c3c4c5c6c7c8}
gcc/ChangeLog:
* config/riscv/riscv-v.cc (sew64_scalar_helper): Bugfix.
---
gcc/config/riscv/riscv-v.cc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 588c127343e..2799a216a0b 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1728,7 +1728,12 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx
vl,
}
if (CONST_INT_P (*scalar_op))
-*scalar_op = force_reg (scalar_mode, *scalar_op);
+{
+ if (maybe_gt (GET_MODE_SIZE (scalar_mode), GET_MODE_SIZE (Pmode)))
+ *scalar_op = force_const_mem (scalar_mode, *scalar_op);
+ else
+ *scalar_op = force_reg (scalar_mode, *scalar_op);
+}
rtx tmp = gen_reg_rtx (vector_mode);
rtx ops[] = {tmp, *scalar_op};
--
2.17.1
[PATCH v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution test) on RV32
From: xuli
This patch fixs the issue of g++.dg/torture/vshuf-v2di.C
and g++.dg/torture/vshuf-v4di.C -Os execution failure with
-march=rv32gcv -mabi=ilp32d.
Consider the following code:
typedef unsigned long long V __attribute__((vector_size(16)));
.LC0: 0xc1c2c3c4c5c6c7c8
before this patch:
lui a5,%hi(.LC0)
addia5,a5,%lo(.LC0)
lw a6,4(a5)//0xc1c2c3c4
lw a5,0(a5)//0xc5c6c7c8
vsetivlizero,2,e64,m1,ta,mu
vmv.v.x v2,a5//v2 is {0xc5c6c7c8, 0xc5c6c7c8}
after this patch:
lui a5,%hi(.LC0)
addia5,a5,%lo(.LC0)
vsetivlizero,2,e64,m1,ta,mu
vlse64.vv2,0(a5),zero//v2 is {0xc1c2c3c4c5c6c7c8, 0xc1c2c3c4c5c6c7c8}
gcc/ChangeLog:
* config/riscv/riscv-v.cc (sew64_scalar_helper): Bugfix.
---
gcc/config/riscv/riscv-v.cc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 588c127343e..2799a216a0b 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1728,7 +1728,12 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx
vl,
}
if (CONST_INT_P (*scalar_op))
-*scalar_op = force_reg (scalar_mode, *scalar_op);
+{
+ if (maybe_gt (GET_MODE_SIZE (scalar_mode), GET_MODE_SIZE (Pmode)))
+ *scalar_op = force_const_mem (scalar_mode, *scalar_op);
+ else
+ *scalar_op = force_reg (scalar_mode, *scalar_op);
+}
rtx tmp = gen_reg_rtx (vector_mode);
rtx ops[] = {tmp, *scalar_op};
--
2.17.1
[PATCH] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution test) on RV32
From: xuli
This patch fixs the issue of g++.dg/torture/vshuf-v2di.C
and g++.dg/torture/vshuf-v4di.C -Os execution failure with
-march=rv32gcv -mabi=ilp32d.
Consider the following code:
typedef unsigned long long V __attribute__((vector_size(16)));
.LC0: 0xc1c2c3c4c5c6c7c8
before this patch:
lui a5,%hi(.LC0)
addia5,a5,%lo(.LC0)
lw a6,4(a5)//0xc1c2c3c4
lw a5,0(a5)//0xc5c6c7c8
vsetivlizero,2,e64,m1,ta,mu
vmv.v.x v2,a5//v2 is {0xc5c6c7c8, 0xc5c6c7c8}
after this patch:
lui a5,%hi(.LC0)
addia5,a5,%lo(.LC0)
vsetivlizero,2,e64,m1,ta,mu
vlse64.vv2,0(a5),zero//v2 is {0xc1c2c3c4c5c6c7c8, 0xc1c2c3c4c5c6c7c8}
gcc/ChangeLog:
* config/riscv/riscv-v.cc (sew64_scalar_helper): Bugfix.
---
gcc/config/riscv/riscv-v.cc | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 588c127343e..16ab05c40bb 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1728,7 +1728,13 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx
vl,
}
if (CONST_INT_P (*scalar_op))
-*scalar_op = force_reg (scalar_mode, *scalar_op);
+{
+ if (!TARGET_64BIT
+ && maybe_gt (GET_MODE_SIZE (scalar_mode), GET_MODE_SIZE (Pmode)))
+ *scalar_op = force_const_mem (scalar_mode, *scalar_op);
+ else
+ *scalar_op = force_reg (scalar_mode, *scalar_op);
+}
rtx tmp = gen_reg_rtx (vector_mode);
rtx ops[] = {tmp, *scalar_op};
--
2.17.1
[PATCH] RISC-V: Add explicit braces to eliminate warning.
From: xuli
../.././gcc/gcc/config/riscv/riscv.cc: In function ‘void
riscv_option_override()’:
../.././gcc/gcc/config/riscv/riscv.cc:8673:6: warning: suggest explicit braces
to avoid ambiguous ‘else’ [-Wdangling-else]
if (TARGET_RVE)
^
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): Eliminate warning.
---
gcc/config/riscv/riscv.cc | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a4fc858fb50..2f8d391579a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8671,10 +8671,12 @@ riscv_option_override (void)
/* RVE requires specific ABI. */
if (TARGET_RVE)
-if (!TARGET_64BIT && riscv_abi != ABI_ILP32E)
- error ("rv32e requires ilp32e ABI");
-else if (TARGET_64BIT && riscv_abi != ABI_LP64E)
- error ("rv64e requires lp64e ABI");
+{
+ if (!TARGET_64BIT && riscv_abi != ABI_ILP32E)
+ error ("rv32e requires ilp32e ABI");
+ else if (TARGET_64BIT && riscv_abi != ABI_LP64E)
+ error ("rv64e requires lp64e ABI");
+}
/* Zfinx require abi ilp32, ilp32e, lp64 or lp64e. */
if (TARGET_ZFINX
--
2.17.1
Re: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537]
Committed, thanks jeff and juzhe. Thanks, Li Xu xu...@eswincomputing.com From: juzhe.zh...@rivai.ai Date: 2023-11-20 09:55 To: Li Xu; jeffreyalaw; gcc-patches CC: kito.cheng; palmer; Robin Dapp Subject: Re: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537] Jeff has approved your patch. You can commit it now. Btw, CC Robin to let him know this patch. Since he will support strcpy/strlenetc builtin with RVV instruction sequence. He will definitely needs compile option like this patch introduce. Thanks. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-11-20 09:09 To: Jeff Law; gcc-patches CC: kito.cheng; palmer; juzhe.zhong Subject: Re: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537] I've tested it and there are no issues with regression testing. Thanks, Li Xu xu...@eswincomputing.com From: Jeff Law Date: 2023-11-20 05:42 To: Li Xu; gcc-patches CC: kito.cheng; palmer; juzhe.zhong Subject: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537] On 11/16/23 22:12, Li Xu wrote: > From: xuli > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537 > > -mmemcpy-strategy=[auto|libcall|scalar|vector] > > auto: Current status, use scalar or vector instructions. > libcall: Always use a library call. > scalar: Only use scalar instructions. > vector: Only use vector instructions. > > PR target/112537 > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum): Strategy > enum. > * config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled based on > options. > (expand_block_move): Ditto. > * config/riscv/riscv.opt: Add -mmemcpy-strategy=. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/cpymem-strategy-1.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-2.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-5.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy.h: New test. This is OK assuming you have tested it to ensure there aren't any regressions in the testsuite. I don't expect problems, but let's be sure :-) Thanks, jeff
Re: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537]
I've tested it and there are no issues with regression testing. Thanks, Li Xu xu...@eswincomputing.com From: Jeff Law Date: 2023-11-20 05:42 To: Li Xu; gcc-patches CC: kito.cheng; palmer; juzhe.zhong Subject: Re: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537] On 11/16/23 22:12, Li Xu wrote: > From: xuli > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537 > > -mmemcpy-strategy=[auto|libcall|scalar|vector] > > auto: Current status, use scalar or vector instructions. > libcall: Always use a library call. > scalar: Only use scalar instructions. > vector: Only use vector instructions. > > PR target/112537 > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum): Strategy > enum. > * config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled based on > options. > (expand_block_move): Ditto. > * config/riscv/riscv.opt: Add -mmemcpy-strategy=. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/cpymem-strategy-1.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-2.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy-5.c: New test. > * gcc.target/riscv/rvv/base/cpymem-strategy.h: New test. This is OK assuming you have tested it to ensure there aren't any regressions in the testsuite. I don't expect problems, but let's be sure :-) Thanks, jeff
[PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537]
From: xuli
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537
-mmemcpy-strategy=[auto|libcall|scalar|vector]
auto: Current status, use scalar or vector instructions.
libcall: Always use a library call.
scalar: Only use scalar instructions.
vector: Only use vector instructions.
PR target/112537
gcc/ChangeLog:
* config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum):
Strategy enum.
* config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled
based on options.
(expand_block_move): Ditto.
* config/riscv/riscv.opt: Add -mmemcpy-strategy=.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cpymem-strategy-1.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-2.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-5.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy.h: New test.
---
gcc/config/riscv/riscv-opts.h | 12 +++
gcc/config/riscv/riscv-string.cc | 7 ++-
gcc/config/riscv/riscv.opt| 20 +++
.../riscv/rvv/base/cpymem-strategy-1.c| 6 ++
.../riscv/rvv/base/cpymem-strategy-2.c| 6 ++
.../riscv/rvv/base/cpymem-strategy-3.c| 6 ++
.../riscv/rvv/base/cpymem-strategy-4.c| 6 ++
.../riscv/rvv/base/cpymem-strategy-5.c| 6 ++
.../riscv/rvv/base/cpymem-strategy.h | 12 +++
9 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy.h
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 532b1b6b84a..0b242f068e1 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -102,6 +102,18 @@ enum riscv_entity
MAX_RISCV_ENTITIES
};
+/* RISC-V stringop strategy. */
+enum riscv_stringop_strategy_enum {
+ /* Use scalar or vector instructions. */
+ USE_AUTO,
+ /* Always use a library call. */
+ USE_LIBCALL,
+ /* Only use scalar instructions. */
+ USE_SCALAR,
+ /* Only use vector instructions. */
+ USE_VECTOR
+};
+
#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS &&
TARGET_64BIT))
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 57e8ad698d7..3b5e05e2c44 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -710,6 +710,10 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned
HOST_WIDE_INT length,
bool
riscv_expand_block_move (rtx dest, rtx src, rtx length)
{
+ if (riscv_memcpy_strategy == USE_LIBCALL
+ || riscv_memcpy_strategy == USE_VECTOR)
+return false;
+
if (CONST_INT_P (length))
{
unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
@@ -773,7 +777,8 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in)
bnez a2, loop # Any more?
ret # Return
*/
- if (!TARGET_VECTOR)
+ if (!TARGET_VECTOR || riscv_memcpy_strategy == USE_LIBCALL
+ || riscv_memcpy_strategy == USE_SCALAR)
return false;
HOST_WIDE_INT potential_ew
= (MIN (MIN (MEM_ALIGN (src_in), MEM_ALIGN (dst_in)), BITS_PER_WORD)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..4f3ce2233b2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -527,3 +527,23 @@ Target Var(TARGET_ADJUST_LMUL_COST) Init(0)
Target Undocumented Bool Var(riscv_vector_abi) Init(0)
Enable the use of vector registers for function arguments and return value.
This is an experimental switch and may be subject to change in the future.
+
+Enum
+Name(riscv_stringop_strategy) Type(enum riscv_stringop_strategy_enum)
+Valid arguments to -mmemcpy-strategy=:
+
+EnumValue
+Enum(riscv_stringop_strategy) String(auto) Value(USE_AUTO)
+
+EnumValue
+Enum(riscv_stringop_strategy) String(libcall) Value(USE_LIBCALL)
+
+EnumValue
+Enum(riscv_stringop_strategy) String(scalar) Value(USE_SCALAR)
+
+EnumValue
+Enum(riscv_stringop_strategy) String(vector) Value(USE_VECTOR)
+
+mmemcpy-strategy=
+Target RejectNegative Joined Enum(riscv_stringop_strategy)
Var(riscv_memcpy_strategy) Init(USE_AUTO)
+Specify memcpy expansion strategy.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-1.c
[PATCH] RISC-V: Eliminate unused parameter warning.
From: xuli
The parameter orig_fndecl is not used, use anonymous parameters instead.
../.././gcc/gcc/config/riscv/riscv-c.cc: In function ‘bool
riscv_check_builtin_call(location_t, vec, tree, tree, unsigned
int, tree_node**)’:
../.././gcc/gcc/config/riscv/riscv-c.cc:207:11: warning: unused parameter
‘orig_fndecl’ [-Wunused-parameter]
tree orig_fndecl, unsigned int nargs, tree *args)
^~~
gcc/ChangeLog:
* config/riscv/riscv-c.cc (riscv_check_builtin_call): Eliminate warning.
---
gcc/config/riscv/riscv-c.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index bedf7217390..b7f9ba204f7 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -204,7 +204,7 @@ riscv_pragma_intrinsic (cpp_reader *)
/* Implement TARGET_CHECK_BUILTIN_CALL. */
static bool
riscv_check_builtin_call (location_t loc, vec arg_loc, tree fndecl,
- tree orig_fndecl, unsigned int nargs, tree *args)
+ tree, unsigned int nargs, tree *args)
{
unsigned int code = DECL_MD_FUNCTION_CODE (fndecl);
unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
--
2.17.1
Re: Re: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
Committed, thanks juzhe.
xu...@eswincomputing.com
From: juzhe.zh...@rivai.ai
Date: 2023-11-02 09:00
To: Li Xu; gcc-patches
CC: kito.cheng; palmer; Li Xu
Subject: Re: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-02 08:54
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple intrinsics.
* config/riscv/riscv-vector-builtins-functions.def (vcreate): Define non-tuple
intrinsics.
* config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def): Ditto.
* config/riscv/riscv-vector-builtins.cc: Add arg types.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple_create.c: Rename to vcreate.c.
* gcc.target/riscv/rvv/base/vcreate.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 21 +-
.../riscv/riscv-vector-builtins-functions.def | 6 +
.../riscv/riscv-vector-builtins-shapes.cc | 25 +-
gcc/config/riscv/riscv-vector-builtins.cc | 53
.../gcc.target/riscv/rvv/base/tuple_create.c | 123 -
.../gcc.target/riscv/rvv/base/vcreate.c | 260 ++
6 files changed, 357 insertions(+), 131 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 0b1409a52e0..25ba31e2659 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1798,6 +1798,10 @@ public:
{
unsigned int nargs = gimple_call_num_args (f.call);
tree lhs_type = TREE_TYPE (f.lhs);
+/* LMUL > 1 non-tuple vector types are not structure,
+ we can't use __val[index] to set the subpart. */
+if (!riscv_v_ext_tuple_mode_p (TYPE_MODE (lhs_type)))
+ return NULL;
/* Replace the call with a clobber of the result (to prevent it from
becoming upwards exposed) followed by stores into each individual
@@ -1823,9 +1827,22 @@ public:
return clobber;
}
- rtx expand (function_expander &) const override
+ rtx expand (function_expander ) const override
{
-gcc_unreachable ();
+if (!e.target)
+ return NULL_RTX;
+gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (e.target)));
+unsigned int nargs = call_expr_nargs (e.exp);
+for (unsigned int i = 0; i < nargs; i++)
+ {
+ rtx src = expand_normal (CALL_EXPR_ARG (e.exp, i));
+ poly_int64 offset = i * GET_MODE_SIZE (GET_MODE (src));
+ rtx subreg = simplify_gen_subreg (GET_MODE (src), e.target,
+ GET_MODE (e.target), offset);
+ emit_move_insn (subreg, src);
+ }
+
+return e.target;
}
};
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 911fd520195..1c37fd5fffe 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -617,6 +617,12 @@ DEF_RVV_FUNCTION (vget, vget, none_preds,
all_v_vget_lmul1_x8_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul2_x2_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul2_x4_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul4_x2_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x2_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x4_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x8_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x2_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x4_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul4_x2_ops)
// Tuple types
DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 0bda934ae16..72b0d6a96a3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -728,13 +728,17 @@ struct vcreate_def : public build_base
if (!return_type)
continue;
- machine_mode mode = TYPE_MODE (return_type);
- unsigned int nf = get_nf (mode);
+ tree arg_type = function_instance.op_info->args[0].get_tree_type (
+ function_instance.type.index);
- for (unsigned int i = 0; i < nf; i++)
- argument_types.quick_push (
- function_instance.op_info->args[0].get_tree_type (
- function_instance.type.index));
+ machine_mode outer_mode = TYPE_MODE (return_type);
+ machine_mode inner_mode = TYPE_MODE (arg_type);
+ unsigned int nargs
+ = exact_div (GET_MODE_SIZE (outer_mode), GET_MO
[PATCH] RISC-V: Support vcreate intrinsics for non-tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple
intrinsics.
* config/riscv/riscv-vector-builtins-functions.def (vcreate): Define
non-tuple intrinsics.
* config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def):
Ditto.
* config/riscv/riscv-vector-builtins.cc: Add arg types.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple_create.c: Rename to vcreate.c.
* gcc.target/riscv/rvv/base/vcreate.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 21 +-
.../riscv/riscv-vector-builtins-functions.def | 6 +
.../riscv/riscv-vector-builtins-shapes.cc | 25 +-
gcc/config/riscv/riscv-vector-builtins.cc | 53
.../gcc.target/riscv/rvv/base/tuple_create.c | 123 -
.../gcc.target/riscv/rvv/base/vcreate.c | 260 ++
6 files changed, 357 insertions(+), 131 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 0b1409a52e0..25ba31e2659 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1798,6 +1798,10 @@ public:
{
unsigned int nargs = gimple_call_num_args (f.call);
tree lhs_type = TREE_TYPE (f.lhs);
+/* LMUL > 1 non-tuple vector types are not structure,
+ we can't use __val[index] to set the subpart. */
+if (!riscv_v_ext_tuple_mode_p (TYPE_MODE (lhs_type)))
+ return NULL;
/* Replace the call with a clobber of the result (to prevent it from
becoming upwards exposed) followed by stores into each individual
@@ -1823,9 +1827,22 @@ public:
return clobber;
}
- rtx expand (function_expander &) const override
+ rtx expand (function_expander ) const override
{
-gcc_unreachable ();
+if (!e.target)
+ return NULL_RTX;
+gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (e.target)));
+unsigned int nargs = call_expr_nargs (e.exp);
+for (unsigned int i = 0; i < nargs; i++)
+ {
+ rtx src = expand_normal (CALL_EXPR_ARG (e.exp, i));
+ poly_int64 offset = i * GET_MODE_SIZE (GET_MODE (src));
+ rtx subreg = simplify_gen_subreg (GET_MODE (src), e.target,
+ GET_MODE (e.target), offset);
+ emit_move_insn (subreg, src);
+ }
+
+return e.target;
}
};
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 911fd520195..1c37fd5fffe 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -617,6 +617,12 @@ DEF_RVV_FUNCTION (vget, vget, none_preds,
all_v_vget_lmul1_x8_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul2_x2_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul2_x4_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul4_x2_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x2_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x4_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul1_x8_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x2_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul2_x4_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_lmul4_x2_ops)
// Tuple types
DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 0bda934ae16..72b0d6a96a3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -728,13 +728,17 @@ struct vcreate_def : public build_base
if (!return_type)
continue;
- machine_mode mode = TYPE_MODE (return_type);
- unsigned int nf = get_nf (mode);
+ tree arg_type = function_instance.op_info->args[0].get_tree_type (
+ function_instance.type.index);
- for (unsigned int i = 0; i < nf; i++)
- argument_types.quick_push (
- function_instance.op_info->args[0].get_tree_type (
- function_instance.type.index));
+ machine_mode outer_mode = TYPE_MODE (return_type);
+ machine_mode inner_mode = TYPE_MODE (arg_type);
+ unsigned int nargs
+ = exact_div (GET_MODE_SIZE (outer_mode), GET_MODE_SIZE (inner_mode))
+ .to_constant ();
+
+ for (unsigned int i = 0; i < nargs; i++)
+ argument_types.quick_push (arg_type);
b.add_unique_function (function_instance, (*group.shape), return_type,
[PATCH] RISC-V: Support vundefine intrinsics for tuple types
From: xuli
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def (vundefined): Add
vundefine intrinsics for tuple types.
* config/riscv/riscv-vector-builtins.cc: Ditto.
* config/riscv/vector.md (@vundefined): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple_vundefined.c: New test.
---
.../riscv/riscv-vector-builtins-functions.def | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 8 ++
gcc/config/riscv/vector.md| 7 ++
.../riscv/rvv/base/tuple_vundefined.c | 73 +++
4 files changed, 89 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 18ed2c2b8f6..911fd520195 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -622,6 +622,7 @@ DEF_RVV_FUNCTION (vget, vget, none_preds,
all_v_vget_lmul4_x2_ops)
DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_tuple_ops)
DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_tuple_ops)
+DEF_RVV_FUNCTION (vundefined, vundefined, none_preds, all_none_void_tuple_ops)
DEF_RVV_FUNCTION (vlseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ops)
DEF_RVV_FUNCTION (vsseg, seg_loadstore, none_m_preds, tuple_v_scalar_ptr_ops)
DEF_RVV_FUNCTION (vlsseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ptrdiff_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 5d4dc264fa6..2e33bf73549 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2509,6 +2509,14 @@ static CONSTEXPR const rvv_op_info
all_v_vcreate_tuple_ops
rvv_arg_type_info (RVV_BASE_vector), /* Return type */
tuple_vcreate_args /* Args */};
+/* A static operand information for vector_type func () function registration.
+ */
+static CONSTEXPR const rvv_op_info all_none_void_tuple_ops
+ = {tuple_ops, /* Types */
+ OP_TYPE_none, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+ void_args /* Args */};
+
/* A list of all RVV base function types. */
static CONSTEXPR const function_type_info function_types[] = {
#define DEF_RVV_TYPE_INDEX(
\
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0297e4f0227..35bb6c3dc58 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -880,6 +880,13 @@
""
[(set_attr "type" "vector")])
+(define_insn "@vundefined"
+ [(set (match_operand:VT 0 "register_operand" "=vr")
+ (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
+ "TARGET_VECTOR"
+ ""
+ [(set_attr "type" "vector")])
+
(define_expand "@vreinterpret"
[(set (match_operand:V 0 "register_operand")
(match_operand 1 "vector_any_register_operand"))]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
new file mode 100644
index 000..174860de559
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4x2_t
+test_vundefined_f16mf4x2 ()
+{
+ return __riscv_vundefined_f16mf4x2 ();
+}
+
+vfloat32m1x3_t
+test_vundefined_f32m1x3 ()
+{
+ return __riscv_vundefined_f32m1x3 ();
+}
+
+vfloat64m1x5_t
+test_vundefined_f64m1x5 ()
+{
+ return __riscv_vundefined_f64m1x5 ();
+}
+
+vint8mf4x2_t
+test_vundefined_i8mf4x2 ()
+{
+ return __riscv_vundefined_i8mf4x2 ();
+}
+
+vint16mf4x8_t
+test_vundefined_i16mf4x8 ()
+{
+ return __riscv_vundefined_i16mf4x8 ();
+}
+
+vint32m1x7_t
+test_vundefined_i32m1x7 ()
+{
+ return __riscv_vundefined_i32m1x7 ();
+}
+
+vint64m1x4_t
+test_vundefined_i64m1x4 ()
+{
+ return __riscv_vundefined_i64m1x4 ();
+}
+
+vuint8mf8x2_t
+test_vundefined_u8mf8x2 ()
+{
+ return __riscv_vundefined_u8mf8x2 ();
+}
+
+vuint16mf4x4_t
+test_vundefined_u16mf4x4 ()
+{
+ return __riscv_vundefined_u16mf4x4 ();
+}
+
+vuint32m1x7_t
+test_vundefined_u32m1x7 ()
+{
+ return __riscv_vundefined_u32m1x7 ();
+}
+
+vuint64m4x2_t
+test_vundefined_u64m4x2 ()
+{
+ return __riscv_vundefined_u64m4x2 ();
+}
+
+/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)}
18 } } */
+/* { dg-final { scan-assembler-times
{vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */
--
2.17.1
Re: Re: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
All overload and non-overload intrinsics have been tested successfully on gcc and g++. Thanks. > -原始邮件-发件人:"juzhe.zh...@rivai.ai" > 发送时间:2023-10-31 17:07:11 (星期二)收件人:"Li Xu" > , gcc-patches > 抄送:"kito.cheng" , palmer > , "Li Xu" 主题:Re: [PATCH v6] > RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic > > LGTM from my side. > > Give kito one more day to review it. > > Thanks for support this feature ! > > juzhe.zh...@rivai.ai > > From: Li Xu > Date: 2023-10-31 17:03 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; xuli > Subject: [PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV > intrinsic > From: xuli > > Update in v6: > * Rename maybe_require_frm_p to may_require_frm_p. > * Rename maybe_require_vxrm_p to may_require_vxrm_p. > * Move may_require_frm_p and may_require_vxrm_p to function_base. > > Update in v5: > * Split has_vxrm_or_frm_p into maybe_require_frm_p and > maybe_require_vxrm_p. > * Adjust comments. > > Update in v4: > * Remove class function_resolver. > * Remove function get_non_overloaded_instance. > * Add overloaded hash traits for non-overloaded intrinsic. > * All overloaded intrinsics are implemented, and the tests pass. > > Update in v3: > > * Rewrite comment for overloaded function add. > * Move get_non_overloaded_instance to function_base. > > Update in v2: > > * Add get_non_overloaded_instance for function instance. > * Fix overload check for policy function. > * Enrich the test cases check. > > Original log: > > This patch would like add the framework to support the RVV overloaded > intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did. > > However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN > with below steps. > > * Register overloaded functions. > * Add function_resolver for overloaded function resolving. > * Add resolve API for function shape with default implementation. > * Implement HOOK for navigating the overloaded API to non-overloaded API. > > gcc/ChangeLog: > > * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): New > function for the hook. > (riscv_register_pragmas): Register the hook. > * config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl. > * config/riscv/riscv-vector-builtins-bases.cc: New function impl. > * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Register > overloaded function. > * config/riscv/riscv-vector-builtins.cc (struct > non_overloaded_registered_function_hasher): New hash table. > (function_builder::add_function): Add overloaded arg. > (function_builder::add_unique_function): Map overloaded function to > non-overloaded function. > (function_builder::add_overloaded_function): New API impl. > (registered_function::overloaded_hash): Calculate hash value. > (has_vxrm_or_frm_p): New function impl. > (non_overloaded_registered_function_hasher::hash): Ditto. > (non_overloaded_registered_function_hasher::equal): Ditto. > (handle_pragma_vector): Allocate space for hash table. > (resolve_overloaded_builtin): New function impl. > * config/riscv/riscv-vector-builtins.h > (function_base::may_require_frm_p): Ditto. > (function_base::may_require_vxrm_p): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c: New test. > * gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: New test. > * gcc.target/riscv/rvv/base/overloaded_vadd.h: New test. > * gcc.target/riscv/rvv/base/overloaded_vfadd.h: New test. > * gcc.target/riscv/rvv/base/overloaded_vget_vset.h: New test. > * gcc.target/riscv/rvv/base/overloaded_vloxseg2ei16.h: New test. > * gcc.target/riscv/rvv/base/overloaded_vmv.h: New test. &g
[PATCH v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
From: xuli Update in v6: * Rename maybe_require_frm_p to may_require_frm_p. * Rename maybe_require_vxrm_p to may_require_vxrm_p. * Move may_require_frm_p and may_require_vxrm_p to function_base. Update in v5: * Split has_vxrm_or_frm_p into maybe_require_frm_p and maybe_require_vxrm_p. * Adjust comments. Update in v4: * Remove class function_resolver. * Remove function get_non_overloaded_instance. * Add overloaded hash traits for non-overloaded intrinsic. * All overloaded intrinsics are implemented, and the tests pass. Update in v3: * Rewrite comment for overloaded function add. * Move get_non_overloaded_instance to function_base. Update in v2: * Add get_non_overloaded_instance for function instance. * Fix overload check for policy function. * Enrich the test cases check. Original log: This patch would like add the framework to support the RVV overloaded intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did. However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN with below steps. * Register overloaded functions. * Add function_resolver for overloaded function resolving. * Add resolve API for function shape with default implementation. * Implement HOOK for navigating the overloaded API to non-overloaded API. gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): New function for the hook. (riscv_register_pragmas): Register the hook. * config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl. * config/riscv/riscv-vector-builtins-bases.cc: New function impl. * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Register overloaded function. * config/riscv/riscv-vector-builtins.cc (struct non_overloaded_registered_function_hasher): New hash table. (function_builder::add_function): Add overloaded arg. (function_builder::add_unique_function): Map overloaded function to non-overloaded function. (function_builder::add_overloaded_function): New API impl. (registered_function::overloaded_hash): Calculate hash value. (has_vxrm_or_frm_p): New function impl. (non_overloaded_registered_function_hasher::hash): Ditto. (non_overloaded_registered_function_hasher::equal): Ditto. (handle_pragma_vector): Allocate space for hash table. (resolve_overloaded_builtin): New function impl. * config/riscv/riscv-vector-builtins.h (function_base::may_require_frm_p): Ditto. (function_base::may_require_vxrm_p): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: New test. * gcc.target/riscv/rvv/base/overloaded_vadd.h: New test. * gcc.target/riscv/rvv/base/overloaded_vfadd.h: New test. * gcc.target/riscv/rvv/base/overloaded_vget_vset.h: New test. * gcc.target/riscv/rvv/base/overloaded_vloxseg2ei16.h: New test. * gcc.target/riscv/rvv/base/overloaded_vmv.h: New test. * gcc.target/riscv/rvv/base/overloaded_vreinterpret.h: New test. Signed-off-by: Li Xu Co-Authored-By: Pan Li --- gcc/config/riscv/riscv-c.cc | 36 ++- gcc/config/riscv/riscv-protos.h | 1 + .../riscv/riscv-vector-builtins-bases.cc | 69 +- .../riscv/riscv-vector-builtins-shapes.cc | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 226 +- gcc/config/riscv/riscv-vector-builtins.h | 27 ++- .../riscv/rvv/base/overloaded_rv32_vadd.c | 12 + .../riscv/rvv/base/overloaded_rv32_vfadd.c| 12 + .../rvv/base/overloaded_rv32_vget_vset.c | 7 + .../rvv/base/overloaded_rv32_vloxseg2ei16.c | 11 + .../riscv/rvv/base/overloaded_rv32_vmv.c | 10 + .../rvv/base/overloaded_rv32_vreinterpret.c | 10 + .../riscv/rvv/base/overloaded_rv64_vadd.c | 11 + .../riscv/rvv/base/overloaded_rv64_vfadd.c| 11 + .../rvv/base/overloaded_rv64_vget_vset.c | 6 + .../rvv/base/overloaded_rv64_vloxseg2ei16.c | 10 + .../riscv/rvv/base/overloaded_rv64_vmv.c | 10 + .../rvv/base/overloaded_rv64_vreinterpret.c | 9 + .../riscv/rvv/base/overloaded_vadd.h | 59
Re: Re: [PATCH V5] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
Since the following three instances share the class binop,
I cannot distinguish between vadd and vfadd.
I think it is difficult to add maybe_require_frm_p
and maybe_require_vxrm_p to function_base.
static CONSTEXPR const binop vadd_obj;
static CONSTEXPR const binop vfadd_obj;
static CONSTEXPR const binop vfadd_frm_obj;
template
class binop : public function_base
{
public:
bool maybe_require_frm_p () const override { return true; }//vadd is true
...
}
--
Li Xu
>+static bool
>+maybe_require_frm_p (function_instance )
>+{
>+ return instance.base == bases::vfwredusum
>+ || instance.base == bases::vfwredosum || instance.base == bases::vfadd
>+ || instance.base == bases::vfwsub || instance.base == bases::vfwnmsac
>+ || instance.base == bases::vfwnmacc || instance.base == bases::vfwmul
>+ || instance.base == bases::vfcvt_x || instance.base == bases::vfcvt_f
>+ || instance.base == bases::vfcvt_xu || instance.base == bases::vfwmsac
>+ || instance.base == bases::vfwmacc || instance.base == bases::vfwcvt_x
>+ || instance.base == bases::vfwadd || instance.base == bases::vfsub
>+ || instance.base == bases::vfsqrt || instance.base == bases::vfredusum
>+ || instance.base == bases::vfrsub || instance.base == bases::vfredosum
>+ || instance.base == bases::vfrec7 || instance.base == bases::vfrdiv
>+ || instance.base == bases::vfnmsub || instance.base == bases::vfnmsac
>+ || instance.base == bases::vfnmadd || instance.base == bases::vfnmacc
>+ || instance.base == bases::vfncvt_f || instance.base == bases::vfncvt_x
>+ || instance.base == bases::vfncvt_xu || instance.base == bases::vfmul
>+ || instance.base == bases::vfmsub || instance.base == bases::vfmsac
>+ || instance.base == bases::vfmadd || instance.base == bases::vfmacc
>+ || instance.base == bases::vfdiv || instance.base == bases::vfwcvt_xu;
>+}
>+
>+static bool
>+maybe_require_vxrm_p (function_instance )
>+{
>+ return instance.base == bases::vaadd || instance.base == bases::vaaddu
>+ || instance.base == bases::vasub || instance.base == bases::vasubu
>+ || instance.base == bases::vssrl || instance.base == bases::vssra
>+ || instance.base == bases::vsmul || instance.base == bases::vnclipu
>+ || instance.base == bases::vnclip;
>+}
>
>I am sorry that I didn't was wrong before.
>
>Could we add maybe_require_frm_p and maybe_require_vxrm_p into function_base ?
>By default it is FALSE.
>
>In riscv-vector-builtins-bases.cc, set them in each corresponding
>function_base:
>
>For example:
>
>class vsmul :: public function_base
>bool maybe_require_vxrm_p () const
>{
> return true;
>}
>
>The benefits is that you only need to use instance.base.maybe_require_frm_p ()
>or instance.base.maybe_require_vxrm_p ()
>And no need to compare them one by one.
>
>Thanks.
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-31 10:24
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH V5] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV
>intrinsic
>From: xuli
>
>Update in v5:
>* Split has_vxrm_or_frm_p into maybe_require_frm_p and
> maybe_require_vxrm_p.
>* Adjust comments.
>
>Update in v4:
>* Remove class function_resolver.
>* Remove function get_non_overloaded_instance.
>* Add overloaded hash traits for non-overloaded intrinsic.
>* All overloaded intrinsics are implemented, and the tests pass.
>
>Update in v3:
>
>* Rewrite comment for overloaded function add.
>* Move get_non_overloaded_instance to function_base.
>
>Update in v2:
>
>* Add get_non_overloaded_instance for function instance.
>* Fix overload check for policy function.
>* Enrich the test cases check.
>
>Original log:
>
>This patch would like add the framework to support the RVV overloaded
>intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did.
>
>However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN
>with below steps.
>
>* Register overloaded functions.
>* Add function_resolver for overloaded function resolving.
>* Add resolve API for function shape with default implementation.
>* Implement HOOK for navigating the overloaded API to non-overloaded API.
>
>gcc/ChangeLog:
>
> * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): New
>function for the hook.
> (riscv_register_
Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Already backported to releases/gcc-13.
--
Li Xu
>Ok for gcc 13 but just wait one more week to make sure everything is fine
>as gcc convention :)
>
>Li Xu 於 2023年10月24日 週二，15:49寫道：
>
>> Committed to trunk. Thanks juzhe.
>>
>>
>> ------
>>
>>
>>
>> Li Xu
>>
>>
>>
>> >Ok for trunk (You can commit it to the trunk now).
>>
>>
>>
>> >
>>
>>
>>
>> >For GCC-13, I'd like to wait for kito's comment.
>>
>>
>>
>> >
>>
>>
>>
>> >Thanks.
>>
>>
>>
>> >
>>
>>
>>
>> >
>>
>>
>>
>> >juzhe.zh...@rivai.ai
>>
>>
>>
>> >
>>
>>
>>
>> >From: Li Xu
>>
>>
>>
>> >Date: 2023-10-24 15:29
>>
>>
>>
>> >To: gcc-patches
>>
>>
>>
>> >CC: kito.cheng; palmer; juzhe.zhong
>>
>>
>>
>> >Subject: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
>>
>>
>>
>> >
>>
>>
>>
>> >Calling vget/vset intrinsic without receiving a return value will cause
>>
>>
>>
>> >a crash. Because in this case e.target is null.
>>
>>
>>
>> >This patch should be backported to releases/gcc-13.
>>
>>
>>
>> >
>>
>>
>>
>> > PR/target 111935
>>
>>
>>
>> >
>>
>>
>>
>> >gcc/ChangeLog:
>>
>>
>>
>> >
>>
>>
>>
>> > * config/riscv/riscv-vector-builtins-bases.cc: fix bug.
>>
>>
>>
>> >
>>
>>
>>
>> >gcc/testsuite/ChangeLog:
>>
>>
>>
>> >
>>
>>
>>
>> > * gcc.target/riscv/rvv/base/pr111935.c: New test.
>>
>>
>>
>> >---
>>
>>
>>
>> > .../riscv/riscv-vector-builtins-bases.cc | 4 +++
>>
>>
>>
>> > .../gcc.target/riscv/rvv/base/pr111935.c | 26 +++
>>
>>
>>
>> > 2 files changed, 30 insertions(+)
>>
>>
>>
>> > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>>
>>
>>
>> >
>>
>>
>>
>> >diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>>
>>
>>
>> >index ab12e130907..0b1409a52e0 100644
>>
>>
>>
>> >--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>>
>>
>>
>> >+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>>
>>
>>
>> >@@ -1740,6 +1740,8 @@ public:
>>
>>
>>
>> >
>>
>>
>>
>> > rtx expand (function_expander ) const override
>>
>>
>>
>> > {
>>
>>
>>
>> >+ if (!e.target)
>>
>>
>>
>> >+ return NULL_RTX;
>>
>>
>>
>> > rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0));
>>
>>
>>
>> > gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest)));
>>
>>
>>
>> > rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
>>
>>
>>
>> >@@ -1777,6 +1779,8 @@ public:
>>
>>
>>
>> >
>>
>>
>>
>> > rtx expand (function_expander ) const override
>>
>>
>>
>> > {
>>
>>
>>
>> >+ if (!e.target)
>>
>>
>>
>> >+ return NULL_RTX;
>>
>>
>>
>> > rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
>>
>>
>>
>> > gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
>>
[PATCH V5] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
From: xuli Update in v5: * Split has_vxrm_or_frm_p into maybe_require_frm_p and maybe_require_vxrm_p. * Adjust comments. Update in v4: * Remove class function_resolver. * Remove function get_non_overloaded_instance. * Add overloaded hash traits for non-overloaded intrinsic. * All overloaded intrinsics are implemented, and the tests pass. Update in v3: * Rewrite comment for overloaded function add. * Move get_non_overloaded_instance to function_base. Update in v2: * Add get_non_overloaded_instance for function instance. * Fix overload check for policy function. * Enrich the test cases check. Original log: This patch would like add the framework to support the RVV overloaded intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did. However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN with below steps. * Register overloaded functions. * Add function_resolver for overloaded function resolving. * Add resolve API for function shape with default implementation. * Implement HOOK for navigating the overloaded API to non-overloaded API. gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): New function for the hook. (riscv_register_pragmas): Register the hook. * config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl. * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Register overloaded function. * config/riscv/riscv-vector-builtins.cc (struct non_overloaded_registered_function_hasher): New hash table. (function_builder::add_function): Add overloaded arg. (function_builder::add_unique_function): Map overloaded function to non-overloaded function. (function_builder::add_overloaded_function): New API impl. (registered_function::overloaded_hash): Calculate hash value. (maybe_require_frm_p): New function impl. (maybe_require_vxrm_p): Ditto. (has_vxrm_or_frm_p): Ditto. (non_overloaded_registered_function_hasher::hash): Ditto. (non_overloaded_registered_function_hasher::equal): Ditto. (handle_pragma_vector): Allocate space for hash table. (resolve_overloaded_builtin): New function impl. * config/riscv/riscv-vector-builtins.h: Add additional parameters to add_function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: New test. * gcc.target/riscv/rvv/base/overloaded_vadd.h: New test. * gcc.target/riscv/rvv/base/overloaded_vfadd.h: New test. * gcc.target/riscv/rvv/base/overloaded_vget_vset.h: New test. * gcc.target/riscv/rvv/base/overloaded_vloxseg2ei16.h: New test. * gcc.target/riscv/rvv/base/overloaded_vmv.h: New test. * gcc.target/riscv/rvv/base/overloaded_vreinterpret.h: New test. Signed-off-by: Li Xu Co-Authored-By: Pan Li --- gcc/config/riscv/riscv-c.cc | 36 ++- gcc/config/riscv/riscv-protos.h | 1 + .../riscv/riscv-vector-builtins-shapes.cc | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 259 +- gcc/config/riscv/riscv-vector-builtins.h | 5 +- .../riscv/rvv/base/overloaded_rv32_vadd.c | 12 + .../riscv/rvv/base/overloaded_rv32_vfadd.c| 12 + .../rvv/base/overloaded_rv32_vget_vset.c | 7 + .../rvv/base/overloaded_rv32_vloxseg2ei16.c | 11 + .../riscv/rvv/base/overloaded_rv32_vmv.c | 10 + .../rvv/base/overloaded_rv32_vreinterpret.c | 10 + .../riscv/rvv/base/overloaded_rv64_vadd.c | 11 + .../riscv/rvv/base/overloaded_rv64_vfadd.c| 11 + .../rvv/base/overloaded_rv64_vget_vset.c | 6 + .../rvv/base/overloaded_rv64_vloxseg2ei16.c | 10 + .../riscv/rvv/base/overloaded_rv64_vmv.c | 10 + .../rvv/base/overloaded_rv64_vreinterpret.c | 9 + .../riscv/rvv/base/overloaded_vadd.h | 59 .../riscv/rvv/base/overloaded_vfadd.h | 67 + .../riscv/rvv/base/overloaded_vget_vset.h | 27 ++ .../riscv/rvv/base/overloaded_vloxseg2ei16.h | 39 +++ .../riscv/rvv/base/overloaded_vmv.h | 26 ++ .../riscv/rvv/base/overloaded_vreinterpret.h | 29 ++ 23
Re: Re: [PATCH V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
OK, I will send patch v5.
--
Li Xu
>Ok. Understand.
>
>Could you add wrapper "maybe_require_vxrm_p" and "maybe_require_frm_p" ?
>
>static bool
>maybe_require_frm_p
>return instance.base == bases::vfwredusum || instance.base == bases::vfwredosum
>+ || instance.base == bases::vfadd || instance.base == bases::vfwsub
>+ || instance.base == bases::vfwnmsac || instance.base == bases::vfwnmacc
>+ || instance.base == bases::vfwmul || instance.base == bases::vfcvt_x
>+ || instance.base == bases::vfcvt_f || instance.base == bases::vfcvt_xu
>+ || instance.base == bases::vfwmsac || instance.base == bases::vfwmacc
>+ || instance.base == bases::vfwcvt_x || instance.base == bases::vfwadd
>+ || instance.base == bases::vfsub || instance.base == bases::vfsqrt
>+ || instance.base == bases::vfredusum || instance.base == bases::vfrsub
>+ || instance.base == bases::vfredosum || instance.base == bases::vfrec7
>+ || instance.base == bases::vfrdiv || instance.base == bases::vfnmsub
>+ || instance.base == bases::vfnmsac || instance.base == bases::vfnmadd
>+ || instance.base == bases::vfnmacc || instance.base == bases::vfncvt_f
>+ || instance.base == bases::vfncvt_x || instance.base == bases::vfncvt_xu
>+ || instance.base == bases::vfmul || instance.base == bases::vfmsub
>+ || instance.base == bases::vfmsac || instance.base == bases::vfmadd
>+ || instance.base == bases::vfmacc || instance.base == bases::vfdiv
>+ || instance.base == bases::vfwcvt_xu
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-30 18:04
>To: juzhe.zhong; gcc-patches
>CC: kito.cheng; palmer
>Subject: Re: Re: [PATCH V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for
>RVV intrinsic
>
>
>
>--
>
>
>
>Li Xu
>
>
>
>>Thanks.
>
>
>
>>
>
>
>
>>I like this 'HASH' solution which is much more reasonable to me.
>
>
>
>>
>
>
>
>>Some comments here:
>
>
>
>>
>
>
>
>>+bool
>
>
>
>>+has_vxrm_or_frm_p (function_instance , const vec
>>)
>
>
>
>>+{
>
>
>
>>+ /* Vector fixed-point arithmetic instructions requiring argument vxrm.
>
>
>
>>+ For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2, vuint32m4_t
>>vs1,
>
>
>
>>+ unsigned int vxrm, size_t vl);
>
>
>
>>+ The user calls vaaddu intrinsic in the form of __riscv_vaaddu(vs2, vs1,
>>2,
>
>
>
>>+ vl). The compiler recognizes that the parameter vxrm is a signed int,
>>which
>
>
>
>>+ is inconsistent with the parameter unsigned int vxrm declared by
>>intrinsic,
>
>
>
>>+ so the parameter vxrm is converted to an unsigned int type in order to
>>get
>
>
>
>>+ correct hash value. */
>
>
>
>>+ if (instance.base == bases::vaadd || instance.base == bases::vaaddu
>
>
>
>>+ || instance.base == bases::vasub || instance.base == bases::vasubu
>
>
>
>>+ || instance.base == bases::vssrl || instance.base == bases::vssra
>
>
>
>>+ || instance.base == bases::vsmul || instance.base == bases::vnclipu
>
>
>
>>+ || instance.base == bases::vnclip)
>
>
>
>>+ return true;
>
>
>
>>+
>
>
>
>>+ /* Vector Floating-Point Instructions requiring argument frm. */
>
>
>
>>+ if (instance.base == bases::vfwredusum || instance.base ==
>>bases::vfwredosum
>
>
>
>>+ || instance.base == bases::vfadd || instance.base == bases::vfwsub
>
>
>
>>+ || instance.base == bases::vfwnmsac || instance.base == bases::vfwnmacc
>
>
>
>>+ || instance.base == bases::vfwmul || instance.base == bases::vfcvt_x
>
>
>
>>+ || instance.base == bases::vfcvt_f || instance.base == bases::vfcvt_xu
>
>
>
>>+ || instance.base == bases::vfwmsac || instance.base == bases::vfwmacc
>
>
>
>>+
Re: Re: [PATCH V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
--
Li Xu
>Thanks.
>
>I like this 'HASH' solution which is much more reasonable to me.
>
>Some comments here:
>
>+bool
>+has_vxrm_or_frm_p (function_instance , const vec
>)
>+{
>+ /* Vector fixed-point arithmetic instructions requiring argument vxrm.
>+ For example: vuint32m4_t __riscv_vaaddu(vuint32m4_t vs2, vuint32m4_t vs1,
>+ unsigned int vxrm, size_t vl);
>+ The user calls vaaddu intrinsic in the form of __riscv_vaaddu(vs2, vs1,
>2,
>+ vl). The compiler recognizes that the parameter vxrm is a signed int,
>which
>+ is inconsistent with the parameter unsigned int vxrm declared by
>intrinsic,
>+ so the parameter vxrm is converted to an unsigned int type in order to
>get
>+ correct hash value. */
>+ if (instance.base == bases::vaadd || instance.base == bases::vaaddu
>+ || instance.base == bases::vasub || instance.base == bases::vasubu
>+ || instance.base == bases::vssrl || instance.base == bases::vssra
>+ || instance.base == bases::vsmul || instance.base == bases::vnclipu
>+ || instance.base == bases::vnclip)
>+ return true;
>+
>+ /* Vector Floating-Point Instructions requiring argument frm. */
>+ if (instance.base == bases::vfwredusum || instance.base == bases::vfwredosum
>+ || instance.base == bases::vfadd || instance.base == bases::vfwsub
>+ || instance.base == bases::vfwnmsac || instance.base == bases::vfwnmacc
>+ || instance.base == bases::vfwmul || instance.base == bases::vfcvt_x
>+ || instance.base == bases::vfcvt_f || instance.base == bases::vfcvt_xu
>+ || instance.base == bases::vfwmsac || instance.base == bases::vfwmacc
>+ || instance.base == bases::vfwcvt_x || instance.base == bases::vfwadd
>+ || instance.base == bases::vfsub || instance.base == bases::vfsqrt
>+ || instance.base == bases::vfredusum || instance.base == bases::vfrsub
>+ || instance.base == bases::vfredosum || instance.base == bases::vfrec7
>+ || instance.base == bases::vfrdiv || instance.base == bases::vfnmsub
>+ || instance.base == bases::vfnmsac || instance.base == bases::vfnmadd
>+ || instance.base == bases::vfnmacc || instance.base == bases::vfncvt_f
>+ || instance.base == bases::vfncvt_x || instance.base == bases::vfncvt_xu
>+ || instance.base == bases::vfmul || instance.base == bases::vfmsub
>+ || instance.base == bases::vfmsac || instance.base == bases::vfmadd
>+ || instance.base == bases::vfmacc || instance.base == bases::vfdiv
>+ || instance.base == bases::vfwcvt_xu)
>+ {
>+ /* DEF_RVV_FUNCTION (vfadd, alu, full_preds, f_vvv_ops)
>+ DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops)
>+ Taking vfadd as an example, theoretically we can add base or shape to
>+ the hash value to distinguish whether the frm parameter is required.
>+ vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, float32_t rs1, size_t vl);
>+ vfloat32m1_t __riscv_vfadd(vfloat32m1_t vs2, vfloat32m1_t vs1, unsigned
>+ int frm, size_t vl);
>+
>+ However, the current registration mechanism of overloaded intinsic for
>+ gcc limits the intrinsic obtained by entering the hook to always be
>+ vfadd, not vfadd_frm. Therefore, the correct hash value cannot be
>+ obtained through the parameter list and overload name, base or shape.
>+ ++---+---+
>+ | index | name | kind |
>+ ++---+---+
>+ | 124733 | __riscv_vfadd | Overloaded | <- Hook fun
>code
>+ ++---+---+
>+ | 124735 | __riscv_vfadd_vv_f32m1 | Non-overloaded |
>+ ++---+---+
>+ | 124737 | __riscv_vfadd | Placeholder |
>+ ++---+---+
>+ | ... |
>+ ++---+---+
>+ | ... |
>+ ++---+---+
>+ | 125739 | __riscv_vfadd | Overloaded |
>+ ++---+---+
>+ | 125741 | __riscv_vfadd_vv_f32m1_rm | Non-overloaded |
>+ ++---+-
[PATCH V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
From: xuli Update in v4: * Remove class function_resolver. * Remove function get_non_overloaded_instance. * Add overloaded hash traits for non-overloaded intrinsic. * All overloaded intrinsics are implemented, and the tests pass. Update in v3: * Rewrite comment for overloaded function add. * Move get_non_overloaded_instance to function_base. Update in v2: * Add get_non_overloaded_instance for function instance. * Fix overload check for policy function. * Enrich the test cases check. Original log: This patch would like add the framework to support the RVV overloaded intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did. However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN with below steps. * Register overloaded functions. * Add function_resolver for overloaded function resolving. * Add resolve API for function shape with default implementation. * Implement HOOK for navigating the overloaded API to non-overloaded API. We validated this framework by the vmv_v intrinsic API(s), and we will add more intrins API support in the underlying patches. gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): New function for the hook. (riscv_register_pragmas): Register the hook. * config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl. * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Register overloaded function. * config/riscv/riscv-vector-builtins.cc (struct non_overloaded_registered_function_hasher): New hash table. (function_builder::add_function): Add overloaded arg. (function_builder::add_unique_function): Map overloaded function to non-overloaded function. (function_builder::add_overloaded_function): New API impl. (registered_function::overloaded_hash): Calculate hash value. (has_vxrm_or_frm_p): New function impl. (non_overloaded_registered_function_hasher::hash): Ditto. (non_overloaded_registered_function_hasher::equal): Ditto. (handle_pragma_vector): Allocate space for hash table. (resolve_overloaded_builtin): New function impl. * config/riscv/riscv-vector-builtins.h: Add additional parameters to add_function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c: New test. * gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: New test. * gcc.target/riscv/rvv/base/overloaded_vadd.h: New test. * gcc.target/riscv/rvv/base/overloaded_vfadd.h: New test. * gcc.target/riscv/rvv/base/overloaded_vget_vset.h: New test. * gcc.target/riscv/rvv/base/overloaded_vloxseg2ei16.h: New test. * gcc.target/riscv/rvv/base/overloaded_vmv.h: New test. * gcc.target/riscv/rvv/base/overloaded_vreinterpret.h: New test. Signed-off-by: Li Xu Co-Authored-By: Pan Li --- gcc/config/riscv/riscv-c.cc | 36 ++- gcc/config/riscv/riscv-protos.h | 1 + .../riscv/riscv-vector-builtins-shapes.cc | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 255 +- gcc/config/riscv/riscv-vector-builtins.h | 5 +- .../riscv/rvv/base/overloaded_rv32_vadd.c | 12 + .../riscv/rvv/base/overloaded_rv32_vfadd.c| 12 + .../rvv/base/overloaded_rv32_vget_vset.c | 7 + .../rvv/base/overloaded_rv32_vloxseg2ei16.c | 11 + .../riscv/rvv/base/overloaded_rv32_vmv.c | 10 + .../rvv/base/overloaded_rv32_vreinterpret.c | 10 + .../riscv/rvv/base/overloaded_rv64_vadd.c | 11 + .../riscv/rvv/base/overloaded_rv64_vfadd.c| 11 + .../rvv/base/overloaded_rv64_vget_vset.c | 6 + .../rvv/base/overloaded_rv64_vloxseg2ei16.c | 10 + .../riscv/rvv/base/overloaded_rv64_vmv.c | 10 + .../rvv/base/overloaded_rv64_vreinterpret.c | 9 + .../riscv/rvv/base/overloaded_vadd.h | 59 .../riscv/rvv/base/overloaded_vfadd.h | 67 + .../riscv/rvv/base/overloaded_vget_vset.h | 27 ++ .../riscv/rvv/base/overloaded_vloxseg2ei16.h | 39 +++ .../riscv/rvv/base/overloaded_vmv.h | 26 ++ .../riscv/rvv/base/overloaded_vreinterpret.h | 29 ++ 23 files changed, 653 insertions(+), 11 deletions(-) create mode 100644 gcc
Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Committed to trunk. Thanks juzhe.
--
Li Xu
>Ok for trunk (You can commit it to the trunk now).
>
>For GCC-13, I'd like to wait for kito's comment.
>
>Thanks.
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-24 15:29
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong
>Subject: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
>
>Calling vget/vset intrinsic without receiving a return value will cause
>a crash. Because in this case e.target is null.
>This patch should be backported to releases/gcc-13.
>
> PR/target 111935
>
>gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc: fix bug.
>
>gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr111935.c: New test.
>---
> .../riscv/riscv-vector-builtins-bases.cc | 4 +++
> .../gcc.target/riscv/rvv/base/pr111935.c | 26 +++
> 2 files changed, 30 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>
>diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>index ab12e130907..0b1409a52e0 100644
>--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>@@ -1740,6 +1740,8 @@ public:
>
> rtx expand (function_expander ) const override
> {
>+ if (!e.target)
>+ return NULL_RTX;
> rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0));
> gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest)));
> rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
>@@ -1777,6 +1779,8 @@ public:
>
> rtx expand (function_expander ) const override
> {
>+ if (!e.target)
>+ return NULL_RTX;
> rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
> gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
> rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>new file mode 100644
>index 000..0b936d849a1
>--- /dev/null
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>@@ -0,0 +1,26 @@
>+/* { dg-do compile } */
>+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */
>+
>+#include "riscv_vector.h"
>+
>+inline vuint32m4_t __attribute__((__always_inline__)) transpose_indexes() {
>+ static const uint32_t idx_[16] = {0, 4, 8, 12,
>+ 1, 5, 9, 13,
>+ 2, 6, 10, 14,
>+ 3, 7, 11, 15};
>+ return __riscv_vle32_v_u32m4(idx_, 16);
>+}
>+
>+void pffft_real_preprocess_4x4(const float *in) {
>+ vfloat32m1_t r0=__riscv_vle32_v_f32m1(in,4);
>+ vfloat32m4_t tmp = __riscv_vundefined_f32m4();
>+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 0, r0);
>+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 1, r0);
>+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 2, r0);
>+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 3, r0);
>+ tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16);
>+ r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0);
>+}
>+
>+/* { dg-final { scan-assembler-times
>{vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 10 } } */
>+/* { dg-final { scan-assembler-times
>{vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 8 } } */
>--
>2.17.1
>
>
>xu...@eswincomputing.com
[PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Calling vget/vset intrinsic without receiving a return value will cause
a crash. Because in this case e.target is null.
This patch should be backported to releases/gcc-13.
PR/target 111935
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: fix bug.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr111935.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 4 +++
.../gcc.target/riscv/rvv/base/pr111935.c | 26 +++
2 files changed, 30 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ab12e130907..0b1409a52e0 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1740,6 +1740,8 @@ public:
rtx expand (function_expander ) const override
{
+if (!e.target)
+ return NULL_RTX;
rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0));
gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest)));
rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
@@ -1777,6 +1779,8 @@ public:
rtx expand (function_expander ) const override
{
+if (!e.target)
+ return NULL_RTX;
rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
new file mode 100644
index 000..0b936d849a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+inline vuint32m4_t __attribute__((__always_inline__)) transpose_indexes() {
+ static const uint32_t idx_[16] = {0, 4, 8, 12,
+ 1, 5, 9, 13,
+ 2, 6, 10, 14,
+ 3, 7, 11, 15};
+ return __riscv_vle32_v_u32m4(idx_, 16);
+}
+
+void pffft_real_preprocess_4x4(const float *in) {
+ vfloat32m1_t r0=__riscv_vle32_v_f32m1(in,4);
+ vfloat32m4_t tmp = __riscv_vundefined_f32m4();
+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 0, r0);
+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 1, r0);
+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 2, r0);
+ tmp = __riscv_vset_v_f32m1_f32m4(tmp, 3, r0);
+ tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16);
+ r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0);
+}
+
+/* { dg-final { scan-assembler-times
{vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 10 } } */
+/* { dg-final { scan-assembler-times
{vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 8 } } */
--
2.17.1
xu...@eswincomputing.com
RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Calling vget/vset intrinsic without receiving a return value will cause
a crash. Because in this case e.target is null.
This patch should be backported to releases/gcc-13.
PR target/111935
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Don't use the e.target directly.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vget_vset.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 13 ++--
.../gcc.target/riscv/rvv/base/vget_vset.c | 74 +++
2 files changed, 81 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ab12e130907..4c9209bec6d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1745,11 +1745,12 @@ public:
rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 2));
poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (src));
-emit_move_insn (e.target, dest);
-rtx subreg = simplify_gen_subreg (GET_MODE (src), e.target,
- GET_MODE (e.target), offset);
+rtx ret = gen_reg_rtx (GET_MODE (dest));
+emit_move_insn (ret, dest);
+rtx subreg = simplify_gen_subreg (GET_MODE (src), ret,
+ GET_MODE (ret), offset);
emit_move_insn (subreg, src);
-return e.target;
+return ret;
}
};
@@ -1780,9 +1781,9 @@ public:
rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
-poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (e.target));
+poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (e.ret_mode ());
rtx subreg
- = simplify_gen_subreg (GET_MODE (e.target), src, GET_MODE (src), offset);
+ = simplify_gen_subreg (e.ret_mode (), src, GET_MODE (src), offset);
return subreg;
}
};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
new file mode 100644
index 000..e0d03871a64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
@@ -0,0 +1,74 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O0 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+void test_vget_v_f16m8_f16m1(vfloat16m8_t src, size_t index) {
+ __riscv_vget_v_f16m8_f16m1(src, 0);
+}
+
+void test_vget_v_f32m4_f32m1(vfloat32m4_t src, size_t index) {
+ __riscv_vget_v_f32m4_f32m1(src, 0);
+}
+
+void test_vget_v_f64m2_f64m1(vfloat64m2_t src, size_t index) {
+ __riscv_vget_v_f64m2_f64m1(src, 0);
+}
+
+void test_vget_v_i8m4_i8m1(vint8m4_t src, size_t index) {
+ __riscv_vget_v_i8m4_i8m1(src, 0);
+}
+
+void test_vget_v_i16m2_i16m1(vint16m2_t src, size_t index) {
+ __riscv_vget_v_i16m2_i16m1(src, 0);
+}
+
+void test_vget_v_i32m4_i32m1(vint32m4_t src, size_t index) {
+ __riscv_vget_v_i32m4_i32m1(src, 0);
+}
+
+void test_vget_v_i64m4_i64m1(vint64m4_t src, size_t index) {
+ __riscv_vget_v_i64m4_i64m1(src, 0);
+}
+
+void test_vset_v_f16m1_f16m4(vfloat16m4_t dest, size_t index,
+ vfloat16m1_t value) {
+ __riscv_vset_v_f16m1_f16m4(dest, 0, value);
+}
+
+void test_vset_v_f32m1_f32m2(vfloat32m2_t dest, size_t index,
+ vfloat32m1_t value) {
+ __riscv_vset_v_f32m1_f32m2(dest, 0, value);
+}
+
+void test_vset_v_f64m1_f64m4(vfloat64m4_t dest, size_t index,
+ vfloat64m1_t value) {
+ __riscv_vset_v_f64m1_f64m4(dest, 0, value);
+}
+
+void test_vset_v_i8m1_i8m4(vint8m4_t dest, size_t index, vint8m1_t value) {
+ __riscv_vset_v_i8m1_i8m4(dest, 0, value);
+}
+
+void test_vset_v_i16m1_i16m2(vint16m2_t dest, size_t index,
+ vint16m1_t value) {
+ __riscv_vset_v_i16m1_i16m2(dest, 0, value);
+}
+
+void test_vset_v_i32m1_i32m4(vint32m4_t dest, size_t index,
+ vint32m1_t value) {
+ __riscv_vset_v_i32m1_i32m4(dest, 0, value);
+}
+
+void test_vset_v_i64m1_i64m2(vint64m2_t dest, size_t index,
+ vint64m1_t value) {
+ __riscv_vset_v_i64m1_i64m2(dest, 0, value);
+}
+
+/* { dg-final { scan-assembler-times
{vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 27 } } */
+/* { dg-final { scan-assembler-times
{vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 21 } } */
--
2.17.1
xu...@eswincomputing.com
Re: Re: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
Commited, thanks juzhe.
--
Li Xu
>OK.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-07 11:18
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
>From: xuli
>
>gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust assembler
>times.
> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto.
>---
>.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +-
>.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 +-
>2 files changed, 10 insertions(+), 10 deletions(-)
>
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>index c566f8a4751..2ec9487a6c6 100644
>--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>@@ -88,8 +88,8 @@ void f (void * restrict in, void * restrict out, int n, int
>cond)
> }
>}
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0"
>no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
>"-g" } } } } */
>+/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 10 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-times {vsetvli} 19 { target { no-opts "-O0"
>no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
>"-g" } } } } */
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>index d0e75258188..bcafce36895 100644
>--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>@@ -80,8 +80,8 @@ void f (void * restrict in, void * restrict out, int n, int
>cond)
> }
>}
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>
[PATCH] RISC-V: Fix scan-assembler-times of RVV test case
From: xuli
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust assembler
times.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto.
---
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
index c566f8a4751..2ec9487a6c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
@@ -88,8 +88,8 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
}
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 10 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} { target { no-opts
"-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops"
no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 19 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
index d0e75258188..bcafce36895 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
@@ -80,8 +80,8 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
}
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 9 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-not
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
Re: Re: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
Committed, thanks juzhe.
--
Li Xu
>LGTM. Thanks for fixing it.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-09-28 09:33
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
>From: xuli
>
>Consider the flowing situation:
>BB5: local_dem(RVV Insn 1, AVL(reg zero))
>RVV Insn 1: vmv.s.x, AVL (const_int 1)
>RVV Insn 2: vredsum.vs, AVL(reg zero)
>
>vmv.s.x has vl operand, the following code will get
>avl (cosnt_int) from RVV Insn 1.
>rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ())
> : dem.get_avl ();
>
>If use REGNO for const_int, the compiler will crash:
>
>during RTL pass: vsetvl
>res_debug.c: In function '__dn_count_labels':
>res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg',
>have 'const_int' in rhs_regno, at rtl.h:1934
>1050 | }
> | ^
>0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
>char const*)
>../.././gcc/gcc/rtl.cc:770
>0x1399818 rhs_regno(rtx_def const*)
>../.././gcc/gcc/rtl.h:1934
>0x1399818 anticipatable_occurrence_p
>../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348
>
>So in this case avl should be obtained from dem.
>
>Another issue is caused by the following code:
>HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i;
>
>during RTL pass: expand
>../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4':
>../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler
>error: RTL check:
>expected code 'const_int', have 'const_poly_int' in expand_const_vector,
>at config/riscv/riscv-v.cc:1149
>
>The builder.elt (i) can be either const_int or const_poly_int.
>
>PR target/111533
>
>gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (expand_const_vector): Fix bug.
>* config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug.
>
>gcc/testsuite/ChangeLog:
>
>* gcc.target/riscv/rvv/base/pr111533-1.c: New test.
>* gcc.target/riscv/rvv/base/pr111533-2.c: New test.
>---
>gcc/config/riscv/riscv-v.cc | 5 ++--
>gcc/config/riscv/riscv-vsetvl.cc | 3 +-
>.../gcc.target/riscv/rvv/base/pr111533-1.c | 15 ++
>.../gcc.target/riscv/rvv/base/pr111533-2.c | 29 +++
>4 files changed, 48 insertions(+), 4 deletions(-)
>create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
>create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c
>
>diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
>index 359fb2ced8b..26700cfc732 100644
>--- a/gcc/config/riscv/riscv-v.cc
>+++ b/gcc/config/riscv/riscv-v.cc
>@@ -1149,8 +1149,9 @@ expand_const_vector (rtx target, rtx src)
> for (unsigned int i = 0; i < v.npatterns (); ++i)
>{
> /* Calculate the diff between the target sequence and
>- vid sequence. */
>- HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i;
>+ vid sequence. The elt (i) can be either const_int or
>+ const_poly_int. */
>+ poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i;
> v.quick_push (gen_int_mode (diff, v.inner_mode ()));
>}
> /* Step 2: Generate result = VID + diff. */
>diff --git a/gcc/config/riscv/riscv-vsetvl.cc
>b/gcc/config/riscv/riscv-vsetvl.cc
>index 7af33e7ea6f..af8c31d873c 100644
>--- a/gcc/config/riscv/riscv-vsetvl.cc
>+++ b/gcc/config/riscv/riscv-vsetvl.cc
>@@ -307,8 +307,7 @@ anticipatable_occurrence_p (const bb_info *bb, const
>vector_insn_info dem)
> if (dem.has_avl_reg ())
> {
> /* rs1 (avl) are not modified in the basic block prior to the VSETVL.
>*/
>- rtx avl
>- = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl ();
>+ rtx avl = dem.get_avl_or_vl_reg ();
> if (dem.dirty_p ())
>{
> gcc_assert (!vsetvl_insn_p (insn->rtl ()));
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
>b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
>new file mode 100644
>index 000..aba26dfac89
>--- /dev/null
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
>@@ -0,0 +1,15 @@
>+/* { dg-do compile } */
>+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -ffast-math -ftree-vectorize"
>} */
>+
>+#include
>+
>+typedef _Complex float GFC_COMPLEX_4;
>+
>+void
>+test (GFC_COMPLEX_4 *a, GFC_COMPLEX_4 *b, GFC_COMPLEX_4 c, ptrdiff_t i,
>ptrdiff_t j)
>+{
>+ ptrdiff_t l;
>+ for (l = 0; l <= i; ++l)
>+ c += b[l] * a[j];
>+ b[j] = c;
>+}
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c
>b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c
&
[PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV Insn 1: vmv.s.x, AVL (const_int 1)
RVV Insn 2: vredsum.vs, AVL(reg zero)
vmv.s.x has vl operand, the following code will get
avl (cosnt_int) from RVV Insn 1.
rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ())
: dem.get_avl ();
If use REGNO for const_int, the compiler will crash:
during RTL pass: vsetvl
res_debug.c: In function '__dn_count_labels':
res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg',
have 'const_int' in rhs_regno, at rtl.h:1934
1050 | }
| ^
0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
../.././gcc/gcc/rtl.cc:770
0x1399818 rhs_regno(rtx_def const*)
../.././gcc/gcc/rtl.h:1934
0x1399818 anticipatable_occurrence_p
../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348
So in this case avl should be obtained from dem.
Another issue is caused by the following code:
HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i;
during RTL pass: expand
../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4':
../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler
error: RTL check:
expected code 'const_int', have 'const_poly_int' in expand_const_vector,
at config/riscv/riscv-v.cc:1149
The builder.elt (i) can be either const_int or const_poly_int.
PR target/111533
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Fix bug.
* config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr111533-1.c: New test.
* gcc.target/riscv/rvv/base/pr111533-2.c: New test.
---
gcc/config/riscv/riscv-v.cc | 5 ++--
gcc/config/riscv/riscv-vsetvl.cc | 3 +-
.../gcc.target/riscv/rvv/base/pr111533-1.c| 15 ++
.../gcc.target/riscv/rvv/base/pr111533-2.c| 29 +++
4 files changed, 48 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 359fb2ced8b..26700cfc732 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1149,8 +1149,9 @@ expand_const_vector (rtx target, rtx src)
for (unsigned int i = 0; i < v.npatterns (); ++i)
{
/* Calculate the diff between the target sequence and
-vid sequence. */
- HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i;
+vid sequence. The elt (i) can be either const_int or
+const_poly_int. */
+ poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i;
v.quick_push (gen_int_mode (diff, v.inner_mode ()));
}
/* Step 2: Generate result = VID + diff. */
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 7af33e7ea6f..af8c31d873c 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -307,8 +307,7 @@ anticipatable_occurrence_p (const bb_info *bb, const
vector_insn_info dem)
if (dem.has_avl_reg ())
{
/* rs1 (avl) are not modified in the basic block prior to the VSETVL. */
- rtx avl
- = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl ();
+ rtx avl = dem.get_avl_or_vl_reg ();
if (dem.dirty_p ())
{
gcc_assert (!vsetvl_insn_p (insn->rtl ()));
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
new file mode 100644
index 000..aba26dfac89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -ffast-math -ftree-vectorize"
} */
+
+#include
+
+typedef _Complex float GFC_COMPLEX_4;
+
+void
+test (GFC_COMPLEX_4 *a, GFC_COMPLEX_4 *b, GFC_COMPLEX_4 c, ptrdiff_t i,
ptrdiff_t j)
+{
+ ptrdiff_t l;
+ for (l = 0; l <= i; ++l)
+c += b[l] * a[j];
+ b[j] = c;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c
new file mode 100644
index 000..a4d2011b74b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111533-2.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+
+#include
+
+/* Return the number of DNS hierarchy levels in the name. */
+int
+test (const char *name) {
+ int i, len, count;
+
+ len = strlen(name);
+ for (i = 0, count = 0; i < len; i++) {
+ /* XXX need to check for \. or use named's nlabels(). */
+ if (name[i] == '.')
+
[PATCH] RISC-V: Bugfix for RTL check[PR111533]
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV Insn 1: vmv.s.x, AVL (const_int 1)
RVV Insn 2: vredsum.vs, AVL(reg zero)
vmv.s.x has vl operand, the following code will get
avl (cosnt_int) from RVV Insn 1.
rtx avl = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ())
: dem.get_avl ();
If use REGNO for const_int, the compiler will crash:
during RTL pass: vsetvl
res_debug.c: In function '__dn_count_labels':
res_debug.c:1050:1: internal compiler error: RTL check: expected code 'reg',
have 'const_int' in rhs_regno, at rtl.h:1934
1050 | }
| ^
0x8fb169 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
../.././gcc/gcc/rtl.cc:770
0x1399818 rhs_regno(rtx_def const*)
../.././gcc/gcc/rtl.h:1934
0x1399818 anticipatable_occurrence_p
../.././gcc/gcc/config/riscv/riscv-vsetvl.cc:348
So in this case avl should be obtained from dem.
Another issue is caused by the following code:
HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i;
during RTL pass: expand
../../.././gcc/libgfortran/generated/matmul_c4.c: In function 'matmul_c4':
../../.././gcc/libgfortran/generated/matmul_c4.c:2906:39: internal compiler
error: RTL check:
expected code 'const_int', have 'const_poly_int' in expand_const_vector,
at config/riscv/riscv-v.cc:1149
The builder.elt (i) can be either const_int or const_poly_int.
PR target/111533
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Fix bug.
* config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix bug.
---
gcc/config/riscv/riscv-v.cc | 6 --
gcc/config/riscv/riscv-vsetvl.cc | 5 -
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 5f738634219..fb3c55b4705 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1147,8 +1147,10 @@ expand_const_vector (rtx target, rtx src)
for (unsigned int i = 0; i < v.npatterns (); ++i)
{
/* Calculate the diff between the target sequence and
-vid sequence. */
- HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i;
+vid sequence. The elt (i) can be either const_int or
+const_poly_int. */
+ HOST_WIDE_INT diff = rtx_to_poly_int64 (builder.elt
(i)).to_constant () - i;
+
v.quick_push (gen_int_mode (diff, v.inner_mode ()));
}
/* Step 2: Generate result = VID + diff. */
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 7af33e7ea6f..27000434341 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -308,7 +308,10 @@ anticipatable_occurrence_p (const bb_info *bb, const
vector_insn_info dem)
{
/* rs1 (avl) are not modified in the basic block prior to the VSETVL. */
rtx avl
- = has_vl_op (insn->rtl ()) ? get_vl (insn->rtl ()) : dem.get_avl ();
+ = (has_vl_op (insn->rtl ()) && REG_P (get_vl (insn->rtl (
+ ? get_vl (insn->rtl ())
+ : dem.get_avl ();
+
if (dem.dirty_p ())
{
gcc_assert (!vsetvl_insn_p (insn->rtl ()));
--
2.17.1
Re: Re: [PATCH V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
Committed, thanks Juzhe.
--
Li Xu
>LGTM. You can commit it after you pass the regression.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-09-22 10:37
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH V2] RISC-V: Optimization of vrgather.vv into
>vrgatherei16.vv[PR111451]
>From: xuli
>
>Consider this following case:
>
>typedef int32_t vnx32si __attribute__ ((vector_size (128)));
>
> __attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2,
>\
> TYPE *out) \
> {
>\
> TYPE v
>\
> = __builtin_shufflevector (values1, values2, MASK_##NUNITS (0, NUNITS));
>\
> *(TYPE *) out = v;
>\
> }
>
> T (vnx32si, 32)
>\
>
>TEST_ALL (PERMUTE)
>
>Before this patch:
> li a4,31
> vsetvli a5,zero,e32,m8,ta,ma
> vl8re32.v v24,0(a0)
> vid.v v8
> vrsub.vx v8,v8,a4
> vrgather.vv v16,v24,v8
> vs8r.v v16,0(a2)
> ret
>
>The index vector register "v8" occupies 8 registers.
>We should optimize it into vrgatherei16.vv which is
>using int16 as the index elements.
>
>After this patch:
> vsetvli a5,zero,e16,m4,ta,ma
> li a4,31
> vid.v v4
> vl8re32.v v16,0(a0)
> vrsub.vx v4,v4,a4
> vsetvli zero,zero,e32,m8,ta,ma
> vrgatherei16.vv v8,v16,v4
> vs8r.v v8,0(a2)
> ret
>With vrgatherei16.vv, the v8 will occupy 4 registers instead
>of 8. Lower the register consuming and register pressure.
>
>PR target/111451
>
>gcc/ChangeLog:
>
>* config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of
>vrgather.vv into vrgatherei16.vv.
>
>gcc/testsuite/ChangeLog:
>
>* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case.
>* gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto.
>---
>gcc/config/riscv/riscv-v.cc | 18 ++
>.../riscv/rvv/autovec/vls-vlmax/perm-4.c | 3 ++-
>.../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 3 ++-
>3 files changed, 22 insertions(+), 2 deletions(-)
>
>diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
>index 64a71a128d4..455efa7ea8a 100644
>--- a/gcc/config/riscv/riscv-v.cc
>+++ b/gcc/config/riscv/riscv-v.cc
>@@ -790,6 +790,24 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
> icode = code_for_pred_gather_scalar (data_mode);
> sel = elt;
> }
>+ else if (CONST_VECTOR_P (sel)
>+ && GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)) > 16
>+ && riscv_get_v_regno_alignment (data_mode) > 1)
>+ {
>+ /* If the inner mode of data is not QI or HI and data_lmul > 1,
>+ emitting vrgatherei16.vv instruction will lower register
>+ pressure.
>+ data_mode sel_mode ei16
>+ RVVM1QI RVVM1QI RVVM2HI not needed
>+ RVVM2QI RVVM2QI RVVM4HI not needed
>+ RVVM2HI RVVM2HI RVVM2HI not needed
>+ RVVM2SI RVVM2SI RVVM1HI need
>+ RVVM4SI RVVM4SI RVVM2HI need
>+ RVVM8DI RVVM8DI RVVM2HI need */
>+ PUT_MODE (sel, get_vector_mode (HImode,
>+ GET_MODE_NUNITS (data_mode)).require ());
>+ icode = code_for_pred_gatherei16 (data_mode);
>+ }
> else
> icode = code_for_pred_gather (data_mode);
> rtx ops[] = {target, op, sel};
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
>b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
>index 9df69a0cc2c..7ab31043547 100644
>--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
>@@ -55,6 +55,7 @@
>TEST_ALL (PERMUTE)
>-/* { dg-final { scan-assembler-times
>{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
>+/* { dg-final { scan-assembler-times
>{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
>+/* { dg-final { scan-assembler-times
>{vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
>/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
>/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
>b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
>index 46cad8ea2f4..4d6862cf1c0 100644
>--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
>@@ -3,6 +3,7 @@
>#include &q
[PATCH V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
From: xuli
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{\
TYPE v \
= __builtin_shufflevector (values1, values2, MASK_##NUNITS (0, NUNITS)); \
*(TYPE *) out = v; \
}
T (vnx32si, 32) \
TEST_ALL (PERMUTE)
Before this patch:
lia4,31
vsetvli a5,zero,e32,m8,ta,ma
vl8re32.v v24,0(a0)
vid.v v8
vrsub.vx v8,v8,a4
vrgather.vv v16,v24,v8
vs8r.vv16,0(a2)
ret
The index vector register "v8" occupies 8 registers.
We should optimize it into vrgatherei16.vv which is
using int16 as the index elements.
After this patch:
vsetvli a5,zero,e16,m4,ta,ma
lia4,31
vid.v v4
vl8re32.v v16,0(a0)
vrsub.vx v4,v4,a4
vsetvli zero,zero,e32,m8,ta,ma
vrgatherei16.vv v8,v16,v4
vs8r.vv8,0(a2)
ret
With vrgatherei16.vv, the v8 will occupy 4 registers instead
of 8. Lower the register consuming and register pressure.
PR target/111451
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of
vrgather.vv into vrgatherei16.vv.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case.
* gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto.
---
gcc/config/riscv/riscv-v.cc| 18 ++
.../riscv/rvv/autovec/vls-vlmax/perm-4.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 3 ++-
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 64a71a128d4..455efa7ea8a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -790,6 +790,24 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
icode = code_for_pred_gather_scalar (data_mode);
sel = elt;
}
+ else if (CONST_VECTOR_P (sel)
+ && GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)) > 16
+ && riscv_get_v_regno_alignment (data_mode) > 1)
+{
+ /* If the inner mode of data is not QI or HI and data_lmul > 1,
+ emitting vrgatherei16.vv instruction will lower register
+ pressure.
+ data_mode sel_mode ei16
+ RVVM1QIRVVM1QI RVVM2HI not needed
+ RVVM2QIRVVM2QI RVVM4HI not needed
+ RVVM2HIRVVM2HI RVVM2HI not needed
+ RVVM2SIRVVM2SI RVVM1HI need
+ RVVM4SIRVVM4SI RVVM2HI need
+ RVVM8DIRVVM8DI RVVM2HI need */
+ PUT_MODE (sel, get_vector_mode (HImode,
+GET_MODE_NUNITS (data_mode)).require ());
+ icode = code_for_pred_gatherei16 (data_mode);
+}
else
icode = code_for_pred_gather (data_mode);
rtx ops[] = {target, op, sel};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index 9df69a0cc2c..7ab31043547 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -55,6 +55,7 @@
TEST_ALL (PERMUTE)
-/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times
{vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
index 46cad8ea2f4..4d6862cf1c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
@@ -3,6 +3,7 @@
#include "../vls-vlmax/perm-4.c"
-/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times
{vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
--
2.17.1
[PATCH] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
From: xuli
Consider this following case:
typedef int32_t vnx32si __attribute__ ((vector_size (128)));
__attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \
TYPE *out) \
{\
TYPE v \
= __builtin_shufflevector (values1, values2, MASK_##NUNITS (0, NUNITS)); \
*(TYPE *) out = v; \
}
T (vnx32si, 32) \
TEST_ALL (PERMUTE)
Before this patch:
lia4,31
vsetvli a5,zero,e32,m8,ta,ma
vl8re32.v v24,0(a0)
vid.v v8
vrsub.vx v8,v8,a4
vrgather.vv v16,v24,v8
vs8r.vv16,0(a2)
ret
The index vector register "v8" occupies 8 registers.
We should optimize it into vrgatherei16.vv which is
using int16 as the index elements.
After this patch:
vsetvli a5,zero,e16,m4,ta,ma
lia4,31
vid.v v4
vl8re32.v v16,0(a0)
vrsub.vx v4,v4,a4
vsetvli zero,zero,e32,m8,ta,ma
vrgatherei16.vv v8,v16,v4
vs8r.vv8,0(a2)
ret
With vrgatherei16.vv, the v8 will occupy 4 registers instead
of 8. Lower the register consuming and register pressure.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of
vrgather.vv into vrgatherei16.vv.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case.
* gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto.
---
gcc/config/riscv/riscv-v.cc | 20 +++
.../riscv/rvv/autovec/vls-vlmax/perm-4.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 3 ++-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 64a71a128d4..271e0ff6dfc 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -783,6 +783,8 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
insn_code icode;
machine_mode data_mode = GET_MODE (target);
machine_mode sel_mode = GET_MODE (sel);
+ unsigned int data_sew = get_sew (data_mode);
+ enum vlmul_type data_lmul = get_vlmul (data_mode);
if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode)))
icode = code_for_pred_gatherei16 (data_mode);
else if (const_vec_duplicate_p (sel, ))
@@ -790,6 +792,24 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
icode = code_for_pred_gather_scalar (data_mode);
sel = elt;
}
+ else if (CONST_VECTOR_P (sel) && data_sew != 16
+ && data_sew != 8 && (data_lmul == LMUL_2
+ || data_lmul == LMUL_4 || data_lmul == LMUL_8))
+{
+ /* If the inner mode of data is not QI or HI and data_lmul > 1,
+ emitting vrgatherei16.vv instruction will lower register
+ pressure.
+ data_mode sel_mode ei16
+ RVVM1QIRVVM1QI RVVM2HI not needed
+ RVVM2QIRVVM2QI RVVM4HI not needed
+ RVVM2HIRVVM2HI RVVM2HI not needed
+ RVVM2SIRVVM2SI RVVM1HI need
+ RVVM4SIRVVM4SI RVVM2HI need
+ RVVM8DIRVVM8DI RVVM2HI need */
+ PUT_MODE (sel, get_vector_mode (HImode,
+GET_MODE_NUNITS (data_mode)).require ());
+ icode = code_for_pred_gatherei16 (data_mode);
+}
else
icode = code_for_pred_gather (data_mode);
rtx ops[] = {target, op, sel};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index 9df69a0cc2c..7ab31043547 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -55,6 +55,7 @@
TEST_ALL (PERMUTE)
-/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times
{vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 } } */
/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
index 46cad8ea2f4..4d6862cf1c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
@@ -3,6 +3,7 @@
#include "../vls-vlmax/perm-4.c"
-/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
+/* { dg-final { scan-assembler-times
{vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-times
{vrgatherei16\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 12 }
Re: Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]
Committed, thanks Juzhe. -- Li Xu >Thanks a lot. LGTM. > > > >juzhe.zh...@rivai.ai > >From: Li Xu >Date: 2023-09-21 11:12 >To: gcc-patches >CC: kito.cheng; palmer; juzhe.zhong; xuli >Subject: [PATCH] RISC-V: Optimized for strided load/store with stride == >element width[PR111450] >From: xuli > >When stride == element width, vlsse should be optimized into vle.v. >vsse should be optimized into vse.v. > >PR target/111450 > >gcc/ChangeLog: > >*config/riscv/constraints.md (c01): const_int 1. >(c02): const_int 2. >(c04): const_int 4. >(c08): const_int 8. >* config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for >stride operand. >(vector_eew16_stride_operand): Ditto. >(vector_eew32_stride_operand): Ditto. >(vector_eew64_stride_operand): Ditto. >* config/riscv/vector-iterators.md: New iterator for stride operand. >* config/riscv/vector.md: Add stride = element width constraint. > >gcc/testsuite/ChangeLog: > >* gcc.target/riscv/rvv/base/pr111450.c: New test. >--- >gcc/config/riscv/constraints.md | 20 >gcc/config/riscv/predicates.md | 18 >gcc/config/riscv/vector-iterators.md | 87 +++ >gcc/config/riscv/vector.md | 42 +--- >.../gcc.target/riscv/rvv/base/pr111450.c | 100 ++ >5 files changed, 250 insertions(+), 17 deletions(-) >create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c > >diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md >index 3f52bc76f67..964fdd450c9 100644 >--- a/gcc/config/riscv/constraints.md >+++ b/gcc/config/riscv/constraints.md >@@ -45,6 +45,26 @@ > (and (match_code "const_int") > (match_test "ival == 0"))) >+(define_constraint "c01" >+ "Constant value 1." >+ (and (match_code "const_int") >+ (match_test "ival == 1"))) >+ >+(define_constraint "c02" >+ "Constant value 2" >+ (and (match_code "const_int") >+ (match_test "ival == 2"))) >+ >+(define_constraint "c04" >+ "Constant value 4" >+ (and (match_code "const_int") >+ (match_test "ival == 4"))) >+ >+(define_constraint "c08" >+ "Constant value 8" >+ (and (match_code "const_int") >+ (match_test "ival == 8"))) >+ >(define_constraint "K" > "A 5-bit unsigned immediate for CSR access instructions." > (and (match_code "const_int") >diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md >index 4bc7ff2c9d8..7845998e430 100644 >--- a/gcc/config/riscv/predicates.md >+++ b/gcc/config/riscv/predicates.md >@@ -514,6 +514,24 @@ > (ior (match_operand 0 "const_0_operand") > (match_operand 0 "pmode_register_operand"))) >+;; [1, 2, 4, 8] means strided load/store with stride == element width >+(define_special_predicate "vector_eew8_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 1 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew16_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 2 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew32_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 4 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew64_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 8 || INTVAL (op) == 0" >+ >;; A special predicate that doesn't match a particular mode. >(define_special_predicate "vector_any_register_operand" > (match_code "reg")) >diff --git a/gcc/config/riscv/vector-iterators.md >b/gcc/config/riscv/vector-iterators.md >index 73df55a69c8..f85d1cc80d1 100644 >--- a/gcc/config/riscv/vector-iterators.md >+++ b/gcc/config/riscv/vector-iterators.md >@@ -2596,6 +2596,93 @@ > (V512DI "V512BI") >]) >+(define_mode_attr stride_predicate [ >+ (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI >"vector_eew8_stride_operand") >+ (RVVM2QI "vector_eew8_stride_operand") (RV
[PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]
From: xuli When stride == element width, vlsse should be optimized into vle.v. vsse should be optimized into vse.v. PR target/111450 gcc/ChangeLog: *config/riscv/constraints.md (c01): const_int 1. (c02): const_int 2. (c04): const_int 4. (c08): const_int 8. * config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand. (vector_eew16_stride_operand): Ditto. (vector_eew32_stride_operand): Ditto. (vector_eew64_stride_operand): Ditto. * config/riscv/vector-iterators.md: New iterator for stride operand. * config/riscv/vector.md: Add stride = element width constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111450.c: New test. --- gcc/config/riscv/constraints.md | 20 gcc/config/riscv/predicates.md| 18 gcc/config/riscv/vector-iterators.md | 87 +++ gcc/config/riscv/vector.md| 42 +--- .../gcc.target/riscv/rvv/base/pr111450.c | 100 ++ 5 files changed, 250 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 3f52bc76f67..964fdd450c9 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -45,6 +45,26 @@ (and (match_code "const_int") (match_test "ival == 0"))) +(define_constraint "c01" + "Constant value 1." + (and (match_code "const_int") + (match_test "ival == 1"))) + +(define_constraint "c02" + "Constant value 2" + (and (match_code "const_int") + (match_test "ival == 2"))) + +(define_constraint "c04" + "Constant value 4" + (and (match_code "const_int") + (match_test "ival == 4"))) + +(define_constraint "c08" + "Constant value 8" + (and (match_code "const_int") + (match_test "ival == 8"))) + (define_constraint "K" "A 5-bit unsigned immediate for CSR access instructions." (and (match_code "const_int") diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 4bc7ff2c9d8..7845998e430 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -514,6 +514,24 @@ (ior (match_operand 0 "const_0_operand") (match_operand 0 "pmode_register_operand"))) +;; [1, 2, 4, 8] means strided load/store with stride == element width +(define_special_predicate "vector_eew8_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 1 || INTVAL (op) == 0" +(define_special_predicate "vector_eew16_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 2 || INTVAL (op) == 0" +(define_special_predicate "vector_eew32_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 4 || INTVAL (op) == 0" +(define_special_predicate "vector_eew64_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 8 || INTVAL (op) == 0" + ;; A special predicate that doesn't match a particular mode. (define_special_predicate "vector_any_register_operand" (match_code "reg")) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 73df55a69c8..f85d1cc80d1 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2596,6 +2596,93 @@ (V512DI "V512BI") ]) +(define_mode_attr stride_predicate [ + (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI "vector_eew8_stride_operand") + (RVVM2QI "vector_eew8_stride_operand") (RVVM1QI "vector_eew8_stride_operand") + (RVVMF2QI "vector_eew8_stride_operand") (RVVMF4QI "vector_eew8_stride_operand") + (RVVMF8QI "vector_eew8_stride_operand") + + (RVVM8HI "vector_eew16_stride_operand") (RVVM4HI "vector_eew16_stride_operand") + (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI "vector_eew16_stride_operand") + (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI "vector_eew16_stride_operand") + + (RVVM8HF "vector_eew16_stride_operand") (RVVM4HF "vector_eew16_stride_operand") + (RVVM2HF "vector_eew16_stride_operand") (RVVM1HF "vector_eew16_stride_operand") + (RVVMF2HF "vector_eew16_stride_operand") (RVVMF4HF "vector_eew16_stride_operand") + + (RVVM8SI "vector_eew32_stride_operand") (RVVM4SI "vector_eew32_stride_operand") + (RVVM2SI "vector_eew32_stride_operand") (RVVM1SI "vector_eew32_stride_operand") + (RVVMF2SI "vector_eew32_stride_operand") + + (RVVM8SF "vector_eew32_stride_operand") (RVVM4SF "vector_eew32_stride_operand") + (RVVM2SF "vector_eew32_stride_operand") (RVVM1SF "vector_eew32_stride_operand") + (RVVMF2SF
Re: Re: [PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]
commited, thanks kito and juzhe. -- Li Xu >I think it's not make too much sense to back port GCC14's change to >GCC 13, removing phase 6 optimization is reasonable to me, so LGTM :) > >On Mon, Sep 18, 2023 at 2:44 PM juzhe.zh...@rivai.ai > wrote: >> >> Thanks for fixing it. >> I am ok remove phase 6 optimization which has many latent bugs (in GCC 14 >> kito has refactored it) there. >> But I think we need kito's more comments about that. >> >> >> >> juzhe.zh...@rivai.ai >> >> From: Li Xu >> Date: 2023-09-18 12:19 >> To: gcc-patches >> CC: kito.cheng; palmer; juzhe.zhong; xuli >> Subject: [PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] >> From: xuli >> >> vsetvl pass has been refactored in gcc14, and the optimization >> is more reasonable than releases/gcc-13. This problem does not >> exist in gcc14. >> >> Phase 6 of gcc13 is an optimization patch. Due to lack of consideration, >> there will be some hidden bugs, so we decided to remove phase 6. >> Although the generated code will be redundant, the program is correct. >> >> PR target/111412 >> >> gcc/ChangeLog: >> >> * config/riscv/riscv-vsetvl.cc (vector_infos_manager::release): >>Remove. >> (pass_vsetvl::refine_vsetvls): Ditto. >> (pass_vsetvl::cleanup_vsetvls): Ditto. >> (pass_vsetvl::propagate_avl): Ditto. >> (pass_vsetvl::lazy_vsetvl): Ditto. >> * config/riscv/riscv-vsetvl.h: Ditto. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Adjust case. >> * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Ditto. >> * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Ditto. >> * gcc.target/riscv/rvv/base/pr111412.c: New test. >> --- >> gcc/config/riscv/riscv-vsetvl.cc | 153 +- >> gcc/config/riscv/riscv-vsetvl.h | 2 - >> .../gcc.target/riscv/rvv/base/pr111412.c | 41 + >> .../riscv/rvv/vsetvl/avl_single-79.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-80.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-86.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-87.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-88.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-89.c | 4 +- >> .../riscv/rvv/vsetvl/avl_single-90.c | 4 +- >> .../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +- >> .../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 +- >> .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c | 6 +- >> .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c | 2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 4 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 4 +- >> 21 files changed, 80 insertions(+), 190 deletions(-) >> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111412.c >> >> diff --git a/gcc/config/riscv/riscv-vsetvl.cc >> b/gcc/config/riscv/riscv-vsetvl.cc >> index 0cf4bc818e2..9dca2ce709d 100644 >> --- a/gcc/config/riscv/riscv-vsetvl.cc >> +++ b/gcc/config/riscv/riscv-vsetvl.cc >> @@ -2494,8 +2494,6 @@ vector_infos_manager::release (void) >> if (!vector_exprs.is_empty ()) >> vector_exprs.releas
[PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]
From: xuli
vsetvl pass has been refactored in gcc14, and the optimization
is more reasonable than releases/gcc-13. This problem does not
exist in gcc14.
Phase 6 of gcc13 is an optimization patch. Due to lack of consideration,
there will be some hidden bugs, so we decided to remove phase 6.
Although the generated code will be redundant, the program is correct.
PR target/111412
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (vector_infos_manager::release): Remove.
(pass_vsetvl::refine_vsetvls): Ditto.
(pass_vsetvl::cleanup_vsetvls): Ditto.
(pass_vsetvl::propagate_avl): Ditto.
(pass_vsetvl::lazy_vsetvl): Ditto.
* config/riscv/riscv-vsetvl.h: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Adjust case.
* gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Ditto.
* gcc.target/riscv/rvv/base/pr111412.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 153 +-
gcc/config/riscv/riscv-vsetvl.h | 2 -
.../gcc.target/riscv/rvv/base/pr111412.c | 41 +
.../riscv/rvv/vsetvl/avl_single-79.c | 4 +-
.../riscv/rvv/vsetvl/avl_single-80.c | 4 +-
.../riscv/rvv/vsetvl/avl_single-86.c | 4 +-
.../riscv/rvv/vsetvl/avl_single-87.c | 4 +-
.../riscv/rvv/vsetvl/avl_single-88.c | 4 +-
.../riscv/rvv/vsetvl/avl_single-89.c | 4 +-
.../riscv/rvv/vsetvl/avl_single-90.c | 4 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c | 6 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c| 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 4 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 4 +-
21 files changed, 80 insertions(+), 190 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111412.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 0cf4bc818e2..9dca2ce709d 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2494,8 +2494,6 @@ vector_infos_manager::release (void)
if (!vector_exprs.is_empty ())
vector_exprs.release ();
- gcc_assert (to_refine_vsetvls.is_empty ());
- gcc_assert (to_delete_vsetvls.is_empty ());
if (optimize > 0)
free_bitmap_vectors ();
}
@@ -2702,9 +2700,6 @@ private:
/* Phase 5. */
void cleanup_insns (void) const;
- /* Phase 6. */
- void propagate_avl (void) const;
-
void init (void);
void done (void);
void compute_probabilities (void);
@@ -3823,10 +3818,8 @@ pass_vsetvl::refine_vsetvls (void) const
/* We can't refine user vsetvl into vsetvl zero,zero since the dest
will be used by the following instructions. */
if (vector_config_insn_p (rinsn))
- {
- m_vector_manager->to_refine_vsetvls.add (rinsn);
continue;
- }
+
rinsn = PREV_INSN (rinsn);
rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX);
change_insn (rinsn, new_pat);
@@ -3862,10 +3855,7 @@ pass_vsetvl::cleanup_vsetvls ()
/* We can't eliminate user vsetvl since the dest will be used
* by the following instructions. */
if (vector_config_insn_p (insn->rtl ()))
- {
- m_vector_manager->to_delete_vsetvls.add (insn->rtl ());
- continue;
- }
+ continue;
gcc_assert (has_vtype_op (insn->rtl ()));
rinsn = PREV_INSN (insn->rtl ());
@@ -4067,139 +4057,6 @@
Re: Re: [PATCH v3] RISC-V: Elimilate warning in class vcreate
Committed, thanks juzhe. -- Li Xu >lgtm > Replied Message >FromLi Xu >Date09/12/2023 14:20 >togcc-patc...@gcc.gnu.org >cckito.ch...@gmail.com, >pal...@dabbelt.com, >juzhe.zh...@rivai.ai, >xuli >Subject[PATCH v3] RISC-V: Elimilate warning in class vcreate
[PATCH v3] RISC-V: Elimilate warning in class vcreate
From: xuli
The following is the content of class vcreate:
class vcreate : public function_base
{
public:
gimple *fold (gimple_folder ) const override
{
}
rtx expand (function_expander ) const override
{
return NULL_RTX;
}
};
The warning caused is:
./riscv-gcc/gcc/config/riscv/riscv-vector-builtins-bases.cc:1719:34:
warning: unused parameter 'e' [-Wunused-parameter]
rtx expand (function_expander ) const override
^
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: remove unused parameter
e and replace NULL_RTX with gcc_unreachable.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index be3df2c1ea2..ee218a03017 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1856,9 +1856,9 @@ public:
return clobber;
}
- rtx expand (function_expander ) const override
+ rtx expand (function_expander &) const override
{
-return NULL_RTX;
+gcc_unreachable ();
}
};
--
2.17.1
[PATCH v2] RISC-V: Elimilate warning in class vcreate
From: xuli
The following is the content of class vcreate:
class vcreate : public function_base
{
public:
gimple *fold (gimple_folder ) const override
{
}
rtx expand (function_expander ) const override
{
return NULL_RTX;
}
};
The warning caused is:
./riscv-gcc/gcc/config/riscv/riscv-vector-builtins-bases.cc:1719:34:
warning: unused parameter 'e' [-Wunused-parameter]
rtx expand (function_expander ) const override
^
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: remove unused parameter
e.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index be3df2c1ea2..e2de95db88a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1856,7 +1856,7 @@ public:
return clobber;
}
- rtx expand (function_expander ) const override
+ rtx expand (function_expander &) const override
{
return NULL_RTX;
}
--
2.17.1
[PATCH] RISC-V: Elimilate warning
From: xuli
./riscv-gcc/gcc/config/riscv/riscv-vector-builtins-bases.cc:1719:34:
warning: unused parameter 'e' [-Wunused-parameter]
rtx expand (function_expander ) const override
^
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: remove unused parameter.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index be3df2c1ea2..e2de95db88a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1856,7 +1856,7 @@ public:
return clobber;
}
- rtx expand (function_expander ) const override
+ rtx expand (function_expander &) const override
{
return NULL_RTX;
}
--
2.17.1
Re: Re: [PATCH] RISC-V: Add vcreate intrinsics for RVV tuple types
Committed, thanks juzhe and kito.
--
Li Xu
>LGTM, thanks for implement this :)
>
>On Tue, Sep 12, 2023 at 10:16 AM juzhe.zh...@rivai.ai
> wrote:
>>
>> Thanks for support it.
>> LGTM from my side.
>> Wait for kito's more comments.
>>
>>
>>
>> juzhe.zh...@rivai.ai
>>
>> From: Li Xu
>> Date: 2023-09-12 10:08
>> To: gcc-patches
>> CC: kito.cheng; palmer; juzhe.zhong; pan2.li; gaofei; wangfeng; xuli
>> Subject: [PATCH] RISC-V: Add vcreate intrinsics for RVV tuple types
>> From: xuli
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-vector-builtins-bases.cc (class vcreate):
>> (BASE): New class.
>> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
>> * config/riscv/riscv-vector-builtins-functions.def (vcreate): Add
>>vcreate support.
>> * config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def):
>>Ditto.
>> (SHAPE): Ditto.
>> * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
>> * config/riscv/riscv-vector-builtins.cc: Add args type.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/rvv/base/tuple_create.c: New test.
>> ---
>> .../riscv/riscv-vector-builtins-bases.cc | 40 ++
>> .../riscv/riscv-vector-builtins-bases.h | 1 +
>> .../riscv/riscv-vector-builtins-functions.def | 1 +
>> .../riscv/riscv-vector-builtins-shapes.cc | 50 +++
>> .../riscv/riscv-vector-builtins-shapes.h | 1 +
>> gcc/config/riscv/riscv-vector-builtins.cc | 12 ++
>> .../gcc.target/riscv/rvv/base/tuple_create.c | 123 ++
>> 7 files changed, 228 insertions(+)
>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c
>>
>> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> index 8e679f72392..be3df2c1ea2 100644
>> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>> @@ -1824,6 +1824,44 @@ public:
>> }
>> };
>> +class vcreate : public function_base
>> +{
>> +public:
>> + gimple *fold (gimple_folder ) const override
>> + {
>> + unsigned int nargs = gimple_call_num_args (f.call);
>> + tree lhs_type = TREE_TYPE (f.lhs);
>> +
>> + /* Replace the call with a clobber of the result (to prevent it from
>> + becoming upwards exposed) followed by stores into each individual
>> + vector of tuple.
>> +
>> + The fold routines expect the replacement statement to have the
>> + same lhs as the original call, so return the clobber statement
>> + rather than the final vector store. */
>> + gassign *clobber = gimple_build_assign (f.lhs, build_clobber
>> (lhs_type));
>> +
>> + for (unsigned int i = nargs; i-- > 0; )
>> + {
>> + tree rhs_vector = gimple_call_arg (f.call, i);
>> + tree field = tuple_type_field (TREE_TYPE (f.lhs));
>> + tree lhs_array = build3 (COMPONENT_REF, TREE_TYPE (field),
>> + unshare_expr (f.lhs), field, NULL_TREE);
>> + tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector),
>> + lhs_array, size_int (i),
>> + NULL_TREE, NULL_TREE);
>> + gassign *assign = gimple_build_assign (lhs_vector, rhs_vector);
>> + gsi_insert_after (f.gsi, assign, GSI_SAME_STMT);
>> + }
>> + return clobber;
>> + }
>> +
>> + rtx expand (function_expander ) const override
>> + {
>> + return NULL_RTX;
>> + }
>> +};
>> +
>> class read_vl : public function_base
>> {
>> public:
>> @@ -2285,6 +2323,7 @@ static CONSTEXPR const vlmul_ext vlmul_ext_obj;
>> static CONSTEXPR const vlmul_trunc vlmul_trunc_obj;
>> static CONSTEXPR const vset vset_obj;
>> static CONSTEXPR const vget vget_obj;
>> +static CONSTEXPR const vcreate vcreate_obj;
>> static CONSTEXPR const read_vl read_vl_obj;
>> static CONSTEXPR const vleff vleff_obj;
>> static CONSTEXPR const vlenb vlenb_obj;
>> @@ -2546,6 +2585,7 @@ BASE (vlmul_ext)
>> BASE (vlmul_trunc)
>> BASE (vset)
>> BASE (vget)
>> +BASE (vcreate)
>> BASE (read_vl)
>> BASE (vleff)
>> BASE (vlenb)
>> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
>> b/gcc/config/riscv/riscv-vector-builtins-bases.h
>> index 69d4562091f..131041ea66f 100644
>> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
>> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
>> @@ -267,6 +267,
[PATCH] RISC-V: Add vcreate intrinsics for RVV tuple types
From: xuli
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vcreate):
(BASE): New class.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vcreate): Add
vcreate support.
* config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def):
Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc: Add args type.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple_create.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 40 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/riscv-vector-builtins-shapes.cc | 50 +++
.../riscv/riscv-vector-builtins-shapes.h | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 12 ++
.../gcc.target/riscv/rvv/base/tuple_create.c | 123 ++
7 files changed, 228 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 8e679f72392..be3df2c1ea2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1824,6 +1824,44 @@ public:
}
};
+class vcreate : public function_base
+{
+public:
+ gimple *fold (gimple_folder ) const override
+ {
+unsigned int nargs = gimple_call_num_args (f.call);
+tree lhs_type = TREE_TYPE (f.lhs);
+
+/* Replace the call with a clobber of the result (to prevent it from
+ becoming upwards exposed) followed by stores into each individual
+ vector of tuple.
+
+ The fold routines expect the replacement statement to have the
+ same lhs as the original call, so return the clobber statement
+ rather than the final vector store. */
+gassign *clobber = gimple_build_assign (f.lhs, build_clobber (lhs_type));
+
+for (unsigned int i = nargs; i-- > 0; )
+ {
+ tree rhs_vector = gimple_call_arg (f.call, i);
+ tree field = tuple_type_field (TREE_TYPE (f.lhs));
+ tree lhs_array = build3 (COMPONENT_REF, TREE_TYPE (field),
+unshare_expr (f.lhs), field, NULL_TREE);
+ tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector),
+ lhs_array, size_int (i),
+ NULL_TREE, NULL_TREE);
+ gassign *assign = gimple_build_assign (lhs_vector, rhs_vector);
+ gsi_insert_after (f.gsi, assign, GSI_SAME_STMT);
+ }
+return clobber;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+return NULL_RTX;
+ }
+};
+
class read_vl : public function_base
{
public:
@@ -2285,6 +2323,7 @@ static CONSTEXPR const vlmul_ext vlmul_ext_obj;
static CONSTEXPR const vlmul_trunc vlmul_trunc_obj;
static CONSTEXPR const vset vset_obj;
static CONSTEXPR const vget vget_obj;
+static CONSTEXPR const vcreate vcreate_obj;
static CONSTEXPR const read_vl read_vl_obj;
static CONSTEXPR const vleff vleff_obj;
static CONSTEXPR const vlenb vlenb_obj;
@@ -2546,6 +2585,7 @@ BASE (vlmul_ext)
BASE (vlmul_trunc)
BASE (vset)
BASE (vget)
+BASE (vcreate)
BASE (read_vl)
BASE (vleff)
BASE (vlenb)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 69d4562091f..131041ea66f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -267,6 +267,7 @@ extern const function_base *const vlmul_ext;
extern const function_base *const vlmul_trunc;
extern const function_base *const vset;
extern const function_base *const vget;
+extern const function_base *const vcreate;
extern const function_base *const read_vl;
extern const function_base *const vleff;
extern const function_base *const vlenb;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 3ce06dc60b7..18ed2c2b8f6 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -621,6 +621,7 @@ DEF_RVV_FUNCTION (vget, vget, none_preds,
all_v_vget_lmul4_x2_ops)
// Tuple types
DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_tuple_ops)
+DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_tuple_ops)
DEF_RVV_FUNCTION (vlseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ops)
DEF_RVV_FUNCTION (vsseg, seg_loadstore, none_m_preds, tuple_v_scalar_ptr_ops)
DEF_RVV_FUNCTION (vlsseg, seg_loadstore, full_preds,
tuple_v_scalar_const_ptr_ptrdiff_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index
Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.
This patch should be backported to releases/gcc-13 to address
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111076
--
Li Xu
>This issue happens is because the operand1 of scalar move can be
>REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
>not insert the vsetvl instruction correctly, and the compiler crashes.
>
>Consider this following case:
>int16_t foo1 (void *base, size_t vl)
>{
> int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base,
>vl));
> return maxVal;
>}
>
>Before this patch:
>bug.c:15:1: internal compiler error: Segmentation fault
> 15 | }
> | ^
>0x145d723 crash_signal
> ../.././riscv-gcc/gcc/toplev.cc:314
>0x22929dd const_csr_operand(rtx_def*, machine_mode)
> ../.././riscv-gcc/gcc/config/riscv/predicates.md:44
>0x2292a21 csr_operand(rtx_def*, machine_mode)
> ../.././riscv-gcc/gcc/config/riscv/predicates.md:46
>0x23dfbb0 recog_356
> ../.././riscv-gcc/gcc/config/riscv/iterators.md:72
>0x23efecd recog(rtx_def*, rtx_insn*, int*)
> ../.././riscv-gcc/gcc/config/riscv/iterators.md:89
>0xdddc15 recog_memoized(rtx_insn*)
> ../.././riscv-gcc/gcc/recog.h:273
>
>After this patch:
> vsetivlizero,0,e16,m1,ta,ma
> vmv.x.s a5,v1
>
>gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
>intruction replace null avl with (const_int 0).
>
>gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
> * gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
>---
> gcc/config/riscv/riscv-vsetvl.cc | 5 +++
> .../riscv/rvv/base/scalar_move-10.c | 31 +++
> .../riscv/rvv/base/scalar_move-11.c | 20
> 3 files changed, 56 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
>
>diff --git a/gcc/config/riscv/riscv-vsetvl.cc
>b/gcc/config/riscv/riscv-vsetvl.cc
>index d4d6f336ef9..14ebae1f3f6 100644
>--- a/gcc/config/riscv/riscv-vsetvl.cc
>+++ b/gcc/config/riscv/riscv-vsetvl.cc
>@@ -618,6 +618,11 @@ static rtx
> gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info , rtx vl)
> {
> rtx avl = info.get_avl ();
>+ /* if optimization == 0 and the instruction is vmv.x.s/vfmv.f.s,
>+ set the value of avl to (const_int 0) so that VSETVL PASS will
>+ insert vsetvl correctly.*/
>+ if (info.has_avl_no_reg ())
>+ avl = GEN_INT (0);
> rtx sew = gen_int_mode (info.get_sew (), Pmode);
> rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
> rtx ta = gen_int_mode (info.get_ta (), Pmode);
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
>b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
>new file mode 100644
>index 000..9760d77fb22
>--- /dev/null
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
>@@ -0,0 +1,31 @@
>+/* { dg-do compile } */
>+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
>+/* { dg-final { check-function-bodies "**" "" } } */
>+
>+#include "riscv_vector.h"
>+
>+/*
>+** foo1:
>+** ...
>+** vsetivli\tzero,0,e16,m1,t[au],m[au]
>+** vmv.x.s\t[a-x0-9]+,v[0-9]+
>+** ...
>+*/
>+int16_t foo1 (void *base, size_t vl)
>+{
>+ int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base,
>vl));
>+ return maxVal;
>+}
>+
>+/*
>+** foo2:
>+** ...
>+** vsetivli\tzero,0,e32,m1,t[au],m[au]
>+** vfmv.f.s\tf[a-x0-9]+,v[0-9]+
>+** ...
>+*/
>+float foo2 (void *base, size_t vl)
>+{
>+ float maxVal = __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (base,
>vl));
>+ return maxVal;
>+}
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
>b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
>new file mode 100644
>index 000..8036acd0a52
>--- /dev/null
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
>@@ -0,0 +1,20 @@
>+/* { dg-do compile } */
>+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */
>+/* { dg-final { check-function-bodies "**" "" } } */
>+
>+#include "riscv_vector.h"
>+
>+/*
>+** foo:
>+** ...
>+** vsetivli\tzero,0,e64,m4,t[au],m[au]
>+** vmv.x.s\t[a-x0-9]+,v[0-9]+
>+** vsetivli\tzero,0,e64,m4,t[au],m[au]
>+** vmv.x.s\t[a-x0-9]+,v[0-9]+
>+** ...
>+*/
>+int16_t foo (void *base, size_t vl)
>+{
>+ int16_t maxVal = __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 (base,
>vl));
>+ return maxVal;
>+}
>--
>2.17.1
Re: Re: [PATCH] RISCV: Fix PR111074 [GCC13 BUG]
Committed, thanks all. -- Li Xu >The test case is too complicated and I can't simplify it, so no test case is >added. > >------ >Li Xu >>From: xuli >> >>This patch fixes this issue happens on GCC-13. >>https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074 >> >>This patch should be backported to GCC-13. >>GCC-14 has rewritten propagate_avl function, so there is no issue. >> >>PR target/111074 >> >>gcc/ChangeLog: >> >> * config/riscv/riscv-vsetvl.cc (extract_single_source): Fix bug. >>--- >> gcc/config/riscv/riscv-vsetvl.cc | 3 +++ >> 1 file changed, 3 insertions(+) >> >>diff --git a/gcc/config/riscv/riscv-vsetvl.cc >>b/gcc/config/riscv/riscv-vsetvl.cc >>index 789eb04b78d..bd45cb97e63 100644 >>--- a/gcc/config/riscv/riscv-vsetvl.cc >>+++ b/gcc/config/riscv/riscv-vsetvl.cc >>@@ -1183,6 +1183,9 @@ extract_single_source (set_info *set) >> return nullptr; >> hash_set sets = get_all_sets (set, true, false, true); >> >>+ if (sets.is_empty ()) >>+ return nullptr; >>+ >> insn_info *first_insn = (*sets.begin ())->insn (); >> if (first_insn->is_artificial ()) >> return nullptr; >>-- >>2.17.1
Re: [PATCH] RISCV: Fix PR111074 [GCC13 BUG]
The test case is too complicated and I can't simplify it, so no test case is added. -- Li Xu >From: xuli > >This patch fixes this issue happens on GCC-13. >https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074 > >This patch should be backported to GCC-13. >GCC-14 has rewritten propagate_avl function, so there is no issue. > >PR target/111074 > >gcc/ChangeLog: > > * config/riscv/riscv-vsetvl.cc (extract_single_source): Fix bug. >--- > gcc/config/riscv/riscv-vsetvl.cc | 3 +++ > 1 file changed, 3 insertions(+) > >diff --git a/gcc/config/riscv/riscv-vsetvl.cc >b/gcc/config/riscv/riscv-vsetvl.cc >index 789eb04b78d..bd45cb97e63 100644 >--- a/gcc/config/riscv/riscv-vsetvl.cc >+++ b/gcc/config/riscv/riscv-vsetvl.cc >@@ -1183,6 +1183,9 @@ extract_single_source (set_info *set) > return nullptr; > hash_set sets = get_all_sets (set, true, false, true); > >+ if (sets.is_empty ()) >+ return nullptr; >+ > insn_info *first_insn = (*sets.begin ())->insn (); > if (first_insn->is_artificial ()) > return nullptr; >-- >2.17.1
[PATCH] RISCV: Fix PR111074 [GCC13 BUG]
From: xuli This patch fixes this issue happens on GCC-13. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111074 This patch should be backported to GCC-13. GCC-14 has rewritten propagate_avl function, so there is no issue. PR target/111074 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (extract_single_source): Fix bug. --- gcc/config/riscv/riscv-vsetvl.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 789eb04b78d..bd45cb97e63 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1183,6 +1183,9 @@ extract_single_source (set_info *set) return nullptr; hash_set sets = get_all_sets (set, true, false, true); + if (sets.is_empty ()) +return nullptr; + insn_info *first_insn = (*sets.begin ())->insn (); if (first_insn->is_artificial ()) return nullptr; -- 2.17.1
[committed] MAINTAINERS: Add myself to write after approval
From: xuli Signed-off-by: Li Xu ChangeLog: * MAINTAINERS: Add myself. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index e9b11b43a0f..49aa6bae73b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -712,6 +712,7 @@ Jonathan Wright Ruoyao Xi Mingjie Xing Chenghua Xu +Li Xu Canqun Yang Fei Yang Jeffrey Yasskin -- 2.17.1
[PATCH] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]
From: xuli Computation of `vsadd`, `vsaddu`, `vssub`, and `vssubu` do not need the rounding mode, therefore the intrinsics of these instructions do not have the parameter for rounding mode control. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: remove rounding mode of vsadd[u] and vssub[u]. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/bug-12.C: Adapt testcase. * g++.target/riscv/rvv/base/bug-14.C: Ditto. * g++.target/riscv/rvv/base/bug-18.C: Ditto. * g++.target/riscv/rvv/base/bug-19.C: Ditto. * g++.target/riscv/rvv/base/bug-20.C: Ditto. * g++.target/riscv/rvv/base/bug-21.C: Ditto. * g++.target/riscv/rvv/base/bug-22.C: Ditto. * g++.target/riscv/rvv/base/bug-23.C: Ditto. * g++.target/riscv/rvv/base/bug-3.C: Ditto. * g++.target/riscv/rvv/base/bug-8.C: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-103.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-104.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-105.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-106.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-107.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-109.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-110.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-111.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-112.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-113.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-115.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-116.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-117.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-118.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-97.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-98.c: Ditto. * gcc.target/riscv/rvv/base/merge_constraint-1.c: Ditto. * gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c: New test. * gcc.target/riscv/rvv/base/fixed-point-vxrm.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 6 -- gcc/config/riscv/vector.md| 42 +++--- .../g++.target/riscv/rvv/base/bug-12.C| 2 +- .../g++.target/riscv/rvv/base/bug-14.C| 2 +- .../g++.target/riscv/rvv/base/bug-18.C| 2 +- .../g++.target/riscv/rvv/base/bug-19.C| 2 +- .../g++.target/riscv/rvv/base/bug-20.C| 2 +- .../g++.target/riscv/rvv/base/bug-21.C| 2 +- .../g++.target/riscv/rvv/base/bug-22.C| 2 +- .../g++.target/riscv/rvv/base/bug-23.C| 2 +- .../g++.target/riscv/rvv/base/bug-3.C | 2 +- .../g++.target/riscv/rvv/base/bug-8.C | 2 +- .../riscv/rvv/base/binop_vx_constraint-100.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-101.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-102.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-103.c | 28 +++ .../riscv/rvv/base/binop_vx_constraint-104.c | 16 ++-- .../riscv/rvv/base/binop_vx_constraint-105.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-106.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-107.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-108.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-109.c | 28 +++ .../riscv/rvv/base/binop_vx_constraint-110.c | 16 ++-- .../riscv/rvv/base/binop_vx_constraint-111.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-112.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-113.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-114.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-115.c | 16 ++-- .../riscv/rvv/base/binop_vx_constraint-116.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-117.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-118.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-119.c | 4 +- .../riscv/rvv/base/binop_vx_constraint-97.c | 28 +++ .../riscv/rvv/base/binop_vx_constraint-98.c | 16 ++-- .../riscv/rvv/base/fixed-point-vxrm-error.c | 24 ++ .../riscv/rvv/base/fixed-point-vxrm.c | 81 +++ .../riscv/rvv/base/merge_constraint-1.c | 4 +- 37 files changed, 233 insertions(+), 152 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c diff --git
[PATCH] RISC-V: Fix vector tuple intrinsic
Consider this following case:
void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex,
vint32mf2x3_t v_tuple, size_t vl) {
return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl);
}
Compiler failed with:
test.c:19:1: internal compiler error: in vl_vtype_info, at
config/riscv/riscv-vsetvl.cc:1679
19 | }
| ^
0x1439ec2 riscv_vector::vl_vtype_info::vl_vtype_info(riscv_vector::avl_info,
unsigned char, riscv_vector::vlmul_type, unsigned char, bool, bool)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1679
0x143f788 get_vl_vtype_info
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:807
0x143f788 riscv_vector::vector_insn_info::parse_insn(rtl_ssa::insn_info*)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1843
0x1440371 riscv_vector::vector_infos_manager::vector_infos_manager()
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:2350
0x14407ee pass_vsetvl::init()
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4581
0x14471cf pass_vsetvl::execute(function*)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Change
scalar type to float16, eliminate warning.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/vector-iterators.md: add RVVM4x2DF in iterator V4T.
* config/riscv/vector.md: add tuple mode in attr sew.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple-intrinsic.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.def| 50 +--
gcc/config/riscv/vector-iterators.md | 1 +
gcc/config/riscv/vector.md| 1 +
.../riscv/rvv/base/tuple-intrinsic.c | 23 +
4 files changed, 50 insertions(+), 25 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.def
b/gcc/config/riscv/riscv-vector-builtins.def
index 0e49480703b..6661629aad8 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -441,47 +441,47 @@ DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64,
RVVM8DI, _u64m8, _u64,
DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, RVVMF4HF,
_f16mf4,
_f16, _e16mf4)
/* Define tuple types for SEW = 16, LMUL = MF4. */
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t,
float, 2, _f16mf4x2)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t,
float, 3, _f16mf4x3)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t,
float, 4, _f16mf4x4)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t,
float, 5, _f16mf4x5)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t,
float, 6, _f16mf4x6)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t,
float, 7, _f16mf4x7)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t,
float, 8, _f16mf4x8)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t,
float16, 2, _f16mf4x2)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t,
float16, 3, _f16mf4x3)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t,
float16, 4, _f16mf4x4)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t,
float16, 5, _f16mf4x5)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t,
float16, 6, _f16mf4x6)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t,
float16, 7, _f16mf4x7)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t,
float16, 8, _f16mf4x8)
/* LMUL = 1/2. */
DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, RVVMF2HF,
_f16mf2,
_f16, _e16mf2)
/* Define tuple types for SEW = 16, LMUL = MF2. */
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t,
float, 2, _f16mf2x2)
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t,
float, 3, _f16mf2x3)
[PATCH v2] RISC-V: Fix vector tuple intrinsic
Consider this following case:
void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex,
vint32mf2x3_t v_tuple, size_t vl) {
return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl);
}
Compiler failed with:
test.c:19:1: internal compiler error: in vl_vtype_info, at
config/riscv/riscv-vsetvl.cc:1679
19 | }
| ^
0x1439ec2 riscv_vector::vl_vtype_info::vl_vtype_info(riscv_vector::avl_info,
unsigned char, riscv_vector::vlmul_type, unsigned char, bool, bool)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1679
0x143f788 get_vl_vtype_info
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:807
0x143f788 riscv_vector::vector_insn_info::parse_insn(rtl_ssa::insn_info*)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1843
0x1440371 riscv_vector::vector_infos_manager::vector_infos_manager()
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:2350
0x14407ee pass_vsetvl::init()
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4581
0x14471cf pass_vsetvl::execute(function*)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Change
scalar type to float16, eliminate warning.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/vector-iterators.md: add RVVM4x2DF in iterator V4T.
* config/riscv/vector.md: add tuple mode in attr sew.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/tuple-intrinsic.c: New test.
---
gcc/config/riscv/riscv-vector-builtins.def| 50 +--
gcc/config/riscv/vector-iterators.md | 1 +
gcc/config/riscv/vector.md| 1 +
.../riscv/rvv/base/tuple-intrinsic.c | 23 +
4 files changed, 50 insertions(+), 25 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.def
b/gcc/config/riscv/riscv-vector-builtins.def
index 0e49480703b..6661629aad8 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -441,47 +441,47 @@ DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64,
RVVM8DI, _u64m8, _u64,
DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, RVVMF4HF,
_f16mf4,
_f16, _e16mf4)
/* Define tuple types for SEW = 16, LMUL = MF4. */
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t,
float, 2, _f16mf4x2)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t,
float, 3, _f16mf4x3)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t,
float, 4, _f16mf4x4)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t,
float, 5, _f16mf4x5)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t,
float, 6, _f16mf4x6)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t,
float, 7, _f16mf4x7)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t,
float, 8, _f16mf4x8)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t,
float16, 2, _f16mf4x2)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t,
float16, 3, _f16mf4x3)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t,
float16, 4, _f16mf4x4)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t,
float16, 5, _f16mf4x5)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t,
float16, 6, _f16mf4x6)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t,
float16, 7, _f16mf4x7)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t,
float16, 8, _f16mf4x8)
/* LMUL = 1/2. */
DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, RVVMF2HF,
_f16mf2,
_f16, _e16mf2)
/* Define tuple types for SEW = 16, LMUL = MF2. */
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t,
float, 2, _f16mf2x2)
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t,
float, 3, _f16mf2x3)
[PATCH] RISC-V: Fix vector tuple intrinsic
Consider this following case:
void test_vsoxseg3ei32_v_i32mf2x3(int32_t *base, vuint32mf2_t bindex,
vint32mf2x3_t v_tuple, size_t vl) {
return __riscv_vsoxseg3ei32_v_i32mf2x3(base, bindex, v_tuple, vl);
}
Compiler failed with:
test.c:19:1: internal compiler error: in vl_vtype_info, at
config/riscv/riscv-vsetvl.cc:1679
19 | }
| ^
0x1439ec2 riscv_vector::vl_vtype_info::vl_vtype_info(riscv_vector::avl_info,
unsigned char, riscv_vector::vlmul_type, unsigned char, bool, bool)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1679
0x143f788 get_vl_vtype_info
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:807
0x143f788 riscv_vector::vector_insn_info::parse_insn(rtl_ssa::insn_info*)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:1843
0x1440371 riscv_vector::vector_infos_manager::vector_infos_manager()
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:2350
0x14407ee pass_vsetvl::init()
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4581
0x14471cf pass_vsetvl::execute(function*)
../.././riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Change
scalar type to float16, eliminate warning.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/vector-iterators.md: add RVVM4x2DF in iterator V4T.
* config/riscv/vector.md: add tuple mode in attr sew.
---
gcc/config/riscv/riscv-vector-builtins.def | 50 +++---
gcc/config/riscv/vector-iterators.md | 1 +
gcc/config/riscv/vector.md | 1 +
3 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def
b/gcc/config/riscv/riscv-vector-builtins.def
index 0e49480703b..6661629aad8 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -441,47 +441,47 @@ DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64,
RVVM8DI, _u64m8, _u64,
DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, RVVMF4HF,
_f16mf4,
_f16, _e16mf4)
/* Define tuple types for SEW = 16, LMUL = MF4. */
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t,
float, 2, _f16mf4x2)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t,
float, 3, _f16mf4x3)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t,
float, 4, _f16mf4x4)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t,
float, 5, _f16mf4x5)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t,
float, 6, _f16mf4x6)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t,
float, 7, _f16mf4x7)
-DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t,
float, 8, _f16mf4x8)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t,
float16, 2, _f16mf4x2)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t,
float16, 3, _f16mf4x3)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t,
float16, 4, _f16mf4x4)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t,
float16, 5, _f16mf4x5)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t,
float16, 6, _f16mf4x6)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t,
float16, 7, _f16mf4x7)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t,
float16, 8, _f16mf4x8)
/* LMUL = 1/2. */
DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, RVVMF2HF,
_f16mf2,
_f16, _e16mf2)
/* Define tuple types for SEW = 16, LMUL = MF2. */
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t,
float, 2, _f16mf2x2)
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t,
float, 3, _f16mf2x3)
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x4_t, 20, __rvv_float16mf2x4_t, vfloat16mf2_t,
float, 4, _f16mf2x4)
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x5_t, 20, __rvv_float16mf2x5_t, vfloat16mf2_t,
float, 5, _f16mf2x5)
-DEF_RVV_TUPLE_TYPE (vfloat16mf2x6_t, 20,
[PATCH] RISCV: Fix local_eliminate_vsetvl_insn bug in VSETVL PASS[PR110560]
This patch fixes this issue happens on GCC-13.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110560
This patch should be backported to GCC-13.
GCC-14 has rewritten this function, so there is no issue.
PR target/110560
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): Fix bug.
---
gcc/config/riscv/riscv-vsetvl.cc | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 35403b5679c..3355ca4e3fb 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1078,6 +1078,10 @@ local_eliminate_vsetvl_insn (const vector_insn_info )
if (has_vtype_op (i->rtl ()))
{
+ if (!PREV_INSN (i->rtl ()))
+ return;
+ if (!NONJUMP_INSN_P (PREV_INSN (i->rtl (
+ return;
if (!vsetvl_discard_result_insn_p (PREV_INSN (i->rtl (
return;
rtx avl = get_avl (i->rtl ());
--
2.17.1
[PATCH] Extend streamer_mode_table size to MACHINE_MODE_BITSIZE.
If MAX_MACHINE_MODE exceeds 8bits, a warning will appear in the following code.
waring: writing 293 bytes into a region of size 256 overflows the destination
gcc/lto-streamer-out.cc
void
lto_output_init_mode_table (void)
{
memset (streamer_mode_table, '\0', MAX_MACHINE_MODE);
}
gcc/ChangeLog:
* tree-streamer.cc: Extend streamer_mode_table size to
MACHINE_MODE_BITSIZE.
* tree-streamer.h: Ditto.
---
gcc/tree-streamer.cc | 2 +-
gcc/tree-streamer.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-streamer.cc b/gcc/tree-streamer.cc
index ed65a7692e3..14c222698bf 100644
--- a/gcc/tree-streamer.cc
+++ b/gcc/tree-streamer.cc
@@ -35,7 +35,7 @@ along with GCC; see the file COPYING3. If not see
During streaming in, we translate the on the disk mode using this
table. For normal LTO it is set to identity, for ACCEL_COMPILER
depending on the mode_table content. */
-unsigned char streamer_mode_table[1 << 8];
+unsigned char streamer_mode_table[1 << MACHINE_MODE_BITSIZE];
/* Check that all the TS_* structures handled by the streamer_write_* and
streamer_read_* routines are exactly ALL the structures defined in
diff --git a/gcc/tree-streamer.h b/gcc/tree-streamer.h
index 170d61cf20b..8bc757be189 100644
--- a/gcc/tree-streamer.h
+++ b/gcc/tree-streamer.h
@@ -75,7 +75,7 @@ void streamer_write_tree_body (struct output_block *, tree);
void streamer_write_integer_cst (struct output_block *, tree);
/* In tree-streamer.cc. */
-extern unsigned char streamer_mode_table[1 << 8];
+extern unsigned char streamer_mode_table[1 << MACHINE_MODE_BITSIZE];
void streamer_check_handled_ts_structures (void);
bool streamer_tree_cache_insert (struct streamer_tree_cache_d *, tree,
hashval_t, unsigned *);
--
2.17.1
Re: [PATCH v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic
Hi, Jeff: I have filled out the form. May I ask if you have received my application? Is there anything else I need to do? Thanks. -- Li Xu > > >On 6/25/23 03:13, juzhe.zh...@rivai.ai wrote: >> LGTM. >> Thanks for fixing it. >Agreed. I didn't see the V2 had already been posted. > >> >> Hi, Jeff: >> I saw Li Xu is frequently helping RVV support in GCC. Is it possible to >> give him the write access? >Yes, we can do that with the normal process. > >Li Xu, fill out this form: > >https://sourceware.org/cgi-bin/pdw/ps_form.cgi > >List me as approving the request. >Jeff
[PATCH v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}
Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
5 | }
| ^
(insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32])
(mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1
(nil))
during RTL pass: vregs
test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
../.././riscv-gcc/gcc/rtl-error.cc:108
0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
../.././riscv-gcc/gcc/rtl-error.cc:116
0xed58a7 extract_insn(rtx_insn*)
../.././riscv-gcc/gcc/recog.cc:2791
0xb7f789 instantiate_virtual_regs_in_insn
../.././riscv-gcc/gcc/function.cc:1611
0xb7f789 instantiate_virtual_regs
../.././riscv-gcc/gcc/function.cc:1984
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: change emit_insn to
emit_move_insn
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8
2 files changed, 9 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c6c53dc13a5..5c8deda900d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1567,7 +1567,7 @@ public:
{
tree arg = CALL_EXPR_ARG (e.exp, 0);
rtx src = expand_normal (arg);
-emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
return e.target;
}
};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
new file mode 100644
index 000..2b088b53546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+
+#include "riscv_vector.h"
+
+void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
+ vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
+}
--
2.17.1
[PATCH] RISC-V: force arg and target to reg rtx under -O0
arg and target should be expanded to reg rtx during expand pass.
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}
Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
5 | }
| ^
(insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32])
(mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1
(nil))
during RTL pass: vregs
test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
../.././riscv-gcc/gcc/rtl-error.cc:108
0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
../.././riscv-gcc/gcc/rtl-error.cc:116
0xed58a7 extract_insn(rtx_insn*)
../.././riscv-gcc/gcc/recog.cc:2791
0xb7f789 instantiate_virtual_regs_in_insn
../.././riscv-gcc/gcc/function.cc:1611
0xb7f789 instantiate_virtual_regs
../.././riscv-gcc/gcc/function.cc:1984
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: force arg and target to
reg rtx.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 5 -
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8
2 files changed, 12 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c6c53dc13a5..f135f7971fa 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1567,7 +1567,10 @@ public:
{
tree arg = CALL_EXPR_ARG (e.exp, 0);
rtx src = expand_normal (arg);
-emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+if (MEM_P (e.target))
+ e.target = force_reg (GET_MODE (e.target), e.target);
+emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target),
+ MEM_P (src) ? force_reg (GET_MODE (src), src) : src));
return e.target;
}
};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
new file mode 100644
index 000..2b088b53546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+
+#include "riscv_vector.h"
+
+void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
+ vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
+}
--
2.17.1
[PATCH v2] RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
If reinterpret vnx2bi as vnx16qi, vnx16qi must occupy no more of the underlying
registers than vnx2bi.
Consider this following case:
void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
{
vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vmask);
__riscv_vse8_v_i8m1(out, vout, 16);
}
compiler parameters: -march=rv64gcv -mabi=lp64d
--param=riscv-autovec-preference=fixed-vlmax -O3
Compilation fails with:
test_vreinterpret_v_b64_i8m1during RTL pass: expand
test.c: In function 'test_vreinterpret_v_b64_i8m1':
test.c:11:22: internal compiler error: in gen_lowpart_general, at rtlhooks.cc:57
11 | vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1(src);
| ^~~~
0xf11876 gen_lowpart_general(machine_mode, rtx_def*)
../.././riscv-gcc/gcc/rtlhooks.cc:57
0x191435e gen_vreinterpretvnx16qi(rtx_def*, rtx_def*)
../.././riscv-gcc/gcc/config/riscv/vector.md:486
0xe08858 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
../.././riscv-gcc/gcc/optabs.cc:8213
0x1471209 riscv_vector::function_expander::generate_insn(insn_code)
../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.cc:3813
0x147629c riscv_vector::function_expander::expand()
../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.h:520
0x147629c riscv_vector::expand_builtin(unsigned int, tree_node*, rtx_def*)
../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.cc:4103
0x9868f9 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
../.././riscv-gcc/gcc/builtins.cc:7342
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_regmode_natural_size): set the natural
size of vector mask mode to one rvv register.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: New test.
---
gcc/config/riscv/riscv.cc | 5 +
.../gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c | 11 +++
2 files changed, 16 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6eb63a9d4de..b9c811bcc43 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7362,6 +7362,11 @@ riscv_regmode_natural_size (machine_mode mode)
anything smaller than that. */
/* ??? For now, only do this for variable-width RVV registers.
Doing it for constant-sized registers breaks lower-subreg.c. */
+
+ /* RVV mask modes always consume a single register. */
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+return BYTES_PER_RISCV_VECTOR;
+
if (!riscv_vector_chunks.is_constant () && riscv_v_ext_mode_p (mode))
{
if (riscv_v_ext_tuple_mode_p (mode))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
new file mode 100644
index 000..534d5fe0f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d
--param=riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include "riscv_vector.h"
+
+void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
+{
+ vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
+ vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vmask);
+ __riscv_vse8_v_i8m1(out, vout, 16);
+}
--
2.17.1
[PATCH] RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
If reinterpret vnx2bi as vnx16bi, vnx16bi must occupy no more of the underlying
registers than vnx2bi.
Consider this following case:
void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
{
vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vmask);
__riscv_vse8_v_i8m1(out, vout, 16);
}
compiler parameters: -march=rv64gcv -mabi=lp64d
--param=riscv-autovec-preference=fixed-vlmax -O3
Compilation fails with:
test_vreinterpret_v_b64_i8m1during RTL pass: expand
test.c: In function 'test_vreinterpret_v_b64_i8m1':
test.c:11:22: internal compiler error: in gen_lowpart_general, at rtlhooks.cc:57
11 | vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1(src);
| ^~~~
0xf11876 gen_lowpart_general(machine_mode, rtx_def*)
../.././riscv-gcc/gcc/rtlhooks.cc:57
0x191435e gen_vreinterpretvnx16qi(rtx_def*, rtx_def*)
../.././riscv-gcc/gcc/config/riscv/vector.md:486
0xe08858 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
../.././riscv-gcc/gcc/optabs.cc:8213
0x1471209 riscv_vector::function_expander::generate_insn(insn_code)
../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.cc:3813
0x147629c riscv_vector::function_expander::expand()
../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.h:520
0x147629c riscv_vector::expand_builtin(unsigned int, tree_node*, rtx_def*)
../.././riscv-gcc/gcc/config/riscv/riscv-vector-builtins.cc:4103
0x9868f9 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
../.././riscv-gcc/gcc/builtins.cc:7342
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_regmode_natural_size): set the natural
size of vector mask mode to one rvv register.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: New test.
---
gcc/config/riscv/riscv.cc | 4
.../gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c | 11 +++
2 files changed, 15 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6eb63a9d4de..73454f65086 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7362,6 +7362,10 @@ riscv_regmode_natural_size (machine_mode mode)
anything smaller than that. */
/* ??? For now, only do this for variable-width RVV registers.
Doing it for constant-sized registers breaks lower-subreg.c. */
+
+ if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+return BYTES_PER_RISCV_VECTOR;
+
if (!riscv_vector_chunks.is_constant () && riscv_v_ext_mode_p (mode))
{
if (riscv_v_ext_tuple_mode_p (mode))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
new file mode 100644
index 000..534d5fe0f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d
--param=riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include "riscv_vector.h"
+
+void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
+{
+ vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
+ vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vmask);
+ __riscv_vse8_v_i8m1(out, vout, 16);
+}
--
2.17.1
[PATCH v2] RISC-V: Fix VWEXTF iterator requirement
gcc/ChangeLog: * config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the Zve32f extension. --- gcc/config/riscv/vector-iterators.md | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 8c71c9e22cc..92b372986c7 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -503,12 +503,12 @@ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") -- 2.17.1
[PATCH] RISC-V: Fix iterator requirement
VWF is defined under TARGET_MIN_VLEN >= 128. VWEXTF: zvfh/zvfhmin depends on the Zve32f extension. gcc/ChangeLog: * config/riscv/vector-iterators.md: Fix requirement --- gcc/config/riscv/vector-iterators.md | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 8c71c9e22cc..bc3cde58612 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -330,18 +330,20 @@ ]) (define_mode_iterator VWF [ - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_VECTOR_ELEN_FP_16") (VNx4HF "TARGET_VECTOR_ELEN_FP_16") (VNx8HF "TARGET_VECTOR_ELEN_FP_16") (VNx16HF "TARGET_VECTOR_ELEN_FP_16") - (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") - (VNx1SF "TARGET_MIN_VLEN < 128") VNx2SF VNx4SF VNx8SF (VNx16SF "TARGET_MIN_VLEN > 32") (VNx32SF "TARGET_MIN_VLEN >= 128") + (VNx32HF "TARGET_VECTOR_ELEN_FP_16") + (VNx64HF "TARGET_VECTOR_ELEN_FP_16") + VNx2SF VNx4SF VNx8SF VNx16SF VNx32SF ]) (define_mode_iterator VWF_ZVE64 [ - VNx1HF VNx2HF VNx4HF VNx8HF VNx16HF VNx32HF + (VNx1HF "TARGET_VECTOR_ELEN_FP_16") (VNx2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16") (VNx8HF "TARGET_VECTOR_ELEN_FP_16") + (VNx16HF "TARGET_VECTOR_ELEN_FP_16") + (VNx32HF "TARGET_VECTOR_ELEN_FP_16") VNx1SF VNx2SF VNx4SF VNx8SF VNx16SF ]) @@ -503,12 +505,12 @@ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") -- 2.17.1
[PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.
gcc/ChangeLog: * config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for machine_mode 'MODE'. * config/riscv/vector.md (@pred_indexed_store): change VNX16_QHSI to VNX16_QHSDI. (@pred_indexed_store): Ditto. --- gcc/config/riscv/vector-iterators.md | 26 +- gcc/config/riscv/vector.md | 6 +++--- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 90743ed76c5..42cbbb49894 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -148,7 +148,7 @@ ]) (define_mode_iterator VEEWEXT8 [ - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64") + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -188,7 +188,7 @@ (VNx4SF "TARGET_VECTOR_ELEN_FP_32") (VNx8SF "TARGET_VECTOR_ELEN_FP_32") (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") (VNx4DF "TARGET_VECTOR_ELEN_FP_64") (VNx8DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ -199,7 +199,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") - (VNx4DI "TARGET_VECTOR_ELEN_64") + (VNx4DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -213,11 +213,11 @@ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI (VNx16QI "TARGET_MIN_VLEN >= 128") (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI (VNx8HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI (VNx4SI "TARGET_MIN_VLEN >= 128") - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") ]) @@ -400,26 +400,26 @@ (define_mode_iterator VNX1_QHSDI [ (VNx1QI "TARGET_MIN_VLEN < 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx1SI "TARGET_MIN_VLEN < 128") - (VNx1DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx1DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") ]) (define_mode_iterator VNX2_QHSDI [ VNx2QI VNx2HI VNx2SI - (VNx2DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx2DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) (define_mode_iterator VNX4_QHSDI [ VNx4QI VNx4HI VNx4SI - (VNx4DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx4DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) (define_mode_iterator VNX8_QHSDI [ VNx8QI VNx8HI VNx8SI - (VNx8DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx8DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) -(define_mode_iterator VNX16_QHSI [ - VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_MIN_VLEN >= 128") +(define_mode_iterator VNX16_QHSDI [ + VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VNX32_QHSI [ @@ -435,7 +435,7 @@ (VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") - (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_MIN_VLEN >= 128") + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_VECTOR_ELEN_FP_16") @@ -463,7 +463,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128") (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI
[PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.
This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.
Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base,
vl));
return maxVal;
}
Before this patch:
bug.c:15:1: internal compiler error: Segmentation fault
15 | }
| ^
0x145d723 crash_signal
../.././riscv-gcc/gcc/toplev.cc:314
0x22929dd const_csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:44
0x2292a21 csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:46
0x23dfbb0 recog_356
../.././riscv-gcc/gcc/config/riscv/iterators.md:72
0x23efecd recog(rtx_def*, rtx_insn*, int*)
../.././riscv-gcc/gcc/config/riscv/iterators.md:89
0xdddc15 recog_memoized(rtx_insn*)
../.././riscv-gcc/gcc/recog.h:273
After this patch:
vsetivlizero,0,e16,m1,ta,ma
vmv.x.s a5,v1
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
intruction replace null avl with (const_int 0).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
* gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 5 +++
.../riscv/rvv/base/scalar_move-10.c | 31 +++
.../riscv/rvv/base/scalar_move-11.c | 20
3 files changed, 56 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index d4d6f336ef9..14ebae1f3f6 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -618,6 +618,11 @@ static rtx
gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info , rtx vl)
{
rtx avl = info.get_avl ();
+ /* if optimization == 0 and the instruction is vmv.x.s/vfmv.f.s,
+ set the value of avl to (const_int 0) so that VSETVL PASS will
+ insert vsetvl correctly.*/
+ if (info.has_avl_no_reg ())
+avl = GEN_INT (0);
rtx sew = gen_int_mode (info.get_sew (), Pmode);
rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
rtx ta = gen_int_mode (info.get_ta (), Pmode);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
new file mode 100644
index 000..9760d77fb22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** foo1:
+** ...
+** vsetivli\tzero,0,e16,m1,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** ...
+*/
+int16_t foo1 (void *base, size_t vl)
+{
+int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base,
vl));
+return maxVal;
+}
+
+/*
+** foo2:
+** ...
+** vsetivli\tzero,0,e32,m1,t[au],m[au]
+** vfmv.f.s\tf[a-x0-9]+,v[0-9]+
+** ...
+*/
+float foo2 (void *base, size_t vl)
+{
+float maxVal = __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (base,
vl));
+return maxVal;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
new file mode 100644
index 000..8036acd0a52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** foo:
+** ...
+** vsetivli\tzero,0,e64,m4,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** vsetivli\tzero,0,e64,m4,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** ...
+*/
+int16_t foo (void *base, size_t vl)
+{
+int16_t maxVal = __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 (base,
vl));
+return maxVal;
+}
--
2.17.1
[PATCH] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.
This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.
Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base,
vl));
return maxVal;
}
Before this patch:
bug.c:15:1: internal compiler error: Segmentation fault
15 | }
| ^
0x145d723 crash_signal
../.././riscv-gcc/gcc/toplev.cc:314
0x22929dd const_csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:44
0x2292a21 csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:46
0x23dfbb0 recog_356
../.././riscv-gcc/gcc/config/riscv/iterators.md:72
0x23efecd recog(rtx_def*, rtx_insn*, int*)
../.././riscv-gcc/gcc/config/riscv/iterators.md:89
0xdddc15 recog_memoized(rtx_insn*)
../.././riscv-gcc/gcc/recog.h:273
After this patch:
vsetivlizero,0,e16,m1,ta,ma
vmv.x.s a5,v1
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
intruction replace null avl with (const_int 0).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
* gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 5 +++
.../riscv/rvv/base/scalar_move-10.c | 31 +++
.../riscv/rvv/base/scalar_move-11.c | 20
3 files changed, 56 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index d4d6f336ef9..dfca2515f83 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -618,6 +618,11 @@ static rtx
gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info , rtx vl)
{
rtx avl = info.get_avl ();
+ /* if optimization == 0 and the instruction is vmv.x.s/vfmv.f.s,
+ set the value of avl to (const_int 0) so that VSETVL PASS will
+ insert vsetvl correctly.*/
+ if (avl == NULL_RTX && !optimize)
+avl = GEN_INT (0);
rtx sew = gen_int_mode (info.get_sew (), Pmode);
rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
rtx ta = gen_int_mode (info.get_ta (), Pmode);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
new file mode 100644
index 000..186ae34335e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** foo1:
+** ...
+** vsetivli\tzero,0,e16,m1,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** ...
+*/
+int16_t foo1 (void *base, size_t vl)
+{
+int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base,
vl));
+return maxVal;
+}
+
+/*
+** foo2:
+** ...
+** vsetivli\tzero,0,e32,m1,t[au],m[au]
+** vfmv.f.s\tf[a-x0-9]+,v[0-9]+
+** ...
+*/
+float foo2 (void *base, size_t vl)
+{
+float maxVal = __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (base,
vl));
+return maxVal;
+}
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
new file mode 100644
index 000..724cf74d217
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** foo:
+** ...
+** vsetivli\tzero,0,e64,m4,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** vsetivli\tzero,0,e64,m4,t[au],m[au]
+** vmv.x.s\t[a-x0-9]+,v[0-9]+
+** ...
+*/
+int16_t foo (void *base, size_t vl)
+{
+int16_t maxVal = __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 (base,
vl));
+return maxVal;
+}
\ No newline at end of file
--
2.17.1
[PATCH] RISC-V: Fix typo
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def: Fix typo.
* config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto.
* config/riscv/vector-iterators.md: Ditto.
---
gcc/config/riscv/riscv-vector-builtins.def | 3 +--
gcc/config/riscv/riscv.cc | 4 ++--
gcc/config/riscv/vector-iterators.md | 4 ++--
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def
b/gcc/config/riscv/riscv-vector-builtins.def
index 2d527f76f0a..563ad355342 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -65,8 +65,7 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_BASE_TYPE(NAME, TYPE)
#endif
-/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types.
- The 'NAME' will be concatenated into intrinsic function name. */
+/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types. */
#ifndef DEF_RVV_TYPE_INDEX
#define DEF_RVV_TYPE_INDEX(VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX,
EEW16_INDEX, \
EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..5f542932d13 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7048,8 +7048,8 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i,
unsigned int *factor,
int *offset)
{
/* Polynomial invariant 1 == (VLENB / riscv_bytes_per_vector_chunk) - 1.
- 1. TARGET_MIN_VLEN == 32, olynomial invariant 1 == (VLENB / 4) - 1.
- 2. TARGET_MIN_VLEN > 32, olynomial invariant 1 == (VLENB / 8) - 1.
+ 1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1.
+ 2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1.
*/
gcc_assert (i == 1);
*factor = riscv_bytes_per_vector_chunk;
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 34e486e48ca..194e9b8f57f 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -727,7 +727,7 @@
(VNx1QI "vnx4hi") (VNx2QI "vnx4hi") (VNx4QI "vnx4hi")
(VNx8QI "vnx4hi") (VNx16QI "vnx4hi") (VNx32QI "vnx4hi") (VNx64QI "vnx4hi")
(VNx1HI "vnx2si") (VNx2HI "vnx2si") (VNx4HI "vnx2si")
- (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2SI")
+ (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2si")
(VNx1SI "vnx2di") (VNx2SI "vnx2di") (VNx4SI "vnx2di")
(VNx8SI "vnx2di") (VNx16SI "vnx2di")
(VNx1SF "vnx1df") (VNx2SF "vnx1df")
@@ -738,7 +738,7 @@
(VNx1QI "vnx2hi") (VNx2QI "vnx2hi") (VNx4QI "vnx2hi")
(VNx8QI "vnx2hi") (VNx16QI "vnx2hi") (VNx32QI "vnx2hi")
(VNx1HI "vnx1si") (VNx2HI "vnx1si") (VNx4HI "vnx1si")
- (VNx8HI "vnx1si") (VNx16HI "vnx1SI")
+ (VNx8HI "vnx1si") (VNx16HI "vnx1si")
])
(define_mode_attr VDEMOTE [
--
2.17.1
[PATCH] RISC-V: Fix typo
gcc/ChangeLog: * config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo (vfloat32m8_t): Likewise --- gcc/config/riscv/riscv-vector-builtins.def | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index d4a74befd8a..2d527f76f0a 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -234,7 +234,7 @@ DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI, VNx8SI, _u32m8, _u32, _e32m8) /* SEW = 64: - Disable when TARGET_MIN_VLEN > 32. */ + Enable when TARGET_MIN_VLEN > 32. */ DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1, _i64, _e64m1) DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID, _u64m1, @@ -278,7 +278,7 @@ DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF, _f32m8, _f32, _e32m8) /* SEW = 64: - Disable when TARGET_VECTOR_FP64. */ + Enable when TARGET_VECTOR_FP64. */ DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1, _f64, _e64m1) DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2, -- 2.17.1
