Some indexed SVE FCMLA operations have a 3-bit register field that
requires one of Z0-Z7. This patch adds a public "y" constraint for that.
The patch also documents "x", which is again intended to be a public
constraint.
Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
OK to install?
Richard
2019-08-07 Richard Sandiford
gcc/
* doc/md.texi: Document the x and y constraints for AArch64.
* config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro.
(FP_LO8_REGS): New reg_class.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS.
* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
(aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS.
* config/aarch64/predicates.md (aarch64_simd_register): Use
FP_REGNUM_P instead of checking the classes manually.
* config/aarch64/constraints.md (y): New constraint.
gcc/testsuite/
* gcc.target/aarch64/asm-x-constraint-1.c: New test.
* gcc.target/aarch64/asm-y-constraint-1.c: Likewise.
Index: gcc/doc/md.texi
===
--- gcc/doc/md.texi 2019-07-12 08:54:11.881445730 +0100
+++ gcc/doc/md.texi 2019-08-07 19:17:05.935537080 +0100
@@ -1748,6 +1748,12 @@ The stack pointer register (@code{SP})
@item w
Floating point register, Advanced SIMD vector register or SVE vector register
+@item x
+Like @code{w}, but restricted to registers 0 to 15 inclusive.
+
+@item y
+Like @code{w}, but restricted to registers 0 to 7 inclusive.
+
@item Upl
One of the low eight SVE predicate registers (@code{P0} to @code{P7})
Index: gcc/config/aarch64/aarch64.h
===
--- gcc/config/aarch64/aarch64.h2019-08-05 17:46:20.717723584 +0100
+++ gcc/config/aarch64/aarch64.h2019-08-07 19:17:05.931537111 +0100
@@ -563,6 +563,9 @@ #define FP_REGNUM_P(REGNO) \
#define FP_LO_REGNUM_P(REGNO)\
(((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
+#define FP_LO8_REGNUM_P(REGNO)\
+ (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM))
+
#define PR_REGNUM_P(REGNO)\
(((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM))
@@ -581,6 +584,7 @@ enum reg_class
GENERAL_REGS,
STACK_REG,
POINTER_REGS,
+ FP_LO8_REGS,
FP_LO_REGS,
FP_REGS,
POINTER_AND_FP_REGS,
@@ -600,6 +604,7 @@ #define REG_CLASS_NAMES \
"GENERAL_REGS", \
"STACK_REG", \
"POINTER_REGS", \
+ "FP_LO8_REGS", \
"FP_LO_REGS",\
"FP_REGS", \
"POINTER_AND_FP_REGS", \
@@ -616,6 +621,7 @@ #define REG_CLASS_CONTENTS
\
{ 0x7fff, 0x, 0x0003 }, /* GENERAL_REGS */ \
{ 0x8000, 0x, 0x }, /* STACK_REG */ \
{ 0x, 0x, 0x0003 }, /* POINTER_REGS */ \
+ { 0x, 0x00ff, 0x }, /* FP_LO8_REGS */ \
{ 0x, 0x, 0x }, /* FP_LO_REGS */ \
{ 0x, 0x, 0x }, /* FP_REGS */ \
{ 0x, 0x, 0x0003 }, /* POINTER_AND_FP_REGS */\
Index: gcc/config/aarch64/aarch64.c
===
--- gcc/config/aarch64/aarch64.c2019-08-07 19:07:38.203739735 +0100
+++ gcc/config/aarch64/aarch64.c2019-08-07 19:17:05.931537111 +0100
@@ -1610,6 +1610,7 @@ aarch64_hard_regno_nregs (unsigned regno
{
case FP_REGS:
case FP_LO_REGS:
+case FP_LO8_REGS:
if (aarch64_sve_data_mode_p (mode))
return exact_div (GET_MODE_SIZE (mode),
BYTES_PER_SVE_VECTOR).to_constant ();
@@ -8295,7 +8296,8 @@ aarch64_regno_regclass (unsigned regno)
return POINTER_REGS;
if (FP_REGNUM_P (regno))
-return FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS;
+return (FP_LO8_REGNUM_P (regno) ? FP_LO8_REGS
+ : FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS);
if (PR_REGNUM_P (regno))
return PR_LO_REGNUM_P (regno) ? PR_LO_REGS : PR_HI_REGS;
@@ -8585,6 +8587,7 @@ aarch64_class_max_nregs (reg_class_t reg
case POINTER_AND_FP_REGS:
case FP_REGS:
case FP_LO_REGS:
+case FP_LO8_REGS:
if (aarch64_sve_data_mode_p (mode)
&& constant_multiple_p (GET_MODE_SIZE (mode),
BYTES_PER_SVE_VECTOR, &nregs))
Index: gcc/config/aarch64/predicates.md
===
--- gcc/config/aarch64/predicates.md2019-05-12 12:27:15.753897237 +0100
+++ gcc/config/aarch64/predicates.md2019-08-07 19:17:0
