Re: [PATCH] RISC-V: Add zero_extract support for rv64gc
On Mon, May 6, 2024 at 11:43 PM Vineet Gupta wrote: > > > > On 5/6/24 13:40, Christoph Müllner wrote: > > The combiner attempts to optimize a zero-extension of a logical right shift > > using zero_extract. We already utilize this optimization for those cases > > that result in a single instructions. Let's add a insn_and_split > > pattern that also matches the generic case, where we can emit an > > optimized sequence of a slli/srli. > > > > ... > > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index d4676507b45..80cbecb78e8 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3" > >[(set_attr "type" "shift") > > (set_attr "mode" "SI")]) > > > > +;; Canonical form for a zero-extend of a logical right shift. > > +;; Special cases are handled above. > > +;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb) > > Dumb question: Why not for Zbs: Zb[abs] is going to be very common going > fwd and will end up being unused. > > > +(define_insn_and_split "*lshr3_zero_extend_4" > > + [(set (match_operand:GPR 0 "register_operand" "=r") > > + (zero_extract:GPR > > + (match_operand:GPR 1 "register_operand" " r") > > + (match_operand 2 "const_int_operand") > > + (match_operand 3 "const_int_operand"))) > > + (clobber (match_scratch:GPR 4 "="))] > > + "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1)) > > + && !TARGET_XTHEADBB" > > + "#" > > + "&& reload_completed" > > + [(set (match_dup 4) > > + (ashift:GPR (match_dup 1) (match_dup 2))) > > + (set (match_dup 0) > > + (lshiftrt:GPR (match_dup 4) (match_dup 3)))] > > +{ > > + int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant (); > > + int sizebits = INTVAL (operands[2]); > > + int startbits = INTVAL (operands[3]); > > + int lshamt = regbits - sizebits - startbits; > > + int rshamt = lshamt + startbits; > > + operands[2] = GEN_INT (lshamt); > > + operands[3] = GEN_INT (rshamt); > > +} > > + [(set_attr "type" "shift") > > + (set_attr "mode" "")]) > > + > > ;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into > > ;; two logical shifts. Otherwise it requires 3 instructions: lui, > > ;; xor/addi/srli, and. > > diff --git a/gcc/testsuite/gcc.target/riscv/pr111501.c > > b/gcc/testsuite/gcc.target/riscv/pr111501.c > > new file mode 100644 > > index 000..9355be242e7 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/pr111501.c > > @@ -0,0 +1,32 @@ > > +/* { dg-do compile } */ > > +/* { dg-require-effective-target rv64 } */ > > +/* { dg-options "-march=rv64gc" { target { rv64 } } } */ > > +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ > > +/* { dg-final { check-function-bodies "**" "" } } */ > > Is function body check really needed: isn't count of srli and slli each > sufficient ? > Last year we saw a lot of false failures due to unrelated scheduling > changes as such tripping these up. I've dropped the check-function-bodies in the v2. Thanks! > > > +/* { dg-allow-blank-lines-in-output 1 } */ > > + > > +/* > > +**do_shift: > > +**... > > +**slli\ta[0-9],a[0-9],16 > > +**srli\ta[0-9],a[0-9],48 > > +**... > > +*/ > > +unsigned int > > +do_shift(unsigned long csum) > > +{ > > + return (unsigned short)(csum >> 32); > > +} > > + > > +/* > > +**do_shift2: > > +**... > > +**slli\ta[0-9],a[0-9],16 > > +**srli\ta[0-9],a[0-9],48 > > +**... > > +*/ > > +unsigned int > > +do_shift2(unsigned long csum) > > +{ > > + return (csum << 16) >> 48; > > +} > > diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c > > b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c > > new file mode 100644 > > index 000..2824d6fe074 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c > > @@ -0,0 +1,37 @@ > > +/* { dg-do compile } */ > > +/* { dg-require-effective-target rv32 } */ > > +/* { dg-options "-march=rv32gc" } */ > > +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ > > +/* { dg-final { check-function-bodies "**" "" } } */ > > Same as above, counts where possible. > > -Vineet >
Re: [PATCH] RISC-V: Add zero_extract support for rv64gc
On Mon, May 6, 2024 at 11:24 PM Jeff Law wrote: > > > > On 5/6/24 2:40 PM, Christoph Müllner wrote: > > The combiner attempts to optimize a zero-extension of a logical right shift > > using zero_extract. We already utilize this optimization for those cases > > that result in a single instructions. Let's add a insn_and_split > > pattern that also matches the generic case, where we can emit an > > optimized sequence of a slli/srli. > > > > Tested with SPEC CPU 2017 (rv64gc). > > > > PR 111501 > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.md (*lshr3_zero_extend_4): New > > pattern for zero-extraction. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/pr111501.c: New test. > > * gcc.target/riscv/zero-extend-rshift-32.c: New test. > > * gcc.target/riscv/zero-extend-rshift-64.c: New test. > > * gcc.target/riscv/zero-extend-rshift.c: New test. > So I had Lyut looking in this space as well. Mostly because there's a > desire to avoid the srl+and approach and instead represent this stuff as > shifts (which are fusible in our uarch). SO I've already got some state... > > > > > > Signed-off-by: Christoph Müllner > > --- > > gcc/config/riscv/riscv.md | 30 + > > gcc/testsuite/gcc.target/riscv/pr111501.c | 32 + > > .../gcc.target/riscv/zero-extend-rshift-32.c | 37 ++ > > .../gcc.target/riscv/zero-extend-rshift-64.c | 63 ++ > > .../gcc.target/riscv/zero-extend-rshift.c | 119 ++ > > 5 files changed, 281 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/pr111501.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c > > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index d4676507b45..80cbecb78e8 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3" > > [(set_attr "type" "shift") > > (set_attr "mode" "SI")]) > > > > +;; Canonical form for a zero-extend of a logical right shift. > > +;; Special cases are handled above. > > +;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb) > > +(define_insn_and_split "*lshr3_zero_extend_4" > > + [(set (match_operand:GPR 0 "register_operand" "=r") > > + (zero_extract:GPR > > + (match_operand:GPR 1 "register_operand" " r") > > + (match_operand 2 "const_int_operand") > > + (match_operand 3 "const_int_operand"))) > > + (clobber (match_scratch:GPR 4 "="))] > > + "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1)) > > + && !TARGET_XTHEADBB" > > + "#" > > + "&& reload_completed" > > + [(set (match_dup 4) > > + (ashift:GPR (match_dup 1) (match_dup 2))) > > + (set (match_dup 0) > > + (lshiftrt:GPR (match_dup 4) (match_dup 3)))] > Consider adding support for signed extractions as well. You just need > an iterator across zero_extract/sign_extract and suitable selection of > arithmetic vs logical right shift step. The sign-extension/extraction code was worse than the zero-extension/extraction code. So, I ended up doing some initial work for addressing corner cases first, before converting this pattern using an any_extract iterator for the v2 (already on the list). > > A nit on the condition. Bring the && INTVAL (operands[2]) == 1 down to > a new line like you've gone with !TARGET_XTHEADBB. > > You also want to make sure the condition rejects the cases handled by > this pattern (or merge your pattern with this one): I kept the pattern, but added sign_extract support. > > > ;; Canonical form for a zero-extend of a logical right shift. > > (define_insn "*lshrsi3_zero_extend_2" > > [(set (match_operand:DI 0 "register_operand" "=r") > > (zero_extract:DI (match_operand:DI 1 "register_operand" " r") > > (match_operand 2 "const_int_operand") > > (match_operand 3 "const_int_operand")))] > > "(TARGET_64BIT && (INTVAL (operands[3]) > 0) > > && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))" > > { > > return "srliw\t%0,%1,%3"; > > } > > [(set_attr "type" "shift") > >(set_attr "mode" "SI")]) > > So generally going the right direction. But needs another iteration. Thanks for the review! > > Jeff >
Re: [PATCH] RISC-V: Add zero_extract support for rv64gc
On 5/6/24 3:42 PM, Vineet Gupta wrote: On 5/6/24 13:40, Christoph Müllner wrote: The combiner attempts to optimize a zero-extension of a logical right shift using zero_extract. We already utilize this optimization for those cases that result in a single instructions. Let's add a insn_and_split pattern that also matches the generic case, where we can emit an optimized sequence of a slli/srli. ... diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d4676507b45..80cbecb78e8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3" [(set_attr "type" "shift") (set_attr "mode" "SI")]) +;; Canonical form for a zero-extend of a logical right shift. +;; Special cases are handled above. +;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb) Dumb question: Why not for Zbs: Zb[abs] is going to be very common going fwd and will end up being unused. Zbs only handles single bit extractions. The pattern rejects that case allowing the single bit patterns from bitmanip.md and thead.md to match them. Jeff
Re: [PATCH] RISC-V: Add zero_extract support for rv64gc
On 5/6/24 13:40, Christoph Müllner wrote: > The combiner attempts to optimize a zero-extension of a logical right shift > using zero_extract. We already utilize this optimization for those cases > that result in a single instructions. Let's add a insn_and_split > pattern that also matches the generic case, where we can emit an > optimized sequence of a slli/srli. > > ... > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index d4676507b45..80cbecb78e8 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3" >[(set_attr "type" "shift") > (set_attr "mode" "SI")]) > > +;; Canonical form for a zero-extend of a logical right shift. > +;; Special cases are handled above. > +;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb) Dumb question: Why not for Zbs: Zb[abs] is going to be very common going fwd and will end up being unused. > +(define_insn_and_split "*lshr3_zero_extend_4" > + [(set (match_operand:GPR 0 "register_operand" "=r") > + (zero_extract:GPR > + (match_operand:GPR 1 "register_operand" " r") > + (match_operand 2 "const_int_operand") > + (match_operand 3 "const_int_operand"))) > + (clobber (match_scratch:GPR 4 "="))] > + "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1)) > + && !TARGET_XTHEADBB" > + "#" > + "&& reload_completed" > + [(set (match_dup 4) > + (ashift:GPR (match_dup 1) (match_dup 2))) > + (set (match_dup 0) > + (lshiftrt:GPR (match_dup 4) (match_dup 3)))] > +{ > + int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant (); > + int sizebits = INTVAL (operands[2]); > + int startbits = INTVAL (operands[3]); > + int lshamt = regbits - sizebits - startbits; > + int rshamt = lshamt + startbits; > + operands[2] = GEN_INT (lshamt); > + operands[3] = GEN_INT (rshamt); > +} > + [(set_attr "type" "shift") > + (set_attr "mode" "")]) > + > ;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into > ;; two logical shifts. Otherwise it requires 3 instructions: lui, > ;; xor/addi/srli, and. > diff --git a/gcc/testsuite/gcc.target/riscv/pr111501.c > b/gcc/testsuite/gcc.target/riscv/pr111501.c > new file mode 100644 > index 000..9355be242e7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr111501.c > @@ -0,0 +1,32 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv64 } */ > +/* { dg-options "-march=rv64gc" { target { rv64 } } } */ > +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ > +/* { dg-final { check-function-bodies "**" "" } } */ Is function body check really needed: isn't count of srli and slli each sufficient ? Last year we saw a lot of false failures due to unrelated scheduling changes as such tripping these up. > +/* { dg-allow-blank-lines-in-output 1 } */ > + > +/* > +**do_shift: > +**... > +**slli\ta[0-9],a[0-9],16 > +**srli\ta[0-9],a[0-9],48 > +**... > +*/ > +unsigned int > +do_shift(unsigned long csum) > +{ > + return (unsigned short)(csum >> 32); > +} > + > +/* > +**do_shift2: > +**... > +**slli\ta[0-9],a[0-9],16 > +**srli\ta[0-9],a[0-9],48 > +**... > +*/ > +unsigned int > +do_shift2(unsigned long csum) > +{ > + return (csum << 16) >> 48; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c > b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c > new file mode 100644 > index 000..2824d6fe074 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c > @@ -0,0 +1,37 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target rv32 } */ > +/* { dg-options "-march=rv32gc" } */ > +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ > +/* { dg-final { check-function-bodies "**" "" } } */ Same as above, counts where possible. -Vineet
Re: [PATCH] RISC-V: Add zero_extract support for rv64gc
On 5/6/24 2:40 PM, Christoph Müllner wrote: The combiner attempts to optimize a zero-extension of a logical right shift using zero_extract. We already utilize this optimization for those cases that result in a single instructions. Let's add a insn_and_split pattern that also matches the generic case, where we can emit an optimized sequence of a slli/srli. Tested with SPEC CPU 2017 (rv64gc). PR 111501 gcc/ChangeLog: * config/riscv/riscv.md (*lshr3_zero_extend_4): New pattern for zero-extraction. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr111501.c: New test. * gcc.target/riscv/zero-extend-rshift-32.c: New test. * gcc.target/riscv/zero-extend-rshift-64.c: New test. * gcc.target/riscv/zero-extend-rshift.c: New test. So I had Lyut looking in this space as well. Mostly because there's a desire to avoid the srl+and approach and instead represent this stuff as shifts (which are fusible in our uarch). SO I've already got some state... Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 30 + gcc/testsuite/gcc.target/riscv/pr111501.c | 32 + .../gcc.target/riscv/zero-extend-rshift-32.c | 37 ++ .../gcc.target/riscv/zero-extend-rshift-64.c | 63 ++ .../gcc.target/riscv/zero-extend-rshift.c | 119 ++ 5 files changed, 281 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr111501.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d4676507b45..80cbecb78e8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3" [(set_attr "type" "shift") (set_attr "mode" "SI")]) +;; Canonical form for a zero-extend of a logical right shift. +;; Special cases are handled above. +;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb) +(define_insn_and_split "*lshr3_zero_extend_4" + [(set (match_operand:GPR 0 "register_operand" "=r") +(zero_extract:GPR + (match_operand:GPR 1 "register_operand" " r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand"))) + (clobber (match_scratch:GPR 4 "="))] + "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1)) + && !TARGET_XTHEADBB" + "#" + "&& reload_completed" + [(set (match_dup 4) + (ashift:GPR (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (lshiftrt:GPR (match_dup 4) (match_dup 3)))] Consider adding support for signed extractions as well. You just need an iterator across zero_extract/sign_extract and suitable selection of arithmetic vs logical right shift step. A nit on the condition. Bring the && INTVAL (operands[2]) == 1 down to a new line like you've gone with !TARGET_XTHEADBB. You also want to make sure the condition rejects the cases handled by this pattern (or merge your pattern with this one): ;; Canonical form for a zero-extend of a logical right shift. (define_insn "*lshrsi3_zero_extend_2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extract:DI (match_operand:DI 1 "register_operand" " r") (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand")))] "(TARGET_64BIT && (INTVAL (operands[3]) > 0) && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))" { return "srliw\t%0,%1,%3"; } [(set_attr "type" "shift") (set_attr "mode" "SI")]) So generally going the right direction. But needs another iteration. Jeff
[PATCH] RISC-V: Add zero_extract support for rv64gc
The combiner attempts to optimize a zero-extension of a logical right shift using zero_extract. We already utilize this optimization for those cases that result in a single instructions. Let's add a insn_and_split pattern that also matches the generic case, where we can emit an optimized sequence of a slli/srli. Tested with SPEC CPU 2017 (rv64gc). PR 111501 gcc/ChangeLog: * config/riscv/riscv.md (*lshr3_zero_extend_4): New pattern for zero-extraction. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr111501.c: New test. * gcc.target/riscv/zero-extend-rshift-32.c: New test. * gcc.target/riscv/zero-extend-rshift-64.c: New test. * gcc.target/riscv/zero-extend-rshift.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 30 + gcc/testsuite/gcc.target/riscv/pr111501.c | 32 + .../gcc.target/riscv/zero-extend-rshift-32.c | 37 ++ .../gcc.target/riscv/zero-extend-rshift-64.c | 63 ++ .../gcc.target/riscv/zero-extend-rshift.c | 119 ++ 5 files changed, 281 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr111501.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d4676507b45..80cbecb78e8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2792,6 +2792,36 @@ (define_insn "*lshrsi3_zero_extend_3" [(set_attr "type" "shift") (set_attr "mode" "SI")]) +;; Canonical form for a zero-extend of a logical right shift. +;; Special cases are handled above. +;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb) +(define_insn_and_split "*lshr3_zero_extend_4" + [(set (match_operand:GPR 0 "register_operand" "=r") +(zero_extract:GPR + (match_operand:GPR 1 "register_operand" " r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand"))) + (clobber (match_scratch:GPR 4 "="))] + "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1)) + && !TARGET_XTHEADBB" + "#" + "&& reload_completed" + [(set (match_dup 4) + (ashift:GPR (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (lshiftrt:GPR (match_dup 4) (match_dup 3)))] +{ + int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant (); + int sizebits = INTVAL (operands[2]); + int startbits = INTVAL (operands[3]); + int lshamt = regbits - sizebits - startbits; + int rshamt = lshamt + startbits; + operands[2] = GEN_INT (lshamt); + operands[3] = GEN_INT (rshamt); +} + [(set_attr "type" "shift") + (set_attr "mode" "")]) + ;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into ;; two logical shifts. Otherwise it requires 3 instructions: lui, ;; xor/addi/srli, and. diff --git a/gcc/testsuite/gcc.target/riscv/pr111501.c b/gcc/testsuite/gcc.target/riscv/pr111501.c new file mode 100644 index 000..9355be242e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr111501.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-options "-march=rv64gc" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-allow-blank-lines-in-output 1 } */ + +/* +**do_shift: +**... +**slli\ta[0-9],a[0-9],16 +**srli\ta[0-9],a[0-9],48 +**... +*/ +unsigned int +do_shift(unsigned long csum) +{ + return (unsigned short)(csum >> 32); +} + +/* +**do_shift2: +**... +**slli\ta[0-9],a[0-9],16 +**srli\ta[0-9],a[0-9],48 +**... +*/ +unsigned int +do_shift2(unsigned long csum) +{ + return (csum << 16) >> 48; +} diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c new file mode 100644 index 000..2824d6fe074 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv32 } */ +/* { dg-options "-march=rv32gc" } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#define URT_ZE_UCT_RSHIFT_N_UAT(RT,CT,N,AT)\ +unsigned RT u##RT##_ze_u##CT##_rshift_##N##_u##AT(unsigned AT v) \ +{ \ +return (unsigned CT)(v >> N); \ +} + +#define ULONG_ZE_USHORT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,short,N,long) +#define ULONG_ZE_UINT_RSHIFT_N_ULONG(N) URT_ZE_UCT_RSHIFT_N_UAT(long,int,N,long) + +/* +**ulong_ze_ushort_rshift_9_ulong: +**slli\ta[0-9],a[0-9],7 +**