Re: [PATCH 1/5] RISC-V: Update Types for Vector Instructions
On 9/6/2023 4:23 PM, Kito Cheng wrote: LGTM Edwin Lu 於 2023年9月7日 週四 01:51 寫道： This patch adds types to vector instructions that were added after or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html gcc/ChangeLog: * config/riscv/autovec-opt.md: Update types * config/riscv/autovec.md: likewise Signed-off-by: Edwin Lu --- gcc/config/riscv/autovec-opt.md | 42 ++--- gcc/config/riscv/autovec.md | 28 +++--- 2 files changed, 47 insertions(+), 23 deletions(-) There seems to be around 9 new instructions that were added since this patch. I have tested them for the same extensions but only for linux so far. I'll submit a new patch later today with those changes Edwin
Re: [PATCH 1/5] RISC-V: Update Types for Vector Instructions
LGTM Edwin Lu 於 2023年9月7日 週四 01:51 寫道： > This patch adds types to vector instructions that were added after or were > missed by the original patch > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md: Update types > * config/riscv/autovec.md: likewise > > Signed-off-by: Edwin Lu > --- > gcc/config/riscv/autovec-opt.md | 42 ++--- > gcc/config/riscv/autovec.md | 28 +++--- > 2 files changed, 47 insertions(+), 23 deletions(-) > > diff --git a/gcc/config/riscv/autovec-opt.md > b/gcc/config/riscv/autovec-opt.md > index 1ca5ce97193..6cc1a01629c 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs" > gen_int_mode (GET_MODE_NUNITS > (mode), Pmode), > const0_rtx)); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine vlmax neg and UNSPEC_VCOPYSIGN > (define_insn_and_split "*copysign_neg" > @@ -746,7 +747,8 @@ (define_insn_and_split "*copysign_neg" >riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode), >riscv_vector::BINARY_OP, operands); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf2) and vcond_mask > (define_insn_and_split "*cond_" > @@ -765,7 +767,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf4) and vcond_mask > (define_insn_and_split "*cond_" > @@ -784,7 +787,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf8) and vcond_mask > (define_insn_and_split "*cond_" > @@ -803,7 +807,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine trunc(vf2) + vcond_mask > (define_insn_and_split "*cond_trunc" > @@ -823,7 +828,8 @@ (define_insn_and_split > "*cond_trunc" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask > (define_insn_and_split "*cond_extend" > @@ -842,7 +848,8 @@ (define_insn_and_split > "*cond_extend" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine FP trunc(vf2) + vcond_mask > (define_insn_and_split "*cond_trunc" > @@ -862,7 +869,8 @@ (define_insn_and_split > "*cond_trunc" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(FP->INT) + vcond_mask > (define_insn_and_split "*cond_" > @@ -882,7 +890,8 @@ (define_insn_and_split "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(INT->FP) + vcond_mask > (define_insn_and_split "*cond_" > @@ -902,7 +911,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(FP->2xINT) + vcond_mask > (define_insn_and_split "*cond_" > @@ -922,7 +932,8 @@ (define_insn_and_split "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(INT->2xFP) + vcond_mask > (define_insn_and_split "*cond_" > @@ -942,7 +953,8 @@ (define_insn_and_split > "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(2xFP->INT) + vcond_mask > (define_insn_and_split "*cond_" > @@ -962,7 +974,8 @@ (define_insn_and_split "*cond_" > gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; >riscv_vector::expand_cond_len_unop (icode, ops); >DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(2xINT->FP) + vcond_mask > (define_insn_and_split "*cond_2" > @@ -982,4 +995,5 @@
[PATCH 1/5] RISC-V: Update Types for Vector Instructions
This patch adds types to vector instructions that were added after or were missed by the original patch https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html gcc/ChangeLog: * config/riscv/autovec-opt.md: Update types * config/riscv/autovec.md: likewise Signed-off-by: Edwin Lu --- gcc/config/riscv/autovec-opt.md | 42 ++--- gcc/config/riscv/autovec.md | 28 +++--- 2 files changed, 47 insertions(+), 23 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 1ca5ce97193..6cc1a01629c 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs" gen_int_mode (GET_MODE_NUNITS (mode), Pmode), const0_rtx)); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine vlmax neg and UNSPEC_VCOPYSIGN (define_insn_and_split "*copysign_neg" @@ -746,7 +747,8 @@ (define_insn_and_split "*copysign_neg" riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode), riscv_vector::BINARY_OP, operands); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf2) and vcond_mask (define_insn_and_split "*cond_" @@ -765,7 +767,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf4) and vcond_mask (define_insn_and_split "*cond_" @@ -784,7 +787,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine sign_extend/zero_extend(vf8) and vcond_mask (define_insn_and_split "*cond_" @@ -803,7 +807,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" @@ -823,7 +828,8 @@ (define_insn_and_split "*cond_trunc" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask (define_insn_and_split "*cond_extend" @@ -842,7 +848,8 @@ (define_insn_and_split "*cond_extend" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine FP trunc(vf2) + vcond_mask (define_insn_and_split "*cond_trunc" @@ -862,7 +869,8 @@ (define_insn_and_split "*cond_trunc" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(FP->INT) + vcond_mask (define_insn_and_split "*cond_" @@ -882,7 +890,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(INT->FP) + vcond_mask (define_insn_and_split "*cond_" @@ -902,7 +911,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(FP->2xINT) + vcond_mask (define_insn_and_split "*cond_" @@ -922,7 +932,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(INT->2xFP) + vcond_mask (define_insn_and_split "*cond_" @@ -942,7 +953,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(2xFP->INT) + vcond_mask (define_insn_and_split "*cond_" @@ -962,7 +974,8 @@ (define_insn_and_split "*cond_" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) ;; Combine convert(2xINT->FP) + vcond_mask (define_insn_and_split "*cond_2" @@ -982,4 +995,5 @@ (define_insn_and_split "*cond_2" gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} +[(set_attr "type" "vector")]) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 0f9d1fe2c8e..047a66b238f 100644 --- a/gcc/config/riscv/autovec.md +++
