Re: [PATCH v5] RISC-V:Optimize the MASK opt generation
On 9/7/23 19:26, Feng Wang wrote:
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
index 36de4639318..cbfcf7dabcf 100644
--- a/gcc/opt-functions.awk
+++ b/gcc/opt-functions.awk
@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option,
uinteger_used)
else
return "-1, -1"
}
+
+# Find the index of target variable from extra_target_vars
+function find_index(var, var_arry, n_var_arry)
+{
+for (var_index = 0; var_index < n_var_arry; var_index++)
+{
+if (var_arry[var_index] == var)
+break
+}
+return var_index
+}
So if the mapping isn't found, it looks like this will return
n_var_arry. It looks like the caller expects that and adds a new entry
to var_arry. I would suggest a better comment. Perhaps something like
# Find the index of VAR in VAR_ARRY which as length N_VAR_ARRY. If
# VAR is not found, return N_VAR_ARRY.
I believe there is extensive documentation of the options handling in
doc/options.texi. The new functionality in this patch should be
documented there. Give it your best shot and I can help polish up the
language.
Thanks,
Jeff
Re: [PATCH v5] RISC-V:Optimize the MASK opt generation
Hi Feng: This version is LGTM, but I guess I would like to ask Jeff or another global maintainer to approve that, anyway I'll follow up this in the next gcc sync up meeting :) On Fri, Sep 8, 2023 at 9:28 AM Feng Wang wrote: > > Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)" > to generate MASK and TARGET MACRO automatically. > This patch improve the MACRO generation of MASK_* and TARGET_*. > Due to the more and more riscv extensions are added, the default target_flag > is full. > Before this patch,if you want to add new MACRO,you should define the > MACRO in the riscv-opts.h manually. > After this patch, you just need two steps: > 1.Define the new TargetVariable. > 2.Define "MASK(name) Var(new_target_flag). > > gcc/ChangeLog: > > * config/riscv/riscv-opts.h (MASK_ZICSR): > (MASK_ZIFENCEI): Delete; > (MASK_ZIHINTNTL):Ditto; > (MASK_ZIHINTPAUSE): Ditto; > (TARGET_ZICSR): Ditto; > (TARGET_ZIFENCEI): Ditto; > (TARGET_ZIHINTNTL): Ditto; > (TARGET_ZIHINTPAUSE):Ditto; > (MASK_ZAWRS):Ditto; > (TARGET_ZAWRS): Ditto; > (MASK_ZBA): Ditto; > (MASK_ZBB): Ditto; > (MASK_ZBC): Ditto; > (MASK_ZBS): Ditto; > (TARGET_ZBA):Ditto; > (TARGET_ZBB):Ditto; > (TARGET_ZBC):Ditto; > (TARGET_ZBS):Ditto; > (MASK_ZFINX):Ditto; > (MASK_ZDINX):Ditto; > (MASK_ZHINX):Ditto; > (MASK_ZHINXMIN): Ditto; > (TARGET_ZFINX): Ditto; > (TARGET_ZDINX): Ditto; > (TARGET_ZHINX): Ditto; > (TARGET_ZHINXMIN): Ditto; > (MASK_ZBKB): Ditto; > (MASK_ZBKC): Ditto; > (MASK_ZBKX): Ditto; > (MASK_ZKNE): Ditto; > (MASK_ZKND): Ditto; > (MASK_ZKNH): Ditto; > (MASK_ZKR): Ditto; > (MASK_ZKSED):Ditto; > (MASK_ZKSH): Ditto; > (MASK_ZKT): Ditto; > (TARGET_ZBKB): Ditto; > (TARGET_ZBKC): Ditto; > (TARGET_ZBKX): Ditto; > (TARGET_ZKNE): Ditto; > (TARGET_ZKND): Ditto; > (TARGET_ZKNH): Ditto; > (TARGET_ZKR):Ditto; > (TARGET_ZKSED): Ditto; > (TARGET_ZKSH): Ditto; > (TARGET_ZKT):Ditto; > (MASK_ZTSO): Ditto; > (TARGET_ZTSO): Ditto; > (MASK_VECTOR_ELEN_32): Ditto; > (MASK_VECTOR_ELEN_64): Ditto; > (MASK_VECTOR_ELEN_FP_32):Ditto; > (MASK_VECTOR_ELEN_FP_64):Ditto; > (MASK_VECTOR_ELEN_FP_16):Ditto; > (TARGET_VECTOR_ELEN_32): Ditto; > (TARGET_VECTOR_ELEN_64): Ditto; > (TARGET_VECTOR_ELEN_FP_32):Ditto; > (TARGET_VECTOR_ELEN_FP_64):Ditto; > (TARGET_VECTOR_ELEN_FP_16):Ditto; > (MASK_ZVBB): Ditto; > (MASK_ZVBC): Ditto; > (TARGET_ZVBB): Ditto; > (TARGET_ZVBC): Ditto; > (MASK_ZVKG): Ditto; > (MASK_ZVKNED): Ditto; > (MASK_ZVKNHA): Ditto; > (MASK_ZVKNHB): Ditto; > (MASK_ZVKSED): Ditto; > (MASK_ZVKSH): Ditto; > (MASK_ZVKN): Ditto; > (MASK_ZVKNC): Ditto; > (MASK_ZVKNG): Ditto; > (MASK_ZVKS): Ditto; > (MASK_ZVKSC): Ditto; > (MASK_ZVKSG): Ditto; > (MASK_ZVKT): Ditto; > (TARGET_ZVKG): Ditto; > (TARGET_ZVKNED): Ditto; > (TARGET_ZVKNHA): Ditto; > (TARGET_ZVKNHB): Ditto; > (TARGET_ZVKSED): Ditto; > (TARGET_ZVKSH):Ditto; > (TARGET_ZVKN): Ditto; > (TARGET_ZVKNC):Ditto; > (TARGET_ZVKNG):Ditto; > (TARGET_ZVKS): Ditto; > (TARGET_ZVKSC):Ditto; > (TARGET_ZVKSG):Ditto; > (TARGET_ZVKT): Ditto; > (MASK_ZVL32B): Ditto; > (MASK_ZVL64B): Ditto; > (MASK_ZVL128B):Ditto; > (MASK_ZVL256B):Ditto; > (MASK_ZVL512B):Ditto; > (MASK_ZVL1024B): Ditto; > (MASK_ZVL2048B): Ditto; > (MASK_ZVL4096B): Ditto; > (MASK_ZVL8192B): Ditto; > (MASK_ZVL16384B): Ditto; > (MASK_ZVL32768B): Ditto; > (MASK_ZVL65536B): Ditto; > (TARGET_ZVL32B): Ditto; > (TARGET_ZVL64B): Ditto; > (TARGET_ZVL128B): Ditto; > (TARGET_ZVL256B): Ditto; > (TARGET_ZVL512B): Ditto; > (TARGET_ZVL1024B): Ditto; > (TARGET_ZVL2048B): Ditto; >
[PATCH v5] RISC-V:Optimize the MASK opt generation
Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)" to generate MASK and TARGET MACRO automatically. This patch improve the MACRO generation of MASK_* and TARGET_*. Due to the more and more riscv extensions are added, the default target_flag is full. Before this patch,if you want to add new MACRO,you should define the MACRO in the riscv-opts.h manually. After this patch, you just need two steps: 1.Define the new TargetVariable. 2.Define "MASK(name) Var(new_target_flag). gcc/ChangeLog: * config/riscv/riscv-opts.h (MASK_ZICSR): (MASK_ZIFENCEI): Delete; (MASK_ZIHINTNTL):Ditto; (MASK_ZIHINTPAUSE): Ditto; (TARGET_ZICSR): Ditto; (TARGET_ZIFENCEI): Ditto; (TARGET_ZIHINTNTL): Ditto; (TARGET_ZIHINTPAUSE):Ditto; (MASK_ZAWRS):Ditto; (TARGET_ZAWRS): Ditto; (MASK_ZBA): Ditto; (MASK_ZBB): Ditto; (MASK_ZBC): Ditto; (MASK_ZBS): Ditto; (TARGET_ZBA):Ditto; (TARGET_ZBB):Ditto; (TARGET_ZBC):Ditto; (TARGET_ZBS):Ditto; (MASK_ZFINX):Ditto; (MASK_ZDINX):Ditto; (MASK_ZHINX):Ditto; (MASK_ZHINXMIN): Ditto; (TARGET_ZFINX): Ditto; (TARGET_ZDINX): Ditto; (TARGET_ZHINX): Ditto; (TARGET_ZHINXMIN): Ditto; (MASK_ZBKB): Ditto; (MASK_ZBKC): Ditto; (MASK_ZBKX): Ditto; (MASK_ZKNE): Ditto; (MASK_ZKND): Ditto; (MASK_ZKNH): Ditto; (MASK_ZKR): Ditto; (MASK_ZKSED):Ditto; (MASK_ZKSH): Ditto; (MASK_ZKT): Ditto; (TARGET_ZBKB): Ditto; (TARGET_ZBKC): Ditto; (TARGET_ZBKX): Ditto; (TARGET_ZKNE): Ditto; (TARGET_ZKND): Ditto; (TARGET_ZKNH): Ditto; (TARGET_ZKR):Ditto; (TARGET_ZKSED): Ditto; (TARGET_ZKSH): Ditto; (TARGET_ZKT):Ditto; (MASK_ZTSO): Ditto; (TARGET_ZTSO): Ditto; (MASK_VECTOR_ELEN_32): Ditto; (MASK_VECTOR_ELEN_64): Ditto; (MASK_VECTOR_ELEN_FP_32):Ditto; (MASK_VECTOR_ELEN_FP_64):Ditto; (MASK_VECTOR_ELEN_FP_16):Ditto; (TARGET_VECTOR_ELEN_32): Ditto; (TARGET_VECTOR_ELEN_64): Ditto; (TARGET_VECTOR_ELEN_FP_32):Ditto; (TARGET_VECTOR_ELEN_FP_64):Ditto; (TARGET_VECTOR_ELEN_FP_16):Ditto; (MASK_ZVBB): Ditto; (MASK_ZVBC): Ditto; (TARGET_ZVBB): Ditto; (TARGET_ZVBC): Ditto; (MASK_ZVKG): Ditto; (MASK_ZVKNED): Ditto; (MASK_ZVKNHA): Ditto; (MASK_ZVKNHB): Ditto; (MASK_ZVKSED): Ditto; (MASK_ZVKSH): Ditto; (MASK_ZVKN): Ditto; (MASK_ZVKNC): Ditto; (MASK_ZVKNG): Ditto; (MASK_ZVKS): Ditto; (MASK_ZVKSC): Ditto; (MASK_ZVKSG): Ditto; (MASK_ZVKT): Ditto; (TARGET_ZVKG): Ditto; (TARGET_ZVKNED): Ditto; (TARGET_ZVKNHA): Ditto; (TARGET_ZVKNHB): Ditto; (TARGET_ZVKSED): Ditto; (TARGET_ZVKSH):Ditto; (TARGET_ZVKN): Ditto; (TARGET_ZVKNC):Ditto; (TARGET_ZVKNG):Ditto; (TARGET_ZVKS): Ditto; (TARGET_ZVKSC):Ditto; (TARGET_ZVKSG):Ditto; (TARGET_ZVKT): Ditto; (MASK_ZVL32B): Ditto; (MASK_ZVL64B): Ditto; (MASK_ZVL128B):Ditto; (MASK_ZVL256B):Ditto; (MASK_ZVL512B):Ditto; (MASK_ZVL1024B): Ditto; (MASK_ZVL2048B): Ditto; (MASK_ZVL4096B): Ditto; (MASK_ZVL8192B): Ditto; (MASK_ZVL16384B): Ditto; (MASK_ZVL32768B): Ditto; (MASK_ZVL65536B): Ditto; (TARGET_ZVL32B): Ditto; (TARGET_ZVL64B): Ditto; (TARGET_ZVL128B): Ditto; (TARGET_ZVL256B): Ditto; (TARGET_ZVL512B): Ditto; (TARGET_ZVL1024B): Ditto; (TARGET_ZVL2048B): Ditto; (TARGET_ZVL4096B): Ditto; (TARGET_ZVL8192B): Ditto; (TARGET_ZVL16384B):Ditto; (TARGET_ZVL32768B):Ditto; (TARGET_ZVL65536B):Ditto; (MASK_ZICBOZ): Ditto; (MASK_ZICBOM): Ditto; (MASK_ZICBOP): Ditto; (TARGET_ZICBOZ): Ditto; (TARGET_ZICBOM): Ditto; (TARGET_ZICBOP): Ditto; (MASK_ZICOND): Ditto;
