Go patch commited: tuple receives indicate whether channel closed
The Go language has changed the meaning of
v, ok := -c
Now ok is set to whether the channel is closed, rather than having this
be a nonblocking read in which ok is set to whether the value was
received. Nonblocking reads now require a select statement. This patch
implements this in gccgo. Bootstrapped and ran Go testsuite on
x86_64-unknown-linux-gnu. Committed to mainline.
Ian
diff -r 2ddeb22c4cf0 go/gogo-tree.cc
--- a/go/gogo-tree.cc Wed Mar 23 17:36:50 2011 -0700
+++ b/go/gogo-tree.cc Wed Mar 23 22:54:00 2011 -0700
@@ -3057,7 +3057,7 @@
location,
__go_receive_big,
3,
- void_type_node,
+ boolean_type_node,
ptr_type_node,
channel,
ptr_type_node,
diff -r 2ddeb22c4cf0 go/gogo.cc
--- a/go/gogo.cc Wed Mar 23 17:36:50 2011 -0700
+++ b/go/gogo.cc Wed Mar 23 22:54:00 2011 -0700
@@ -1257,7 +1257,7 @@
Statement* s = sorig;
while (true)
{
- Statement* snew = s-lower(this-gogo_, block);
+ Statement* snew = s-lower(this-gogo_, this-function_, block);
if (snew == s)
break;
s = snew;
@@ -1305,6 +1305,15 @@
this-traverse(lower_parse_tree);
}
+// Lower a block.
+
+void
+Gogo::lower_block(Named_object* function, Block* block)
+{
+ Lower_parse_tree lower_parse_tree(this, function);
+ block-traverse(lower_parse_tree);
+}
+
// Lower an expression.
void
diff -r 2ddeb22c4cf0 go/gogo.h
--- a/go/gogo.h Wed Mar 23 17:36:50 2011 -0700
+++ b/go/gogo.h Wed Mar 23 22:54:00 2011 -0700
@@ -348,6 +348,10 @@
void
lower_parse_tree();
+ // Lower all the statements in a block.
+ void
+ lower_block(Named_object* function, Block*);
+
// Lower an expression.
void
lower_expression(Named_object* function, Expression**);
diff -r 2ddeb22c4cf0 go/parse.cc
--- a/go/parse.cc Wed Mar 23 17:36:50 2011 -0700
+++ b/go/parse.cc Wed Mar 23 22:54:00 2011 -0700
@@ -4179,10 +4179,12 @@
bool is_send = false;
Expression* channel = NULL;
Expression* val = NULL;
+ Expression* closed = NULL;
std::string varname;
+ std::string closedname;
bool is_default = false;
- bool got_case = this-comm_case(is_send, channel, val, varname,
- is_default);
+ bool got_case = this-comm_case(is_send, channel, val, closed,
+ varname, closedname, is_default);
if (this-peek_token()-is_op(OPERATOR_COLON))
this-advance_token();
@@ -4191,6 +4193,7 @@
Block* statements = NULL;
Named_object* var = NULL;
+ Named_object* closedvar = NULL;
if (this-peek_token()-is_op(OPERATOR_SEMICOLON))
this-advance_token();
else if (this-statement_list_may_start_here())
@@ -4206,6 +4209,14 @@
var = this-gogo_-add_variable(varname, v);
}
+ if (!closedname.empty())
+ {
+ // FIXME: LOCATION is slightly wrong here.
+ Variable* v = new Variable(Type::lookup_bool_type(), NULL,
+ false, false, false, location);
+ closedvar = this-gogo_-add_variable(closedname, v);
+ }
+
this-statement_list();
statements = this-gogo_-finish_block(this-location());
}
@@ -4221,7 +4232,8 @@
}
if (got_case)
-clauses-add(is_send, channel, val, var, is_default, statements, location);
+clauses-add(is_send, channel, val, closed, var, closedvar, is_default,
+ statements, location);
else if (statements != NULL)
{
// Add the statements to make sure that any names they define
@@ -4234,7 +4246,8 @@
bool
Parse::comm_case(bool* is_send, Expression** channel, Expression** val,
- std::string* varname, bool* is_default)
+ Expression** closed, std::string* varname,
+ std::string* closedname, bool* is_default)
{
const Token* token = this-peek_token();
if (token-is_keyword(KEYWORD_DEFAULT))
@@ -4245,7 +4258,8 @@
else if (token-is_keyword(KEYWORD_CASE))
{
this-advance_token();
- if (!this-send_or_recv_expr(is_send, channel, val, varname))
+ if (!this-send_or_recv_stmt(is_send, channel, val, closed, varname,
+ closedname))
return false;
}
else
@@ -4259,74 +4273,160 @@
return true;
}
-// RecvExpr = [ Expression ( = | := ) ] - Expression .
+// RecvStmt = [ Expression [ , Expression ] ( = | := ) ] RecvExpr .
+// RecvExpr = Expression .
bool
-Parse::send_or_recv_expr(bool* is_send, Expression** channel, Expression** val,
- std::string* varname)
+Parse::send_or_recv_stmt(bool* is_send, Expression** channel, Expression** val,
+ Expression** closed, std::string* varname,
+ std::string* closedname)
{
const Token* token = this-peek_token();
- source_location location = token-location();
+ bool saw_comma = false;
+ bool closed_is_id = false;
if (token-is_identifier())
{
+ Gogo* gogo = this-gogo_;
std::string recv_var = token-identifier();
- bool is_var_exported = token-is_identifier_exported();
- if (!this-advance_token()-is_op(OPERATOR_COLONEQ))
- this-unget_token(Token::make_identifier_token(recv_var,
- is_var_exported,
-
[Patch, testsuite]: Don't xfail sibcalls on AVR
Target avr now supports tail calls, so don't xfail on that.
testsuite/
2011-03-24 Georg-Johann Lay a...@gjlay.de
* gcc.dg/sibcall-3.c: Don't xfail on AVR.
* gcc.dg/sibcall-4.c: Don't xfail on AVR.
Index: testsuite/gcc.dg/sibcall-3.c
===
--- testsuite/gcc.dg/sibcall-3.c (Revision 171039)
+++ testsuite/gcc.dg/sibcall-3.c (Arbeitskopie)
@@ -5,7 +5,7 @@
Copyright (C) 2002 Free Software Foundation Inc.
Contributed by Hans-Peter Nilsson h...@bitrange.com */
-/* { dg-do run { xfail { { arc-*-* avr-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* { ! arm32 } } } } } */
+/* { dg-do run { xfail { { arc-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* { ! arm32 } } } } } */
/* -mlongcall disables sibcall patterns. */
/* { dg-skip-if { powerpc*-*-* } { -mlongcall } { } } */
/* { dg-options -O2 -foptimize-sibling-calls } */
Index: testsuite/gcc.dg/sibcall-4.c
===
--- testsuite/gcc.dg/sibcall-4.c (Revision 171039)
+++ testsuite/gcc.dg/sibcall-4.c (Arbeitskopie)
@@ -5,7 +5,7 @@
Copyright (C) 2002 Free Software Foundation Inc.
Contributed by Hans-Peter Nilsson h...@bitrange.com */
-/* { dg-do run { xfail { { arc-*-* avr-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* { ! arm32 } } } } } */
+/* { dg-do run { xfail { { arc-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* { ! arm32 } } } } } */
/* -mlongcall disables sibcall patterns. */
/* { dg-skip-if { powerpc*-*-* } { -mlongcall } { } } */
/* { dg-options -O2 -foptimize-sibling-calls } */
[patch, ARM] Enable auto-detection of vector size for NEON
Hi,
This patch implements TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES for ARM NEON.
Regtested on arm-linux-gnueabi.
OK for trunk?
Thanks,
Ira
ChangeLog:
* config/arm/arm.c (arm_autovectorize_vector_sizes): New
function.
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.
testsuite/ChangeLog:
* gcc.dg/vect/vect-outer-5.c: Reduce the distance between data
accesses to preserve the meaning of the test for doubleword vectors.
* gcc.dg/vect/no-vfa-pr29145.c: Likewise.
* gcc.dg/vect/slp-3.c: Reduce the loop bound for the same reason.
Index: config/arm/arm.c
===
--- config/arm/arm.c(revision 171339)
+++ config/arm/arm.c(working copy)
@@ -252,6 +252,7 @@ static bool arm_builtin_support_vector_misalignmen
bool is_packed);
static void arm_conditional_register_usage (void);
static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
+static unsigned int arm_autovectorize_vector_sizes (void);
^L
/* Table of machine attributes. */
@@ -404,6 +405,9 @@ static const struct default_options arm_option_opt
#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
+#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
+#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
+ arm_autovectorize_vector_sizes
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
@@ -23528,6 +23532,12 @@ arm_expand_sync (enum machine_mode mode,
}
}
+static unsigned int
+arm_autovectorize_vector_sizes (void)
+{
+ return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0;
+}
+
static bool
arm_vector_alignment_reachable (const_tree type, bool is_packed)
{
Index: testsuite/gcc.dg/vect/vect-outer-5.c
===
--- testsuite/gcc.dg/vect/vect-outer-5.c(revision 171339)
+++ testsuite/gcc.dg/vect/vect-outer-5.c(working copy)
@@ -17,7 +17,7 @@ int main1 ()
float B[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
float C[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
float D[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
- float E[4] = {0,1,2,480};
+ float E[4] = {0,480,960,1440};
float s;
int i, j;
@@ -55,7 +55,7 @@ int main1 ()
s = 0;
for (j=0; jN; j+=4)
s += C[j];
- B[i+3] = B[i] + s;
+ B[i+1] = B[i] + s;
}
/* check results: */
Index: testsuite/gcc.dg/vect/slp-3.c
===
--- testsuite/gcc.dg/vect/slp-3.c (revision 171339)
+++ testsuite/gcc.dg/vect/slp-3.c (working copy)
@@ -101,7 +101,7 @@ main1 ()
}
/* SLP with unrolling by 8. */
- for (i = 0; i N/2; i++)
+ for (i = 0; i N/4; i++)
{
out[i*9] = in[i*9];
out[i*9 + 1] = in[i*9 + 1];
@@ -115,7 +115,7 @@ main1 ()
}
/* check results: */
- for (i = 0; i N/2; i++)
+ for (i = 0; i N/4; i++)
{
if (out[i*9] != in[i*9]
|| out[i*9 + 1] != in[i*9 + 1]
Index: testsuite/gcc.dg/vect/no-vfa-pr29145.c
===
--- testsuite/gcc.dg/vect/no-vfa-pr29145.c (revision 171339)
+++ testsuite/gcc.dg/vect/no-vfa-pr29145.c (working copy)
@@ -8,7 +8,7 @@ __attribute__ ((noinline))
void with_restrict(int * __restrict p)
{
int i;
- int *q = p - 2;
+ int *q = p - 1;
for (i = 0; i 1000; ++i) {
p[i] = q[i];
@@ -19,7 +19,7 @@ __attribute__ ((noinline))
void without_restrict(int * p)
{
int i;
- int *q = p - 2;
+ int *q = p - 1;
for (i = 0; i 1000; ++i) {
p[i] = q[i];
@@ -38,8 +38,8 @@ int main(void)
a[i] = b[i] = i;
}
- with_restrict(a + 2);
- without_restrict(b + 2);
+ with_restrict(a + 1);
+ without_restrict(b + 1);
for (i = 0; i 1002; ++i) {
if (a[i] != b[i])
Re: [patch middle-end c c++]: Optimize cost of comp_type_attributes
On 03/21/2011 06:36 PM, Kai Tietz wrote:
+ attr = lookup_attribute (IDENTIFIER_POINTER (TREE_PURPOSE (a)),
+ CONST_CAST_TREE (a2));
I might use as-name for the name, and change lookup_attribute to take a
const_tree rather than use CONST_CAST_TREE.
+ if (!a)
+{
+ for (a = a2; a != NULL_TREE; a = TREE_CHAIN (a))
+ {
+ const struct attribute_spec *as;
+ const_tree attr;
+ as = lookup_attribute_spec (TREE_PURPOSE (a));
+ if (!as || as-affects_type_identity == false)
+ continue;
+ attr = lookup_attribute (IDENTIFIER_POINTER (TREE_PURPOSE (a)),
+ CONST_CAST_TREE (a1));
+ if (!attr)
+ break;
+
+ if (TREE_VALUE (a) != NULL_TREE
+ TREE_CODE (TREE_VALUE (a)) == TREE_LIST
+ TREE_VALUE (attr) != NULL
+ TREE_CODE (TREE_VALUE (attr)) == TREE_LIST)
+ {
+ if (simple_cst_list_equal (TREE_VALUE (a),
+TREE_VALUE (attr)) == 1)
+ break;
+ }
+ else if (simple_cst_equal (TREE_VALUE (a), TREE_VALUE (attr)) == 1)
+ break;
+ }
Once we've walked the first list, we don't need to compare the values of
common attributes again; for each attribute in the second list either it
does appear in the first list and we've already established that they
match, or it doesn't appear in the first list and we're done.
Jason
Re: Cleaning up expand optabs code
Anatoly Sokolov ae...@post.ru writes:
This patch casue ICE on H8300 target:
This is due to jump_address_operand checking the wrong mode.
The predicate is:
(define_predicate jump_address_operand
(match_code reg,mem)
{
if (GET_CODE (op) == REG)
return mode == Pmode;
[...]
}
but mode is the mode passed to the predicate, not the mode of OP.
The indirect_jump pattern is:
(define_expand indirect_jump
[(set (pc) (match_operand 0 jump_address_operand ))]
)
which says that VOIDmode should be passed to jump_address_operand,
so all registers end up being rejected.
I've applied the following as the obvious fix. You then hit bug
48263 ( http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48263 );
I'm testing a fix for that now.
Richard
gcc/
* config/h8300/predicates.md (jump_address_operand): Fix register
mode check.
Index: gcc/config/h8300/predicates.md
===
--- gcc/config/h8300/predicates.md 2011-01-05 15:12:08.0 +
+++ gcc/config/h8300/predicates.md 2011-03-24 09:20:15.0 +
@@ -259,7 +259,7 @@ (define_predicate jump_address_operand
(match_code reg,mem)
{
if (GET_CODE (op) == REG)
-return mode == Pmode;
+return GET_MODE (op) == Pmode;
if (GET_CODE (op) == MEM)
{
Re: [lto] Minor cleanups, export some functions (issue4272068)
On Wed, Mar 23, 2011 at 10:24 PM, Diego Novillo dnovi...@google.com wrote:
This patch has a few cleanups and exports 5 functions from the LTO streamer
that we are using from PPH.
- When calling output_string_with_length, every caller would first
write a 0 to indicate that the string is not NULL before writing the
actual string. I moved that into output_string_with_length.
- The functions to read/write raw data blocks was private to
lto-opts.c. I moved it as a general available function into
lto-streamer-*.c.
- Similarly, the functions to read/write strings and the code to emit
decl streams and references were private. I made them extern so
they can be called from pph.
None of the above changes behaviour in LTO. The patch bootstrap and
tests on x86_64. OK for trunk?
Ok.
Thanks,
Richard.
Diego.
* lto-opts.c (input_data_block): Move to lto-streamer-in.c.
* lto-streamer-in.c (input_string_internal): Add clarifying
comments.
(lto_input_data_block): Move from lto-opts.c. Make extern.
Update all users.
(lto_input_string): Rename from input_string. Make extern.
Update all users.
* lto-streamer-out.c (lto_output_string_with_length): Rename from
output_string_with_length.
Output 0 to indicate a non-NULL string. Update all callers to
not emit 0.
(lto_output_string): Rename from output_string. Make extern.
Update all users.
(lto_output_decl_state_streams): Make extern.
(lto_output_decl_state_refs): Make extern.
* lto-streamer.h (lto_input_string): Declare.
(lto_input_data_block): Declare.
(lto_output_string): Declare.
(lto_output_string_with_length): Declare.
(lto_output_decl_state_streams): Declare.
(lto_output_decl_state_refs): Declare.
diff --git a/gcc/lto-opts.c b/gcc/lto-opts.c
index ec4e78d..9979e8d 100644
--- a/gcc/lto-opts.c
+++ b/gcc/lto-opts.c
@@ -162,18 +162,6 @@ output_string_stream (struct lto_output_stream *stream,
const char *string)
output_data_stream (stream, flag, sizeof (flag));
}
-/* Read LENGTH bytes from STREAM to ADDR. */
-
-static void
-input_data_block (struct lto_input_block *ib, void *addr, size_t length)
-{
- size_t i;
- unsigned char *const buffer = (unsigned char *const) addr;
-
- for (i = 0; i length; i++)
- buffer[i] = lto_input_1_unsigned (ib);
-}
-
/* Return a string from IB. The string is allocated, and the caller is
responsible for freeing it. */
@@ -182,15 +170,15 @@ input_string_block (struct lto_input_block *ib)
{
bool flag;
- input_data_block (ib, flag, sizeof (flag));
+ lto_input_data_block (ib, flag, sizeof (flag));
if (flag)
{
size_t length;
char *string;
- input_data_block (ib, length, sizeof (length));
+ lto_input_data_block (ib, length, sizeof (length));
string = (char *) xcalloc (1, length + 1);
- input_data_block (ib, string, length);
+ lto_input_data_block (ib, string, length);
return string;
}
@@ -336,16 +324,16 @@ input_options (struct lto_input_block *ib)
{
size_t length, i;
- input_data_block (ib, length, sizeof (length));
+ lto_input_data_block (ib, length, sizeof (length));
for (i = 0; i length; i++)
{
opt_t o;
- input_data_block (ib, o.type, sizeof (o.type));
- input_data_block (ib, o.code, sizeof (o.code));
+ lto_input_data_block (ib, o.type, sizeof (o.type));
+ lto_input_data_block (ib, o.code, sizeof (o.code));
o.arg = input_string_block (ib);
- input_data_block (ib, o.value, sizeof (o.value));
+ lto_input_data_block (ib, o.value, sizeof (o.value));
VEC_safe_push (opt_t, heap, file_options, o);
}
}
diff --git a/gcc/lto-streamer-in.c b/gcc/lto-streamer-in.c
index a873258..383bfc2 100644
--- a/gcc/lto-streamer-in.c
+++ b/gcc/lto-streamer-in.c
@@ -140,7 +140,10 @@ input_string_internal (struct data_in *data_in, struct
lto_input_block *ib,
unsigned int loc;
const char *result;
+ /* Read the location of the string from IB. */
loc = lto_input_uleb128 (ib);
+
+ /* Get the string stored at location LOC in DATA_IN-STRINGS. */
LTO_INIT_INPUT_BLOCK (str_tab, data_in-strings, loc, data_in-strings_len);
len = lto_input_uleb128 (str_tab);
*rlen = len;
@@ -191,10 +194,24 @@ input_identifier (struct data_in *data_in, struct
lto_input_block *ib)
return get_identifier_with_length (ptr, len);
}
+
+/* Read LENGTH bytes from STREAM to ADDR. */
+
+void
+lto_input_data_block (struct lto_input_block *ib, void *addr, size_t length)
+{
+ size_t i;
+ unsigned char *const buffer = (unsigned char *const) addr;
+
+ for (i = 0; i length; i++)
+ buffer[i] = lto_input_1_unsigned (ib);
+}
+
+
/* Read a NULL terminated string from the string table in DATA_IN. */
-static const char *
-input_string (struct data_in
Re: [doc patch] obvious partial fix for other/48254
On Wed, Mar 23, 2011 at 11:03 PM, Jonathan Wakely jwakely@gmail.com wrote:
Committed to 4.4 and 4.5 branches as obvious, will apply to 4.6 after
4.6.0 is released. The option's gone on the trunk so not relevant
there.
If you apply anything to 4.6 it should probably simply change
the docs to say This option does nothing.. Or maybe don't
pretend it exists in any useful form and remove it completely.
Richard.
2011-03-23 Jonathan Wakely jwakely@gmail.com
PR other/48254
* doc/invoke.texi (-fipa-struct-reorg): Fix typo.
Index: doc/invoke.texi
===
--- doc/invoke.texi (revision 171365)
+++ doc/invoke.texi (working copy)
@@ -6121,7 +6121,7 @@ Enabled by default at @option{-O} and hi
@opindex fipa-struct-reorg
Perform structure reorganization optimization, that change C-like structures
layout in order to better utilize spatial locality. This transformation is
-affective for programs containing arrays of structures. Available in two
+effective for programs containing arrays of structures. Available in two
compilation modes: profile-based (enabled with @option{-fprofile-generate})
or static (which uses built-in heuristics). Require
@option{-fipa-type-escape}
to provide the safety of this transformation. It works only in whole program
Re: [doc patch] obvious partial fix for other/48254
On 24 March 2011 10:12, Richard Guenther wrote: On Wed, Mar 23, 2011 at 11:03 PM, Jonathan Wakely jwakely@gmail.com wrote: Committed to 4.4 and 4.5 branches as obvious, will apply to 4.6 after 4.6.0 is released. The option's gone on the trunk so not relevant there. If you apply anything to 4.6 it should probably simply change the docs to say This option does nothing.. Or maybe don't pretend it exists in any useful form and remove it completely. Ah, I didn't realise that was the case, thanks!
Re: [patch middle-end c c++]: Optimize cost of comp_type_attributes
2011/3/24 Jason Merrill ja...@redhat.com:
On 03/21/2011 06:36 PM, Kai Tietz wrote:
+ attr = lookup_attribute (IDENTIFIER_POINTER (TREE_PURPOSE (a)),
+ CONST_CAST_TREE (a2));
I might use as-name for the name, and change lookup_attribute to take a
const_tree rather than use CONST_CAST_TREE.
I changed patch to use as-name here instead. The CONST_CAST_TREE
part - as we discussed on irc - is necessary, as lookup_attribute
returns as result a non-const tree.
+ if (!a)
+ {
+ for (a = a2; a != NULL_TREE; a = TREE_CHAIN (a))
+ {
+ const struct attribute_spec *as;
+ const_tree attr;
+ as = lookup_attribute_spec (TREE_PURPOSE (a));
+ if (!as || as-affects_type_identity == false)
+ continue;
+ attr = lookup_attribute (IDENTIFIER_POINTER (TREE_PURPOSE (a)),
+ CONST_CAST_TREE (a1));
+ if (!attr)
+ break;
+
+ if (TREE_VALUE (a) != NULL_TREE
+ TREE_CODE (TREE_VALUE (a)) == TREE_LIST
+ TREE_VALUE (attr) != NULL
+ TREE_CODE (TREE_VALUE (attr)) == TREE_LIST)
+ {
+ if (simple_cst_list_equal (TREE_VALUE (a),
+ TREE_VALUE (attr)) == 1)
+ break;
+ }
+ else if (simple_cst_equal (TREE_VALUE (a), TREE_VALUE (attr)) ==
1)
+ break;
+ }
Once we've walked the first list, we don't need to compare the values of
common attributes again; for each attribute in the second list either it
does appear in the first list and we've already established that they match,
or it doesn't appear in the first list and we're done.
Yes
Updated patch attached. Ok for apply to trunk?
Regards,
Kai
--
| (\_/) This is Bunny. Copy and paste
| (='.'=) Bunny into your signature to help
| ()_() him gain world domination
Index: gcc/gcc/c-typeck.c
===
--- gcc.orig/gcc/c-typeck.c 2011-03-24 08:23:42.441173500 +0100
+++ gcc/gcc/c-typeck.c 2011-03-24 09:24:53.445892300 +0100
@@ -1079,7 +1079,7 @@ comptypes_internal (const_tree type1, co
return 1;
/* 1 if no need for warning yet, 2 if warning cause has been seen. */
- if (!(attrval = targetm.comp_type_attributes (t1, t2)))
+ if (!(attrval = comp_type_attributes (t1, t2)))
return 0;
/* 1 if no need for warning yet, 2 if warning cause has been seen. */
Index: gcc/gcc/cp/decl.c
===
--- gcc.orig/gcc/cp/decl.c 2011-03-24 08:23:42.443173500 +0100
+++ gcc/gcc/cp/decl.c 2011-03-24 09:24:53.573408500 +0100
@@ -1012,8 +1012,8 @@ decls_match (tree newdecl, tree olddecl)
types_match =
compparms (p1, p2)
(TYPE_ATTRIBUTES (TREE_TYPE (newdecl)) == NULL_TREE
- || targetm.comp_type_attributes (TREE_TYPE (newdecl),
- TREE_TYPE (olddecl)) != 0);
+ || comp_type_attributes (TREE_TYPE (newdecl),
+ TREE_TYPE (olddecl)) != 0);
}
else
types_match = 0;
Index: gcc/gcc/cp/search.c
===
--- gcc.orig/gcc/cp/search.c2011-03-24 08:23:42.444173500 +0100
+++ gcc/gcc/cp/search.c 2011-03-24 09:24:53.645417600 +0100
@@ -1897,7 +1897,7 @@ check_final_overrider (tree overrider, t
}
/* Check for conflicting type attributes. */
- if (!targetm.comp_type_attributes (over_type, base_type))
+ if (!comp_type_attributes (over_type, base_type))
{
error (conflicting type attributes specified for %q+#D, overrider);
error ( overriding %q+#D, basefn);
Index: gcc/gcc/cp/typeck.c
===
--- gcc.orig/gcc/cp/typeck.c2011-03-24 08:23:42.495173500 +0100
+++ gcc/gcc/cp/typeck.c 2011-03-24 09:24:53.697424200 +0100
@@ -1338,7 +1338,7 @@ structural_comptypes (tree t1, tree t2,
/* If we get here, we know that from a target independent POV the
types are the same. Make sure the target attributes are also
the same. */
- return targetm.comp_type_attributes (t1, t2);
+ return comp_type_attributes (t1, t2);
}
/* Return true if T1 and T2 are related as allowed by STRICT. STRICT
Index: gcc/gcc/gimple.c
===
--- gcc.orig/gcc/gimple.c 2011-03-24 08:23:42.496173500 +0100
+++ gcc/gcc/gimple.c2011-03-24 09:24:53.793936500 +0100
@@ -3615,7 +3615,7 @@ gimple_types_compatible_p_1 (tree t1, tr
state, sccstack, sccstate, sccstate_obstack))
goto different_types;
- if (!targetm.comp_type_attributes (t1, t2))
+ if (!comp_type_attributes (t1, t2))
goto different_types;
if (TYPE_ARG_TYPES (t1)
Re: [PATCH 3/6] Allow jumps in epilogues
On 03/23/2011 06:27 PM, Richard Henderson wrote: On 03/23/2011 10:22 AM, Bernd Schmidt wrote: On 03/23/2011 06:19 PM, Richard Henderson wrote: body body restore r1 XXX restore r2 XXX jmp L2 XXX L1: bodyYYY bodyYYY restore r2 L2: restore r3 return In general, with shrink-wrapping, we can have essentially arbitrary differences in unwind info between blocks that are sequential. I don't think this can actually happen with the current implementation. There is only one prologue, and all epilogues (the normal one and the sibcall epilogues) match it exactly. I don't believe we can generate code as in the example above, both before and after my patch. Um.. then what's this allow jumps in epilogues thing of which you speak? If there's a jump, then it goes somewhere, and branches over something. I see no constraints on what that something might be. Could you give an example of a transformation that is allowed by this? The idea was to be able to share a single return instruction between epilogue/non-epilogue return paths, so that e.g. on i686 a conditional return could be implemented as a conditional jump to a common return insn. The allow-jumps patch then becomes necessary because bbro can move the blocks around. It does seem, however, that bbro can in fact cause problems for the unwind information when the prologue is no longer in the first block. Let me try to come up with a solution for that. Bernd
[Patch] New bfin divsi/udivsi implementations
The attached patch updates the blackfin ___divsi3 and ___udivsi3 implementations (and updates ___umodsi3 to match), as well as adding .size directives to all functions in the file. 2011-03-24 Stuart Henderson stuart.hender...@analog.com * gcc/config/bfin/lib1funcs.asm (___divsi3): New implementation, add .size directive and unguard .text directive. (___udivsi3): New implementation and add .size directive. (___umodsi3): Update to match new ___divsi3/___udivsi3 implementations and add .size directive. (___modsi3): Add .size directive. (___umulsi3_highpart): Likewise. (___smulsi3_highpart): Likewise. I don't have write permissions. Thanks, Stu upstream.patch Description: upstream.patch
[PATCH] Fix PR 48144
Hello,
As noted in the PR audit trail, this is a case when we fail to find a
transformed insn due to incomplete transformation history attached to it.
The earlier fixes of this issue worked only for bookkeeping copies, but now
we need a more general mechanism. Fixed by simply picking up additional
transformation history from the av sets of basic blocks on the way. The
problem can only happen on the bookkeeping blocks which have somewhat newer
av sets available.
Bootstrapping and testing on x86-64 and ia64 is in progress, ok if it succeeds?
Andrey
2011-03-24 Andrey Belevantsev a...@ispras.ru
gcc/
PR rtl-optimization/48144
* sel-sched-ir.c (merge_history_vect): Factor out from ...
(merge_expr_data): ... here.
(av_set_intersect): Rename to av_set_code_motion_filter.
Update all callers. Call merge_history_vect when an expression
is found in both sets.
* sel-sched-ir.h (av_set_code_motion_filter): Add prototype.
gcc/testsuite
PR rtl-optimization/48144
* gcc.dg/pr48144.c: New test.
diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c
index b88dad1..61f3ffb 100644
--- a/gcc/sel-sched-ir.c
+++ b/gcc/sel-sched-ir.c
@@ -1564,6 +1564,20 @@ free_history_vect (VEC (expr_history_def, heap) **pvect)
*pvect = NULL;
}
+/* Merge vector FROM to PVECT. */
+static void
+merge_history_vect (VEC (expr_history_def, heap) **pvect,
+ VEC (expr_history_def, heap) *from)
+{
+ expr_history_def *phist;
+ int i;
+
+ /* We keep this vector sorted. */
+ for (i = 0; VEC_iterate (expr_history_def, from, i, phist); i++)
+insert_in_history_vect (pvect, phist-uid, phist-type,
+phist-old_expr_vinsn, phist-new_expr_vinsn,
+phist-spec_ds);
+}
/* Compare two vinsns as rhses if possible and as vinsns otherwise. */
bool
@@ -1796,9 +1810,6 @@ update_speculative_bits (expr_t to, expr_t from, insn_t split_point)
void
merge_expr_data (expr_t to, expr_t from, insn_t split_point)
{
- int i;
- expr_history_def *phist;
-
/* For now, we just set the spec of resulting expr to be minimum of the specs
of merged exprs. */
if (EXPR_SPEC (to) EXPR_SPEC (from))
@@ -1822,20 +1833,12 @@ merge_expr_data (expr_t to, expr_t from, insn_t split_point)
EXPR_ORIG_SCHED_CYCLE (to) = MIN (EXPR_ORIG_SCHED_CYCLE (to),
EXPR_ORIG_SCHED_CYCLE (from));
- /* We keep this vector sorted. */
- for (i = 0;
- VEC_iterate (expr_history_def, EXPR_HISTORY_OF_CHANGES (from),
-i, phist);
- i++)
-insert_in_history_vect (EXPR_HISTORY_OF_CHANGES (to),
-phist-uid, phist-type,
-phist-old_expr_vinsn, phist-new_expr_vinsn,
-phist-spec_ds);
-
EXPR_WAS_SUBSTITUTED (to) |= EXPR_WAS_SUBSTITUTED (from);
EXPR_WAS_RENAMED (to) |= EXPR_WAS_RENAMED (from);
EXPR_CANT_MOVE (to) |= EXPR_CANT_MOVE (from);
+ merge_history_vect (EXPR_HISTORY_OF_CHANGES (to),
+ EXPR_HISTORY_OF_CHANGES (from));
update_target_availability (to, from, split_point);
update_speculative_bits (to, from, split_point);
}
@@ -2328,16 +2331,24 @@ av_set_split_usefulness (av_set_t av, int prob, int all_prob)
}
/* Leave in AVP only those expressions, which are present in AV,
- and return it. */
+ and return it, merging history expressions. */
void
-av_set_intersect (av_set_t *avp, av_set_t av)
+av_set_code_motion_filter (av_set_t *avp, av_set_t av)
{
av_set_iterator i;
- expr_t expr;
+ expr_t expr, expr2;
FOR_EACH_EXPR_1 (expr, i, avp)
-if (av_set_lookup (av, EXPR_VINSN (expr)) == NULL)
+if ((expr2 = av_set_lookup (av, EXPR_VINSN (expr))) == NULL)
av_set_iter_remove (i);
+else
+ /* When updating av sets in bookkeeping blocks, we can add more insns
+ there which will be transformed but the upper av sets will not
+ reflect those transformations. We then fail to undo those
+ when searching for such insns. So merge the history saved
+ in the av set of the block we are processing. */
+ merge_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
+ EXPR_HISTORY_OF_CHANGES (expr2));
}
diff --git a/gcc/sel-sched-ir.h b/gcc/sel-sched-ir.h
index 1f3dec4..5516da9 100644
--- a/gcc/sel-sched-ir.h
+++ b/gcc/sel-sched-ir.h
@@ -1565,7 +1565,7 @@ extern void av_set_leave_one_nonspec (av_set_t *);
extern expr_t av_set_element (av_set_t, int);
extern void av_set_substract_cond_branches (av_set_t *);
extern void av_set_split_usefulness (av_set_t, int, int);
-extern void av_set_intersect (av_set_t *, av_set_t);
+extern void av_set_code_motion_filter (av_set_t *, av_set_t);
extern void sel_save_haifa_priorities (void);
diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index e26ddac..9179249 100644
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -6481,7 +6481,7 @@ code_motion_path_driver (insn_t insn,
Re: [patch, ARM] Fix PR48250, adjust DImode reload address legitimizing
On Thu, 2011-03-24 at 12:56 +0900, Chung-Lin Tang wrote:
Hi,
PR48250 happens under TARGET_NEON, where DImode is included within the
valid NEON modes. This turns the range of legitimate constant indexes to
step-4 (coproc load/store), thus arm_legitimize_reload_address() when
trying to decompose the [reg+index] reload address into
[(reg+index_high)+index_low], can cause an ICE later when 'index_low'
part is not aligned to 4.
I'm not sure why the current DImode index is computed as:
low = ((val 0xf) ^ 0x8) - 0x8; the sign-extending into negative
values, then subtracting back, actually creates further off indexes.
e.g. in the supplied testcase, [sp+13] was turned into [(sp+16)-3].
Hysterical Raisins... the code there was clearly written for the days
before we had LDRD in the architecture. At that time the most efficient
way to load a 64-bit object was to use the LDM{ia,ib,da,db}
instructions. The computation here was (I think), intended to try and
make the most efficient use of an add/sub instruction followed by
LDM/STM offsetting. At that time the architecture had no unaligned
access either, so dealing with 64-bit that were less than 32-bit aligned
(in those days 32-bit was the maximum alignment) probably wasn't
considered, or couldn't even get through to reload.
My patch changes the index decomposing to a more straightforward way; it
also sort of outlines the way the other reload address indexes are
broken by using and-masks, is not the most effective. The address is
computed by addition, subtracting away the parts to obtain low+high
should be the optimal way of giving the largest computable index range.
I have included a few Thumb-2 bits in the patch; I know currently
arm_legitimize_reload_address() is only used under TARGET_ARM, but I
guess it might eventually be turned into TARGET_32BIT.
I think this needs to be looked at carefully on ARMv4/ARMv4T to check
that it doesn't cause regressions there when we don't have LDRD in the
instruction set.
Cross-tested on QEMU without regressions, is this okay?
Thanks,
Chung-Lin
2011-03-24 Chung-Lin Tang clt...@codesourcery.com
PR target/48250
* config/arm/arm.c (arm_legitimize_reload_address): Adjust
DImode constant index decomposing. Mask out lower 2-bits for
NEON and Thumb-2.
testsuite/
* gcc.target/arm/pr48250.c: New.
R.
Re: [patch] Fix PR48183, NEON ICE in emit-rtl.c:immed_double_const() under -g
Chung-Lin Tang clt...@codesourcery.com writes:
PR48183 is a case where ARM NEON instrinsics, under -O -g, produce debug
insns that tries to expand OImode (32-byte integer) zero constants, much
too large to represent as two HOST_WIDE_INTs; as the internals manual
indicates, such large constants are not supported in general, and ICEs
on the GET_MODE_BITSIZE(mode) == 2*HOST_BITS_PER_WIDE_INT assertion.
This patch allows the cases where the large integer constant is still
representable using a single CONST_INT, such as zero(0). Bootstrapped
and tested on i686 and x86_64, cross-tested on ARM, all without
regressions. Okay for trunk?
Thanks,
Chung-Lin
2011-03-20 Chung-Lin Tang clt...@codesourcery.com
* emit-rtl.c (immed_double_const): Allow wider than
2*HOST_BITS_PER_WIDE_INT mode constants when they are
representable as a single const_int RTX.
I realise this might be seen as a good expedient fix, but it makes
me a bit uneasy. Not a very constructive rationale, sorry.
For this particular case, the problem is that vst2q_s32 and the
like initialise a union directly:
union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b; };
and this gets translated into a zeroing of the whole union followed
by an assignment to __i:
__bu = {};
__bu.__i = __b;
We later optimise away the first assignment, but it still exists
in the debug info.
Another expedient fix might be to replace these initialisations with:
union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu;
__bu.__i = __b;
so that we never get a zeroing statement.
I realise both fixes are papering over the real problem. What we really
need is arbitrary-length constant integers, like we already have for vectors.
But that's going to be a much bigger patch. It just seems to me that,
if we're going for a work-around, the arm_neon.h change is neutral,
while changing immed_double_const feels more risky.
Richard
Re: [patch, ARM] Enable auto-detection of vector size for NEON
On 24 March 2011 13:03, Joseph S. Myers jos...@codesourcery.com wrote: On Thu, 24 Mar 2011, Ira Rosen wrote: Hi, This patch implements TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES for ARM NEON. Given the multiple vector sizes support, is there a reason not to enable -mvectorize-with-neon-quad by default? I don't see any reason, and I am going to submit a follow-up patch that does that. Ira -- Joseph S. Myers jos...@codesourcery.com
Update config.sub
I've updated config.sub to the latest version from config.git. This will facilitate further cleanups by ensuring that certain obsolete triplets can never appear as canonical hosts or targets in gcc or src builds. Index: ChangeLog === --- ChangeLog (revision 171384) +++ ChangeLog (working copy) @@ -1,3 +1,7 @@ +2011-03-24 Joseph Myers jos...@codesourcery.com + + * config.sub: Update to version 2011-03-23. + 2011-03-22 Joseph Myers jos...@codesourcery.com * configure.ac (arm-semi-aof, crx-*-*, parisc*-*-linux*, Index: config.sub === --- config.sub (revision 171384) +++ config.sub (working copy) @@ -4,7 +4,7 @@ # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, # 2011 Free Software Foundation, Inc. -timestamp='2011-02-24' +timestamp='2011-03-23' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software @@ -288,7 +288,7 @@ | ns16k | ns32k \ | or32 \ | pdp10 | pdp11 | pj | pjl \ - | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ + | powerpc | powerpc64 | powerpc64le | powerpcle \ | pyramid \ | rx \ | score \ @@ -296,12 +296,12 @@ | sh64 | sh64le \ | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ - | spu | strongarm \ - | tahoe | thumb | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ + | spu \ + | tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ | ubicom32 \ | v850 | v850e \ | we32k \ - | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ + | x86 | xc16x | xstormy16 | xtensa \ | z8k | z80) basic_machine=$basic_machine-unknown ;; @@ -325,6 +325,18 @@ basic_machine=mt-unknown ;; + strongarm | thumb | xscale) + basic_machine=arm-unknown + ;; + + xscaleeb) + basic_machine=armeb-unknown + ;; + + xscaleel) + basic_machine=armel-unknown + ;; + # We use `pc' rather than `unknown' # because (1) that's what they normally are, and # (2) the word unknown tends to confuse beginning users. @@ -384,22 +396,22 @@ | none-* | np1-* | ns16k-* | ns32k-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ - | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ | pyramid-* \ | romp-* | rs6000-* | rx-* \ | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ | sparclite-* \ - | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \ - | tahoe-* | thumb-* \ + | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \ + | tahoe-* \ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ | tile-* | tilegx-* \ | tron-* \ | ubicom32-* \ | v850-* | v850e-* | vax-* \ | we32k-* \ - | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ + | x86-* | x86_64-* | xc16x-* | xps100-* \ | xstormy16-* | xtensa*-* \ | ymp-* \ | z8k-* | z80-*) @@ -950,9 +962,10 @@ ;; power) basic_machine=power-ibm ;; - ppc)basic_machine=powerpc-unknown + ppc | ppcbe)basic_machine=powerpc-unknown ;; - ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ppc-* | ppcbe-*) + basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown @@ -1046,6 +1059,9 @@ basic_machine=i860-stratus os=-sysv4 ;; + strongarm-* | thumb-*) + basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; sun2) basic_machine=m68000-sun ;; @@ -1178,6 +1194,9 @@ xps | xps100) basic_machine=xps100-honeywell ;; + xscale-* | xscalee[bl]-*) + basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'` + ;; ymp) basic_machine=ymp-cray os=-unicos -- Joseph S. Myers jos...@codesourcery.com
Remove dead cases from toplevel configure.ac
This patch removes various dead cases from the toplevel configure.ac.
Target ep9312-* isn't known to config.sub at all so those cases have
been dead for a long time; likewise parisc*64*-* (those parisc cases
it does know have also been handled by config.sub as aliases for
hppa-* for a long time). With my recent config.sub changes,
strongarm-*, xscale*-*, thumb-* and ppc*-* will always be converted by
config.sub to arm*-* or powerpc*-* when accepted at all (most ppc*-*
cases were already so converted before my changes). OK to commit?
2011-03-24 Joseph Myers jos...@codesourcery.com
* configure.ac (ppc*-*-pe): Remove host case.
(strongarm-*-coff | xscale-*-coff, strongarm-*-elf* |
xscale-*-elf*, thumb-*-coff, thumb-*-elf, thumb-*-pe, ep9312-*-elf
| ep9312-*-coff, parisc*64*-*-linux*, ppc*-*-pe): Remove target
cases.
* configure: Regenerate.
Index: configure.ac
===
--- configure.ac(revision 171384)
+++ configure.ac(working copy)
@@ -451,9 +451,6 @@
*-*-netbsd*)
noconfigdirs=$noconfigdirs rcs
;;
- ppc*-*-pe)
-noconfigdirs=$noconfigdirs patch diff make tk tcl expect dejagnu autoconf
automake texinfo bison send-pr gprof rcs guile perl itcl gnuserv
-;;
powerpc-*-beos*)
noconfigdirs=$noconfigdirs tk itcl libgui gdb dejagnu readline
;;
@@ -672,11 +669,11 @@
arc-*-*)
noconfigdirs=$noconfigdirs target-libgloss
;;
- arm-*-coff | strongarm-*-coff | xscale-*-coff)
+ arm-*-coff)
noconfigdirs=$noconfigdirs ${libgcj}
libgloss_dir=arm
;;
- arm-*-elf* | strongarm-*-elf* | xscale-*-elf* | arm*-*-eabi* )
+ arm-*-elf* | arm*-*-eabi* )
noconfigdirs=$noconfigdirs target-libffi target-qthreads
libgloss_dir=arm
;;
@@ -694,15 +691,6 @@
arm-*-pe*)
noconfigdirs=$noconfigdirs target-libgloss ${libgcj}
;;
- thumb-*-coff)
-noconfigdirs=$noconfigdirs target-libgloss ${libgcj}
-;;
- thumb-*-elf)
-noconfigdirs=$noconfigdirs target-libgloss ${libgcj}
-;;
- thumb-*-pe)
-noconfigdirs=$noconfigdirs target-libgloss ${libgcj}
-;;
arm-*-riscix*)
noconfigdirs=$noconfigdirs ld target-libgloss ${libgcj}
;;
@@ -747,9 +735,6 @@
d30v-*-*)
noconfigdirs=$noconfigdirs ${libgcj} gdb
;;
- ep9312-*-elf | ep9312-*-coff)
-libgloss_dir=arm
-;;
fr30-*-elf*)
noconfigdirs=$noconfigdirs ${libgcj} gdb
;;
@@ -768,7 +753,7 @@
;;
hppa1.1-*-osf* | hppa1.1-*-bsd* )
;;
- hppa*64*-*-linux* | parisc*64*-*-linux*)
+ hppa*64*-*-linux*)
# In this case, it's because the hppa64-linux target is for
# the kernel only at this point and has no libc, and thus no
# headers, crt*.o, etc., all of which are needed by these.
@@ -912,7 +897,7 @@
# copied from rs6000-*-* entry
noconfigdirs=$noconfigdirs gprof target-libgloss target-libssp
target-newlib ${libgcj}
;;
- powerpc*-*-winnt* | powerpc*-*-pe* | ppc*-*-pe)
+ powerpc*-*-winnt* | powerpc*-*-pe*)
target_configdirs=$target_configdirs target-winsup
noconfigdirs=$noconfigdirs gdb tcl tk make expect target-libgloss itcl
gnuserv ${libgcj}
# always build newlib.
--
Joseph S. Myers
jos...@codesourcery.com
[PATCH] use cfglayout mode for instatiate_virtual_regs
As $SUBJECT suggests. The patch looks much bigger than it actually is
due to re-indentation.
Tested on x86_64-unknown-linux-gnu. OK to commit?
-Nathan
* function.c (instantiate_virtual_regs): Use FOR_EACH_BB and
FOR_BB_INSNS_SAFE to iterate through insns. Re-indent.
* passes.c (init_optimization_passes): Move
pass_instantiate_virtual_regs after pass_into_cfg_layout_mode.
diff --git a/gcc/function.c b/gcc/function.c
index a1ea482..49404c8 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -1883,7 +1883,7 @@ instantiate_decls (tree fndecl)
static unsigned int
instantiate_virtual_regs (void)
{
- rtx insn;
+ basic_block bb;
/* Compute the offsets to use for this function. */
in_arg_offset = FIRST_PARM_OFFSET (current_function_decl);
@@ -1901,33 +1901,40 @@ instantiate_virtual_regs (void)
/* Scan through all the insns, instantiating every virtual register still
present. */
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-if (INSN_P (insn))
- {
- /* These patterns in the instruction stream can never be recognized.
- Fortunately, they shouldn't contain virtual registers either. */
- if (GET_CODE (PATTERN (insn)) == USE
- || GET_CODE (PATTERN (insn)) == CLOBBER
- || GET_CODE (PATTERN (insn)) == ADDR_VEC
- || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
- || GET_CODE (PATTERN (insn)) == ASM_INPUT)
- continue;
- else if (DEBUG_INSN_P (insn))
- for_each_rtx (INSN_VAR_LOCATION (insn),
- instantiate_virtual_regs_in_rtx, NULL);
- else
- instantiate_virtual_regs_in_insn (insn);
+ FOR_EACH_BB (bb)
+{
+ rtx insn, curr;
- if (INSN_DELETED_P (insn))
- continue;
+ FOR_BB_INSNS_SAFE (bb, insn, curr)
+ {
+ if (INSN_P (insn))
+ {
+ /* These patterns in the instruction stream can never be
recognized.
+Fortunately, they shouldn't contain virtual registers either.
*/
+ if (GET_CODE (PATTERN (insn)) == USE
+ || GET_CODE (PATTERN (insn)) == CLOBBER
+ || GET_CODE (PATTERN (insn)) == ADDR_VEC
+ || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
+ || GET_CODE (PATTERN (insn)) == ASM_INPUT)
+ continue;
+ else if (DEBUG_INSN_P (insn))
+ for_each_rtx (INSN_VAR_LOCATION (insn),
+ instantiate_virtual_regs_in_rtx, NULL);
+ else
+ instantiate_virtual_regs_in_insn (insn);
- for_each_rtx (REG_NOTES (insn), instantiate_virtual_regs_in_rtx, NULL);
+ if (INSN_DELETED_P (insn))
+ continue;
- /* Instantiate any virtual registers in CALL_INSN_FUNCTION_USAGE. */
- if (CALL_P (insn))
- for_each_rtx (CALL_INSN_FUNCTION_USAGE (insn),
- instantiate_virtual_regs_in_rtx, NULL);
- }
+ for_each_rtx (REG_NOTES (insn), instantiate_virtual_regs_in_rtx,
NULL);
+
+ /* Instantiate any virtual registers in CALL_INSN_FUNCTION_USAGE.
*/
+ if (CALL_P (insn))
+ for_each_rtx (CALL_INSN_FUNCTION_USAGE (insn),
+ instantiate_virtual_regs_in_rtx, NULL);
+ }
+ }
+}
/* Instantiate the virtual registers in the DECLs for debugging purposes. */
instantiate_decls (current_function_decl);
@@ -1963,7 +1970,7 @@ struct rtl_opt_pass pass_instantiate_virtual_regs =
NULL, /* next */
0,/* static_pass_number */
TV_NONE, /* tv_id */
- 0,/* properties_required */
+ PROP_cfglayout, /* properties_required */
0,/* properties_provided */
0,/* properties_destroyed */
0,/* todo_flags_start */
diff --git a/gcc/passes.c b/gcc/passes.c
index 42a3239..3353557 100644
--- a/gcc/passes.c
+++ b/gcc/passes.c
@@ -956,8 +956,8 @@ init_optimization_passes (void)
NEXT_PASS (pass_rtl_eh);
NEXT_PASS (pass_initial_value_sets);
NEXT_PASS (pass_unshare_all_rtl);
- NEXT_PASS (pass_instantiate_virtual_regs);
NEXT_PASS (pass_into_cfg_layout_mode);
+ NEXT_PASS (pass_instantiate_virtual_regs);
NEXT_PASS (pass_jump2);
NEXT_PASS (pass_lower_subreg);
NEXT_PASS (pass_df_initialize_opt);
Re: [patch middle-end c c++]: Optimize cost of comp_type_attributes
On 03/24/2011 11:56 AM, Kai Tietz wrote:
+ if (TREE_VALUE (a) != NULL_TREE
+ TREE_CODE (TREE_VALUE (a)) == TREE_LIST
+ TREE_VALUE (attr) != NULL
+ TREE_CODE (TREE_VALUE (attr)) == TREE_LIST)
+ {
+ if (simple_cst_list_equal (TREE_VALUE (a),
+TREE_VALUE (attr)) == 1)
+ break;
+ }
+ else if (simple_cst_equal (TREE_VALUE (a), TREE_VALUE (attr)) == 1)
How about splitting this out into a separate function that can compare
either list or expression arguments? That would also be useful for
merge_attributes and attribute_list_contained.
Jason
Re: Cleaning up expand optabs code
Andreas Krebbel kreb...@linux.vnet.ibm.com writes:
On 03/22/2011 06:48 PM, Richard Henderson wrote:
Ok. Watch out for other target problems this week.
This unfortunately broke bootstrap on s390.
This is PR 48263. Since it seems to be affecting several targets,
and since my bootstrap seems to be taking a looong time, I'll post
the patch here before testing has finished.
Just copying the pre-patch behaviour fixes the problem for me:
I think we need to undo more of the patch, and leave the conversion
outside of the new interface.
Sorry for the breakage.
Richard
gcc/
PR rtl-optimization/48263
* optabs.c (expand_binop_directly): Reinstate convert_modes code
and original commutative_p handling. Use maybe_gen_insn.
Index: gcc/optabs.c
===
--- gcc/optabs.c2011-03-24 09:18:00.0 +
+++ gcc/optabs.c2011-03-24 09:36:46.0 +
@@ -1269,6 +1269,38 @@ expand_binop_directly (enum machine_mode
if (!shift_optab_p (binoptab))
xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp);
+ /* In case the insn wants input operands in modes different from
+ those of the actual operands, convert the operands. It would
+ seem that we don't need to convert CONST_INTs, but we do, so
+ that they're properly zero-extended, sign-extended or truncated
+ for their mode. */
+
+ if (GET_MODE (xop0) != mode0 mode0 != VOIDmode)
+xop0 = convert_modes (mode0,
+ GET_MODE (xop0) != VOIDmode
+ ? GET_MODE (xop0)
+ : mode,
+ xop0, unsignedp);
+
+ if (GET_MODE (xop1) != mode1 mode1 != VOIDmode)
+xop1 = convert_modes (mode1,
+ GET_MODE (xop1) != VOIDmode
+ ? GET_MODE (xop1)
+ : mode,
+ xop1, unsignedp);
+
+ /* If operation is commutative,
+ try to make the first operand a register.
+ Even better, try to make it the same as the target.
+ Also try to make the last operand a constant. */
+ if (commutative_p
+ swap_commutative_operands_with_target (target, xop0, xop1))
+{
+ swap = xop1;
+ xop1 = xop0;
+ xop0 = swap;
+}
+
/* Now, if insn's predicates don't allow our operands, put them into
pseudo regs. */
@@ -1291,41 +1323,25 @@ expand_binop_directly (enum machine_mode
tmp_mode = mode;
create_output_operand (ops[0], target, tmp_mode);
- create_convert_operand_from (ops[1], xop0, mode, unsignedp);
- create_convert_operand_from (ops[2], xop1, mode, unsignedp);
- if (maybe_legitimize_operands (icode, 0, 3, ops))
-{
- /* If operation is commutative,
-try to make the first operand a register.
-Even better, try to make it the same as the target.
-Also try to make the last operand a constant. */
- if (commutative_p
- swap_commutative_operands_with_target (ops[0].value, ops[1].value,
- ops[2].value))
- {
- swap = ops[2].value;
- ops[2].value = ops[1].value;
- ops[1].value = swap;
- }
-
- pat = GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value);
- if (pat)
+ create_input_operand (ops[1], xop0, mode0);
+ create_input_operand (ops[2], xop1, mode1);
+ pat = maybe_gen_insn (icode, 3, ops);
+ if (pat)
+{
+ /* If PAT is composed of more than one insn, try to add an appropriate
+REG_EQUAL note to it. If we can't because TEMP conflicts with an
+operand, call expand_binop again, this time without a target. */
+ if (INSN_P (pat) NEXT_INSN (pat) != NULL_RTX
+ ! add_equal_note (pat, ops[0].value, binoptab-code,
+ ops[1].value, ops[2].value))
{
- /* If PAT is composed of more than one insn, try to add an appropriate
-REG_EQUAL note to it. If we can't because TEMP conflicts with an
-operand, call expand_binop again, this time without a target. */
- if (INSN_P (pat) NEXT_INSN (pat) != NULL_RTX
- ! add_equal_note (pat, ops[0].value, binoptab-code,
- ops[1].value, ops[2].value))
- {
- delete_insns_since (last);
- return expand_binop (mode, binoptab, op0, op1, NULL_RTX,
- unsignedp, methods);
- }
-
- emit_insn (pat);
- return ops[0].value;
+ delete_insns_since (last);
+ return expand_binop (mode, binoptab, op0, op1, NULL_RTX,
+ unsignedp, methods);
}
+
+ emit_insn (pat);
+ return ops[0].value;
}
delete_insns_since (last);
return NULL_RTX;
Re: [patch] Enhance conditional store sinking
On Thu, Mar 24, 2011 at 11:03 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Tue, Mar 22, 2011 at 6:28 AM, Ira Rosen ira.ro...@linaro.org wrote:
On 17 March 2011 16:48, Richard Guenther richard.guent...@gmail.com wrote:
+ then_datarefs = VEC_alloc (data_reference_p, heap, 1);
+ else_datarefs = VEC_alloc (data_reference_p, heap, 1);
+ then_ddrs = VEC_alloc (ddr_p, heap, 1);
+ else_ddrs = VEC_alloc (ddr_p, heap, 1);
+ if (!compute_data_dependences_for_bb (then_bb, false, then_datarefs,
+ then_ddrs)
Can we avoid computing dependencies if the other BB would have no
data-refs? Thus, split collecting datarefs and computing dependences?
Done.
+ || !compute_data_dependences_for_bb (else_bb, false, else_datarefs,
+ else_ddrs)
+ || !VEC_length (data_reference_p, then_datarefs)
+ || !VEC_length (data_reference_p, else_datarefs))
+ {
+ free_data_refs (then_datarefs);
+ free_data_refs (else_datarefs);
+ free_dependence_relations (then_ddrs);
+ free_dependence_relations (else_ddrs);
+ return false;
+ }
+
+ /* Check that there are no read-after-write or write-after-write
dependencies
+ in THEN_BB. */
+ FOR_EACH_VEC_ELT (ddr_p, then_ddrs, i, ddr)
+ {
+ struct data_reference *dra = DDR_A (ddr);
+ struct data_reference *drb = DDR_B (ddr);
+
+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
+ ((DR_IS_READ (dra) DR_IS_WRITE (drb)
+ gimple_uid (DR_STMT (dra)) gimple_uid (DR_STMT (drb)))
+ || (DR_IS_READ (drb) DR_IS_WRITE (dra)
+ gimple_uid (DR_STMT (drb)) gimple_uid (DR_STMT
(dra)))
+ || (DR_IS_WRITE (dra) DR_IS_WRITE (drb
The gimple_uids are not initialized here, you need to make sure to
call renumber_gimple_stmt_uids () before starting. Note that phiopt
incrementally changes the IL, so I'm not sure those uids will stay
valid as stmts are moved across blocks.
I added a call to renumber_gimple_stmt_uids_in_blocks() before data
dependence checks, and there are no code changes between that and the
checks, so, I think, it should be OK.
+ {
+ free_data_refs (then_datarefs);
+ free_data_refs (else_datarefs);
+ free_dependence_relations (then_ddrs);
+ free_dependence_relations (else_ddrs);
+ return false;
+ }
+ }
+
+ /* Check that there are no read-after-write or write-after-write
dependencies
+ in ELSE_BB. */
+ FOR_EACH_VEC_ELT (ddr_p, else_ddrs, i, ddr)
+ {
+ struct data_reference *dra = DDR_A (ddr);
+ struct data_reference *drb = DDR_B (ddr);
+
+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
+ ((DR_IS_READ (dra) DR_IS_WRITE (drb)
+ gimple_uid (DR_STMT (dra)) gimple_uid (DR_STMT (drb)))
+ || (DR_IS_READ (drb) DR_IS_WRITE (dra)
+ gimple_uid (DR_STMT (drb)) gimple_uid (DR_STMT
(dra)))
+ || (DR_IS_WRITE (dra) DR_IS_WRITE (drb
+ {
+ free_data_refs (then_datarefs);
+ free_data_refs (else_datarefs);
+ free_dependence_relations (then_ddrs);
+ free_dependence_relations (else_ddrs);
+ return false;
+ }
+ }
+
+ /* Found pairs of stores with equal LHS. */
+ FOR_EACH_VEC_ELT (data_reference_p, then_datarefs, i, then_dr)
+ {
+ if (DR_IS_READ (then_dr))
+ continue;
+
+ then_store = DR_STMT (then_dr);
+ then_lhs = gimple_assign_lhs (then_store);
+ found = false;
+
+ FOR_EACH_VEC_ELT (data_reference_p, else_datarefs, j, else_dr)
+ {
+ if (DR_IS_READ (else_dr))
+ continue;
+
+ else_store = DR_STMT (else_dr);
+ else_lhs = gimple_assign_lhs (else_store);
+
+ if (operand_equal_p (then_lhs, else_lhs, 0))
+ {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found)
+ continue;
+
+ res = cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
+ then_store, else_store);
So you are executing if-else store replacement for common data reference
pairs only. I think it's cheaper to collect those pairs before computing
dependences and only if there is at least one pair perform the optimization.
OK, I changed the order.
You basically perform store sinking, creating a PHI node for each store
you sink (that's then probably if-converted by if-conversion later,
eventually
redundant with -ftree-loop-if-convert-stores?)
I am concerned that having no bound on the number of stores sunk will
increase register pressure and does not allow scheduling of the stores
in an optimal way. Consider two BBs similar to
t = a + b;
*p = t;
t = c + d;
*q = t;
where the transformation undoes
Re: [patch] Enhance conditional store sinking
On Thu, Mar 24, 2011 at 1:39 PM, Richard Guenther
richard.guent...@gmail.com wrote:
On Thu, Mar 24, 2011 at 11:03 AM, H.J. Lu hjl.to...@gmail.com wrote:
On Tue, Mar 22, 2011 at 6:28 AM, Ira Rosen ira.ro...@linaro.org wrote:
On 17 March 2011 16:48, Richard Guenther richard.guent...@gmail.com wrote:
+ then_datarefs = VEC_alloc (data_reference_p, heap, 1);
+ else_datarefs = VEC_alloc (data_reference_p, heap, 1);
+ then_ddrs = VEC_alloc (ddr_p, heap, 1);
+ else_ddrs = VEC_alloc (ddr_p, heap, 1);
+ if (!compute_data_dependences_for_bb (then_bb, false, then_datarefs,
+ then_ddrs)
Can we avoid computing dependencies if the other BB would have no
data-refs? Thus, split collecting datarefs and computing dependences?
Done.
+ || !compute_data_dependences_for_bb (else_bb, false,
else_datarefs,
+ else_ddrs)
+ || !VEC_length (data_reference_p, then_datarefs)
+ || !VEC_length (data_reference_p, else_datarefs))
+ {
+ free_data_refs (then_datarefs);
+ free_data_refs (else_datarefs);
+ free_dependence_relations (then_ddrs);
+ free_dependence_relations (else_ddrs);
+ return false;
+ }
+
+ /* Check that there are no read-after-write or write-after-write
dependencies
+ in THEN_BB. */
+ FOR_EACH_VEC_ELT (ddr_p, then_ddrs, i, ddr)
+ {
+ struct data_reference *dra = DDR_A (ddr);
+ struct data_reference *drb = DDR_B (ddr);
+
+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
+ ((DR_IS_READ (dra) DR_IS_WRITE (drb)
+ gimple_uid (DR_STMT (dra)) gimple_uid (DR_STMT
(drb)))
+ || (DR_IS_READ (drb) DR_IS_WRITE (dra)
+ gimple_uid (DR_STMT (drb)) gimple_uid (DR_STMT
(dra)))
+ || (DR_IS_WRITE (dra) DR_IS_WRITE (drb
The gimple_uids are not initialized here, you need to make sure to
call renumber_gimple_stmt_uids () before starting. Note that phiopt
incrementally changes the IL, so I'm not sure those uids will stay
valid as stmts are moved across blocks.
I added a call to renumber_gimple_stmt_uids_in_blocks() before data
dependence checks, and there are no code changes between that and the
checks, so, I think, it should be OK.
+ {
+ free_data_refs (then_datarefs);
+ free_data_refs (else_datarefs);
+ free_dependence_relations (then_ddrs);
+ free_dependence_relations (else_ddrs);
+ return false;
+ }
+ }
+
+ /* Check that there are no read-after-write or write-after-write
dependencies
+ in ELSE_BB. */
+ FOR_EACH_VEC_ELT (ddr_p, else_ddrs, i, ddr)
+ {
+ struct data_reference *dra = DDR_A (ddr);
+ struct data_reference *drb = DDR_B (ddr);
+
+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
+ ((DR_IS_READ (dra) DR_IS_WRITE (drb)
+ gimple_uid (DR_STMT (dra)) gimple_uid (DR_STMT
(drb)))
+ || (DR_IS_READ (drb) DR_IS_WRITE (dra)
+ gimple_uid (DR_STMT (drb)) gimple_uid (DR_STMT
(dra)))
+ || (DR_IS_WRITE (dra) DR_IS_WRITE (drb
+ {
+ free_data_refs (then_datarefs);
+ free_data_refs (else_datarefs);
+ free_dependence_relations (then_ddrs);
+ free_dependence_relations (else_ddrs);
+ return false;
+ }
+ }
+
+ /* Found pairs of stores with equal LHS. */
+ FOR_EACH_VEC_ELT (data_reference_p, then_datarefs, i, then_dr)
+ {
+ if (DR_IS_READ (then_dr))
+ continue;
+
+ then_store = DR_STMT (then_dr);
+ then_lhs = gimple_assign_lhs (then_store);
+ found = false;
+
+ FOR_EACH_VEC_ELT (data_reference_p, else_datarefs, j, else_dr)
+ {
+ if (DR_IS_READ (else_dr))
+ continue;
+
+ else_store = DR_STMT (else_dr);
+ else_lhs = gimple_assign_lhs (else_store);
+
+ if (operand_equal_p (then_lhs, else_lhs, 0))
+ {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found)
+ continue;
+
+ res = cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
+ then_store, else_store);
So you are executing if-else store replacement for common data reference
pairs only. I think it's cheaper to collect those pairs before computing
dependences and only if there is at least one pair perform the
optimization.
OK, I changed the order.
You basically perform store sinking, creating a PHI node for each store
you sink (that's then probably if-converted by if-conversion later,
eventually
redundant with -ftree-loop-if-convert-stores?)
I am concerned that having no bound on the number of stores sunk will
increase register pressure and does not allow scheduling of the stores
in an optimal way. Consider two BBs
[PATCH] Fix PR48269
This removes a double-accounting for MEM_REF offsets. The code still
looks somewhat fishy, but at least is consistent in what it does now ;)
Bootstrapped and tested on x86_64-unknonw-linux-gnu, applied to trunk.
Richard.
2011-03-24 Richard Guenther rguent...@suse.de
PR middle-end/48269
* tree-object-size.c (addr_object_size): Do not double-account
for MEM_REF offsets.
* gcc.dg/builtin-object-size-10.c: New testcase.
Index: gcc/tree-object-size.c
===
*** gcc/tree-object-size.c (revision 171384)
--- gcc/tree-object-size.c (working copy)
*** addr_object_size (struct object_size_inf
*** 348,355
tree bytes2 = compute_object_offset (TREE_OPERAND (ptr, 0), pt_var);
if (bytes2 != error_mark_node)
{
- bytes2 = size_binop (PLUS_EXPR, bytes2,
- TREE_OPERAND (pt_var, 1));
if (TREE_CODE (bytes2) == INTEGER_CST
tree_int_cst_lt (pt_var_size, bytes2))
bytes2 = size_zero_node;
--- 348,353
Index: gcc/testsuite/gcc.dg/builtin-object-size-10.c
===
*** gcc/testsuite/gcc.dg/builtin-object-size-10.c (revision 0)
--- gcc/testsuite/gcc.dg/builtin-object-size-10.c (revision 0)
***
*** 0
--- 1,26
+ /* { dg-do compile } */
+ /* { dg-options -O2 -fdump-tree-objsz-details } */
+
+ typedef struct {
+ char sentinel[4];
+ char data[0];
+ } drone_packet;
+ typedef struct {
+ char type_str[16];
+ char channel_hop;
+ } drone_source_packet;
+ drone_packet *
+ foo(char *x)
+ {
+ drone_packet *dpkt = __builtin_malloc(sizeof(drone_packet)
+ + sizeof(drone_source_packet));
+ drone_source_packet *spkt = (drone_source_packet *) dpkt-data;
+ __builtin___snprintf_chk (spkt-type_str, 16,
+ 1, __builtin_object_size (spkt-type_str, 1),
+ %s, x);
+ return dpkt;
+ }
+
+ /* { dg-final { scan-tree-dump maximum object size 21 objsz } } */
+ /* { dg-final { scan-tree-dump maximum subobject size 16 objsz } } */
+ /* { dg-final { cleanup-tree-dump objsz } } */
Re: [PATCH] finish hookization of FUNCTION_ARG co.
On Sun, Nov 21, 2010 at 21:52, Nathan Froyd froy...@codesourcery.com wrote: * system.h (FUNCTION_ARG, FUNCTION_INCOMING_ARG): Poison. (FUNCTION_ARG_ADVANCE): Likewise. * tm.texi.in: Change references to them to hook references. * tm.texi: Regenerate. * targhooks.c (default_function_arg): Eliminate check for target macro. (default_function_incoming_arg): Likewise. (default_function_arg_advance): Likewise. * target.def (function_arg, function_incoming_arg): Change to DEFHOOK. (function_arg_advance): Likewise. * target-def.h: Eliminate FUNCTION_INCOMING_ARG check. OK. Diego.
Re: [PATCH][RFC] Add gimple_fold
On Tue, Mar 22, 2011 at 04:59, Richard Guenther rguent...@suse.de wrote: I simply put it in place as a possibility, I currently don't plan to implement any GF_KIND_COMPLEX folders (the caller would need to re-gimplify them which doesn't sound too useful). Maybe I should simply drop it. Perhaps. Not supporting an everything else bucket would help us not fall into the usual trap of having to support too many weird cases. Though I'm sure we can find other ways of falling into that ;) For instance, if folding ends up producing a complex tree, would it need to be gimplified? Maybe we could generate the gimplified statement and return the SSA name on the LHS? Though I'm not sure I like even this. Hm, I tried to avoid making the folder rewrite existing or emit new stmts - the idea was to make the interface cheap, not allocating GC memory for expressions or statements. Sounds reasonable. Perhaps this could be done by a wrapper, if needed. Diego.
Scheduler cleanups, 1/N
I have a number of patches that will be necessary for a new target. Some
of these can be applied now as cleanups, so I'm submit them now.
This changes the schedule_block main loop not to move instructions while
computing the schedule. Instead, we collect them in a VEC and modify the
RTL afterwards. The real motivation for this is to add support for
backtracking later.
Bootstrapped and tested on i686-linux. No changes in generated code on
any of my testcases.
Bernd
* sched-ebb.c (begin_schedule_ready): Remove second argument.
Split most of the code into...
(begin_move_insn): ... here. New function.
(ebb_sched_info): Add a pointer to it.
* haifa-sched.c (scheduled_insns): New static variable.
(sched_extend_ready_list): Allocate it.
(schedule_block): Use it to record the order of scheduled insns.
Perform RTL changes to move insns only after all scheduling
decisions have been made.
* modulo-sched.c (sms_sched_haifa_sched_info): Add NULL entry for the
begin_move_insn field.
* sel-sched-ir.c (sched_sel_haifa_sched_info): Likewise.
* sched-int.h (struct haifa_sched_info): Remove second argument
from begin_schedule_ready hook. Add new member begin_move_insn.
* sched-rgn.c (begin_schedule_ready): Remove second argument.
(rgn_const_sched_info): Add NULL entry for the begin_move_insn field.
Index: gcc/sched-ebb.c
===
--- gcc/sched-ebb.c.orig
+++ gcc/sched-ebb.c
@@ -59,7 +59,7 @@ static basic_block last_bb;
/* Implementations of the sched_info functions for region scheduling. */
static void init_ready_list (void);
-static void begin_schedule_ready (rtx, rtx);
+static void begin_schedule_ready (rtx);
static int schedule_more_p (void);
static const char *ebb_print_insn (const_rtx, int);
static int rank (rtx, rtx);
@@ -125,10 +125,15 @@ init_ready_list (void)
/* INSN is being scheduled after LAST. Update counters. */
static void
-begin_schedule_ready (rtx insn, rtx last)
+begin_schedule_ready (rtx insn ATTRIBUTE_UNUSED)
{
sched_rgn_n_insns++;
+}
+/* INSN is being moved to its place in the schedule, after LAST. */
+static void
+begin_move_insn (rtx insn, rtx last)
+{
if (BLOCK_FOR_INSN (insn) == last_bb
/* INSN is a jump in the last block, ... */
control_flow_insn_p (insn)
@@ -288,6 +293,7 @@ static struct haifa_sched_info ebb_sched
ebb_add_remove_insn,
begin_schedule_ready,
+ begin_move_insn,
advance_target_bb,
SCHED_EBB
/* We can create new blocks in begin_schedule_ready (). */
Index: gcc/haifa-sched.c
===
--- gcc/haifa-sched.c.orig
+++ gcc/haifa-sched.c
@@ -302,6 +302,10 @@ static struct ready_list *readyp = read
/* Scheduling clock. */
static int clock_var;
+/* This records the actual schedule. It is built up during the main phase
+ of schedule_block, and afterwards used to reorder the insns in the RTL. */
+static VEC(rtx, heap) *scheduled_insns;
+
static int may_trap_exp (const_rtx, int);
/* Nonzero iff the address is comprised from at most 1 register. */
@@ -2813,6 +2817,51 @@ choose_ready (struct ready_list *ready,
}
}
+/* This function is called when we have successfully scheduled a
+ block. It uses the schedule stored in the scheduled_insns vector
+ to rearrange the RTL. PREV_HEAD is used as the anchor to which we
+ append the scheduled insns; TAIL is the insn after the scheduled
+ block. TARGET_BB is the argument passed to schedule_block. */
+
+static void
+commit_schedule (rtx prev_head, rtx tail, basic_block *target_bb)
+{
+ int i;
+
+ last_scheduled_insn = prev_head;
+ for (i = 0; i (int)VEC_length (rtx, scheduled_insns); i++)
+{
+ rtx insn = VEC_index (rtx, scheduled_insns, i);
+
+ if (control_flow_insn_p (last_scheduled_insn)
+ || current_sched_info-advance_target_bb (*target_bb, insn))
+ {
+ *target_bb = current_sched_info-advance_target_bb (*target_bb, 0);
+
+ if (sched_verbose)
+ {
+ rtx x;
+
+ x = next_real_insn (last_scheduled_insn);
+ gcc_assert (x);
+ dump_new_block_header (1, *target_bb, x, tail);
+ }
+
+ last_scheduled_insn = bb_note (*target_bb);
+ }
+
+ if (current_sched_info-begin_move_insn)
+ (*current_sched_info-begin_move_insn) (insn, last_scheduled_insn);
+ move_insn (insn, last_scheduled_insn,
+current_sched_info-next_tail);
+ if (!DEBUG_INSN_P (insn))
+ reemit_notes (insn);
+ last_scheduled_insn = insn;
+}
+
+ VEC_truncate (rtx, scheduled_insns, 0);
+}
+
/* Use forward list scheduling to rearrange insns of block pointed to by
TARGET_BB, possibly bringing insns from subsequent blocks in the same
region. */
@@ -2934,6 +2983,7 @@ schedule_block
Scheduler cleanups, 2/N
This prints a bit more information in debugging dumps. Bootstrapped and
tested on i686-linux.
Bernd
* haifa-sched.c (queue_insn): New arg REASON. All callers
changed. Print it in debugging output.
Index: gcc/haifa-sched.c
===
--- gcc/haifa-sched.c.orig
+++ gcc/haifa-sched.c
@@ -493,7 +493,7 @@ haifa_classify_insn (const_rtx insn)
static int priority (rtx);
static int rank_for_schedule (const void *, const void *);
static void swap_sort (rtx *, int);
-static void queue_insn (rtx, int);
+static void queue_insn (rtx, int, const char *);
static int schedule_insn (rtx);
static void adjust_priority (rtx);
static void advance_one_cycle (void);
@@ -1318,10 +1318,11 @@ swap_sort (rtx *a, int n)
/* Add INSN to the insn queue so that it can be executed at least
N_CYCLES after the currently executing insn. Preserve insns
- chain for debugging purposes. */
+ chain for debugging purposes. REASON will be printed in debugging
+ output. */
HAIFA_INLINE static void
-queue_insn (rtx insn, int n_cycles)
+queue_insn (rtx insn, int n_cycles, const char *reason)
{
int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
@@ -1337,7 +1338,7 @@ queue_insn (rtx insn, int n_cycles)
fprintf (sched_dump, ;;\t\tReady--Q: insn %s: ,
(*current_sched_info-print_insn) (insn, 0));
- fprintf (sched_dump, queued for %d cycles.\n, n_cycles);
+ fprintf (sched_dump, queued for %d cycles (%s).\n, n_cycles, reason);
}
QUEUE_INDEX (insn) = next_q;
@@ -2067,11 +2068,7 @@ queue_to_ready (struct ready_list *ready
ready-n_ready - ready-n_debug MAX_SCHED_READY_INSNS
!SCHED_GROUP_P (insn)
insn != skip_insn)
- {
- if (sched_verbose = 2)
- fprintf (sched_dump, requeued because ready full\n);
- queue_insn (insn, 1);
- }
+ queue_insn (insn, 1, ready full);
else
{
ready_add (ready, insn, false);
@@ -2975,7 +2972,7 @@ schedule_block (basic_block *target_bb)
insn = ready_remove (ready, i);
if (insn != skip_insn)
- queue_insn (insn, 1);
+ queue_insn (insn, 1, list truncated);
}
}
}
@@ -3176,7 +3173,7 @@ schedule_block (basic_block *target_bb)
if (cost = 1)
{
- queue_insn (insn, cost);
+ queue_insn (insn, cost, resource conflict);
if (SCHED_GROUP_P (insn))
{
advance = cost;
@@ -3961,7 +3958,7 @@ change_queue_index (rtx next, int delay)
if (delay == QUEUE_READY)
ready_add (readyp, next, false);
else if (delay = 1)
-queue_insn (next, delay);
+queue_insn (next, delay, change queue index);
if (sched_verbose = 2)
{
[PATCH PING] fortran-specific bits of tree-slimming patches
The Fortran-specific bits of these patches: [PATCH 02/18] enforce TREE_CHAIN and TREE_TYPE accesses http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00565.html [PATCH 07/18] generalize build_case_label to the rest of the compiler http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00557.html [PATCH 17/18] introduce block_chainon and use BLOCK_CHAIN more http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00566.html are still pending review. -Nathan
Scheduler cleanups, 3/N
This caches dependency costs. The target adjust_cost macro can be quite
expensive. This may not make much of a difference now, but in the final
backtracking scheduler patches (which I'm omitting for the moment) we
look at these costs a bit more often.
Bernd
gcc/
* sched-int.h (struct _dep): New member COST.
(DEP_COST): New macro.
(UNKNOWN_DEP_COST): Define.
* sched-deps.c (init_dep_1): Initialize cost member.
* haifa-sched.c (dep_cost_1): Use precomputed cost if available,
compute and set it otherwise.
(sched_change_pattern): Reset costs of dependencies.
Index: gcc/haifa-sched.c
===
--- gcc/haifa-sched.c.orig
+++ gcc/haifa-sched.c
@@ -845,6 +845,9 @@ dep_cost_1 (dep_t link, dw_t dw)
rtx used = DEP_CON (link);
int cost;
+ if (DEP_COST (link) != UNKNOWN_DEP_COST)
+return DEP_COST (link);
+
/* A USE insn should never require the value used to be computed.
This allows the computation of a function's result and parameter
values to overlap the return and call. We don't care about the
@@ -902,6 +905,7 @@ dep_cost_1 (dep_t link, dw_t dw)
cost = 0;
}
+ DEP_COST (link) = cost;
return cost;
}
@@ -4854,11 +4858,20 @@ fix_recovery_deps (basic_block rec)
void
sched_change_pattern (rtx insn, rtx new_pat)
{
+ sd_iterator_def sd_it;
+ dep_t dep;
int t;
t = validate_change (insn, PATTERN (insn), new_pat, 0);
gcc_assert (t);
dfa_clear_single_insn_cache (insn);
+
+ for (sd_it = sd_iterator_start (insn, SD_LIST_FORW | SD_LIST_BACK);
+ sd_iterator_cond (sd_it, dep);)
+{
+ DEP_COST (dep) = UNKNOWN_DEP_COST;
+ sd_iterator_next (sd_it);
+}
}
/* Change pattern of INSN to NEW_PAT. Invalidate cached haifa
Index: gcc/sched-deps.c
===
--- gcc/sched-deps.c.orig
+++ gcc/sched-deps.c
@@ -106,6 +106,7 @@ init_dep_1 (dep_t dep, rtx pro, rtx con,
DEP_CON (dep) = con;
DEP_TYPE (dep) = type;
DEP_STATUS (dep) = ds;
+ DEP_COST (dep) = UNKNOWN_DEP_COST;
}
/* Init DEP with the arguments.
Index: gcc/sched-int.h
===
--- gcc/sched-int.h.orig
+++ gcc/sched-int.h
@@ -239,6 +239,9 @@ struct _dep
/* Dependency status. This field holds all dependency types and additional
information for speculative dependencies. */
ds_t status;
+
+ /* Cached cost of the dependency. */
+ int cost;
};
typedef struct _dep dep_def;
@@ -248,6 +251,9 @@ typedef dep_def *dep_t;
#define DEP_CON(D) ((D)-con)
#define DEP_TYPE(D) ((D)-type)
#define DEP_STATUS(D) ((D)-status)
+#define DEP_COST(D) ((D)-cost)
+
+#define UNKNOWN_DEP_COST INT_MIN
/* Functions to work with dep. */
Scheduler cleanups, 5/5
We can currently select an insn to be scheduled, only to find out that
it's not actually valid at the current time, either due to state
conflicts or being an asm with something else already scheduled in the
same cycle. Not only is this pointless, it causes problem with the
sched_reorder logic in the TI C6X port (which will be submitted later).
The solution is to prune the ready list earlier. More code is moved out
of the schedule_block main loop, which is IMO always a good thing.
Bootstrapped and tested (a slightly earlier version with an unused
variable) on i686-linux; I also verified that there are no changes in
code generation on any of my testcases.
Bernd
* haifa-sched.c (prune_ready_list): New function, broken out of
schedule_block.
(schedule_block): Use it.
Index: gcc/haifa-sched.c
===
--- gcc/haifa-sched.c.orig
+++ gcc/haifa-sched.c
@@ -2614,8 +2614,8 @@ max_issue (struct ready_list *ready, int
{
if (state_dead_lock_p (state)
|| insn_finishes_cycle_p (insn))
- /* We won't issue any more instructions in the next
- choice_state. */
+ /* We won't issue any more instructions in the next
+ choice_state. */
top-rest = 0;
else
top-rest--;
@@ -2863,6 +2863,52 @@ commit_schedule (rtx prev_head, rtx tail
VEC_truncate (rtx, scheduled_insns, 0);
}
+/* Examine all insns on the ready list and queue those which can't be
+ issued in this cycle. TEMP_STATE is temporary scheduler state we
+ can use as scratch space. If FIRST_CYCLE_INSN_P is true, no insns
+ have been issued for the current cycle, which means it is valid to
+ issue an asm statement. */
+
+static void
+prune_ready_list (state_t temp_state, bool first_cycle_insn_p)
+{
+ int i;
+
+ restart:
+ for (i = 0; i ready.n_ready; i++)
+{
+ rtx insn = ready_element (ready, i);
+ int cost = 0;
+ const char *reason = resource conflict;
+
+ if (recog_memoized (insn) 0)
+ {
+ if (!first_cycle_insn_p
+ (GET_CODE (PATTERN (insn)) == ASM_INPUT
+ || asm_noperands (PATTERN (insn)) = 0))
+ cost = 1;
+ reason = asm;
+ }
+ else if (flag_sched_pressure)
+ cost = 0;
+ else
+ {
+ memcpy (temp_state, curr_state, dfa_state_size);
+ cost = state_transition (temp_state, insn);
+ if (cost 0)
+ cost = 0;
+ else if (cost == 0)
+ cost = 1;
+ }
+ if (cost = 1)
+ {
+ ready_remove (ready, i);
+ queue_insn (insn, cost, reason);
+ goto restart;
+ }
+}
+}
+
/* Use forward list scheduling to rearrange insns of block pointed to by
TARGET_BB, possibly bringing insns from subsequent blocks in the same
region. */
@@ -3014,6 +3060,10 @@ schedule_block (basic_block *target_bb)
}
while (advance 0);
+ prune_ready_list (temp_state, true);
+ if (ready.n_ready == 0)
+continue;
+
if (sort_p)
{
/* Sort the ready list based on priority. */
@@ -3144,44 +3194,6 @@ schedule_block (basic_block *target_bb)
}
sort_p = TRUE;
- memcpy (temp_state, curr_state, dfa_state_size);
- if (recog_memoized (insn) 0)
- {
- asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
- || asm_noperands (PATTERN (insn)) = 0);
- if (!first_cycle_insn_p asm_p)
- /* This is asm insn which is tried to be issued on the
- cycle not first. Issue it on the next cycle. */
- cost = 1;
- else
- /* A USE insn, or something else we don't need to
- understand. We can't pass these directly to
- state_transition because it will trigger a
- fatal error for unrecognizable insns. */
- cost = 0;
- }
- else if (sched_pressure_p)
- cost = 0;
- else
- {
- cost = state_transition (temp_state, insn);
- if (cost 0)
- cost = 0;
- else if (cost == 0)
- cost = 1;
- }
-
- if (cost = 1)
- {
- queue_insn (insn, cost, resource conflict);
- if (SCHED_GROUP_P (insn))
- {
- advance = cost;
- break;
- }
-
- continue;
- }
if (current_sched_info-can_schedule_ready_p
! (*current_sched_info-can_schedule_ready_p) (insn))
@@ -3202,14 +3214,20 @@ schedule_block (basic_block *target_bb)
/* Update counters, etc in the scheduler's front end. */
(*current_sched_info-begin_schedule_ready) (insn);
- VEC_safe_push
Re: [PATCH][ARM] Discourage use of NEON on Cortex-A8
On Tue, 2011-03-22 at 14:08 +, Andrew Stubbs wrote: And again, with the patch ... On 22/03/11 14:05, Andrew Stubbs wrote: On 14/03/11 18:17, Richard Earnshaw wrote: I think the order should be: not-a8, core-regs, core-regs, only-a8. Ok, how about this? I've tested that it still builds spec2k crafty. Andrew OK
Re: [RFC] Add a new argument to SELECT_CC_MODE
On Tue, 2011-03-22 at 21:00 +0100, Eric Botcazou wrote: Like in the attached patch. Sandra expressed an interest for it so I've installed it on the mainline after bootstrapping and regtesting on x86_64-suse-linux. 2011-03-22 Eric Botcazou ebotca...@adacore.com * combine.c (simplify_set): Try harder to find the best CC mode when simplifying a nested COMPARE on the RHS. So I've always suspected that the way the ARM port handles this is broken. I think this now confirms that suspicion. Taking a look at the x86 backend the code there looks far more sensible and more in-line with what I think ARM should be doing. For a floating point operation the code is: TARGET_IEEE_FP ? CCFPUmode : CCFPmode; That is, if generating IEEE compliant code, then use non-excepting comparisions, otherwise use exception raising ones. R.
Re: [patch] Fix PR48183, NEON ICE in emit-rtl.c:immed_double_const() under -g
On Thu, 24 Mar 2011 10:57:06 +
Richard Sandiford richard.sandif...@linaro.org wrote:
Chung-Lin Tang clt...@codesourcery.com writes:
PR48183 is a case where ARM NEON instrinsics, under -O -g, produce
debug insns that tries to expand OImode (32-byte integer) zero
constants, much too large to represent as two HOST_WIDE_INTs; as
the internals manual indicates, such large constants are not
supported in general, and ICEs on the GET_MODE_BITSIZE(mode) ==
2*HOST_BITS_PER_WIDE_INT assertion.
This patch allows the cases where the large integer constant is
still representable using a single CONST_INT, such as zero(0).
Bootstrapped and tested on i686 and x86_64, cross-tested on ARM,
all without regressions. Okay for trunk?
Thanks,
Chung-Lin
2011-03-20 Chung-Lin Tang clt...@codesourcery.com
* emit-rtl.c (immed_double_const): Allow wider than
2*HOST_BITS_PER_WIDE_INT mode constants when they are
representable as a single const_int RTX.
I realise this might be seen as a good expedient fix, but it makes
me a bit uneasy. Not a very constructive rationale, sorry.
FWIW I also had a fix for this issue, which is equivalent to
Chung-Lin's patch apart from only allowing constant-zero (attached).
That's not really a vote from me for this approach, but maybe limiting
the extent to which we pretend to support wide-integer constants like
this is sensible, if we do go that way.
Julian--- gcc/expr.c (revision 314639)
+++ gcc/expr.c (working copy)
@@ -8458,6 +8458,18 @@ expand_expr_real_1 (tree exp, rtx target
return decl_rtl;
case INTEGER_CST:
+ if (GET_MODE_BITSIZE (mode) 2 * HOST_BITS_PER_WIDE_INT)
+ {
+ /* FIXME: We can't generally represent wide integer constants,
+ but GCC sometimes tries to initialise wide integer values (such
+ as used by the ARM NEON support) with zero. Handle that as a
+ special case here. */
+ if (initializer_zerop (exp))
+ return CONST0_RTX (mode);
+
+ gcc_unreachable ();
+ }
+
temp = immed_double_const (TREE_INT_CST_LOW (exp),
TREE_INT_CST_HIGH (exp), mode);
Remove old host cases from toplevel configure
This patch removes cases for a range of old hosts from the toplevel
configure.ac, as I think those cases are no longer useful. All the
removed code comes from Cygnus configure before the toplevel configure
was converted to be an autoconf-generated script.
In general those hosts, if ever supported as targets by GCC at all,
had their GCC target support obsoleted in GCC 4.3 or earlier. It is
of course theoretically possible to build cross tools hosted on a
system not supported as a target by GCC, using a non-GCC compiler, but
it's much more of a niche than building native tools there and these
targets all became unsupported for native tools a long time ago for
lack of interest in maintaining support for them. Thus I don't think
it's useful any more to maintain cases for these hosts in toplevel
configure.
Furthermore, the whole idea of the toplevel configure tentative_cc
setting code is dubious since this is an autoconf-generated script and
it's autoconf's job to deal with finding a working compiler, putting
it in ANSI C mode, etc. - so if someone did wish to resupport one of
these hosts (and in the unlikely event that building current tools
using the old system compiler is at all possible) it would be better
to put system-specific pieces in autoconf and make toolchain configure
code work using features not host triplet tests as far as possible.
OK to commit?
2011-03-24 Joseph Myers jos...@codesourcery.com
* configure.ac (i[[3456789]]86-*-vsta, i[[3456789]]86-*-go32*,
i[[3456789]]86-*-beos*, powerpc-*-beos*, m68k-hp-hpux*,
m68k-apollo-sysv*, m68k-apollo-bsd*, m88k-dg-dgux*,
m88k-harris-cxux*, m88k-motorola-sysv*, mips*-dec-ultrix*,
mips*-nec-sysv4*, mips*-sgi-irix4*, mips*-*-sysv4*, mips*-*-sysv*,
i370-ibm-opened*, i[[3456789]]86-*-sysv5*, i[[3456789]]86-*-dgux*,
i[[3456789]]86-ncr-sysv4.3*, i[[3456789]]86-ncr-sysv4*,
i[[3456789]]86-*-sco3.2v5*, i[[3456789]]86-*-sco*,
i[[3456789]]86-*-udk*, vax-*-ultrix2*, m68k-sun-sunos*,
hppa*-*-hiux*, *-*-hiux*, rs6000-*-lynxos*, *-*-sysv4*,
*-*-rhapsody*): Remove host cases.
* configure: Regenerate.
config:
2011-03-24 Joseph Myers jos...@codesourcery.com
* mh-cxux, mh-decstation, mh-dgux386, mh-lynxrs6k, mh-ncr3000,
mh-necv4, mh-sco, mh-sysv5: Remove.
Index: configure.ac
===
--- configure.ac(revision 171390)
+++ configure.ac(working copy)
@@ -429,10 +429,7 @@
hppa*64*-*-*)
noconfigdirs=$noconfigdirs byacc
;;
- i[[3456789]]86-*-vsta)
-noconfigdirs=$noconfigdirs tcl expect dejagnu make texinfo bison patch
flex byacc send-pr gprof uudecode dejagnu diff guile perl itcl gnuserv gettext
-;;
- i[[3456789]]86-*-go32* | i[[3456789]]86-*-msdosdjgpp*)
+ i[[3456789]]86-*-msdosdjgpp*)
noconfigdirs=$noconfigdirs tcl tk expect dejagnu send-pr uudecode guile
itcl gnuserv libffi
;;
x86_64-*-mingw*)
@@ -442,18 +439,12 @@
# noconfigdirs=tcl tk expect dejagnu make texinfo bison patch flex byacc
send-pr uudecode dejagnu diff guile perl itcl gnuserv
noconfigdirs=$noconfigdirs expect dejagnu autoconf automake send-pr rcs
guile perl texinfo libtool newlib
;;
- i[[3456789]]86-*-beos*)
-noconfigdirs=$noconfigdirs tk itcl libgui gdb
-;;
*-*-cygwin*)
noconfigdirs=$noconfigdirs autoconf automake send-pr rcs guile perl
;;
*-*-netbsd*)
noconfigdirs=$noconfigdirs rcs
;;
- powerpc-*-beos*)
-noconfigdirs=$noconfigdirs tk itcl libgui gdb dejagnu readline
-;;
esac
@@ -966,8 +957,6 @@
;;
sh-*-* | sh64-*-*)
case ${host} in
- i[[3456789]]86-*-vsta) ;; # don't add gprof back in
- i[[3456789]]86-*-go32*) ;; # don't add gprof back in
i[[3456789]]86-*-msdosdjgpp*) ;; # don't add gprof back in
*) skipdirs=`echo ${skipdirs} | sed -e 's/ gprof / /'` ;;
esac
@@ -1049,104 +1038,6 @@
host_makefile_frag=/dev/null
if test -d ${srcdir}/config ; then
case ${host} in
- m68k-hp-hpux*)
-# Avoid too much defining errors from HPUX compiler.
-tentative_cc=cc -Wp,-H256000
-# If ar in $PATH is GNU ar, the symbol table may need rebuilding.
-# If it's HP/UX ar, this should be harmless.
-RANLIB=ar ts
-;;
- m68k-apollo-sysv*)
-tentative_cc=cc -A ansi -A runtype,any -A systype,any -U__STDC__ -DUSG
-;;
- m68k-apollo-bsd*)
-#None of the Apollo compilers can compile gas or binutils. The
preprocessor
-# chokes on bfd, the compiler won't let you assign integers to enums, and
-# other problems. Defining CC to gcc is a questionable way to say don't
use
-# the apollo compiler (the preferred version of GCC could be called cc,
-# or whatever), but I'm not sure leaving CC as cc is any better...
-#CC=cc -A ansi -A runtype,any -A systype,any -U__STDC__ -DNO_STDARG
-# Used to have BISON=yacc.
-tentative_cc=gcc
-;;
-
Re: Problem with ARM longcalls
On 03/24/2011 03:24 PM, Richard Earnshaw wrote: On Wed, 2011-03-23 at 16:46 +0100, Bernd Schmidt wrote: I've discovered a problem with -mlong-calls on ARM. The bug was first reported against a new target, but I'd copied the relevant code from the ARM backend. We use current_function_section in arm_is_long_call_p to decide whether we're calling something that goes into the same section. The problem with this is that current_function_section can only be used during final, since it relies on the global variable in_cold_section_p which is set up only in assemble_start_function. On ARM, this problem manifests as short-calls when a long-call would be required; in the other port it was an insn doesn't satisfy its constraints error. The following patch is against 4.5, since the problem appears hidden in mainline (the initialization of first_function_block_is_cold has changed). Ok for trunk and branches after arm-linux tests complete? Bernd The ARM port currently doesn't support hot/cold partitioning of code (and can't until the constant pool code is rewritten to deal with it), so how is this a problem? Different functions can still go into different sections. When we start expanding a function, in_cold_section_p still contains the value that was correct for the previous one. It will change at the start of final, which means that current_function_section can return different values while compiling a function. See the included testcase. Bernd
[patch] Preserve source location in folder
Hi,
when fold_ternary_loc is attempting to make the tree prettier, e.g. by swapping
the arguments of a COND_EXPR, it does:
tem = fold_truth_not_expr (loc, arg0);
Now LOC is the location that will be put on the whole expression and there is
no reason it should override the location of ARG0, if any, when inverting it.
The attached patch only ensures that - this gives more precise coverage info.
Bootstrapped/regtested on x86_64-suse-linux, OK for the mainline?
2011-03-24 Eric Botcazou ebotca...@adacore.com
* fold-const.c (fold_ternary_loc): Preserve the location (if any) of
the argument in calls to fold_truth_not_expr.
--
Eric Botcazou
Index: fold-const.c
===
--- fold-const.c (revision 171345)
+++ fold-const.c (working copy)
@@ -13327,7 +13327,10 @@ fold_ternary_loc (location_t loc, enum t
TREE_OPERAND (arg0, 1))
!HONOR_SIGNED_ZEROS (TYPE_MODE (TREE_TYPE (op2
{
- tem = fold_truth_not_expr (loc, arg0);
+ location_t loc0 = EXPR_LOCATION (arg0);
+ if (loc0 == UNKNOWN_LOCATION)
+ loc0 = loc;
+ tem = fold_truth_not_expr (loc0, arg0);
if (tem COMPARISON_CLASS_P (tem))
{
tem = fold_cond_expr_with_comparison (loc, type, tem, op2, op1);
@@ -13341,10 +13344,13 @@ fold_ternary_loc (location_t loc, enum t
if (truth_value_p (TREE_CODE (arg0))
tree_swap_operands_p (op1, op2, false))
{
+ location_t loc0 = EXPR_LOCATION (arg0);
+ if (loc0 == UNKNOWN_LOCATION)
+ loc0 = loc;
/* See if this can be inverted. If it can't, possibly because
it was a floating-point inequality comparison, don't do
anything. */
- tem = fold_truth_not_expr (loc, arg0);
+ tem = fold_truth_not_expr (loc0, arg0);
if (tem)
return fold_build3_loc (loc, code, type, tem, op2, op1);
}
@@ -13489,8 +13495,11 @@ fold_ternary_loc (location_t loc, enum t
truth_value_p (TREE_CODE (arg0))
truth_value_p (TREE_CODE (arg1)))
{
+ location_t loc0 = EXPR_LOCATION (arg0);
+ if (loc0 == UNKNOWN_LOCATION)
+ loc0 = loc;
/* Only perform transformation if ARG0 is easily inverted. */
- tem = fold_truth_not_expr (loc, arg0);
+ tem = fold_truth_not_expr (loc0, arg0);
if (tem)
return fold_build2_loc (loc, TRUTH_ORIF_EXPR, type,
fold_convert_loc (loc, type, tem),
@@ -13502,8 +13511,11 @@ fold_ternary_loc (location_t loc, enum t
truth_value_p (TREE_CODE (arg0))
truth_value_p (TREE_CODE (op2)))
{
+ location_t loc0 = EXPR_LOCATION (arg0);
+ if (loc0 == UNKNOWN_LOCATION)
+ loc0 = loc;
/* Only perform transformation if ARG0 is easily inverted. */
- tem = fold_truth_not_expr (loc, arg0);
+ tem = fold_truth_not_expr (loc0, arg0);
if (tem)
return fold_build2_loc (loc, TRUTH_ANDIF_EXPR, type,
fold_convert_loc (loc, type, tem),
[patch] Do not generate useless branches for multi-word comparison
Hi,
this improves the RTL generated for multi-word comparison to avoid generating
useless branches. In do_jump_by_parts_greater_rtx:
1) do not generate the last cond jump,
2) do not generate the uncond branch to the drop-through label, if any,
3) generate only one comparison for the special (0 x) case.
Tested on i586-suse-linux, OK for the mainline?
2011-03-24 Eric Botcazou ebotca...@adacore.com
* dojump.c (do_jump_by_parts_greater_rtx): Optimize in specific cases.
--
Eric Botcazou
Index: dojump.c
===
--- dojump.c (revision 171345)
+++ dojump.c (working copy)
@@ -637,14 +637,32 @@ do_jump_by_parts_greater_rtx (enum machi
{
int nwords = (GET_MODE_SIZE (mode) / UNITS_PER_WORD);
rtx drop_through_label = 0;
+ bool drop_through_if_true = false, drop_through_if_false = false;
+ enum rtx_code code = GT;
int i;
if (! if_true_label || ! if_false_label)
drop_through_label = gen_label_rtx ();
if (! if_true_label)
-if_true_label = drop_through_label;
+{
+ if_true_label = drop_through_label;
+ drop_through_if_true = true;
+}
if (! if_false_label)
-if_false_label = drop_through_label;
+{
+ if_false_label = drop_through_label;
+ drop_through_if_false = true;
+}
+
+ /* Deal with the special case 0 x: only one comparison is necessary and
+ we reverse it to avoid jumping to the drop-through label. */
+ if (op0 == const0_rtx drop_through_if_true !drop_through_if_false)
+{
+ code = LE;
+ if_true_label = if_false_label;
+ if_false_label = drop_through_label;
+ drop_through_if_false = true;
+}
/* Compare a word at a time, high order first. */
for (i = 0; i nwords; i++)
@@ -663,17 +681,20 @@ do_jump_by_parts_greater_rtx (enum machi
}
/* All but high-order word must be compared as unsigned. */
- do_compare_rtx_and_jump (op0_word, op1_word, GT,
- (unsignedp || i 0), word_mode, NULL_RTX,
- NULL_RTX, if_true_label, prob);
+ do_compare_rtx_and_jump (op0_word, op1_word, code, (unsignedp || i 0),
+ word_mode, NULL_RTX, NULL_RTX, if_true_label,
+ prob);
+
+ /* Emit only one comparison for 0. Do not emit the last cond jump. */
+ if (op0 == const0_rtx || i == nwords - 1)
+ break;
/* Consider lower words only if these are equal. */
do_compare_rtx_and_jump (op0_word, op1_word, NE, unsignedp, word_mode,
- NULL_RTX, NULL_RTX, if_false_label,
- inv (prob));
+ NULL_RTX, NULL_RTX, if_false_label, inv (prob));
}
- if (if_false_label)
+ if (!drop_through_if_false)
emit_jump (if_false_label);
if (drop_through_label)
emit_label (drop_through_label);
[PATCH] fix memory accounting for copying nodes
tree.c can gather optionally statistics--counts and total bytes
allocated--when tree nodes are created. Due to an oversight, however,
this accounting is not performed when nodes are copied. The patch below
corrects this oversight and moves things around so the accounting is
done in (almost) only one place. (The almost is due to special
decrementing when we reuse types, which is arguably bogus, since we've
created a node already, so we shouldn't be playing games to pretend we
didn't touch memory.)
Tested on x86_64-unknown-linux-gnu, with and without
--enable-gather-detailed-mem-stats. OK to commit?
-Nathan
* tree.c (record_node_allocation_statistics): New function.
(make_node_stat, copy_node_stat, build_string): Call it.
(make_tree_binfo_stat, make_tree_vec_stat, tree_cons_stat): Likewise.
(build1_stat, build_omp_clause): Likewise.
diff --git a/gcc/tree.c b/gcc/tree.c
index efa51bd..2066c84 100644
--- a/gcc/tree.c
+++ b/gcc/tree.c
@@ -769,20 +769,15 @@ tree_size (const_tree node)
}
}
-/* Return a newly allocated node of code CODE. For decl and type
- nodes, some other fields are initialized. The rest of the node is
- initialized to zero. This function cannot be used for TREE_VEC or
- OMP_CLAUSE nodes, which is enforced by asserts in tree_code_size.
+/* Record interesting allocation statistics for a tree node with CODE
+ and LENGTH. */
- Achoo! I got a code in the node. */
-
-tree
-make_node_stat (enum tree_code code MEM_STAT_DECL)
+static void
+record_node_allocation_statistics (enum tree_code code ATTRIBUTE_UNUSED,
+ size_t length ATTRIBUTE_UNUSED)
{
- tree t;
- enum tree_code_class type = TREE_CODE_CLASS (code);
- size_t length = tree_code_size (code);
#ifdef GATHER_STATISTICS
+ enum tree_code_class type = TREE_CODE_CLASS (code);
tree_node_kind kind;
switch (type)
@@ -841,12 +836,20 @@ make_node_stat (enum tree_code code MEM_STAT_DECL)
kind = constr_kind;
break;
+ case OMP_CLAUSE:
+ kind = omp_clause_kind;
+ break;
+
default:
kind = x_kind;
break;
}
break;
+case tcc_vl_exp:
+ kind = e_kind;
+ break;
+
default:
gcc_unreachable ();
}
@@ -854,6 +857,23 @@ make_node_stat (enum tree_code code MEM_STAT_DECL)
tree_node_counts[(int) kind]++;
tree_node_sizes[(int) kind] += length;
#endif
+}
+
+/* Return a newly allocated node of code CODE. For decl and type
+ nodes, some other fields are initialized. The rest of the node is
+ initialized to zero. This function cannot be used for TREE_VEC or
+ OMP_CLAUSE nodes, which is enforced by asserts in tree_code_size.
+
+ Achoo! I got a code in the node. */
+
+tree
+make_node_stat (enum tree_code code MEM_STAT_DECL)
+{
+ tree t;
+ enum tree_code_class type = TREE_CODE_CLASS (code);
+ size_t length = tree_code_size (code);
+
+ record_node_allocation_statistics (code, length);
t = ggc_alloc_zone_cleared_tree_node_stat (
(code == IDENTIFIER_NODE) ? tree_id_zone : tree_zone,
@@ -950,6 +970,7 @@ copy_node_stat (tree node MEM_STAT_DECL)
gcc_assert (code != STATEMENT_LIST);
length = tree_size (node);
+ record_node_allocation_statistics (code, length);
t = ggc_alloc_zone_tree_node_stat (tree_zone, length PASS_MEM_STAT);
memcpy (t, node, length);
@@ -1540,10 +1561,7 @@ build_string (int len, const char *str)
/* Do not waste bytes provided by padding of struct tree_string. */
length = len + offsetof (struct tree_string, str) + 1;
-#ifdef GATHER_STATISTICS
- tree_node_counts[(int) c_kind]++;
- tree_node_sizes[(int) c_kind] += length;
-#endif
+ record_node_allocation_statistics (STRING_CST, length);
s = ggc_alloc_tree_node (length);
@@ -1663,10 +1681,7 @@ make_tree_binfo_stat (unsigned base_binfos MEM_STAT_DECL)
size_t length = (offsetof (struct tree_binfo, base_binfos)
+ VEC_embedded_size (tree, base_binfos));
-#ifdef GATHER_STATISTICS
- tree_node_counts[(int) binfo_kind]++;
- tree_node_sizes[(int) binfo_kind] += length;
-#endif
+ record_node_allocation_statistics (TREE_BINFO, length);
t = ggc_alloc_zone_tree_node_stat (tree_zone, length PASS_MEM_STAT);
@@ -1688,10 +1703,7 @@ make_tree_vec_stat (int len MEM_STAT_DECL)
tree t;
int length = (len - 1) * sizeof (tree) + sizeof (struct tree_vec);
-#ifdef GATHER_STATISTICS
- tree_node_counts[(int) vec_kind]++;
- tree_node_sizes[(int) vec_kind] += length;
-#endif
+ record_node_allocation_statistics (TREE_VEC, length);
t = ggc_alloc_zone_cleared_tree_node_stat (tree_zone, length PASS_MEM_STAT);
@@ -2229,10 +2241,7 @@ tree_cons_stat (tree purpose, tree value, tree chain
MEM_STAT_DECL)
PASS_MEM_STAT);
memset (node, 0, sizeof (struct tree_common));
-#ifdef GATHER_STATISTICS
- tree_node_counts[(int) x_kind]++;
- tree_node_sizes[(int)
Re: Fix more minor issues from static checkers
On Thu, Mar 24, 2011 at 10:37, Jeff Law l...@redhat.com wrote: Bootstrapped and regression tested on x86_64-unknown-linux-gnu. OK for trunk? OK. Diego.
Re: [patch] Preserve source location in folder
On Thu, Mar 24, 2011 at 3:38 PM, Eric Botcazou ebotca...@adacore.com wrote: Hi, when fold_ternary_loc is attempting to make the tree prettier, e.g. by swapping the arguments of a COND_EXPR, it does: tem = fold_truth_not_expr (loc, arg0); Now LOC is the location that will be put on the whole expression and there is no reason it should override the location of ARG0, if any, when inverting it. The attached patch only ensures that - this gives more precise coverage info. Bootstrapped/regtested on x86_64-suse-linux, OK for the mainline? Ok. (I shortly thought about a PREFER_OVER_UNKNOWN_LOCATION (maybe_unknown, loc) macro, but well ...) Thanks, Richard. 2011-03-24 Eric Botcazou ebotca...@adacore.com * fold-const.c (fold_ternary_loc): Preserve the location (if any) of the argument in calls to fold_truth_not_expr. -- Eric Botcazou
[rs6000] Fix thinko in output_profile_hook
Hi,
the problematic line is:
label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
On AIX, rs6000_xcoff_strip_name_encoding can return NAME + 1:
static const char *
rs6000_xcoff_strip_name_encoding (const char *name)
{
size_t len;
if (*name == '*')
name++;
len = strlen (name);
if (name[len - 1] == ']')
return ggc_alloc_string (name, len - 4);
else
return name;
}
which means that you can have (ADDR + 1) in some GC tree and gt_ggc_m_S choke:
if (offset)
{
/* Here we've seen a char* which does not point to the beginning
of an allocated object. We assume it points to the middle of
a STRING_CST. */
gcc_assert (offset == offsetof (struct tree_string, str));
p = ((const char *) p) - offset;
gt_ggc_mx_lang_tree_node (CONST_CAST (void *, p));
return;
}
Tested on AIX, OK for the mainline?
2011-03-24 Eric Botcazou ebotca...@adacore.com
* config/rs6000/rs6000.c (output_profile_hook): Fix thinko.
--
Eric Botcazou
Index: config/rs6000/rs6000.c
===
--- config/rs6000/rs6000.c (revision 171345)
+++ config/rs6000/rs6000.c (working copy)
@@ -23002,7 +23002,7 @@ output_profile_hook (int labelno ATTRIBU
rtx fun;
ASM_GENERATE_INTERNAL_LABEL (buf, LP, labelno);
- label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
+ label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
emit_library_call (init_one_libfunc (RS6000_MCOUNT),
Re: Cleaning up expand optabs code
Richard Sandiford richard.sandif...@linaro.org writes:
Andreas Krebbel kreb...@linux.vnet.ibm.com writes:
On 03/22/2011 06:48 PM, Richard Henderson wrote:
Ok. Watch out for other target problems this week.
This unfortunately broke bootstrap on s390.
This is PR 48263. Since it seems to be affecting several targets,
and since my bootstrap seems to be taking a looong time, I'll post
the patch here before testing has finished.
Bootstrap regression-test on x86_64-linux-gnu now finished. OK to install?
Just copying the pre-patch behaviour fixes the problem for me:
I think we need to undo more of the patch, and leave the conversion
outside of the new interface.
Sorry for the breakage.
Richard
gcc/
PR rtl-optimization/48263
* optabs.c (expand_binop_directly): Reinstate convert_modes code
and original commutative_p handling. Use maybe_gen_insn.
Index: gcc/optabs.c
===
--- gcc/optabs.c 2011-03-24 09:18:00.0 +
+++ gcc/optabs.c 2011-03-24 09:36:46.0 +
@@ -1269,6 +1269,38 @@ expand_binop_directly (enum machine_mode
if (!shift_optab_p (binoptab))
xop1 = avoid_expensive_constant (mode1, binoptab, xop1, unsignedp);
+ /* In case the insn wants input operands in modes different from
+ those of the actual operands, convert the operands. It would
+ seem that we don't need to convert CONST_INTs, but we do, so
+ that they're properly zero-extended, sign-extended or truncated
+ for their mode. */
+
+ if (GET_MODE (xop0) != mode0 mode0 != VOIDmode)
+xop0 = convert_modes (mode0,
+ GET_MODE (xop0) != VOIDmode
+ ? GET_MODE (xop0)
+ : mode,
+ xop0, unsignedp);
+
+ if (GET_MODE (xop1) != mode1 mode1 != VOIDmode)
+xop1 = convert_modes (mode1,
+ GET_MODE (xop1) != VOIDmode
+ ? GET_MODE (xop1)
+ : mode,
+ xop1, unsignedp);
+
+ /* If operation is commutative,
+ try to make the first operand a register.
+ Even better, try to make it the same as the target.
+ Also try to make the last operand a constant. */
+ if (commutative_p
+ swap_commutative_operands_with_target (target, xop0, xop1))
+{
+ swap = xop1;
+ xop1 = xop0;
+ xop0 = swap;
+}
+
/* Now, if insn's predicates don't allow our operands, put them into
pseudo regs. */
@@ -1291,41 +1323,25 @@ expand_binop_directly (enum machine_mode
tmp_mode = mode;
create_output_operand (ops[0], target, tmp_mode);
- create_convert_operand_from (ops[1], xop0, mode, unsignedp);
- create_convert_operand_from (ops[2], xop1, mode, unsignedp);
- if (maybe_legitimize_operands (icode, 0, 3, ops))
-{
- /* If operation is commutative,
- try to make the first operand a register.
- Even better, try to make it the same as the target.
- Also try to make the last operand a constant. */
- if (commutative_p
-swap_commutative_operands_with_target (ops[0].value, ops[1].value,
- ops[2].value))
- {
- swap = ops[2].value;
- ops[2].value = ops[1].value;
- ops[1].value = swap;
- }
-
- pat = GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value);
- if (pat)
+ create_input_operand (ops[1], xop0, mode0);
+ create_input_operand (ops[2], xop1, mode1);
+ pat = maybe_gen_insn (icode, 3, ops);
+ if (pat)
+{
+ /* If PAT is composed of more than one insn, try to add an appropriate
+ REG_EQUAL note to it. If we can't because TEMP conflicts with an
+ operand, call expand_binop again, this time without a target. */
+ if (INSN_P (pat) NEXT_INSN (pat) != NULL_RTX
+! add_equal_note (pat, ops[0].value, binoptab-code,
+ops[1].value, ops[2].value))
{
- /* If PAT is composed of more than one insn, try to add an appropriate
- REG_EQUAL note to it. If we can't because TEMP conflicts with an
- operand, call expand_binop again, this time without a target. */
- if (INSN_P (pat) NEXT_INSN (pat) != NULL_RTX
-! add_equal_note (pat, ops[0].value, binoptab-code,
-ops[1].value, ops[2].value))
- {
- delete_insns_since (last);
- return expand_binop (mode, binoptab, op0, op1, NULL_RTX,
-unsignedp, methods);
- }
-
- emit_insn (pat);
- return ops[0].value;
+ delete_insns_since (last);
+ return expand_binop (mode, binoptab, op0, op1, NULL_RTX,
+unsignedp, methods);
}
+
+ emit_insn (pat);
+ return ops[0].value;
}
Re: [Patch ARM] PR47930 Fix documentation for marm / mthumb
On Sun, 2011-03-20 at 15:19 +, Ramana Radhakrishnan wrote:
Hi,
This fixes up documentation for the -marm option and changes the
behaviour of mthumb to reject the negative options to bring this to
behave similar to the marm option. The option needs to be documented
since we now have situations where toolchains default to Thumb state and
folks need a way of overriding this. I would like a review of this
before committing it since this is a change to the command line options.
Tested by building a cross toolchain to arm-linux-gnueabi and verified
that -mno-thumb is rejected and looking up the documentation after it
was rebuilt.
Ok ?
cheers
Ramana
2011-03-20 Ramana Radhakrishnan ramana.radhakrish...@linaro.org
PR target/47930
* config/arm/arm.opt (marm): Document it.
(mthumb): Reject negative variant.
+@item -marm
+@opindex marm
+Generate code for the 32 bit ARM instruction set. This is used to
+override and generate code in ARM state if the compiler has been
+configured to be built in Thumb state. This option is not passed to
the
+assembler.
I'd suggest
@item -mthumb
@itemx -marm
@opindex marm
@opindex mthumb
Select between generating code that executes in ARM and Thumb
states. The default for most configurations is to generate code
that executes in ARM state, but the default can be changed by
configuring GCC with the @option{--with-mode=}@var{state}
configure option.
I don't see any need to talk about the Thumb1/Thumb2 behaviour here any
more than we do about other ISA variants in ARM state. Nor do I think
it's relevant to talk about this option in relation to the assembler.
The arm.opt change is OK, but 'Report' should stay; and it should also
be added to the -marm case.
R.
[Ada] Fix bogus CE raised on call to overloaded function
The attached code (derived from ACATS c34006d) raises a bogus Constraint_Error
since at least GCC 3.4:
raised CONSTRAINT_ERROR : p.adb:33 discriminant check failed
This is related to the overloading of function Create.
Tested on i586-suse-linux, applied on the mainline.
2011-03-24 Eric Botcazou ebotca...@adacore.com
* gcc-interface/trans.c (gnat_to_gnu): Remove obsolete case of
non-conversion to the nominal result type at the end.
2011-03-24 Eric Botcazou ebotca...@adacore.com
* gnat.dg/derived_type2.adb: New test.
--
Eric Botcazou
Index: gcc-interface/trans.c
===
--- gcc-interface/trans.c (revision 171345)
+++ gcc-interface/trans.c (working copy)
@@ -5879,15 +5879,11 @@ gnat_to_gnu (Node_Id gnat_node)
since we need to ignore those conversions (for 'Valid).
2. If we have a label (which doesn't have any well-defined type), a
- field or an error, return the result almost unmodified. Also don't
- do the conversion if the result type involves a PLACEHOLDER_EXPR in
- its size since those are the cases where the front end may have the
- type wrong due to instantiating the unconstrained record with
- discriminant values. Similarly, if the two types are record types
- with the same name don't convert. This will be the case when we are
- converting from a packable version of a type to its original type and
- we need those conversions to be NOPs in order for assignments into
- these types to work properly.
+ field or an error, return the result almost unmodified. Similarly,
+ if the two types are record types with the same name, don't convert.
+ This will be the case when we are converting from a packable version
+ of a type to its original type and we need those conversions to be
+ NOPs in order for assignments into these types to work properly.
3. If the type is void or if we have no result, return error_mark_node
to show we have no result.
@@ -5933,12 +5929,8 @@ gnat_to_gnu (Node_Id gnat_node)
else if (TREE_CODE (gnu_result) == LABEL_DECL
|| TREE_CODE (gnu_result) == FIELD_DECL
|| TREE_CODE (gnu_result) == ERROR_MARK
- || (TYPE_SIZE (gnu_result_type)
- TREE_CODE (TYPE_SIZE (gnu_result_type)) != INTEGER_CST
- TREE_CODE (gnu_result) != INDIRECT_REF
- CONTAINS_PLACEHOLDER_P (TYPE_SIZE (gnu_result_type)))
- || ((TYPE_NAME (gnu_result_type)
- == TYPE_NAME (TREE_TYPE (gnu_result)))
+ || (TYPE_NAME (gnu_result_type)
+ == TYPE_NAME (TREE_TYPE (gnu_result))
TREE_CODE (gnu_result_type) == RECORD_TYPE
TREE_CODE (TREE_TYPE (gnu_result)) == RECORD_TYPE))
{
-- { dg-do run }
-- { dg-options -gnatws }
procedure Derived_Type2 is
package Pkg is
type Parent (B : Boolean := True) is record
case B is
when True = S : String (1 .. 5);
when False = F : Float;
end case;
end record;
function Create (X : Parent) return Parent;
end Pkg;
package body Pkg is
function Create (X : Parent) return Parent is
begin
return (True, 12345);
end;
end Pkg;
use Pkg;
type T is new Parent (True);
X : T;
begin
if Create (X).B /= True then
raise Program_Error;
end if;
end;
Re: [PATCH PING] fortran-specific bits of tree-slimming patches
On 03/24/2011 06:10 AM, Nathan Froyd wrote: The Fortran-specific bits of these patches: [PATCH 02/18] enforce TREE_CHAIN and TREE_TYPE accesses http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00565.html [PATCH 07/18] generalize build_case_label to the rest of the compiler http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00557.html [PATCH 17/18] introduce block_chainon and use BLOCK_CHAIN more http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00566.html are still pending review. -Nathan gfortran parts OK. Jerry
[debug] Remove deprecated DW_FORM_sig8 define
Hi,
While reading through the unit type support I noticed some parts were
still using the old DW_FORM_sig8 while others used the actual
DW_FORM_ref_sig8 as used in the dwarf spec. I missed some things in a
first scan because of this, so I thought I just clean it up.
2010-03-24 Mark Wielaard m...@redhat.com
* dwarf2.h (dwarf_form): Remove deprecated DW_FORM_sig8 define.
2011-03-24 Mark Wielaard m...@redhat.com
* dwarf2out.c (size_of_die): Modify comment to say DW_FORM_ref_sig8.
(value_format): Use DW_FORM_ref_sig8, not DW_FORM_sig8.
binutils already only uses the new definition.
I have a similar cleanup patch for gdb.
OK, to commit?
Thanks,
Mark
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9dec3e4..41d55bf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-24 Mark Wielaard m...@redhat.com
+
+ * dwarf2out.c (size_of_die): Modify comment to say DW_FORM_ref_sig8.
+ (value_format): Use DW_FORM_ref_sig8, not DW_FORM_sig8.
+
2011-03-24 Richard Guenther rguent...@suse.de
PR tree-optimization/46562
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index aa6f6b6..bc05982 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -10729,7 +10729,7 @@ size_of_die (dw_die_ref die)
case dw_val_class_die_ref:
if (AT_ref_external (a))
{
- /* In DWARF4, we use DW_FORM_sig8; for earlier versions
+ /* In DWARF4, we use DW_FORM_ref_sig8; for earlier versions
we use DW_FORM_ref_addr. In DWARF2, DW_FORM_ref_addr
is sized by target address length, whereas in DWARF3
it's always sized as an offset. */
@@ -11005,7 +11005,7 @@ value_format (dw_attr_ref a)
return DW_FORM_flag;
case dw_val_class_die_ref:
if (AT_ref_external (a))
- return dwarf_version = 4 ? DW_FORM_sig8 : DW_FORM_ref_addr;
+ return dwarf_version = 4 ? DW_FORM_ref_sig8 : DW_FORM_ref_addr;
else
return DW_FORM_ref;
case dw_val_class_fde_ref:
diff --git a/include/ChangeLog b/include/ChangeLog
index a0585b0..4a09ab6 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2010-03-24 Mark Wielaard m...@redhat.com
+
+ * dwarf2.h (dwarf_form): Remove deprecated DW_FORM_sig8 define.
+
2010-03-23 Rafael Ávila de Espíndola respind...@mozilla.com
* plugin-api.h (ld_plugin_get_view): New.
diff --git a/include/dwarf2.h b/include/dwarf2.h
index 46f2291..ef0fa5f 100644
--- a/include/dwarf2.h
+++ b/include/dwarf2.h
@@ -189,7 +189,6 @@ enum dwarf_form
DW_FORM_exprloc = 0x18,
DW_FORM_flag_present = 0x19,
DW_FORM_ref_sig8 = 0x20
-#define DW_FORM_sig8 DW_FORM_ref_sig8 /* Note: The use of DW_FORM_sig8 is deprecated. */
};
/* Attribute names and codes. */
Tighten ARM's CANNOT_CHANGE_MODE_CLASS
We currently generate very poor code for tests like:
#include arm_neon.h
void
foo (uint32_t *a, uint32_t *b, uint32_t *c)
{
uint32x4x3_t x, y;
x = vld3q_u32 (a);
y = vld3q_u32 (b);
x.val[0] = vaddq_u32 (x.val[0], y.val[0]);
x.val[1] = vaddq_u32 (x.val[1], y.val[1]);
x.val[2] = vaddq_u32 (x.val[2], y.val[2]);
vst3q_u32 (a, x);
}
This is because we force the uint32x4x3_t values to the stack and
then load and store the individual vectors.
What we actually want is for the uint32x4x3_t values to be stored
in registers, and for the individual vectors to be accessed as
subregs of those registers. The first part involves some middle-end
mode changes (see recent gcc@ thread), while the second part requires
a change to ARM's CANNOT_CHANGE_MODE_CLASS.
CANNOT_CHANGE_MODE_CLASS is defined as:
/* FPA registers can't do subreg as all values are reformatted to internal
precision. VFP registers may only be accessed in the mode they
were set. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (FPA_REGS, (CLASS))\
|| reg_classes_intersect_p (VFP_REGS, (CLASS)) \
: 0)
But this VFP restriction appears to apply only to VFPv1; thanks to
Peter Maydell for the archaeology.
Tested on arm-linux-gnueabi. OK to install?
This doesn't have any direct benefit without the middle-end mode change,
but it needs to go in first in order for that change not to regress.
Richard
gcc/
* config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS
case to VFPv1.
Index: gcc/config/arm/arm.h
===
--- gcc/config/arm/arm.h2011-03-24 13:47:14.0 +
+++ gcc/config/arm/arm.h2011-03-24 15:26:19.0 +
@@ -1167,12 +1167,14 @@ #define IRA_COVER_CLASSES
\
}
/* FPA registers can't do subreg as all values are reformatted to internal
- precision. VFP registers may only be accessed in the mode they
+ precision. VFPv1 registers may only be accessed in the mode they
were set. */
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
- (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
- ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
- || reg_classes_intersect_p (VFP_REGS, (CLASS))\
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
+ ? (reg_classes_intersect_p (FPA_REGS, (CLASS)) \
+ || (TARGET_VFP \
+ arm_fpu_desc-rev == 1 \
+ reg_classes_intersect_p (VFP_REGS, (CLASS \
: 0)
/* The class value for index registers, and the one for base regs. */
Re: [x32] PATCH: PR middle-end/47725: [x32] error: unable to find a register to spill in class DIREG
Pointer is promoted to Pmode from ptr_mode.
Indeed. However the problem is the 2 in assign_parm_setup_reg:
/* Store the parm in a pseudoregister during the function, but we may
need to do it in a wider mode. Using 2 here makes the result
consistent with promote_decl_mode and thus expand_expr_real_1. */
promoted_nominal_mode
= promote_function_mode (data-nominal_type, data-nominal_mode, unsignedp,
TREE_TYPE (current_function_decl), 2);
which is supposed to match the 2 in promote_decl_mode:
if (TREE_CODE (decl) == RESULT_DECL
|| TREE_CODE (decl) == PARM_DECL)
pmode = promote_function_mode (type, mode, unsignedp,
TREE_TYPE (current_function_decl), 2);
else
pmode = promote_mode (type, mode, unsignedp);
but doesn't match the 0 in assign_parm_find_data_types:
promoted_mode = promote_function_mode (passed_type, passed_mode, unsignedp,
TREE_TYPE (current_function_decl), 0);
so you get the redundant extension in the callee. The solution is to define
the promote_function_mode hook for x86 to something like:
static enum machine_mode
ix86_promote_function_mode (const_tree type,
enum machine_mode mode,
int *punsignedp,
const_tree fntype ATTRIBUTE_UNUSED,
int for_return ATTRIBUTE_UNUSED)
{
if (POINTER_TYPE_P (type))
{
*punsignedp = POINTERS_EXTEND_UNSIGNED;
return Pmode;
}
return mode;
}
--
Eric Botcazou
Tweak ARM vld3q and vld4q patterns
The ARM vld3q and vld4q .md patterns expand into two individual vld3/vld4
instructions. Each instruction loads half of the total elements.
The problem is that this is implemented as:
array = vld3a (array, mem1)
array = vld3b (array, mem2)
with array being an input to the _first_ load as well as the second.
This input is dead, but results in unnecessary loads from the stack.
E.g. for:
#include arm_neon.h
void
foo (uint32_t *a, uint32_t *b, uint32_t *c)
{
uint32x4x3_t x, y;
x = vld3q_u32 (a);
y = vld3q_u32 (b);
x.val[0] = vaddq_u32 (x.val[0], y.val[0]);
x.val[1] = vaddq_u32 (x.val[1], y.val[1]);
x.val[2] = vaddq_u32 (x.val[2], y.val[2]);
vst3q_u32 (a, x);
}
we get:
stmfd sp!, {r3, fp}
ldr r2, .L2
add fp, sp, #4
vldmia r2, {d16-d21}
sub sp, sp, #112
vmovq11, q8 @ ti
vmovq12, q9 @ ti
vmovq13, q10 @ ti
...
where the vldmia is loading the x and y inputs to the two vld3q_u32s
from the corresponding stack slots.
It's true that vld?a doesn't _change_ the whole of the array,
but that doesn't matter; we no longer care what values the
other elements have.
Tested on arm-linux-gnueabi. OK to install?
Richard
gcc/
* config/arm/neon.md (neon_vld3qamode, neon_vld4qamode): Remove
operand 1 and reshuffle the operands to match.
(neon_vld3mode, neon_vld4mode): Update accordingly.
Index: gcc/config/arm/neon.md
===
--- gcc/config/arm/neon.md 2011-03-24 13:47:13.0 +
+++ gcc/config/arm/neon.md 2011-03-24 15:51:59.0 +
@@ -4605,8 +4605,7 @@ (define_expand neon_vld3mode
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
TARGET_NEON
{
- emit_insn (gen_neon_vld3qamode (operands[0], operands[0],
-operands[1], operands[1]));
+ emit_insn (gen_neon_vld3qamode (operands[0], operands[1], operands[1]));
emit_insn (gen_neon_vld3qbmode (operands[0], operands[0],
operands[1], operands[1]));
DONE;
@@ -4614,12 +4613,11 @@ (define_expand neon_vld3mode
(define_insn neon_vld3qamode
[(set (match_operand:CI 0 s_register_operand =w)
-(unspec:CI [(mem:CI (match_operand:SI 3 s_register_operand 2))
-(match_operand:CI 1 s_register_operand 0)
+(unspec:CI [(mem:CI (match_operand:SI 2 s_register_operand 1))
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD3A))
- (set (match_operand:SI 2 s_register_operand =r)
-(plus:SI (match_dup 3)
+ (set (match_operand:SI 1 s_register_operand =r)
+(plus:SI (match_dup 2)
(const_int 24)))]
TARGET_NEON
{
@@ -4628,7 +4626,7 @@ (define_insn neon_vld3qamode
ops[0] = gen_rtx_REG (DImode, regno);
ops[1] = gen_rtx_REG (DImode, regno + 4);
ops[2] = gen_rtx_REG (DImode, regno + 8);
- ops[3] = operands[2];
+ ops[3] = operands[1];
output_asm_insn (vld3.V_sz_elem\t{%P0, %P1, %P2}, [%3]!, ops);
return ;
}
@@ -4897,8 +4895,7 @@ (define_expand neon_vld4mode
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
TARGET_NEON
{
- emit_insn (gen_neon_vld4qamode (operands[0], operands[0],
-operands[1], operands[1]));
+ emit_insn (gen_neon_vld4qamode (operands[0], operands[1], operands[1]));
emit_insn (gen_neon_vld4qbmode (operands[0], operands[0],
operands[1], operands[1]));
DONE;
@@ -4906,12 +4903,11 @@ (define_expand neon_vld4mode
(define_insn neon_vld4qamode
[(set (match_operand:XI 0 s_register_operand =w)
-(unspec:XI [(mem:XI (match_operand:SI 3 s_register_operand 2))
-(match_operand:XI 1 s_register_operand 0)
+(unspec:XI [(mem:XI (match_operand:SI 2 s_register_operand 1))
(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_VLD4A))
- (set (match_operand:SI 2 s_register_operand =r)
-(plus:SI (match_dup 3)
+ (set (match_operand:SI 1 s_register_operand =r)
+(plus:SI (match_dup 2)
(const_int 32)))]
TARGET_NEON
{
@@ -4921,7 +4917,7 @@ (define_insn neon_vld4qamode
ops[1] = gen_rtx_REG (DImode, regno + 4);
ops[2] = gen_rtx_REG (DImode, regno + 8);
ops[3] = gen_rtx_REG (DImode, regno + 12);
- ops[4] = operands[2];
+ ops[4] = operands[1];
output_asm_insn (vld4.V_sz_elem\t{%P0, %P1, %P2, %P3}, [%4]!, ops);
return ;
}
[debug] dwarf2out emits unnecessary null byte in empty .debug_abbrev section
Hi, Detected by the elfutils dwarflint tool. Example: $ echo empty.c $ gcc -g -c empty.c $ readelf -x .debug_abbrev empty.o Hex dump of section '.debug_abbrev': 0x 00 . Although harmless it might add up if a project has a lot of objects without any real debuginfo in them. There might not actually be many such projects though. 2011-03-24 Mark Wielaard m...@redhat.com PR debug/48041 * dwarf2out.c (output_abbrev_section): Only terminate table when abbrev_die_table_in_use 1. Bootstraps fine on x86_64-gnu-linux and no regressions seen with make check -k OK, to commit? Thanks, Mark --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -11084,7 +11084,8 @@ output_abbrev_section (void) } /* Terminate the table. */ - dw2_asm_output_data (1, 0, NULL); + if (abbrev_die_table_in_use 1) +dw2_asm_output_data (1, 0, NULL); } /* Output a symbol we can use to refer to this DIE from another CU. */
Re: [PATCH, C++ testsuite] Fix g++.dg/abi/arm_cxa_vec1.C
On Thu, 2011-03-03 at 11:35 +, Yufeng Zhang wrote: Hi, Here is a patch that fixes a problem in one g++ test case. A typo (of using the macro ___ARM_EABI__ rather than __ARM_EABI__) has made the original test case almost a NOP. Also with a few other changes that make the test work properly. I have already tested the updated test case that it still passes with arm-eabi as an expected pass and passes with x86 as an unsupported test. OK for the trunk? Thanks, Yufeng 2011-03-03 Yufeng Zhang yufeng.zh...@arm.com * g++.dg/abi/arm_cxa_vec1.C: Correct the typos/errors in the test case. OK. R.
[libgo] Improve Solaris 2/SPARC support
In order to improve Go test results on Solaris 2/SPARC, I need the
following patch.
* go-test.exp wasn't updated for the change from sparcv9 to sparc64.
While I still don't agree with the new name, at least the two should
be consistent.
* env.go needs to accept sparc and sparc64.
* Just like 32-bit Solaris 2/x86, 32-bit Solaris 2/SPARC needs to use
the largefile variants of several functions. I've not introduced a
new LIBGO_IS_SOLARIS32 conditional for that, but perhaps one should?
With this patch, results are considerably improved, though still not
good: the rpc and websocket tests hang indefinitely, as reported in PR
go/48242, so one cannot include Go in a default bootstrap. I'll
investigate those shortly. Apart from that, many tests fail, cf. PR
go/48243.
I'll have a look at them in the future, but wanted the get the
low-hanging fruit out of the door.
Rainer
2011-03-24 Rainer Orth r...@cebitec.uni-bielefeld.de
go:
* go.test/go-test.exp (go-set-goarch): Use sparc64 for 64-bit SPARC.
* go.test/test/env.go (main): Handle sparc, sparc64.
libgo:
* Makefile.am (go_os_dir_file) [LIBGO_IS_SPARC]: Use
go/os/dir_largefile.go.
(syscall_filesize_file) [LIBGO_IS_SPARC]: Use
syscalls/sysfile_largefile.go.
(syscall_stat_file) [LIBGO_IS_SPARC]: Use
syscalls/sysfile_stat_largefile.go.
* Makefile.in: Regenerate.
diff -r de1b3baf021b gcc/testsuite/go.test/go-test.exp
--- a/gcc/testsuite/go.test/go-test.exp Thu Mar 24 13:19:30 2011 +0100
+++ b/gcc/testsuite/go.test/go-test.exp Thu Mar 24 13:22:43 2011 +0100
@@ -129,7 +129,7 @@
if [check_effective_target_ilp32] {
set goarch sparc
} else {
- set goarch sparcv9
+ set goarch sparc64
}
}
default {
diff -r de1b3baf021b gcc/testsuite/go.test/test/env.go
--- a/gcc/testsuite/go.test/test/env.go Thu Mar 24 13:19:30 2011 +0100
+++ b/gcc/testsuite/go.test/test/env.go Thu Mar 24 13:22:43 2011 +0100
@@ -1,7 +1,7 @@
// [ $GOOS != nacl ] || exit 0 # NaCl runner does not expose environment
// $G $F.go $L $F.$A ./$A.out
-// Copyright 2009 The Go Authors. All rights reserved.
+// Copyright 2009, 2011 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
@@ -15,7 +15,8 @@
print($GOARCH: , e0.String(), \n)
os.Exit(1)
}
- if ga != amd64 ga != 386 ga != arm {
+ if ga != 386 ga != amd64 ga != arm ga != sparc
+ ga != sparc64 {
print($GOARCH=, ga, \n)
os.Exit(1)
}
diff -r de1b3baf021b libgo/Makefile.am
--- a/libgo/Makefile.am Thu Mar 24 13:19:30 2011 +0100
+++ b/libgo/Makefile.am Thu Mar 24 13:22:43 2011 +0100
@@ -676,8 +676,12 @@
if LIBGO_IS_386
go_os_dir_file = go/os/dir_largefile.go
else
+if LIBGO_IS_SPARC
+go_os_dir_file = go/os/dir_largefile.go
+else
go_os_dir_file = go/os/dir_regfile.go
endif
+endif
else
if LIBGO_IS_LINUX
go_os_dir_file = go/os/dir_largefile.go
@@ -1188,16 +1192,21 @@
syscall_stat_file = syscalls/sysfile_stat_largefile.go
else # !LIBGO_IS_LINUX
if LIBGO_IS_SOLARIS
-# FIXME: Same for sparc vs. sparc64. Introduce new/additional conditional?
if LIBGO_IS_386
-# Use lseek64 on 386 Solaris.
+# Use lseek64 on 32-bit Solaris/x86.
syscall_filesize_file = syscalls/sysfile_largefile.go
syscall_stat_file = syscalls/sysfile_stat_largefile.go
-else # !LIBGO_IS_LINUX LIBGO_IS_SOLARIS !LIBGO_IS_386
-# Use lseek on amd64 Solaris.
+else # !LIBGO_IS_386
+if LIBGO_IS_SPARC
+# Use lseek64 on 32-bit Solaris/SPARC.
+syscall_filesize_file = syscalls/sysfile_largefile.go
+syscall_stat_file = syscalls/sysfile_stat_largefile.go
+else # !LIBGO_IS_386 !LIBGO_IS_SPARC
+# Use lseek on 64-bit Solaris.
syscall_filesize_file = syscalls/sysfile_regfile.go
syscall_stat_file = syscalls/sysfile_stat_regfile.go
-endif # !LIBGO_IS_386
+endif # !LIBGO_IS_386 !LIBGO_IS_SPARC
+endif # !LIBGO_IS_SOLARIS
else # !LIBGO_IS_LINUX !LIBGO_IS_SOLARIS
# Use lseek by default.
syscall_filesize_file = syscalls/sysfile_regfile.go
--
-
Rainer Orth, Center for Biotechnology, Bielefeld University
Re: Remove old host cases from toplevel configure
On 03/24/2011 03:11 PM, Joseph S. Myers wrote: Furthermore, the whole idea of the toplevel configure tentative_cc setting code is dubious since this is an autoconf-generated script and it's autoconf's job to deal with finding a working compiler, putting it in ANSI C mode, etc. - so if someone did wish to resupport one of these hosts (and in the unlikely event that building current tools using the old system compiler is at all possible) it would be better to put system-specific pieces in autoconf and make toolchain configure code work using features not host triplet tests as far as possible. 100% agreed, I've meant to clean this up for a long time. OK to commit? Yes, thank you very much. Paolo
[libgo] Support Solaris 8/9
When I tried to build libgo on Solaris 9/x86 with native tools, I ran into a couple of issues: * To correctly build sysinfo.go, one needs a different set of flags to compile sysinfo.c that conflict with the onces needed on Solaris 10+. Since there seems to be no easy way to autoconf this knowledge, I'm hardcoding it in configure.ac (OSCFLAGS) and pass it to mksysinfo.sh. * As documented in the Autoconf manual, the native grep cannot handle \|. One needs to use egrep for that instead. I've only updated the affected invocations, but one may want (or need) to either do this wholesale and/or replace the hardcoded egrep by autoconfed $EGREP. * Similarly, native sed cannot handle \?, so I'm substituting both alternatives in sequence. * For native TLS to work, libgo needs to be linked with -pthread, so libthread.so is included in the link. On Solaris 8, -pthread takes care of even more contortions necessary to get the proper thread library. In order for that to happen, I've introduced libgo_la_LDFLAGS. With those changes (and the strerror_r replacement since Solaris 8 and 9 also lack that function), I could successfully build and test libgo, with relatively decent results: FAIL: fmt Can't open -n grep: can't open -n grep: can't open -n mallocs per Sprintf(): 1 mallocs per Sprintf(xxx): 1 mallocs per Sprintf(%x): 3 mallocs per Sprintf(%x %x): 4 /vol/gcc/src/hg/trunk/local/libgo/testsuite/gotest[325]: 22734 Segmentation Fault make: *** [fmt/check] Error 1 FAIL: archive/zip Can't open -n grep: can't open -n grep: can't open -n --- FAIL: zip.TestReader (0.0 seconds) error=open testdata/dd.zip: No such file or directory, want nil FAIL make: *** [archive/zip/check] Error 1 FAIL: crypto/rand Can't open -n grep: can't open -n grep: can't open -n --- FAIL: rand.TestRead (0.0 seconds) Read(buf) = 1040, %!s(nil) FAIL make: *** [crypto/rand/check] Error 1 FAIL: image/png Can't open -n grep: can't open -n grep: can't open -n --- FAIL: png.TestReader (1.0 seconds) basn0g01-30 open testdata/pngsuite/basn0g01-30.png: No such file or directory basn0g02-29 open testdata/pngsuite/basn0g02-29.png: No such file or directory basn0g04-31 open testdata/pngsuite/basn0g04-31.png: No such file or directory --- FAIL: png.TestWriter (0.2 seconds) basn0g01-30 open testdata/pngsuite/basn0g01-30.png: No such file or directory basn0g02-29 open testdata/pngsuite/basn0g02-29.png: No such file or directory basn0g04-31 open testdata/pngsuite/basn0g04-31.png: No such file or directory FAIL make: *** [image/png/check] Error 1 I'll be running make check-go shortly. Rainer 2011-03-24 Rainer Orth r...@cebitec.uni-bielefeld.de * configure.ac (OSCFLAGS): Define. * Makefile.am (s-sysinfo): Use it. (libgo_la_LDFLAGS): Define. * mksysinfo.sh (sysinfo.c) [__sun__ __svr4__]: Remove. Replace \| in grep REs with egrep and |. Replace \? in sed REs with two variants. * Makefile.in: Regenerate. * configure: Regenerate. diff -r 75d0e839ffe1 libgo/Makefile.am --- a/libgo/Makefile.am Thu Mar 24 13:22:54 2011 +0100 +++ b/libgo/Makefile.am Thu Mar 24 16:45:53 2011 +0100 @@ -1459,6 +1459,8 @@ libgo_la_SOURCES = $(runtime_files) +libgo_la_LDFLAGS = $(PTHREAD_CFLAGS) + libgo_la_LIBADD = \ $(libgo_go_objs) $(LIBFFI) $(PTHREAD_LIBS) $(MATH_LIBS) $(NET_LIBS) @@ -2512,7 +2514,7 @@ sysinfo.go: s-sysinfo; @true s-sysinfo: $(srcdir)/mksysinfo.sh config.h - CC=$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(SHELL) $(srcdir)/mksysinfo.sh + CC=$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(OSCFLAGS) $(SHELL) $(srcdir)/mksysinfo.sh $(SHELL) $(srcdir)/../move-if-change tmp-sysinfo.go sysinfo.go $(STAMP) $@ diff -r 75d0e839ffe1 libgo/configure.ac --- a/libgo/configure.acThu Mar 24 13:22:54 2011 +0100 +++ b/libgo/configure.acThu Mar 24 16:45:53 2011 +0100 @@ -229,6 +229,22 @@ fi AC_SUBST(GO_DEBUG_PROC_REGS_OS_ARCH_FILE) +dnl Some targets need special flags to build sysinfo.go. +case $target in +*-*-solaris2.[[89]]) + # Solaris 8/9 need this so struct msghdr gets the msg_control + # etc. fields in sys/socket.h (_XPG4_2). + OSCFLAGS='-D_XOPEN_SOURCE=500 -D_XOPEN_SOURCE_EXTENDED -D__EXTENSIONS__' + ;; +*-*-solaris2.1[[01]]) + # Solaris 10+ needs this so struct msghdr gets the msg_control + # etc. fields in sys/socket.h (_XPG4_2). _XOPEN_SOURCE=500 as + # above doesn't work with C99. + OSCFLAGS='-D_XOPEN_SOURCE=600 -D__EXTENSIONS__' + ;; +esac +AC_SUBST(OSCFLAGS) + dnl Use -fsplit-stack when compiling C code if available. AC_CACHE_CHECK([whether -fsplit-stack is supported], [libgo_cv_c_split_stack_supported], diff -r 75d0e839ffe1 libgo/mksysinfo.sh --- a/libgo/mksysinfo.shThu Mar 24 13:22:54 2011 +0100 +++
Re: Tighten ARM's CANNOT_CHANGE_MODE_CLASS
On Thu, 2011-03-24 at 15:40 +, Richard Sandiford wrote:
We currently generate very poor code for tests like:
#include arm_neon.h
void
foo (uint32_t *a, uint32_t *b, uint32_t *c)
{
uint32x4x3_t x, y;
x = vld3q_u32 (a);
y = vld3q_u32 (b);
x.val[0] = vaddq_u32 (x.val[0], y.val[0]);
x.val[1] = vaddq_u32 (x.val[1], y.val[1]);
x.val[2] = vaddq_u32 (x.val[2], y.val[2]);
vst3q_u32 (a, x);
}
This is because we force the uint32x4x3_t values to the stack and
then load and store the individual vectors.
What we actually want is for the uint32x4x3_t values to be stored
in registers, and for the individual vectors to be accessed as
subregs of those registers. The first part involves some middle-end
mode changes (see recent gcc@ thread), while the second part requires
a change to ARM's CANNOT_CHANGE_MODE_CLASS.
CANNOT_CHANGE_MODE_CLASS is defined as:
/* FPA registers can't do subreg as all values are reformatted to internal
precision. VFP registers may only be accessed in the mode they
were set. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
|| reg_classes_intersect_p (VFP_REGS, (CLASS)) \
: 0)
But this VFP restriction appears to apply only to VFPv1; thanks to
Peter Maydell for the archaeology.
Tested on arm-linux-gnueabi. OK to install?
This doesn't have any direct benefit without the middle-end mode change,
but it needs to go in first in order for that change not to regress.
Richard
gcc/
* config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS
case to VFPv1.
GCC doesn't support VFPv1 (see the all_fpus table), and I don't think
many chips based on that ever escaped into the wild world, so I'm not
worried about trying to add that now.
So it's probably safe to just kill that check for VFP entirely.
R.
Re: [PATCH] reload: Avoid superfluous reloads after find_reloads_subreg_address
Andreas Krebbel wrote: 2011-03-23 Andreas Krebbel andreas.kreb...@de.ibm.com * reload.c (find_reloads_subreg_address): Add address_reloaded parameter and return true there if the full address has been reloaded. (find_reloads_toplev): Pass address_reloaded flag. (find_reloads_address_1): Don't use address_reloaded parameter. This is OK. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com
cleanup host fragments more 1/n
AR_CFLAGS = cr is already the default. Committed to gcc and src. Paolo 2011-03-24 Paolo Bonzini bonz...@gnu.org * mh-sysv4: Remove AR_CFLAGS. Index: mh-sysv4 === --- mh-sysv4(revision 171413) +++ mh-sysv4(working copy) @@ -1,4 +1 @@ -# The l flag generates a warning from the SVR4 archiver, remove it. -AR_FLAGS = cr - X11_EXTRA_LIBS = -lnsl
[v3] Fix negative_binomial_distribution
Hi,
this does fix a bad thinko of mine in negative_binomial_distribution
(the fix will certainly go in 4.6.1, unless Jakub wants it now) + I'm
adding basic statistical tests (adapted from GSL) for all the other
discrete distributions.
Thanks,
Paolo.
//
2011-03-24 Paolo Carlini paolo.carl...@oracle.com
* include/bits/random.h (negative_binomial_distribution::
negative_binomial_distribution(_IntType, double),
negative_binomial_distribution::
negative_binomial_distribution(const param_type)): Fix
construction of _M_gd.
* include/bits/random.tcc (negative_binomial_distribution::
operator()): Fix computation, per Leger's algorithm.
* testsuite/util/testsuite_random.h (discrete_pdf,
negative_binomial_pdf, poisson_pdf, uniform_int_pdf): New.
(binomial_pdf): Swap last two parameters.
* testsuite/26_numerics/random/discrete_distribution/
operators/values.cc: New.
* testsuite/26_numerics/random/negative_binomial_distribution/
operators/values.cc: Likewise.
* testsuite/26_numerics/random/poisson_distribution/
operators/values.cc: Likewise.
* testsuite/26_numerics/random/uniform_int_distribution/
operators/values.cc: Likewise.
* testsuite/26_numerics/random/binomial_distribution/
operators/values.cc: Adjust.Index: include/bits/random.tcc
===
--- include/bits/random.tcc (revision 171401)
+++ include/bits/random.tcc (working copy)
@@ -1075,7 +1075,7 @@
return __is;
}
-
+ // This is Leger's algorithm.
templatetypename _IntType
templatetypename _UniformRandomNumberGenerator
typename negative_binomial_distribution_IntType::result_type
@@ -1085,7 +1085,8 @@
const double __y = _M_gd(__urng);
// XXX Is the constructor too slow?
- std::poisson_distributionresult_type __poisson(__y);
+ std::poisson_distributionresult_type __poisson(__y * (1.0 - p())
+/ p());
return __poisson(__urng);
}
@@ -1099,10 +1100,10 @@
typedef typename std::gamma_distributionresult_type::param_type
param_type;
- const double __y =
- _M_gd(__urng, param_type(__p.k(), __p.p() / (1.0 - __p.p(;
+ const double __y = _M_gd(__urng, param_type(__p.k(), 1.0));
- std::poisson_distributionresult_type __poisson(__y);
+ std::poisson_distributionresult_type __poisson(__y * (1.0 - __p.p())
+/ __p.p() );
return __poisson(__urng);
}
Index: include/bits/random.h
===
--- include/bits/random.h (revision 171401)
+++ include/bits/random.h (working copy)
@@ -3611,8 +3611,7 @@
param_type(double __p = 0.5)
: _M_p(__p)
{
- _GLIBCXX_DEBUG_ASSERT((_M_p 0.0)
- (_M_p 1.0));
+ _GLIBCXX_DEBUG_ASSERT((_M_p 0.0) (_M_p 1.0));
_M_initialize();
}
@@ -3782,7 +3781,9 @@
explicit
param_type(_IntType __k = 1, double __p = 0.5)
: _M_k(__k), _M_p(__p)
- { }
+ {
+ _GLIBCXX_DEBUG_ASSERT((_M_k 0) (_M_p 0.0) (_M_p = 1.0));
+ }
_IntType
k() const
@@ -3803,12 +3804,12 @@
explicit
negative_binomial_distribution(_IntType __k = 1, double __p = 0.5)
- : _M_param(__k, __p), _M_gd(__k, __p / (1.0 - __p))
+ : _M_param(__k, __p), _M_gd(__k, 1.0)
{ }
explicit
negative_binomial_distribution(const param_type __p)
- : _M_param(__p), _M_gd(__p.k(), __p.p() / (1.0 - __p.p()))
+ : _M_param(__p), _M_gd(__p.k(), 1.0)
{ }
/**
Index: testsuite/26_numerics/random/uniform_int_distribution/operators/values.cc
===
--- testsuite/26_numerics/random/uniform_int_distribution/operators/values.cc
(revision 0)
+++ testsuite/26_numerics/random/uniform_int_distribution/operators/values.cc
(revision 0)
@@ -0,0 +1,50 @@
+// { dg-options -std=gnu++0x }
+// { dg-require-cstdint }
+//
+// Copyright (C) 2011 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public
Re: [patch middle-end c c++]: Optimize cost of comp_type_attributes
2011/3/24 Jason Merrill ja...@redhat.com:
How about splitting this out into a separate function that can compare
either list or expression arguments? That would also be useful for
merge_attributes and attribute_list_contained.
Jason
Ok, here is the patch
ChangeLog gcc/
2011-03-11 Kai Tietz
* c-typeck.c (comptypes_internal): Replace target
hook call of comp_type_attributes by version in tree.c file.
* gimple.c (gimple_types_compatible_p_1): Likewise.
* tree-ssa.c (useless_type_conversion_p): Likewise.
* tree.c (build_type_attribute_qual_variant): Likewise.
(attribute_equal): New static helper function.
(comp_type_attributes): New function.
(merge_attributes): Use attribute_equal for comparison.
(attribute_list_contained): Likewise.
* tree.h (comp_type_attributes): New prototype.
ChangeLog cp/
2011-03-11 Kai Tietz
* decl.c (decls_match): Replace target hook
call of comp_type_attributes by version in tree.c file.
* search.c (check_final_overrider): Likewise.
* typeck.c (structural_comptypes): Likewise.
Regards,
Kai
Index: gcc/gcc/c-typeck.c
===
--- gcc.orig/gcc/c-typeck.c 2011-03-24 08:23:42.441173500 +0100
+++ gcc/gcc/c-typeck.c 2011-03-24 09:24:53.445892300 +0100
@@ -1079,7 +1079,7 @@ comptypes_internal (const_tree type1, co
return 1;
/* 1 if no need for warning yet, 2 if warning cause has been seen. */
- if (!(attrval = targetm.comp_type_attributes (t1, t2)))
+ if (!(attrval = comp_type_attributes (t1, t2)))
return 0;
/* 1 if no need for warning yet, 2 if warning cause has been seen. */
Index: gcc/gcc/cp/decl.c
===
--- gcc.orig/gcc/cp/decl.c 2011-03-24 08:23:42.443173500 +0100
+++ gcc/gcc/cp/decl.c 2011-03-24 09:24:53.573408500 +0100
@@ -1012,8 +1012,8 @@ decls_match (tree newdecl, tree olddecl)
types_match =
compparms (p1, p2)
(TYPE_ATTRIBUTES (TREE_TYPE (newdecl)) == NULL_TREE
- || targetm.comp_type_attributes (TREE_TYPE (newdecl),
- TREE_TYPE (olddecl)) != 0);
+ || comp_type_attributes (TREE_TYPE (newdecl),
+ TREE_TYPE (olddecl)) != 0);
}
else
types_match = 0;
Index: gcc/gcc/cp/search.c
===
--- gcc.orig/gcc/cp/search.c2011-03-24 08:23:42.444173500 +0100
+++ gcc/gcc/cp/search.c 2011-03-24 09:24:53.645417600 +0100
@@ -1897,7 +1897,7 @@ check_final_overrider (tree overrider, t
}
/* Check for conflicting type attributes. */
- if (!targetm.comp_type_attributes (over_type, base_type))
+ if (!comp_type_attributes (over_type, base_type))
{
error (conflicting type attributes specified for %q+#D, overrider);
error ( overriding %q+#D, basefn);
Index: gcc/gcc/cp/typeck.c
===
--- gcc.orig/gcc/cp/typeck.c2011-03-24 08:23:42.495173500 +0100
+++ gcc/gcc/cp/typeck.c 2011-03-24 09:24:53.697424200 +0100
@@ -1338,7 +1338,7 @@ structural_comptypes (tree t1, tree t2,
/* If we get here, we know that from a target independent POV the
types are the same. Make sure the target attributes are also
the same. */
- return targetm.comp_type_attributes (t1, t2);
+ return comp_type_attributes (t1, t2);
}
/* Return true if T1 and T2 are related as allowed by STRICT. STRICT
Index: gcc/gcc/gimple.c
===
--- gcc.orig/gcc/gimple.c 2011-03-24 08:23:42.496173500 +0100
+++ gcc/gcc/gimple.c2011-03-24 09:24:53.793936500 +0100
@@ -3615,7 +3615,7 @@ gimple_types_compatible_p_1 (tree t1, tr
state, sccstack, sccstate, sccstate_obstack))
goto different_types;
- if (!targetm.comp_type_attributes (t1, t2))
+ if (!comp_type_attributes (t1, t2))
goto different_types;
if (TYPE_ARG_TYPES (t1) == TYPE_ARG_TYPES (t2))
Index: gcc/gcc/tree-ssa.c
===
--- gcc.orig/gcc/tree-ssa.c 2011-03-24 08:23:42.498173500 +0100
+++ gcc/gcc/tree-ssa.c 2011-03-24 09:24:53.831441200 +0100
@@ -1438,7 +1438,7 @@ useless_type_conversion_p (tree outer_ty
/* Defer to the target if necessary. */
if (TYPE_ATTRIBUTES (inner_type) || TYPE_ATTRIBUTES (outer_type))
- return targetm.comp_type_attributes (outer_type, inner_type) != 0;
+ return comp_type_attributes (outer_type, inner_type) != 0;
return true;
}
Index: gcc/gcc/tree.c
===
--- gcc.orig/gcc/tree.c 2011-03-24 08:23:42.499173500 +0100
+++ gcc/gcc/tree.c 2011-03-24
[toplevel] cleanup X11_FLAGS_TO_PASS
Yet another relic of cygnus configure. Eliminate.
Committed to gcc and (shortly) to src.
Paolo
2011-03-24 Paolo Bonzini bonz...@gnu.org
* configure.ac: Remove all mentions of mh-sysv4 and mh-solaris.
* configure: Regenerate.
* Makefile.def: Remove all mentions of X11_FLAGS_TO_PASS.
* Makefile.tpl: Likewise.
* Makefile.in: Regenerate.
config:
2011-03-24 Paolo Bonzini bonz...@gnu.org
* mh-sysv4: Remove.
* mh-solaris: Remove.
Index: configure.ac
===
--- configure.ac(revision 171415)
+++ configure.ac(working copy)
@@ -1037,9 +1037,6 @@ esac
host_makefile_frag=/dev/null
if test -d ${srcdir}/config ; then
case ${host} in
- i[[3456789]]86-*-solaris2*)
-host_makefile_frag=config/mh-sysv4
-;;
i[[3456789]]86-*-msdosdjgpp*)
host_makefile_frag=config/mh-djgpp
;;
@@ -1054,7 +1051,6 @@ case ${host} in
host_makefile_frag=config/mh-interix
;;
*-*-solaris2*)
-host_makefile_frag=config/mh-solaris
;;
hppa*-hp-hpux10*)
host_makefile_frag=config/mh-pa-hpux10
Index: config/mh-solaris
===
--- config/mh-solaris (revision 171414)
+++ config/mh-solaris (working copy)
@@ -1,2 +0,0 @@
-# Makefile changes for Suns running Solaris 2
-X11_EXTRA_LIBS = -lnsl -lsocket
2011-03-24 Joseph Myers jos...@codesourcery.com
Index: config/mh-sysv4
===
--- config/mh-sysv4 (revision 171414)
+++ config/mh-sysv4 (working copy)
@@ -1 +0,0 @@
-X11_EXTRA_LIBS = -lnsl
Index: Makefile.def
===
--- Makefile.def(revision 171414)
+++ Makefile.def(working copy)
@@ -134,10 +134,10 @@ host_modules= { module= uudecode; };
host_modules= { module= wdiff; };
host_modules= { module= zip; no_check_cross=true; };
host_modules= { module= zlib; no_install=true; no_check=true; bootstrap=true;
};
-host_modules= { module= gdb; extra_make_flags=$(X11_FLAGS_TO_PASS); };
-host_modules= { module= expect; extra_make_flags=$(X11_FLAGS_TO_PASS); };
-host_modules= { module= guile; extra_make_flags=$(X11_FLAGS_TO_PASS); };
-host_modules= { module= tk; extra_make_flags=$(X11_FLAGS_TO_PASS); };
+host_modules= { module= gdb; };
+host_modules= { module= expect; };
+host_modules= { module= guile; };
+host_modules= { module= tk; };
host_modules= { module= libtermcap; no_check=true;
missing=mostlyclean;
missing=clean;
Index: Makefile.in
===
--- Makefile.in (revision 169877)
+++ Makefile.in (working copy)
@@ -796,18 +796,6 @@ EXTRA_HOST_FLAGS = \
FLAGS_TO_PASS = $(BASE_FLAGS_TO_PASS) $(EXTRA_HOST_FLAGS)
-# Flags that are concerned with the location of the X11 include files
-# and library files
-#
-# NOTE: until the top-level is getting the values via autoconf, it only
-# causes problems to have this top-level Makefile overriding the autoconf-set
-# values in child directories. Only variables that don't conflict with
-# autoconf'ed ones should be passed by X11_FLAGS_TO_PASS for now.
-#
-X11_FLAGS_TO_PASS = \
- 'X11_EXTRA_CFLAGS=$(X11_EXTRA_CFLAGS)' \
- 'X11_EXTRA_LIBS=$(X11_EXTRA_LIBS)'
-
# Flags to pass to stage2 and later makes.
POSTSTAGE1_FLAGS_TO_PASS = \
@@ -42263,7 +42251,7 @@ all-gdb: configure-gdb
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(HOST_EXPORTS) \
(cd $(HOST_SUBDIR)/gdb \
- $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_HOST_FLAGS)
$(X11_FLAGS_TO_PASS) \
+ $(MAKE) $(BASE_FLAGS_TO_PASS) $(EXTRA_HOST_FLAGS) \
$(TARGET-gdb))
@endif gdb
@@ -42281,7 +42269,7 @@ check-gdb:
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(HOST_EXPORTS) \
(cd $(HOST_SUBDIR)/gdb \
- $(MAKE) $(FLAGS_TO_PASS) $(X11_FLAGS_TO_PASS) check)
+ $(MAKE) $(FLAGS_TO_PASS) check)
@endif gdb
@@ -42296,7 +42284,7 @@ install-gdb: installdirs
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(HOST_EXPORTS) \
(cd $(HOST_SUBDIR)/gdb \
- $(MAKE) $(FLAGS_TO_PASS) $(X11_FLAGS_TO_PASS) install)
+ $(MAKE) $(FLAGS_TO_PASS) install)
@endif gdb
@@ -42311,7 +42299,7 @@ install-strip-gdb: installdirs
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(HOST_EXPORTS) \
(cd $(HOST_SUBDIR)/gdb \
- $(MAKE) $(FLAGS_TO_PASS) $(X11_FLAGS_TO_PASS) install-strip)
+ $(MAKE) $(FLAGS_TO_PASS) install-strip)
@endif gdb
@@ -42329,7 +42317,7 @@ info-gdb: \
r=`${PWD_COMMAND}`; export r; \
s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \
$(HOST_EXPORTS) \
- for flag in $(EXTRA_HOST_FLAGS) $(X11_FLAGS_TO_PASS); do \
+ for flag in $(EXTRA_HOST_FLAGS) ; do \
eval `echo $$flag |
[toplevel] remove empty cases
This enables omit-frame-pointer for i386-solaris. I honestly haven't
bootstrapped it, but I don't expect any problems (and if they appear,
it's much better to fix them ;).
Committed to gcc and (shortly) to src.
Paolo
2011-03-24 Paolo Bonzini bonz...@gnu.org
* configure.ac: Remove empty cases.
* configure: Regenerate.
Index: configure.ac
===
--- configure.ac(revision 171416)
+++ configure.ac(working copy)
@@ -1050,8 +1050,6 @@ case ${host} in
*-interix*)
host_makefile_frag=config/mh-interix
;;
- *-*-solaris2*)
-;;
hppa*-hp-hpux10*)
host_makefile_frag=config/mh-pa-hpux10
;;
@@ -1061,8 +1059,6 @@ case ${host} in
hppa*-*)
host_makefile_frag=config/mh-pa
;;
- *-hp-hpux*)
-;;
*-*-darwin*)
host_makefile_frag=config/mh-darwin
;;
@@ -1072,8 +1068,6 @@ case ${host} in
rs6000-*-aix*)
host_makefile_frag=config/mh-ppc-aix
;;
- *-*-lynxos*)
-;;
# This is placed last to prevent interfering with the cases above.
i[[3456789]]86-*-*)
# Build the stage2 and stage3 compilers with -fomit-frame-pointer.
Index: configure
===
--- configure (revision 171416)
+++ configure (working copy)
@@ -3623,8 +3623,6 @@ fi
*-interix*)
host_makefile_frag=config/mh-interix
;;
- *-*-solaris2*)
-;;
hppa*-hp-hpux10*)
host_makefile_frag=config/mh-pa-hpux10
;;
@@ -3634,8 +3632,6 @@ fi
hppa*-*)
host_makefile_frag=config/mh-pa
;;
- *-hp-hpux*)
-;;
*-*-darwin*)
host_makefile_frag=config/mh-darwin
;;
@@ -3645,8 +3641,6 @@ fi
rs6000-*-aix*)
host_makefile_frag=config/mh-ppc-aix
;;
- *-*-lynxos*)
-;;
# This is placed last to prevent interfering with the cases above.
i[3456789]86-*-*)
# Build the stage2 and stage3 compilers with -fomit-frame-pointer.
Re: [toplevel] remove empty cases
On Thu, 24 Mar 2011, Paolo Bonzini wrote: This enables omit-frame-pointer for i386-solaris. I honestly haven't bootstrapped it, but I don't expect any problems (and if they appear, it's much better to fix them ;). How about killing mh-x86omitfp? The x86 compiler defaults to -fomit-frame-pointer on most platforms now anyway. -- Joseph S. Myers jos...@codesourcery.com
Re: [toplevel] remove empty cases
Joseph S. Myers jos...@codesourcery.com writes: On Thu, 24 Mar 2011, Paolo Bonzini wrote: This enables omit-frame-pointer for i386-solaris. I honestly haven't bootstrapped it, but I don't expect any problems (and if they appear, it's much better to fix them ;). How about killing mh-x86omitfp? The x86 compiler defaults to -fomit-frame-pointer on most platforms now anyway. I'd prefer that: Solaris 10+/x86 defaults to -fomit-frame-pointer for improved debuggability (cf. gcc/config/sol2-10.h: USE_IX86_FRAME_POINTER, USE_X86_64_FRAME_POINTER), so it would be better leave this to the individual platforms instead. Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
Commit: RX: Add alignment for jumps, loops and labels
Hi Guys,
I am applying the patch below to add alignment control for jumps,
loops and labels to the RX backend.
Tested without regressions on an rx-elf target.
Cheers
Nick
gcc/ChangeLog
2011-03-24 Nick Clifton ni...@redhat.com
* config/rx/rx.h (LABEL_ALIGN_FOR_BARRIER): Define.
(ASM_OUTPUT_MAX_SKIP_ALIGN): Define.
* config/rx/rx.c (rx_option_override): Set align_jumps,
align_loops and align_labels if not set by the user.
(rx_align_for_label): New function.
(rx_max_skip_for_label): New function.
(TARGET_ASM_JUMP_ALIGN_MAX_SKIP): Define.
(TARGET_ASM_LOOP_ALIGN_MAX_SKIP): Define.
(TARGET_ASM_LABEL_ALIGN_MAX_SKIP): Define.
(TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP): Define.
* config/rx/rx-protos.h (rx_align_for_label): Add prototype.
Index: gcc/config/rx/rx.h
===
--- gcc/config/rx/rx.h (revision 171417)
+++ gcc/config/rx/rx.h (working copy)
@@ -413,6 +413,25 @@
#undef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX _
+#define LABEL_ALIGN_AFTER_BARRIER(x) rx_align_for_label ()
+
+#define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP) \
+ do \
+{ \
+ if ((LOG) == 0 || (MAX_SKIP) == 0) \
+break; \
+ if (TARGET_AS100_SYNTAX) \
+ { \
+ if ((LOG) = 2) \
+ fprintf (STREAM, \t.ALIGN 4\t; %d alignment actually requested\n,
1 (LOG)); \
+ else \
+ fprintf (STREAM, \t.ALIGN 2\n); \
+ } \
+ else \
+ fprintf (STREAM, \t.balign %d,3,%d\n, 1 (LOG), (MAX_SKIP));
\
+} \
+ while (0)
+
#define ASM_OUTPUT_ALIGN(STREAM, LOG) \
do \
{ \
Index: gcc/config/rx/rx-protos.h
===
--- gcc/config/rx/rx-protos.h (revision 171417)
+++ gcc/config/rx/rx-protos.h (working copy)
@@ -26,6 +26,7 @@
#define Fargs CUMULATIVE_ARGS
#define Rcode enum rtx_code
+extern int rx_align_for_label (void);
extern voidrx_expand_prologue (void);
extern int rx_initial_elimination_offset (int, int);
Index: gcc/config/rx/rx.c
===
--- gcc/config/rx/rx.c (revision 171417)
+++ gcc/config/rx/rx.c (working copy)
@@ -2350,6 +2350,13 @@
flag_strict_volatile_bitfields = 1;
rx_override_options_after_change ();
+
+ if (align_jumps == 0 ! optimize_size)
+align_jumps = 3;
+ if (align_loops == 0 ! optimize_size)
+align_loops = 3;
+ if (align_labels == 0 ! optimize_size)
+align_labels = 3;
}
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
@@ -2740,8 +2747,47 @@
return true;
}
+
+int
+rx_align_for_label (void)
+{
+ return optimize_size ? 1 : 3;
+}
+static int
+rx_max_skip_for_label (rtx lab)
+{
+ int opsize;
+ rtx op;
+
+ if (lab == NULL_RTX)
+return 0;
+
+ op = lab;
+ do
+{
+ op = next_nonnote_nondebug_insn (op);
+}
+ while (op (LABEL_P (op)
+ || (INSN_P (op) GET_CODE (PATTERN (op)) == USE)));
+ if (!op)
+return 0;
+
+ opsize = get_attr_length (op);
+ if (opsize = 0 opsize 8)
+return opsize - 1;
+ return 0;
+}
+#undef TARGET_ASM_JUMP_ALIGN_MAX_SKIP
+#define TARGET_ASM_JUMP_ALIGN_MAX_SKIP rx_max_skip_for_label
+#undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
+#define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rx_max_skip_for_label
+#undef TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
+#define TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP rx_max_skip_for_label
+#undef TARGET_ASM_LABEL_ALIGN_MAX_SKIP
+#define TARGET_ASM_LABEL_ALIGN_MAX_SKIP
rx_max_skip_for_label
+
#undef TARGET_FUNCTION_VALUE
#define TARGET_FUNCTION_VALUE rx_function_value
Re: [toplevel] remove empty cases
On 03/24/2011 06:18 PM, Joseph S. Myers wrote:
On Thu, 24 Mar 2011, Paolo Bonzini wrote:
This enables omit-frame-pointer for i386-solaris. I honestly haven't
bootstrapped it, but I don't expect any problems (and if they appear, it's
much better to fix them;).
How about killing mh-x86omitfp? The x86 compiler defaults to
-fomit-frame-pointer on most platforms now anyway.
Sounds good.
Paolo
2011-03-24 Paolo Bonzini bonz...@gnu.org
* configure.ac: Do not include mh-x86omitfp.
* configure: Regenerate.
config:
2011-03-24 Paolo Bonzini bonz...@gnu.org
* mh-x86omitfp: Remove.
Index: configure.ac
===
--- configure.ac(revision 171419)
+++ configure.ac(working copy)
@@ -1068,11 +1068,6 @@ case ${host} in
rs6000-*-aix*)
host_makefile_frag=config/mh-ppc-aix
;;
- # This is placed last to prevent interfering with the cases above.
- i[[3456789]]86-*-*)
-# Build the stage2 and stage3 compilers with -fomit-frame-pointer.
-host_makefile_frag=config/mh-x86omitfp
-;;
esac
fi
Index: config/mh-x86omitfp
===
--- config/mh-x86omitfp (revision 171414)
+++ config/mh-x86omitfp (working copy)
@@ -1,2 +0,0 @@
-# Add -fomit-frame-pointer to the usual BOOT_CFLAGS to speed up the compiler.
-BOOT_CFLAGS += -fomit-frame-pointer
Re: Can't use SImode as Pmode for x32
On 03/23/2011 08:40 PM, H.J. Lu wrote: Are you suggesting that we should say that SP and BP are 32bits so that x32 has 16 integer registers, 14 are 64 bites and 2 are 32 bits? No, merely that push/pop are valid with (reg:SI 7 sp). r~
[patch i386 windows]: Introduce call-abi for 32-bit mingw and make callee_pop_aggregate_return attribute by default on for 32-bit mingw target
Hi, this patch introduces for windows 32-bit target also the call-abi specifiers (ms_abi/sys_v) and set its default for this target to ms_abi. This patch set the default of the callee_pop_aggregate_return attribute to true for MS_ABI call-abi on 32-bit. Additionally it avoids the check of callee_pop_aggregate_return for any x86_64 target. I didn't changed here by intention the default settings of cygwin-target. But of course, if wished this change could be done as follow-up patch. ChangeLog gcc/ 2011-03-24 Kai Tietz * config/i386/cygming.h (DWARF_FRAME_REGISTERS): Adjust comment. (STACK_BOUNDARY): Check for bit-ness in case of MS_ABI. * config/i386/i386.c (ix86_conditional_register_usage): Adjust comment and use macro TARGET_64BIT_MS_ABI instead. (ix86_keep_aggregate_return_pointer): Optimize for 64-bit case and change default behavior for 32-bit MS_ABI. (ix86_reg_parm_stack_space): Check additionally for bit-ness. (ix86_function_type_abi): Allow check for ms_abi/sysv_abi for 32-bit, too. (ix86_cfun_abi): Likewise. (ix86_maybe_switch_abi): Adjust comment. (init_cumulative_args): Check for bit-ness in MS_ABI case. (ix86_gimplify_va_arg): Check just for not TARGET_64BIT_MS_ABI instead of checking for SYSV_ABI. (ix86_nsaved_sseregs): Likewise. (ix86_compute_frame_layout): Set only for 64-bit MS_ABI alignment to 16 bytes. (ix86_expand_call): Use TARGET_64BIT_MS_ABI macro. * config/i386.h (TARGET_32BIT_MS_ABI): New macro. (ACCUMULATE_OUTGOING_ARGS): Check explicit for 64-bit MS_ABI. (OUTGOING_REG_PARM_STACK_SPACE): Likewise. * config/mingw32.h (DEFAULT_ABI): Change default always to MS_ABI. Tested for x86_64-w64-mingw32, i686-pc-cygwin, and i686-w64-mingw32. Ok for apply? Regards, Kai
Re: mt-mep using EXTRA_TARGET_HOST_ALL_MODULES?
There's a top-level utils/ subdir in some trees. Yes, MeP has a tool there.
Re: [libgo] Support Solaris 8/9
Ian Lance Taylor i...@google.com writes: Just a quick note that I committed patches yesterday which should fix at least some of those problems. I failed to commit some of the test data the last time I updated the library. Fine, I'll give it another try tonight or over the weekend. Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
Re: Remove old host cases from toplevel configure
On Thu, 24 Mar 2011, Joseph S. Myers wrote: Furthermore, the whole idea of the toplevel configure tentative_cc setting code is dubious since this is an autoconf-generated script and it's autoconf's job to deal with finding a working compiler, putting it in ANSI C mode, etc. - so if someone did wish to resupport one of Related to that point, I notice a piece of code starting we might need to use some other shell than /bin/sh for running subshells that tries to determine a shell on Windows hosts. It's autoconf's job to find a suitable shell, so if this code is still relevant I think there's something missing in autoconf. -- Joseph S. Myers jos...@codesourcery.com
Re: [cxx-mem-model] disallow load data races (1 of some)
On 03/24/2011 10:33 AM, Aldy Hernandez wrote: In the example below we usually hoist global into a register or temporary to avoid reading from it at each step. This would cause a race if another thread had modified global in between iterations. for (x=0; x 5; x++) sum[x] = global; Um, what? Doesn't the c++ memory model have, like, sequence points or somesuch verbage that includes some language like an atomic? Your argument above, in absence of some serializing entity, does not sound right at all. r~
Re: [RFC PATCH, i386]: ICE: in final_scan_insn due to late split
Uros Bizjak ubiz...@gmail.com writes: 2011-03-23 Uros Bizjak ubiz...@gmail.com PR target/48237 * config/i386/i386.md (*movdf_internal_rex64): Do not split alternatives that can be handled with movq or movabsq insn. (*movdf_internal): Disable for !TARGET_64BIT. (*movdf_internal_nointeger): Ditto. * config/i386/i386.c (ix86_print_operand): Handle DFmode immediates. This patch broke Solaris/x86 bootstrap: /vol/gcc/src/hg/trunk/local/gcc/config/i386/i386.c: In function 'ix86_print_operand': /vol/gcc/src/hg/trunk/local/gcc/config/i386/i386.c:14416:2: error: format '%lld' expects argument of type 'long long int', but argument 3 has type 'long int' [-Werror=format] Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
More toplevel configure.ac pruning
This toplevel configure patch continues pruning useless or incorrect
code, generally specific to particular hosts or targets.
* There are mentions of target-groff, target-librx and tix, but these
are useless as they are not in Makefile.def, so they can safely be
removed.
* libmudflap is disabled by default for most targets and so there is
no need for a couple of individual targets to re-disable it.
* Disabling byacc based on host CPU architecture is clearly wrong.
* The directories built for a given target should not depend on the
host (if some tools can't be built for a host, that would apply for
all targets and so should go in the case statement over hosts). In
the case of code conditionally adding gprof back in (removing it
from skipdirs), there was no previous code that could have added it
to skipdirs in the first place, so the whole sub-case statement was
dead.
* There doesn't seem to be any use in a commented-out noconfigdirs
setting alongside a smaller non-commented-out setting.
OK to commit?
2011-03-24 Joseph Myers jos...@codesourcery.com
* configure.ac (target_tools): Remove target-groff.
(native_only): Remove target-groff.
(hppa*64*-*-*): Don't disable byacc.
(i[[3456789]]86-*-mingw32*): Remove commented-out noconfigdirs
setting.
(*-*-kaos*): Don't skip target-librx and target-groff.
(*-*-netware*): Don't skip target-libmudflap.
(*-*-tpf*): Don't skip target-libmudflap.
(sh*-*-pe|mips*-*-pe|*arm-wince-pe): Don't condition configured
directories on the host.
(ia64*-*-*vms*): Don't skip tix.
(sh-*-* | sh64-*-*): Don't condition skipped directories on the
host.
* configure: Regenerate.
Index: configure.ac
===
--- configure.ac(revision 171423)
+++ configure.ac(working copy)
@@ -210,7 +210,7 @@
# list belongs in this list. those programs are also very likely
# candidates for the native_only list which follows
#
-target_tools=target-examples target-groff target-gperf target-rda
+target_tools=target-examples target-gperf target-rda
@@ -298,7 +298,7 @@
# Some tools are only suitable for building in a native situation.
# Remove these if host!=target.
-native_only=autoconf automake libtool fileutils find gawk gettext gzip hello
indent m4 rcs recode sed shellutils tar textutils uudecode wdiff target-groff
guile perl time ash bash bzip2 prms gnuserv target-gperf
+native_only=autoconf automake libtool fileutils find gawk gettext gzip hello
indent m4 rcs recode sed shellutils tar textutils uudecode wdiff guile perl
time ash bash bzip2 prms gnuserv target-gperf
# Similarly, some are only suitable for cross toolchains.
# Remove these if host=target.
@@ -426,9 +426,6 @@
# exist yet.
case ${host} in
- hppa*64*-*-*)
-noconfigdirs=$noconfigdirs byacc
-;;
i[[3456789]]86-*-msdosdjgpp*)
noconfigdirs=$noconfigdirs tcl tk expect dejagnu send-pr uudecode guile
itcl gnuserv libffi
;;
@@ -436,7 +433,6 @@
noconfigdirs=$noconfigdirs expect dejagnu autoconf automake send-pr rcs
guile perl texinfo libtool newlib
;;
i[[3456789]]86-*-mingw32*)
-# noconfigdirs=tcl tk expect dejagnu make texinfo bison patch flex byacc
send-pr uudecode dejagnu diff guile perl itcl gnuserv
noconfigdirs=$noconfigdirs expect dejagnu autoconf automake send-pr rcs
guile perl texinfo libtool newlib
;;
*-*-cygwin*)
@@ -583,8 +579,8 @@
;;
*-*-kaos*)
# Remove unsupported stuff on all kaOS configurations.
-skipdirs=target-libiberty ${libgcj} target-libstdc++-v3 target-librx
-skipdirs=$skipdirs target-libobjc target-examples target-groff
target-gperf
+skipdirs=target-libiberty ${libgcj} target-libstdc++-v3
+skipdirs=$skipdirs target-libobjc target-examples target-gperf
skipdirs=$skipdirs zlib fastjar target-libjava target-boehm-gc
target-zlib
noconfigdirs=$noconfigdirs target-libgloss
;;
@@ -602,7 +598,7 @@
esac
;;
*-*-netware*)
-noconfigdirs=$noconfigdirs target-newlib target-libiberty target-libgloss
${libgcj} target-libmudflap
+noconfigdirs=$noconfigdirs target-newlib target-libiberty target-libgloss
${libgcj}
;;
*-*-rtems*)
skipdirs=${skipdirs} target-libiberty
@@ -610,7 +606,7 @@
;;
# The tpf target doesn't support gdb yet.
*-*-tpf*)
-noconfigdirs=$noconfigdirs target-newlib target-libgloss target-libiberty
${libgcj} target-libmudflap gdb tcl tk libgui itcl
+noconfigdirs=$noconfigdirs target-newlib target-libgloss target-libiberty
${libgcj} gdb tcl tk libgui itcl
;;
*-*-uclinux*)
noconfigdirs=$noconfigdirs target-newlib target-libgloss target-rda
${libgcj}
@@ -650,11 +646,6 @@
# the C++ libraries don't build on top of CE's C libraries
Re: [debug] dwarf2out emits unnecessary null byte in empty .debug_abbrev section
On 03/24/2011 09:26 AM, Mark Wielaard wrote: /* Terminate the table. */ - dw2_asm_output_data (1, 0, NULL); + if (abbrev_die_table_in_use 1) +dw2_asm_output_data (1, 0, NULL); I'd prefer this to be handled by if (abbrev_die_table_in_use == 0) return; at the beginning of the function. Ok with that change. r~
Re: [PATCH] Fix PR 48144
On 03/24/2011 06:50 AM, Andrey Belevantsev wrote: Hello, As noted in the PR audit trail, this is a case when we fail to find a transformed insn due to incomplete transformation history attached to it. The earlier fixes of this issue worked only for bookkeeping copies, but now we need a more general mechanism. Fixed by simply picking up additional transformation history from the av sets of basic blocks on the way. The problem can only happen on the bookkeeping blocks which have somewhat newer av sets available. Bootstrapping and testing on x86-64 and ia64 is in progress, ok if it succeeds? Ok, thanks. 2011-03-24 Andrey Belevantsev a...@ispras.ru gcc/ PR rtl-optimization/48144 * sel-sched-ir.c (merge_history_vect): Factor out from ... (merge_expr_data): ... here. (av_set_intersect): Rename to av_set_code_motion_filter. Update all callers. Call merge_history_vect when an expression is found in both sets. * sel-sched-ir.h (av_set_code_motion_filter): Add prototype. gcc/testsuite PR rtl-optimization/48144 * gcc.dg/pr48144.c: New test.
Re: [patch] Do not generate useless branches for multi-word comparison
On 03/24/2011 07:38 AM, Eric Botcazou wrote:
+ /* Deal with the special case 0 x: only one comparison is necessary and
+ we reverse it to avoid jumping to the drop-through label. */
+ if (op0 == const0_rtx drop_through_if_true !drop_through_if_false)
+{
+ code = LE;
+ if_true_label = if_false_label;
+ if_false_label = drop_through_label;
+ drop_through_if_false = true;
+}
Missing drop_through_if_true = false.
Otherwise ok.
r~
Re: [PATCH] use cfglayout mode for instatiate_virtual_regs
On 03/24/2011 04:47 AM, Nathan Froyd wrote: * function.c (instantiate_virtual_regs): Use FOR_EACH_BB and FOR_BB_INSNS_SAFE to iterate through insns. Re-indent. * passes.c (init_optimization_passes): Move pass_instantiate_virtual_regs after pass_into_cfg_layout_mode. Ok. r~
Re: [RFC PATCH, i386]: ICE: in final_scan_insn due to late split
On Thu, Mar 24, 2011 at 8:59 PM, Rainer Orth
r...@cebitec.uni-bielefeld.de wrote:
Uros Bizjak ubiz...@gmail.com writes:
2011-03-23 Uros Bizjak ubiz...@gmail.com
PR target/48237
* config/i386/i386.md (*movdf_internal_rex64): Do not split
alternatives that can be handled with movq or movabsq insn.
(*movdf_internal): Disable for !TARGET_64BIT.
(*movdf_internal_nointeger): Ditto.
* config/i386/i386.c (ix86_print_operand): Handle DFmode immediates.
This patch broke Solaris/x86 bootstrap:
/vol/gcc/src/hg/trunk/local/gcc/config/i386/i386.c: In function
'ix86_print_operand':
/vol/gcc/src/hg/trunk/local/gcc/config/i386/i386.c:14416:2: error: format
'%lld' expects argument of type 'long long int', but argument 3 has type
'long int' [-Werror=format]
Fixed by attached patch that removes all fancy conditional handling.
2011-03-24 Uros Bizjak ubiz...@gmail.com
* config/i386/i386.md (ix86_print_operand): Output DFmode const_double
correctly.
Tested on x86_64-pc-linux-gnu, committed to mainline.
Uros.
Rainer
--
-
Rainer Orth, Center for Biotechnology, Bielefeld University
Index: config/i386/i386.c
===
--- config/i386/i386.c (revision 171422)
+++ config/i386/i386.c (working copy)
@@ -14408,12 +14408,7 @@ ix86_print_operand (FILE *file, rtx x, i
if (ASSEMBLER_DIALECT == ASM_ATT)
putc ('$', file);
- /* We can use %d if the number is 32 bits and positive. */
- if (l[1] || l[0] 0)
- fprintf (file, 0x%lx%08lx,
-(unsigned long) l[1], (unsigned long) l[0]);
- else
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, l[0]);
+ fprintf (file, 0x%lx%08lx, l[1] 0x, l[0] 0x);
}
/* These float cases don't actually occur as immediate operands. */
Re: [cxx-mem-model] disallow load data races (1 of some)
On 03/24/11 14:58, Richard Henderson wrote: On 03/24/2011 10:33 AM, Aldy Hernandez wrote: In the example below we usually hoist global into a register or temporary to avoid reading from it at each step. This would cause a race if another thread had modified global in between iterations. for (x=0; x 5; x++) sum[x] = global; Um, what? Doesn't the c++ memory model have, like, sequence points or somesuch verbage that includes some language like an atomic? Your argument above, in absence of some serializing entity, does not sound right at all. This work is independent of the C++ memory model. It is just to prevent the optimizers from introducing new data races due to code movement. This initial pass is just to make the optimizations data race safe so that if you have a program which is proven to be free of data races, you can run the optimizers and it will still be data race free after the optimizers have been run. See the following summary by Andrew (which in turn is based on a paper by Hans Boehm): http://gcc.gnu.org/wiki/Atomic/GCCMM/DataRaces The code movement is disallowed under specific --param options and will later be used for the C++ memory model, though the kernel folk have been asking for something similar, so it's not C++ specific. Does this make sense now? Or were Andrew and I smoking some heavy duty stuff when reading the specs... and not sharing with you? Aldy
Re: [google] Port lock annotations/analysis to google/main branch (issue4275075)
On Thu, Mar 24, 2011 at 15:30, Le-Chun Wu l...@google.com wrote: 2011-03-24 Le-Chun Wu l...@google.com * Makefile.in: Add new source file and headers in dependencies. * attribs.c (decl_attributes): Handle lock attributes. (is_lock_attribute_with_args): New function. (is_lock_attribute_p): Likewise. (extract_lock_attributes): Likewise. (merge_lock_attr_args): Likewise. * c-decl.c (undeclared_variable): Suppress errors for lock attributes. * c-parser.c (c_parser_declaration_or_fndef): Allow lock attributes on function definitions. Add support for suppressing errors for lock attributes. (c_parser_attributes): Replace the original code that handles the argument list with a call to c_parser_attr_arg_list. (c_parser_attr_arg_list): New function. * common.opt: Add new flags for lock annotations and analysis. * doc/invoke.texi: Add documentation for new flags for lock annotations and analysis. * gimplify.c (lookup_tmp_var): Copy thread safety attributes to tmp variable and save the original variable name. * langhooks-def.h: Define new language hooks. * langhooks.c (lhd_do_nothing_t_return_int): New function. (lhd_do_nothing_t_return_bool): Likewise. (lhd_do_nothing_t_t_return_null_tree): Likewise. * langhooks.h: Add new hook functions in the lang_hooks struct. * passes.c (init_optimization_passes): Add a new pass. * pointer-set.c (pointer_set_copy): New function. (pointer_set_delete): Likewise. (pointer_set_intersection_complement): Likewise. (pointer_set_union_inplace): Likewise. (pointer_set_cardinality): Likewise. * pointer-set.h: Add declarations of new functions. * timevar.def: Add a new time var for thread safety analysis pass. * toplev.c (compile_file): Clean up the global data structures used by the thread safety analysis. * tree-pass.h: Add a new pass declaration. * tree-threadsafe-analyze.c: New file. * tree-threadsafe-analyze.h: New file. * tree.h: Declaration for new functions. c-family/ * c-common.c (c_common_attribute_table): Add new functions to process lock attributes. (attribute_takes_identifier_p): Handle lock attributes. (handle_lockable_attribute): New Handler. (handle_guarded_by_attribute): Likewise. (handle_point_to_guarded_by_attribute): Likewise. (handle_guarded_attribute): Likewise. (handle_point_to_guarded_attribute): Likewise. (handle_acquired_order_attribute): Likewise. (handle_lock_attribute): Likewise. (handle_unlock_attribute): Likewise. (handle_locks_required_excluded_attribute): Likewise. (handle_lock_returned_attribute): Likewise. (handle_no_thread_safety_analysis_attribute): Likewise. (supported_lock_expression): New helper function. (get_lock_decl): Likewise. (populate_acquired_after_map): Likewise. (is_lock_formal_parameter): Likewise. (check_lock_unlock_attr_args): Likewise. * c-cppbuiltin.c (c_cpp_builtins): Define annotalysis-related macros. * c-pretty-print.c (pp_c_expression): Handle SSA_NAME. cp/ * Make-lang.in: Add new includes. * call.c (build_new_op): Support for non-const non-modifying methods. (find_const_memfunc_with_identical_prototype): New function. (build_new_method_call): Suppress errors for calls in lock attributes. Support for non-const non-modifying methods. * class.c (cp_get_virtual_function_decl): New function. (cp_fold_obj_type_ref): Refactored to call cp_get_virtual_function_decl. (cp_decl_is_base_field): New function. (cp_decl_is_constructor): Likewise. (cp_decl_is_destructor): Likewise. (cp_decl_is_const_member_func): Likewise. * cp-lang.c: New language hooks. * cp-tree.h: New function declarations. * decl2.c (is_late_template_attribute): Handle delay parsing of lock attribute arguments. * error.c (dump_expr): Handle SSA_NAME. * lex.c (unqualified_name_lookup_error): Suppress errors for lock attributes. * name-lookup.c (lookup_name_in_func_params): New function. * name-lookup.h: New function declaration. * parser.c (cp_parser): New fields. (cp_parser_name_lookup_error): Suppress errors for lock attributes. (cp_parser_new): Initialize unparsed_attribute_args_queue. (cp_parser_postfix_expression): Add function parameter lookup support. (cp_parser_parenthesized_expression_list): Fix a problem in parsing identifier arguments and skip folding for decl arguments. (cp_parser_lambda_declarator_opt): Add a new argument to cp_parser_attributes_opt.
Re: [google] Port lock annotations/analysis to google/main branch (issue4275075)
Could you also update http://gcc.gnu.org/wiki/ThreadSafetyAnnotation? It still points to the old branch and seems to have stale content. Will do. Any plans for mainline merge? I don't actually have a time frame for that, but that is the ultimate goal. http://codereview.appspot.com/4275075/diff/2001/gcc/common.opt File gcc/common.opt (right): http://codereview.appspot.com/4275075/diff/2001/gcc/common.opt#newcode682 gcc/common.opt:682: Make the thread safety analysis try to bind the function parameters used in the attributes On 2011/03/24 21:42:18, Diego Novillo wrote: Hmm, you've added these warnings twice now. I had added the flags to fix our builds. The warnings I added are just above these. If there's anything new, you can just overwrite it. Ah, I didn't notice that, and the build went OK. Duplicate entries were removed. http://codereview.appspot.com/4275075/diff/2001/gcc/cp/parser.c File gcc/cp/parser.c (left): http://codereview.appspot.com/4275075/diff/2001/gcc/cp/parser.c#oldcode5766 gcc/cp/parser.c:5766: is_attribute_list = non_attr; On 2011/03/24 21:42:18, Diego Novillo wrote: Why are you taking this out? Without doing, the parser would start evaluating/binding the identifier nodes after processing the first argument, which would limit our ability to allow users to use names not in scope. The detailed explanation is in the comments above (line 5778 to 5801 in the patched file). http://codereview.appspot.com/4275075/diff/2001/gcc/cp/parser.c#oldcode5802 gcc/cp/parser.c:5802: VEC_safe_insert (tree, gc, expression_list, 0, identifier); On 2011/03/24 21:42:18, Diego Novillo wrote: Likewise. In the original implementation, the first identifier argument was not pushed into the expression_list vector, so we had to do that here. With my patch, the first argument is pushed to the vector in line 5802 (in patched file). http://codereview.appspot.com/4275075/diff/2001/gcc/cp/parser.c File gcc/cp/parser.c (right): http://codereview.appspot.com/4275075/diff/2001/gcc/cp/parser.c#newcode1742 gcc/cp/parser.c:1742: tree current_declarator_scope; On 2011/03/24 21:42:18, Diego Novillo wrote: You're going to find some amusing merge conflicts the next time google/main merges from trunk ;) All this has been factored out of cp/parser.c Thanks for the heads-up. We will deal with them then. :-) http://codereview.appspot.com/4275075/diff/2001/gcc/tree.h File gcc/tree.h (right): http://codereview.appspot.com/4275075/diff/2001/gcc/tree.h#newcode5366 gcc/tree.h:5366: /* Extract and return all lock attributes from the given attribute list. */ On 2011/03/24 21:42:18, Diego Novillo wrote: Blank line above comment. Done. http://codereview.appspot.com/4275075/
Re: [toplevel] cleanup mh-cygwin
On 24/03/2011 17:11, Paolo Bonzini wrote: The cygwin host fragment is using obsolete variables and constructs, modernize it. Committed to gcc and (shortly) src. Thanks, top-level stuff is a bit of a mystery to me :) cheers, DaveK
Re: [debug] dwarf2out emits unnecessary null byte in empty .debug_abbrev section
On 03/24/2011 01:54 PM, Mark Wielaard wrote:
+ if (abbrev_die_table_in_use == 1)
+return;
+
for (abbrev_id = 1; abbrev_id abbrev_die_table_in_use; ++abbrev_id)
{
dw_die_ref abbrev = abbrev_die_table[abbrev_id];
Still OK?
Yes.
r~
libgo patch committed: Update to current version of Go library
I've committed a patch to libgo to update to the current version of the master Go library. The patch is too large to include here, and is in any case simply a copy of changes available in the master Go library repository. See SVN or http://codereview.appspot.com/4281068/ for the changes as applied to libgo. Ian
Re: [cxx-mem-model] disallow load data races (1 of some)
On Thu, 24 Mar 2011, Aldy Hernandez wrote: This work is independent of the C++ memory model. It is just to prevent the optimizers from introducing new data races due to code movement. This initial pass is just to make the optimizations data race safe so that if you have a program which is proven to be free of data races, you can run the optimizers and it will still be data race free after the optimizers have been run. See the following summary by Andrew (which in turn is based on a paper by Hans Boehm): http://gcc.gnu.org/wiki/Atomic/GCCMM/DataRaces But hoisting global in this case doesn't result in a data race, since the loop always accesses global and contains no synchronisation code. If it were only accessed conditionally, as in the examples under Avoiding Speculation on that page, then there would be a race in hoisting it, but not for the code you gave; any data races with the hoisting would still have been present without it. My fault for not being specific about it... I tend to just use data race as a catch all for all these types of things when talking about them with Aldy. the testcase should have for (x=0; x limit; x++) sum[x] = global; rather than x5, so that its not a known loop count. The hoisted load is then not allowed as it become a speculative load of 'global' on the main path which would not otherwise have been there. When the value of limit 0, this can cause a load race detection on systems with either a software or hardware data race detector. It can be allowed as long as the load happens inside a guard for the loop, but I dont think we are that sophisticated yet. Bottom line is these flags are to prevent the introduction of loads of globals on code paths which didn't have had them before. Andrew
Re: [4.7] Avoid global state in sparc_handle_option
On Thu, 17 Mar 2011, Eric Botcazou wrote: 2011-03-13 Joseph Myers jos...@codesourcery.com * config/sparc/sparc-opts.h: New. Do you really need all the dates in there? They were the dates on sparc.h from which this file was split out. This version uses only the dates of the revisions shown by svn blame on the enumeration in sparc.h. The sparc_cpu/sparc_cpu_option naming is confusing. What about replacing the latter with sparc_cpu_and_features or something along these lines? This version includes that renaming - how does it look to you. Tested building cc1 and xgcc for cross to sparc-elf. 2011-03-24 Joseph Myers jos...@codesourcery.com * config/sparc/sparc-opts.h: New. * config/sparc/sparc.c (sparc_handle_option, sparc_select, sparc_cpu, fpu_option_set, TARGET_HANDLE_OPTION): Remove. (sparc_option_override): Store processor_type enumeration rather than string in cpu_default. Remove name and enumeration from cpu_table. Directly default -mcpu then default -mtune from -mcpu without using sparc_select. Use target_flags_explicit instead of fpu_option_set. * config/sparc/sparc.h (enum processor_type): Move to sparc-opts.h. (sparc_cpu, struct sparc_cpu_select, sparc_select): Remove. * config/sparc/sparc.opt (config/sparc/sparc-opts.h): New HeaderInclude entry. (mcpu=, mtune=): Use Var and Enum. (sparc_processor_type): New Enum and EnumValue entries. Index: gcc/config/sparc/sparc.opt === --- gcc/config/sparc/sparc.opt (revision 171425) +++ gcc/config/sparc/sparc.opt (working copy) @@ -1,6 +1,6 @@ ; Options for the SPARC port of the compiler ; -; Copyright (C) 2005, 2007, 2010 Free Software Foundation, Inc. +; Copyright (C) 2005, 2007, 2010, 2011 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -18,6 +18,9 @@ ; along with GCC; see the file COPYING3. If not see ; http://www.gnu.org/licenses/. +HeaderInclude +config/sparc/sparc-opts.h + mfpu Target Report Mask(FPU) Use hardware FP @@ -83,13 +86,67 @@ Target Optimize tail call instructions in assembler and linker mcpu= -Target RejectNegative Joined +Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Use features of and schedule code for given CPU mtune= -Target RejectNegative Joined +Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Schedule code for given CPU +Enum +Name(sparc_processor_type) Type(enum processor_type) + +EnumValue +Enum(sparc_processor_type) String(v7) Value(PROCESSOR_V7) + +EnumValue +Enum(sparc_processor_type) String(cypress) Value(PROCESSOR_CYPRESS) + +EnumValue +Enum(sparc_processor_type) String(v8) Value(PROCESSOR_V8) + +EnumValue +Enum(sparc_processor_type) String(supersparc) Value(PROCESSOR_SUPERSPARC) + +EnumValue +Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC) + +EnumValue +Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON) + +EnumValue +Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE) + +EnumValue +Enum(sparc_processor_type) String(f930) Value(PROCESSOR_F930) + +EnumValue +Enum(sparc_processor_type) String(f934) Value(PROCESSOR_F934) + +EnumValue +Enum(sparc_processor_type) String(sparclite86x) Value(PROCESSOR_SPARCLITE86X) + +EnumValue +Enum(sparc_processor_type) String(sparclet) Value(PROCESSOR_SPARCLET) + +EnumValue +Enum(sparc_processor_type) String(tsc701) Value(PROCESSOR_TSC701) + +EnumValue +Enum(sparc_processor_type) String(v9) Value(PROCESSOR_V9) + +EnumValue +Enum(sparc_processor_type) String(ultrasparc) Value(PROCESSOR_ULTRASPARC) + +EnumValue +Enum(sparc_processor_type) String(ultrasparc3) Value(PROCESSOR_ULTRASPARC3) + +EnumValue +Enum(sparc_processor_type) String(niagara) Value(PROCESSOR_NIAGARA) + +EnumValue +Enum(sparc_processor_type) String(niagara2) Value(PROCESSOR_NIAGARA2) + mcmodel= Target RejectNegative Joined Var(sparc_cmodel_string) Use given SPARC-V9 code model Index: gcc/config/sparc/sparc-opts.h === --- gcc/config/sparc/sparc-opts.h (revision 0) +++ gcc/config/sparc/sparc-opts.h (revision 0) @@ -0,0 +1,47 @@ +/* Definitions for option handling for SPARC. + Copyright (C) 1996, 1999, 2002, 2006, 2007, 2010, 2011 + Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU
[alpha] Revert input_operand change for vms
While purging Windows code, I failed to remember that VMS has a 32-bit
mode as well, and thus this line still matters.
r~
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 38d40b5..abd96c7 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -177,6 +177,19 @@
(define_attr cannot_copy false,true
(const_string false))
+
+;; Used to control the enabled attribute on a per-instruction basis.
+(define_attr isa base,bwx,max,fix,cix,vms
+ (const_string base))
+
+(define_attr enabled
+ (cond [(eq_attr isa bwx) (symbol_ref TARGET_BWX)
+(eq_attr isa max) (symbol_ref TARGET_MAX)
+(eq_attr isa fix) (symbol_ref TARGET_FIX)
+(eq_attr isa cix) (symbol_ref TARGET_CIX)
+(eq_attr isa vms) (symbol_ref TARGET_ABI_OPEN_VMS)
+ ]
+ (const_int 1)))
;; Include scheduling descriptions.
@@ -1092,130 +1105,60 @@
operands[4] = GEN_INT (mask2);
})
-(define_expand zero_extendqihi2
- [(set (match_operand:HI 0 register_operand )
- (zero_extend:HI (match_operand:QI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
-
-(define_insn *zero_extendqihi2_bwx
+(define_insn zero_extendqihi2
[(set (match_operand:HI 0 register_operand =r,r)
- (zero_extend:HI (match_operand:QI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:HI
+ (match_operand:QI 1 reg_or_bwx_memory_operand r,m)))]
+
@
and %1,0xff,%0
ldbu %0,%1
- [(set_attr type ilog,ild)])
-
-(define_insn *zero_extendqihi2_nobwx
- [(set (match_operand:HI 0 register_operand =r)
- (zero_extend:HI (match_operand:QI 1 register_operand r)))]
- ! TARGET_BWX
- and %1,0xff,%0
- [(set_attr type ilog)])
-
-(define_expand zero_extendqisi2
- [(set (match_operand:SI 0 register_operand )
- (zero_extend:SI (match_operand:QI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
+ [(set_attr type ilog,ild)
+ (set_attr isa *,bwx)])
-(define_insn *zero_extendqisi2_bwx
+(define_insn zero_extendqisi2
[(set (match_operand:SI 0 register_operand =r,r)
- (zero_extend:SI (match_operand:QI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:SI
+ (match_operand:QI 1 reg_or_bwx_memory_operand r,m)))]
+
@
and %1,0xff,%0
ldbu %0,%1
- [(set_attr type ilog,ild)])
-
-(define_insn *zero_extendqisi2_nobwx
- [(set (match_operand:SI 0 register_operand =r)
- (zero_extend:SI (match_operand:QI 1 register_operand r)))]
- ! TARGET_BWX
- and %1,0xff,%0
- [(set_attr type ilog)])
-
-(define_expand zero_extendqidi2
- [(set (match_operand:DI 0 register_operand )
- (zero_extend:DI (match_operand:QI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
+ [(set_attr type ilog,ild)
+ (set_attr isa *,bwx)])
-(define_insn *zero_extendqidi2_bwx
+(define_insn zero_extendqidi2
[(set (match_operand:DI 0 register_operand =r,r)
- (zero_extend:DI (match_operand:QI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:DI
+ (match_operand:QI 1 reg_or_bwx_memory_operand r,m)))]
+
@
and %1,0xff,%0
ldbu %0,%1
- [(set_attr type ilog,ild)])
-
-(define_insn *zero_extendqidi2_nobwx
- [(set (match_operand:DI 0 register_operand =r)
- (zero_extend:DI (match_operand:QI 1 register_operand r)))]
- ! TARGET_BWX
- and %1,0xff,%0
- [(set_attr type ilog)])
+ [(set_attr type ilog,ild)
+ (set_attr isa *,bwx)])
-(define_expand zero_extendhisi2
- [(set (match_operand:SI 0 register_operand )
- (zero_extend:SI (match_operand:HI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (HImode, operands[1]);
-})
-
-(define_insn *zero_extendhisi2_bwx
+(define_insn zero_extendhisi2
[(set (match_operand:SI 0 register_operand =r,r)
- (zero_extend:SI (match_operand:HI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:SI
+ (match_operand:HI 1 reg_or_bwx_memory_operand r,m)))]
+
@
zapnot %1,3,%0
ldwu %0,%1
- [(set_attr type shift,ild)])
-
-(define_insn *zero_extendhisi2_nobwx
- [(set (match_operand:SI 0 register_operand =r)
- (zero_extend:SI (match_operand:HI 1 register_operand r)))]
- ! TARGET_BWX
- zapnot %1,3,%0
- [(set_attr type shift)])
-
-(define_expand zero_extendhidi2
- [(set (match_operand:DI 0 register_operand )
- (zero_extend:DI (match_operand:HI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (HImode, operands[1]);
-})
+ [(set_attr type shift,ild)
+ (set_attr isa *,bwx)])
-(define_insn *zero_extendhidi2_bwx
+(define_insn zero_extendhidi2
[(set (match_operand:DI 0 register_operand =r,r)
- (zero_extend:DI (match_operand:HI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:DI
+ (match_operand:HI 1 reg_or_bwx_memory_operand
[alpha] Unify zero_extend patterns with attribute enabled
The attribute enabled feature can help avoid quite a lot of
duplication in the alpha backend. This begins the process
by tackling the easiest -- zero_extension, conditionalized
on the existance of the BWX instruction set extension.
Tested on alpha{,ev5,ev56,ev67}-linux.
r~
+ * config/alpha/alpha.md (attribute isa): New.
+ (attribute enabled): New.
+ (zero_extendqihi2): Merge from *zero_extendqihi2_{bwx,nobwx}.
+ (zero_extendqisi2, zero_extendqidi2): Similarly.
+ (zero_extendhisi2, zero_extendhidi2): Similarly.
+ * config/alpha/predicates.md (reg_or_bwx_memory_operand): New.
+
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 38d40b5..cb3821c 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -177,6 +177,18 @@
(define_attr cannot_copy false,true
(const_string false))
+
+;; Used to control the enabled attribute on a per-instruction basis.
+(define_attr isa base,bwx,max,fix,cix
+ (const_string base))
+
+(define_attr enabled
+ (cond [(eq_attr isa bwx) (symbol_ref TARGET_BWX)
+(eq_attr isa max) (symbol_ref TARGET_MAX)
+(eq_attr isa fix) (symbol_ref TARGET_FIX)
+(eq_attr isa cix) (symbol_ref TARGET_CIX)
+ ]
+ (const_int 1)))
;; Include scheduling descriptions.
@@ -1092,130 +1104,60 @@
operands[4] = GEN_INT (mask2);
})
-(define_expand zero_extendqihi2
- [(set (match_operand:HI 0 register_operand )
- (zero_extend:HI (match_operand:QI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
-
-(define_insn *zero_extendqihi2_bwx
+(define_insn zero_extendqihi2
[(set (match_operand:HI 0 register_operand =r,r)
- (zero_extend:HI (match_operand:QI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:HI
+ (match_operand:QI 1 reg_or_bwx_memory_operand r,m)))]
+
@
and %1,0xff,%0
ldbu %0,%1
- [(set_attr type ilog,ild)])
+ [(set_attr type ilog,ild)
+ (set_attr isa *,bwx)])
-(define_insn *zero_extendqihi2_nobwx
- [(set (match_operand:HI 0 register_operand =r)
- (zero_extend:HI (match_operand:QI 1 register_operand r)))]
- ! TARGET_BWX
- and %1,0xff,%0
- [(set_attr type ilog)])
-
-(define_expand zero_extendqisi2
- [(set (match_operand:SI 0 register_operand )
- (zero_extend:SI (match_operand:QI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
-
-(define_insn *zero_extendqisi2_bwx
+(define_insn zero_extendqisi2
[(set (match_operand:SI 0 register_operand =r,r)
- (zero_extend:SI (match_operand:QI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:SI
+ (match_operand:QI 1 reg_or_bwx_memory_operand r,m)))]
+
@
and %1,0xff,%0
ldbu %0,%1
- [(set_attr type ilog,ild)])
-
-(define_insn *zero_extendqisi2_nobwx
- [(set (match_operand:SI 0 register_operand =r)
- (zero_extend:SI (match_operand:QI 1 register_operand r)))]
- ! TARGET_BWX
- and %1,0xff,%0
- [(set_attr type ilog)])
-
-(define_expand zero_extendqidi2
- [(set (match_operand:DI 0 register_operand )
- (zero_extend:DI (match_operand:QI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (QImode, operands[1]);
-})
+ [(set_attr type ilog,ild)
+ (set_attr isa *,bwx)])
-(define_insn *zero_extendqidi2_bwx
+(define_insn zero_extendqidi2
[(set (match_operand:DI 0 register_operand =r,r)
- (zero_extend:DI (match_operand:QI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:DI
+ (match_operand:QI 1 reg_or_bwx_memory_operand r,m)))]
+
@
and %1,0xff,%0
ldbu %0,%1
- [(set_attr type ilog,ild)])
-
-(define_insn *zero_extendqidi2_nobwx
- [(set (match_operand:DI 0 register_operand =r)
- (zero_extend:DI (match_operand:QI 1 register_operand r)))]
- ! TARGET_BWX
- and %1,0xff,%0
- [(set_attr type ilog)])
-
-(define_expand zero_extendhisi2
- [(set (match_operand:SI 0 register_operand )
- (zero_extend:SI (match_operand:HI 1 nonimmediate_operand )))]
-
-{
- if (! TARGET_BWX)
-operands[1] = force_reg (HImode, operands[1]);
-})
+ [(set_attr type ilog,ild)
+ (set_attr isa *,bwx)])
-(define_insn *zero_extendhisi2_bwx
+(define_insn zero_extendhisi2
[(set (match_operand:SI 0 register_operand =r,r)
- (zero_extend:SI (match_operand:HI 1 nonimmediate_operand r,m)))]
- TARGET_BWX
+ (zero_extend:SI
+ (match_operand:HI 1 reg_or_bwx_memory_operand r,m)))]
+
@
zapnot %1,3,%0
ldwu %0,%1
- [(set_attr type shift,ild)])
-
-(define_insn *zero_extendhisi2_nobwx
- [(set (match_operand:SI 0 register_operand =r)
- (zero_extend:SI (match_operand:HI 1 register_operand r)))]
- ! TARGET_BWX
- zapnot %1,3,%0
- [(set_attr type shift)])
-
-(define_expand zero_extendhidi2
- [(set (match_operand:DI 0 register_operand )
- (zero_extend:DI (match_operand:HI 1 nonimmediate_operand
[alpha] cleanup sign_extension patterns
We don't get a chance to use attribute enabled here, but we can
eliminate some unnecessary expanders.
The non-BWX expansion paths wound up subregging the input to
DImode to perform the operation and subregging it back. Exactly
as the generic code paths would do.
I didn't investigate what eliminating the sub-word patterns
for BWX code has on the generated code. In theory these are
not needed either, also handled by the generic code paths...
r~
+ * config/alpha/alpha.md (extendqihi2): Implement for BWX only.
+ (extendqisi2, extendhisi2): Likewise.
+ (extendqidi2): Simplify BWX/non-BWX expansions.
+ (extendhidi2): Similarly.
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index cb3821c..f37a5b3 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -1413,194 +1413,103 @@
sra %r1,%2,%0
[(set_attr type shift)])
-(define_expand extendqihi2
- [(set (match_dup 2)
- (ashift:DI (match_operand:QI 1 some_operand )
- (const_int 56)))
- (set (match_operand:HI 0 register_operand )
- (ashiftrt:DI (match_dup 2)
-(const_int 56)))]
-
-{
- if (TARGET_BWX)
-{
- emit_insn (gen_extendqihi2x (operands[0],
- force_reg (QImode, operands[1])));
- DONE;
-}
-
- /* If we have an unaligned MEM, extend to DImode (which we do
- specially) and then copy to the result. */
- if (unaligned_memory_operand (operands[1], HImode))
-{
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_extendqidi2 (temp, operands[1]));
- emit_move_insn (operands[0], gen_lowpart (HImode, temp));
- DONE;
-}
-
- operands[0] = gen_lowpart (DImode, operands[0]);
- operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
- operands[2] = gen_reg_rtx (DImode);
-})
-
-(define_insn extendqidi2x
- [(set (match_operand:DI 0 register_operand =r)
- (sign_extend:DI (match_operand:QI 1 register_operand r)))]
+(define_insn extendqihi2
+ [(set (match_operand:HI 0 register_operand =r)
+ (sign_extend:HI (match_operand:QI 1 register_operand r)))]
TARGET_BWX
sextb %1,%0
[(set_attr type shift)])
-(define_insn extendhidi2x
- [(set (match_operand:DI 0 register_operand =r)
- (sign_extend:DI (match_operand:HI 1 register_operand r)))]
- TARGET_BWX
- sextw %1,%0
- [(set_attr type shift)])
-
-(define_insn extendqisi2x
+(define_insn extendqisi2
[(set (match_operand:SI 0 register_operand =r)
(sign_extend:SI (match_operand:QI 1 register_operand r)))]
TARGET_BWX
sextb %1,%0
[(set_attr type shift)])
-(define_insn extendhisi2x
- [(set (match_operand:SI 0 register_operand =r)
- (sign_extend:SI (match_operand:HI 1 register_operand r)))]
- TARGET_BWX
- sextw %1,%0
- [(set_attr type shift)])
-
-(define_insn extendqihi2x
- [(set (match_operand:HI 0 register_operand =r)
- (sign_extend:HI (match_operand:QI 1 register_operand r)))]
- TARGET_BWX
- sextb %1,%0
- [(set_attr type shift)])
-
-(define_expand extendqisi2
- [(set (match_dup 2)
- (ashift:DI (match_operand:QI 1 some_operand )
- (const_int 56)))
- (set (match_operand:SI 0 register_operand )
- (ashiftrt:DI (match_dup 2)
-(const_int 56)))]
-
-{
- if (TARGET_BWX)
-{
- emit_insn (gen_extendqisi2x (operands[0],
- force_reg (QImode, operands[1])));
- DONE;
-}
-
- /* If we have an unaligned MEM, extend to a DImode form of
- the result (which we do specially). */
- if (unaligned_memory_operand (operands[1], QImode))
-{
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_extendqidi2 (temp, operands[1]));
- emit_move_insn (operands[0], gen_lowpart (SImode, temp));
- DONE;
-}
-
- operands[0] = gen_lowpart (DImode, operands[0]);
- operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
- operands[2] = gen_reg_rtx (DImode);
-})
-
(define_expand extendqidi2
- [(set (match_dup 2)
- (ashift:DI (match_operand:QI 1 some_operand )
- (const_int 56)))
- (set (match_operand:DI 0 register_operand )
- (ashiftrt:DI (match_dup 2)
-(const_int 56)))]
+ [(set (match_operand:DI 0 register_operand )
+ (sign_extend:DI (match_operand:QI 1 some_operand )))]
{
if (TARGET_BWX)
+operands[1] = force_reg (QImode, operands[1]);
+ else
{
- emit_insn (gen_extendqidi2x (operands[0],
- force_reg (QImode, operands[1])));
- DONE;
-}
+ rtx x, t1, t2, i56;
- if (unaligned_memory_operand (operands[1], QImode))
-{
- rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
- alpha_set_memflags (seq, operands[1]);
- emit_insn (seq);
- DONE;
-}
+ if (unaligned_memory_operand (operands[1], QImode))
+ {
+ x = gen_unaligned_extendqidi (operands[0],
[alpha] Unify most move patterns with attribute enabled
This handles everything except movdi, which is more complex.
One perhaps non-obvious thing is the use of the ABI as an isa
entry with respect to the loading of an address constant. This
appears in movsi for VMS. This turns out to be significantly
easier than using two different attributes to control enabled
and I couldn't think of a better name than isa.
r~
+ * config/alpha/alpha.md (attribute isa): Add vms.
+ (attribute enabled): Handle it.
+ (*movsf): Merge *movsf_{nofix,fix,nofp}.
+ (*movdf): Merge *movdf_{nofix,fix,nofp}.
+ (*movtf): Rename from *movtf_internal for consistency.
+ (*movsi): Merge with *movsi_nt_vms.
+ (*movhi): Merge *movhi_nobwx, *movhi_bwx.
+ (*movqi): Merge *movqi_nobwx, *movqi_bwx.
+ (*movVEC): Merge *movVEC_fix, *movVEC_nofix.
+ * config/alpha/constraint.md (f): Use NO_REGS when fpu is disabled.
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index f37a5b3..0f71292 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -179,7 +179,9 @@
(const_string false))
;; Used to control the enabled attribute on a per-instruction basis.
-(define_attr isa base,bwx,max,fix,cix
+;; For convenience, conflate ABI issues re loading of addresses with
+;; an isa.
+(define_attr isa base,bwx,max,fix,cix,vms
(const_string base))
(define_attr enabled
@@ -187,6 +189,7 @@
(eq_attr isa max) (symbol_ref TARGET_MAX)
(eq_attr isa fix) (symbol_ref TARGET_FIX)
(eq_attr isa cix) (symbol_ref TARGET_CIX)
+ (eq_attr isa vms) (symbol_ref TARGET_ABI_OPEN_VMS)
]
(const_int 1)))
@@ -4607,27 +4610,21 @@
;; are done via define_expand. Start with the floating-point insns, since
;; they are simpler.
-(define_insn *movsf_nofix
- [(set (match_operand:SF 0 nonimmediate_operand =f,f,*r,*r,m,m)
- (match_operand:SF 1 input_operand fG,m,*rG,m,fG,*r))]
- TARGET_FPREGS ! TARGET_FIX
-(register_operand (operands[0], SFmode)
- || reg_or_0_operand (operands[1], SFmode))
- @
- cpys %R1,%R1,%0
- ld%, %0,%1
- bis $31,%r1,%0
- ldl %0,%1
- st%, %R1,%0
- stl %r1,%0
- [(set_attr type fcpys,fld,ilog,ild,fst,ist)])
+(define_expand movsf
+ [(set (match_operand:SF 0 nonimmediate_operand )
+ (match_operand:SF 1 general_operand ))]
+
+{
+ if (MEM_P (operands[0])
+ ! reg_or_0_operand (operands[1], SFmode))
+operands[1] = force_reg (SFmode, operands[1]);
+})
-(define_insn *movsf_fix
+(define_insn *movsf
[(set (match_operand:SF 0 nonimmediate_operand =f,f,*r,*r,m,m,f,*r)
(match_operand:SF 1 input_operand fG,m,*rG,m,fG,*r,*r,f))]
- TARGET_FPREGS TARGET_FIX
-(register_operand (operands[0], SFmode)
- || reg_or_0_operand (operands[1], SFmode))
+ register_operand (operands[0], SFmode)
+ || reg_or_0_operand (operands[1], SFmode)
@
cpys %R1,%R1,%0
ld%, %0,%1
@@ -4637,41 +4634,24 @@
stl %r1,%0
itofs %1,%0
ftois %1,%0
- [(set_attr type fcpys,fld,ilog,ild,fst,ist,itof,ftoi)])
-
-(define_insn *movsf_nofp
- [(set (match_operand:SF 0 nonimmediate_operand =r,r,m)
- (match_operand:SF 1 input_operand rG,m,r))]
- ! TARGET_FPREGS
-(register_operand (operands[0], SFmode)
- || reg_or_0_operand (operands[1], SFmode))
- @
- bis $31,%r1,%0
- ldl %0,%1
- stl %r1,%0
- [(set_attr type ilog,ild,ist)])
-
-(define_insn *movdf_nofix
- [(set (match_operand:DF 0 nonimmediate_operand =f,f,*r,*r,m,m)
- (match_operand:DF 1 input_operand fG,m,*rG,m,fG,*r))]
- TARGET_FPREGS ! TARGET_FIX
-(register_operand (operands[0], DFmode)
- || reg_or_0_operand (operands[1], DFmode))
- @
- cpys %R1,%R1,%0
- ld%- %0,%1
- bis $31,%r1,%0
- ldq %0,%1
- st%- %R1,%0
- stq %r1,%0
- [(set_attr type fcpys,fld,ilog,ild,fst,ist)])
+ [(set_attr type fcpys,fld,ilog,ild,fst,ist,itof,ftoi)
+ (set_attr isa *,*,*,*,*,*,fix,fix)])
-(define_insn *movdf_fix
+(define_expand movdf
+ [(set (match_operand:DF 0 nonimmediate_operand )
+ (match_operand:DF 1 general_operand ))]
+
+{
+ if (MEM_P (operands[0])
+ ! reg_or_0_operand (operands[1], DFmode))
+operands[1] = force_reg (DFmode, operands[1]);
+})
+
+(define_insn *movdf
[(set (match_operand:DF 0 nonimmediate_operand =f,f,*r,*r,m,m,f,*r)
(match_operand:DF 1 input_operand fG,m,*rG,m,fG,*r,*r,f))]
- TARGET_FPREGS TARGET_FIX
-(register_operand (operands[0], DFmode)
- || reg_or_0_operand (operands[1], DFmode))
+ register_operand (operands[0], DFmode)
+ || reg_or_0_operand (operands[1], DFmode)
@
cpys %R1,%R1,%0
ld%- %0,%1
@@ -4681,24 +4661,24 @@
stq %r1,%0
itoft %1,%0
ftoit %1,%0
- [(set_attr type fcpys,fld,ilog,ild,fst,ist,itof,ftoi)])
-
-(define_insn *movdf_nofp
- [(set (match_operand:DF 0 nonimmediate_operand =r,r,m)
- (match_operand:DF 1 input_operand rG,m,r))]
- ! TARGET_FPREGS
-(register_operand (operands[0], DFmode)
- || reg_or_0_operand
[alpha] Unify movdi with attribute enabled.
This handles the movdi pattern, of which there were four copies...
r~
+ * config/alpha/alpha.md (attribute isa): Add er, ner.
+ (attribute enabled): Handle them.
+ (*movdi): Merge *movdi_{er_nofix,nofix,er_fix,fix}.
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 0f71292..2161e64 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -181,7 +181,7 @@
;; Used to control the enabled attribute on a per-instruction basis.
;; For convenience, conflate ABI issues re loading of addresses with
;; an isa.
-(define_attr isa base,bwx,max,fix,cix,vms
+(define_attr isa base,bwx,max,fix,cix,vms,ner,er
(const_string base))
(define_attr enabled
@@ -189,7 +189,9 @@
(eq_attr isa max) (symbol_ref TARGET_MAX)
(eq_attr isa fix) (symbol_ref TARGET_FIX)
(eq_attr isa cix) (symbol_ref TARGET_CIX)
- (eq_attr isa vms) (symbol_ref TARGET_ABI_OPEN_VMS)
+(eq_attr isa vms) (symbol_ref TARGET_ABI_OPEN_VMS)
+(eq_attr isa ner) (symbol_ref !TARGET_EXPLICIT_RELOCS)
+(eq_attr isa er) (symbol_ref TARGET_EXPLICIT_RELOCS)
]
(const_int 1)))
@@ -4869,54 +4871,13 @@
operands[2] = pic_offset_table_rtx;
})
-(define_insn *movdi_er_nofix
- [(set (match_operand:DI 0 nonimmediate_operand =r,r,r,r,r,r,r,m,*f,*f,Q)
- (match_operand:DI 1 input_operand rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f))]
- TARGET_EXPLICIT_RELOCS ! TARGET_FIX
-(register_operand (operands[0], DImode)
- || reg_or_0_operand (operands[1], DImode))
- @
- mov %r1,%0
- lda %0,%1($31)
- ldah %0,%h1($31)
- #
- #
- #
- ldq%A1 %0,%1
- stq%A0 %r1,%0
- fmov %R1,%0
- ldt %0,%1
- stt %R1,%0
- [(set_attr type ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst)
- (set_attr usegp *,*,*,yes,*,*,*,*,*,*,*)])
-
-(define_insn *movdi_nofix
- [(set (match_operand:DI 0 nonimmediate_operand =r,r,r,r,r,r,m,*f,*f,Q)
- (match_operand:DI 1 input_operand rJ,K,L,s,n,m,rJ,*fJ,Q,*f))]
- ! TARGET_FIX
-(register_operand (operands[0], DImode)
- || reg_or_0_operand (operands[1], DImode))
- @
- bis $31,%r1,%0
- lda %0,%1($31)
- ldah %0,%h1($31)
- lda %0,%1
- #
- ldq%A1 %0,%1
- stq%A0 %r1,%0
- cpys %R1,%R1,%0
- ldt %0,%1
- stt %R1,%0
- [(set_attr type ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst)])
-
-(define_insn *movdi_er_fix
+(define_insn *movdi
[(set (match_operand:DI 0 nonimmediate_operand
- =r,r,r,r,r,r,r, m, *f,*f, Q, r,*f)
+ =r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f)
(match_operand:DI 1 input_operand
- rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r))]
- TARGET_EXPLICIT_RELOCS TARGET_FIX
-(register_operand (operands[0], DImode)
- || reg_or_0_operand (operands[1], DImode))
+ rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r))]
+ register_operand (operands[0], DImode)
+ || reg_or_0_operand (operands[1], DImode)
@
mov %r1,%0
lda %0,%1($31)
@@ -4924,36 +4885,17 @@
#
#
#
- ldq%A1 %0,%1
- stq%A0 %r1,%0
- fmov %R1,%0
- ldt %0,%1
- stt %R1,%0
- ftoit %1,%0
- itoft %1,%0
- [(set_attr type
ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof)
- (set_attr usegp *,*,*,yes,*,*,*,*,*,*,*,*,*)])
-
-(define_insn *movdi_fix
- [(set (match_operand:DI 0 nonimmediate_operand
=r,r,r,r,r,r,m,*f,*f,Q,r,*f)
- (match_operand:DI 1 input_operand rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r))]
- ! TARGET_EXPLICIT_RELOCS TARGET_FIX
-(register_operand (operands[0], DImode)
- || reg_or_0_operand (operands[1], DImode))
- @
- bis $31,%r1,%0
- lda %0,%1($31)
- ldah %0,%h1($31)
lda %0,%1
- #
ldq%A1 %0,%1
stq%A0 %r1,%0
- cpys %R1,%R1,%0
+ fmov %R1,%0
ldt %0,%1
stt %R1,%0
ftoit %1,%0
itoft %1,%0
- [(set_attr type
ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof)])
+ [(set_attr type
ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof)
+ (set_attr isa *,*,*,er,er,*,ner,*,*,*,*,*,fix,fix)
+ (set_attr usegp *,*,*,yes,*,*,*,*,*,*,*,*,*,*)])
;; VMS needs to set up vms_base_regno for unwinding. This move
;; often appears dead to the life analysis code, at which point we
[alpha] Tidy some byte manipulation users.
We have helper expanders -- originally for the builtins -- so that we can
write mskwh instead of mskxh-plus-magic-argument. Use them more often.
r~
+ * config/alpha/alpha.c (alpha_expand_unaligned_load): Use extql.
+ (alpha_expand_unaligned_store): Use mskwl, mskll, mskql.
+ (alpha_expand_unaligned_load_words): Use extql.
+ (alpha_expand_unaligned_store_words): Use insqh, mskqh, mskql.
+ (emit_insxl): Handle all modes for consistency.
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 4885be6..c55587b 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -3347,7 +3347,7 @@ alpha_expand_unaligned_load (rtx tgt, rtx mem,
HOST_WIDE_INT size,
{
emit_move_insn (addr, plus_constant (mema, ofs+2));
- emit_insn (gen_extxl (extl, meml, GEN_INT (64), addr));
+ emit_insn (gen_extql (extl, meml, addr));
emit_insn (gen_extqh (exth, memh, addr));
/* We must use tgt here for the target. Alpha-vms port fails if we use
@@ -3367,17 +3367,14 @@ alpha_expand_unaligned_load (rtx tgt, rtx mem,
HOST_WIDE_INT size,
emit_insn (gen_extwh (exth, memh, addr));
mode = HImode;
break;
-
case 4:
emit_insn (gen_extlh (exth, memh, addr));
mode = SImode;
break;
-
case 8:
emit_insn (gen_extqh (exth, memh, addr));
mode = DImode;
break;
-
default:
gcc_unreachable ();
}
@@ -3475,16 +3472,13 @@ alpha_expand_unaligned_store (rtx dst, rtx src,
switch ((int) size)
{
case 2:
- emit_insn (gen_mskxl (dstl, dstl, GEN_INT (0x), addr));
+ emit_insn (gen_mskwl (dstl, dstl, addr));
break;
case 4:
- {
- rtx msk = immed_double_const (0x, 0, DImode);
- emit_insn (gen_mskxl (dstl, dstl, msk, addr));
- break;
- }
+ emit_insn (gen_mskll (dstl, dstl, addr));
+ break;
case 8:
- emit_insn (gen_mskxl (dstl, dstl, constm1_rtx, addr));
+ emit_insn (gen_mskql (dstl, dstl, addr));
break;
default:
gcc_unreachable ();
@@ -3516,7 +3510,6 @@ alpha_expand_unaligned_load_words (rtx *out_regs, rtx
smem,
HOST_WIDE_INT words, HOST_WIDE_INT ofs)
{
rtx const im8 = GEN_INT (-8);
- rtx const i64 = GEN_INT (64);
rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
rtx sreg, areg, tmp, smema;
HOST_WIDE_INT i;
@@ -3563,7 +3556,7 @@ alpha_expand_unaligned_load_words (rtx *out_regs, rtx
smem,
1, OPTAB_WIDEN);
for (i = 0; i words; ++i)
{
- emit_insn (gen_extxl (data_regs[i], data_regs[i], i64, sreg));
+ emit_insn (gen_extql (data_regs[i], data_regs[i], sreg));
emit_insn (gen_extqh (ext_tmps[i], data_regs[i+1], sreg));
emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
gen_rtx_IF_THEN_ELSE (DImode,
@@ -3588,7 +3581,6 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx
dmem,
HOST_WIDE_INT words, HOST_WIDE_INT ofs)
{
rtx const im8 = GEN_INT (-8);
- rtx const i64 = GEN_INT (64);
rtx ins_tmps[MAX_MOVE_WORDS];
rtx st_tmp_1, st_tmp_2, dreg;
rtx st_addr_1, st_addr_2, dmema;
@@ -3628,7 +3620,7 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx
dmem,
{
for (i = words-1; i = 0; --i)
{
- emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
+ emit_insn (gen_insqh (ins_tmps[i], data_regs[i], dreg));
emit_insn (gen_insql (data_regs[i], data_regs[i], dreg));
}
for (i = words-1; i 0; --i)
@@ -3640,8 +3632,8 @@ alpha_expand_unaligned_store_words (rtx *data_regs, rtx
dmem,
}
/* Split and merge the ends with the destination data. */
- emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
- emit_insn (gen_mskxl (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
+ emit_insn (gen_mskqh (st_tmp_2, st_tmp_2, dreg));
+ emit_insn (gen_mskql (st_tmp_1, st_tmp_1, dreg));
if (data_regs != NULL)
{
@@ -4311,12 +4303,24 @@ emit_insxl (enum machine_mode mode, rtx op1, rtx op2)
rtx ret = gen_reg_rtx (DImode);
rtx (*fn) (rtx, rtx, rtx);
- if (mode == QImode)
-fn = gen_insbl;
- else
-fn = gen_inswl;
+ switch (mode)
+{
+case QImode:
+ fn = gen_insbl;
+ break;
+case HImode:
+ fn = gen_inswl;
+ break;
+case SImode:
+ fn = gen_insll;
+ break;
+case DImode:
+ fn = gen_insql;
+ break;
+default:
+ gcc_unreachable ();
+}
- /* The insbl and inswl patterns require a register operand. */
op1 = force_reg (mode, op1);
emit_insn (fn (ret, op1, op2));
Re: [PATCH] use cfglayout mode for instatiate_virtual_regs
On Thu, Mar 24, 2011 at 4:47 AM, Nathan Froyd froy...@codesourcery.com wrote: As $SUBJECT suggests. The patch looks much bigger than it actually is due to re-indentation. Tested on x86_64-unknown-linux-gnu. OK to commit? -Nathan * function.c (instantiate_virtual_regs): Use FOR_EACH_BB and FOR_BB_INSNS_SAFE to iterate through insns. Re-indent. * passes.c (init_optimization_passes): Move pass_instantiate_virtual_regs after pass_into_cfg_layout_mode. This caused: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48282 -- H.J.
Go patch committed: Remove closed function
The predeclared function closed has been removed from the Go language,
as it is no longer necessary now that v, ok = -c returns whether the
channel is closed. This patch implements that in gccgo. This patch
also fixes the handling of case v, ok := -c in a select statement.
Bootstrapped and ran Go testsuite on x86_64-unknown-linux-gnu.
Committed to mainline.
Ian
diff -r 8de7f64be423 go/expressions.cc
--- a/go/expressions.cc Thu Mar 24 16:37:44 2011 -0700
+++ b/go/expressions.cc Thu Mar 24 21:58:25 2011 -0700
@@ -6530,7 +6530,6 @@
BUILTIN_APPEND,
BUILTIN_CAP,
BUILTIN_CLOSE,
- BUILTIN_CLOSED,
BUILTIN_COMPLEX,
BUILTIN_COPY,
BUILTIN_IMAG,
@@ -6588,8 +6587,6 @@
this-code_ = BUILTIN_CAP;
else if (name == close)
this-code_ = BUILTIN_CLOSE;
- else if (name == closed)
-this-code_ = BUILTIN_CLOSED;
else if (name == complex)
this-code_ = BUILTIN_COMPLEX;
else if (name == copy)
@@ -7185,9 +7182,6 @@
case BUILTIN_PRINTLN:
return Type::make_void_type();
-case BUILTIN_CLOSED:
- return Type::lookup_bool_type();
-
case BUILTIN_RECOVER:
return Type::make_interface_type(NULL, BUILTINS_LOCATION);
@@ -7451,7 +7445,6 @@
break;
case BUILTIN_CLOSE:
-case BUILTIN_CLOSED:
if (this-check_one_arg())
{
if (this-one_arg()-type()-channel_type() == NULL)
@@ -7936,7 +7929,6 @@
}
case BUILTIN_CLOSE:
-case BUILTIN_CLOSED:
{
const Expression_list* args = this-args();
gcc_assert(args != NULL args-size() == 1);
@@ -7944,28 +7936,14 @@
tree arg_tree = arg-get_tree(context);
if (arg_tree == error_mark_node)
return error_mark_node;
- if (this-code_ == BUILTIN_CLOSE)
- {
- static tree close_fndecl;
- return Gogo::call_builtin(close_fndecl,
- location,
- __go_builtin_close,
- 1,
- void_type_node,
- TREE_TYPE(arg_tree),
- arg_tree);
- }
- else
- {
- static tree closed_fndecl;
- return Gogo::call_builtin(closed_fndecl,
- location,
- __go_builtin_closed,
- 1,
- boolean_type_node,
- TREE_TYPE(arg_tree),
- arg_tree);
- }
+ static tree close_fndecl;
+ return Gogo::call_builtin(close_fndecl,
+ location,
+ __go_builtin_close,
+ 1,
+ void_type_node,
+ TREE_TYPE(arg_tree),
+ arg_tree);
}
case BUILTIN_SIZEOF:
diff -r 8de7f64be423 go/gogo.cc
--- a/go/gogo.cc Thu Mar 24 16:37:44 2011 -0700
+++ b/go/gogo.cc Thu Mar 24 21:58:25 2011 -0700
@@ -173,15 +173,6 @@
close_type-set_is_builtin();
this-globals_-add_function_declaration(close, NULL, close_type, loc);
- Typed_identifier_list* closed_result = new Typed_identifier_list();
- closed_result-push_back(Typed_identifier(, Type::lookup_bool_type(),
- loc));
- Function_type* closed_type = Type::make_function_type(NULL, NULL,
- closed_result, loc);
- closed_type-set_is_varargs();
- closed_type-set_is_builtin();
- this-globals_-add_function_declaration(closed, NULL, closed_type, loc);
-
Typed_identifier_list* copy_result = new Typed_identifier_list();
copy_result-push_back(Typed_identifier(, int_type, loc));
Function_type* copy_type = Type::make_function_type(NULL, NULL,
@@ -3506,12 +3497,15 @@
true);
this-init_ = NULL;
}
+ else if (this-type_from_chan_element_)
+{
+ Expression* init = this-init_;
+ init-determine_type_no_context();
+ this-type_ = this-type_from_chan_element(init, true);
+ this-init_ = NULL;
+}
else
{
- // type_from_chan_element_ should have been cleared during
- // lowering.
- gcc_assert(!this-type_from_chan_element_);
-
Type_context context(this-type_, false);
this-init_-determine_type(context);
if (this-type_ == NULL)
diff -r 8de7f64be423 go/parse.cc
--- a/go/parse.cc Thu Mar 24 16:37:44 2011 -0700
+++ b/go/parse.cc Thu Mar 24 21:58:25 2011 -0700
@@ -1717,6 +1717,7 @@
Statement* s = Statement::make_tuple_receive_assignment(val_var,
received_var,
receive-channel(),
+ false,
location);
if (!this-gogo_-in_global_scope())
@@ -3629,6 +3630,7 @@
Expression* channel = receive-channel();
Statement* s = Statement::make_tuple_receive_assignment(val, success,
channel,
+ false,
location);
this-gogo_-add_statement(s);
}
diff -r 8de7f64be423 go/statements.cc
--- a/go/statements.cc Thu Mar 24 16:37:44 2011 -0700
+++ b/go/statements.cc Thu Mar 24 21:58:25 2011 -0700
@@ -1148,10 +1148,10 @@
{
public:
Tuple_receive_assignment_statement(Expression* val, Expression* closed,
- Expression* channel,
+ Expression* channel, bool for_select,
source_location location)
: Statement(STATEMENT_TUPLE_RECEIVE_ASSIGNMENT, location),
- val_(val), closed_(closed), channel_(channel)
+ val_(val),
Re: [PATCH] use cfglayout mode for instatiate_virtual_regs
On Thu, Mar 24, 2011 at 9:11 PM, H.J. Lu hjl.to...@gmail.com wrote: On Thu, Mar 24, 2011 at 4:47 AM, Nathan Froyd froy...@codesourcery.com wrote: As $SUBJECT suggests. The patch looks much bigger than it actually is due to re-indentation. Tested on x86_64-unknown-linux-gnu. OK to commit? Did you run -m32 tests on Linux/x86-64? Many 32bit tests failed on Linux/x86-64: http://gcc.gnu.org/ml/gcc-testresults/2011-03/msg02419.html -Nathan * function.c (instantiate_virtual_regs): Use FOR_EACH_BB and FOR_BB_INSNS_SAFE to iterate through insns. Re-indent. * passes.c (init_optimization_passes): Move pass_instantiate_virtual_regs after pass_into_cfg_layout_mode. This caused: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48282 -- H.J.
