[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing passed.* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level passed. * build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby passed. * build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest passed. * build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter passed. * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl passed. * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem passed. * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing passed. * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic passed. * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing passed. * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic passed. * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing passed. * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby passed. *
[gem5-dev] review board not working, CPUID fix
I tried to upload these patches to review board but it kept giving me this: abort: The file was not found in the repository (207) stat: fail file: src/arch/x86/cpuid.cc One is a revert of the original CPUID patch, and the second is a new patch which enables just a few feature bits to make SE mode happy. It works for me, but I can only test on my dev machine. Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] KVM and CPUID
Hi folks. I was just thinking about how that CPUID change caused problems when running ChromeOS, and it occurred to me that it doesn't matter what gem5 supports when CPUID is run if the host system doesn't support the features it claims. To be really safe, when running with KVM, we should report at most the features the host supports, as much as that's possible. That could cause a problem, though, if gem5 supports a feature that the host system doesn't. We'd either have to consistently disable that feature if KVM is used, the feature bits reported by CPUID would change depending on what CPU was being used, or we'd just have to hope the simulated system didn't use the feature when under KVM. Food for thought. Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2514: scons: Make the USE_KVM variable available in C++.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2514/#review5692 --- Ship it! Ship It! - Andreas Hansson On Nov. 19, 2014, 6:44 a.m., Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2514/ --- (Updated Nov. 19, 2014, 6:44 a.m.) Review request for Default. Repository: gem5 Description --- Changeset 10548:07c3cbac4cdd --- scons: Make the USE_KVM variable available in C++. We need it to determine whether we should expect KVM related parameters exist in the cirrus graphics device. Diffs - SConstruct 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 Diff: http://reviews.gem5.org/r/2514/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2511: dev: cirrus: Add a simplified device model for the cirrus graphics device.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/#review5693 --- src/dev/Cirrus.py http://reviews.gem5.org/r/2511/#comment5067 Remove? Or add a comment src/dev/cirrus.hh http://reviews.gem5.org/r/2511/#comment5068 all of these public? Why? src/dev/cirrus.cc http://reviews.gem5.org/r/2511/#comment5069 Please use getConstPtr src/dev/cirrus.cc http://reviews.gem5.org/r/2511/#comment5070 Remove? Or add a more elaborate comment src/dev/cirrus.cc http://reviews.gem5.org/r/2511/#comment5071 Can we not simply check if kvmkvm is nullptr? src/dev/cirrus.cc http://reviews.gem5.org/r/2511/#comment5072 I am not too fond of this. Can we note make it null or have a NullKVMVM or similar? src/dev/cirrus.cc http://reviews.gem5.org/r/2511/#comment5073 Rather unfortunate imho. src/dev/cirrus.cc http://reviews.gem5.org/r/2511/#comment5074 What if we have a scheduled updateEvent? - Andreas Hansson On Dec. 17, 2014, 7:39 a.m., Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2511/ --- (Updated Dec. 17, 2014, 7:39 a.m.) Review request for Default. Repository: gem5 Description --- Changeset 10609:07584c650657 --- dev: cirrus: Add a simplified device model for the cirrus graphics device. All control register accesses are dropped on the floor. If used with KVM, the frame buffer is set up as a memory like region to keep performance from tanking. If a VNC server is configured, the buffer is marked dirty once every simulated 100ms. Diffs - src/dev/Cirrus.py PRE-CREATION src/dev/SConscript a0cb57e1c072965dcdd51465beff37b264b41424 src/dev/cirrus.hh PRE-CREATION src/dev/cirrus.cc PRE-CREATION Diff: http://reviews.gem5.org/r/2511/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2514: scons: Make the USE_KVM variable available in C++.
On Dec. 17, 2014, 1:41 p.m., Andreas Hansson wrote: Ship It! Actually, looking at the Cirrus device, could we not simply check if KvmVM is nullptr? - Andreas --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2514/#review5692 --- On Nov. 19, 2014, 6:44 a.m., Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2514/ --- (Updated Nov. 19, 2014, 6:44 a.m.) Review request for Default. Repository: gem5 Description --- Changeset 10548:07c3cbac4cdd --- scons: Make the USE_KVM variable available in C++. We need it to determine whether we should expect KVM related parameters exist in the cirrus graphics device. Diffs - SConstruct 288eb5ee4b0026d0cc1f02ec31748e0eaac06bc3 Diff: http://reviews.gem5.org/r/2514/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2518: x86: i8042: Add VNC mouse support, and flesh out the mouse model.
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2518/#review5695 --- src/dev/x86/i8042.hh http://reviews.gem5.org/r/2518/#comment5077 I know it is not changed, but could you elaborate on the unit? src/dev/x86/i8042.cc http://reviews.gem5.org/r/2518/#comment5075 const? src/dev/x86/i8042.cc http://reviews.gem5.org/r/2518/#comment5076 const? src/dev/x86/i8042.cc http://reviews.gem5.org/r/2518/#comment5078 , _space_ src/dev/x86/i8042.cc http://reviews.gem5.org/r/2518/#comment5079 For the body of this, could you elaborate on why it looks the way it does? At the moment it is very thin on comments src/dev/x86/i8042.cc http://reviews.gem5.org/r/2518/#comment5080 setMouseAt? Looks good, some minor things - Andreas Hansson On Nov. 23, 2014, 1:50 p.m., Gabe Black wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2518/ --- (Updated Nov. 23, 2014, 1:50 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10555:a13dc3596e45 --- x86: i8042: Add VNC mouse support, and flesh out the mouse model. This change fleshes out the mouse model so that it can send mouse data to the simulated system somewhat realistically, and hooks it into the VNC server as the mouse input device. Diffs - src/dev/x86/I8042.py f9fb64a72259a2514080151b5250a04c575d443a src/dev/x86/i8042.hh f9fb64a72259a2514080151b5250a04c575d443a src/dev/x86/i8042.cc f9fb64a72259a2514080151b5250a04c575d443a Diff: http://reviews.gem5.org/r/2518/diff/ Testing --- Thanks, Gabe Black ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] InOrder CPU with ARM
Hi, I try to run the ARM in-order cpu and it still does not work. Is anyone working on this since 2012? Thank you Regards ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] InOrder CPU with ARM
The in-order cpu model is deprecated and will soon be removed from the tree. Id you'd like an in order cpu model use the minor cpu model which supports ARM. Ali Sent from my ARM powered mobile device On Dec 17, 2014, at 2:18 PM, Anastasiia via gem5-dev gem5-dev@gem5.org wrote: Hi, I try to run the ARM in-order cpu and it still does not work. Is anyone working on this since 2012? Thank you Regards ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] InOrder CPU with ARM
Hi all, Given that the InOrderCPU is causing confusion, and only ever compiled for MIPS and SPARC, how would people feel about: 1) Go ahead and remove the two regressions using the model, and also stop compiling it for MIPS and SPARC. This could be done in the next few weeks if no one objects. If someone really wants to use MIPS and SPARC in-order cores I would argue the best path forward is to add support for a branch delay slot to the MinorCPU. 2) Prune the actual InOrderCPU code early Q1 2015. 3) Rename MinorCPU - InOrderCPU shortly after (2). Thoughts around this timeline? Andreas On 17/12/2014 15:11, Ali Saidi via gem5-dev gem5-dev@gem5.org wrote: The in-order cpu model is deprecated and will soon be removed from the tree. Id you'd like an in order cpu model use the minor cpu model which supports ARM. Ali Sent from my ARM powered mobile device On Dec 17, 2014, at 2:18 PM, Anastasiia via gem5-dev gem5-dev@gem5.org wrote: Hi, I try to run the ARM in-order cpu and it still does not work. Is anyone working on this since 2012? Thank you Regards ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Fault Model
Dear developers users you had added the Fault Model(aisopos konistantinus) to gem5. but you didn't any info in gem5 wiki. when i send an email to writer of this fault model he don't reply to my emails. plz if you have some info plz tell me study those. more and less i get some info about tthis fault model. but i don't find how i can run it in runtime. i know i could use --network-fault-model in command line but my mean is this tool uses fixed value to evaluate probability of fault on starting simulation and print the result. so the traffic of gem5 don't effect on fault model. if you dont agree with me so when the fault patterns inject to gem5 . Best ---Babak Aghaei Ph.D candidate ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
