date:20161027

Re: [gem5-dev] Status of RISC-V patches

2016-10-27 Thread Alec Roelke

I'll start with converting as many from "quick" as I can.  If/when I end up
creating my own, is there a convention for what they should be named and
where they should go?

Also, I'm having a bit of a problem with just 00.hello.  I compiled the
source in tests/test-progs/hello/src into
tests/test-progs/hello/bin/riscv/linux (for some reason mine disappeared),
and then created tests/quick/se/00.hello/ref/riscv/linux/simple-atomic.
Then I compiled and ran build/RISCV/gem5.fast, configuring for the atomic
CPU and redirecting the output stats, configuration, stdout, and stderr
into that directory.  But when I run
build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic, it
claims that it couldn't find several stats and that it found several other
unexpected ones in stats.txt (and completely ignored the other files).  Is
there some other configuration I should be using to generate the output for
the regression?  Actually, better yet, is there a way for me to figure out
what the configuration I should be using is, since I imagine I'll run into
this problem for the other CPU models?

On Thu, Oct 27, 2016 at 6:38 PM, Jason Lowe-Power 
wrote:

> Hi Alec,
>
> Thanks for taking the time for writing tests. It's something that we as a
> community need to get better at.
>
> To respond to your questions:
> - It is completely acceptable for you to include RISC-V only tests. In
> fact, I think it's a necessity.
> - Focusing just on the "quick" regressions makes sense to me. If you have
> one or two longer benchmarks, that would be good, but not required. If you
> could stay away from SPEC it would be better. I believe that we can't
> distribute the binaries, which makes it a pain for others to run the
> regression test.
> - Covering corner cases would be amazing, but again, not required. If you
> look at gem5's current regression suite, you'll find that we currently
> don't have anything like that. So, if it doesn't take you too much time,
> this would be a good addition, but just getting coverage of all
> instructions would be a step up from all the other ISAs.
> - For m5threads, no need to implement it for RISC-V. Although, it looks
> like you only need to implement 3 functions, so I don't think it would be
> too hard. But that's a project for another day :).
>
> Again, I want to stress that we can't expect you to spend lots of time
> writing great regressions. It would be very hypocritical :). Anything is
> acceptable. Of course, better regressions mean that RISC-V will be more
> usable and more stable.
>
> Cheers,
> Jason
>
> On Thu, Oct 27, 2016 at 5:29 PM Alec Roelke  wrote:
>
>> I'll certainly add regressions for "hello" for each of the four models,
>> and I'll try to get other "quick" tests done the same way, too.  I won't be
>> able to do all of them as m5threads hasn't been implemented for RISC-V, but
>> I'll do what I can.  I can also do the "long" ones the same way, if time
>> isn't a concern (I noticed some were from SPEC, which could take a long
>> time to complete).
>>
>> Because m5threads hasn't been implemented for RISC-V, and my patches only
>> support SE mode, I can't actually test if the atomic instructions work
>> properly when used concurrently, but I can at least test that they perform
>> the read-modify-write operations properly.  Is it okay if I add a few
>> regressions that only work for RISC-V since they'd use assembly calls?  For
>> that matter, should I be making sure that the existing regressions cover
>> corner cases in instructions, or is it sufficient to see that each
>> instruction is represented at least once by them?  I could write some tests
>> that check corner cases, but at least some would use assembly calls and
>> thus be incompatible with anything other than RISC-V.
>>
>> On Thu, Oct 27, 2016 at 5:55 PM, Jason Lowe-Power 
>> wrote:
>>
>> Hi Alec,
>>
>> Thanks again for implementing RISC-V in gem5. It's an incredibly
>> important and timely addition!
>>
>> As far as I can tell, the patches look good. Hopefully some other will
>> review them soon as well.
>>
>> The only thing that's missing that I would really like to have before
>> pushing the patches is some regression tests for RISC-V. If you could look
>> at http://gem5.org/Regression_Tests and have a go at adding some
>> regressions, it would be helpful. It would be *great* if you could make
>> sure the regressions cover most of what you've implemented (e.g.,
>> multiply/atomic/etc. instructions, Linux syscalls, etc.). If that isn't
>> possible, at least having a "hello" regression for a couple of different
>> CPU models is needed.
>>
>> Thanks again for your contribution!
>>
>> Jason
>>
>>
>>
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Re: [gem5-dev] Status of RISC-V patches

2016-10-27 Thread Alec Roelke

I'll certainly add regressions for "hello" for each of the four models, and
I'll try to get other "quick" tests done the same way, too.  I won't be
able to do all of them as m5threads hasn't been implemented for RISC-V, but
I'll do what I can.  I can also do the "long" ones the same way, if time
isn't a concern (I noticed some were from SPEC, which could take a long
time to complete).

Because m5threads hasn't been implemented for RISC-V, and my patches only
support SE mode, I can't actually test if the atomic instructions work
properly when used concurrently, but I can at least test that they perform
the read-modify-write operations properly.  Is it okay if I add a few
regressions that only work for RISC-V since they'd use assembly calls?  For
that matter, should I be making sure that the existing regressions cover
corner cases in instructions, or is it sufficient to see that each
instruction is represented at least once by them?  I could write some tests
that check corner cases, but at least some would use assembly calls and
thus be incompatible with anything other than RISC-V.

On Thu, Oct 27, 2016 at 5:55 PM, Jason Lowe-Power 
wrote:

> Hi Alec,
>
> Thanks again for implementing RISC-V in gem5. It's an incredibly important
> and timely addition!
>
> As far as I can tell, the patches look good. Hopefully some other will
> review them soon as well.
>
> The only thing that's missing that I would really like to have before
> pushing the patches is some regression tests for RISC-V. If you could look
> at http://gem5.org/Regression_Tests and have a go at adding some
> regressions, it would be helpful. It would be *great* if you could make
> sure the regressions cover most of what you've implemented (e.g.,
> multiply/atomic/etc. instructions, Linux syscalls, etc.). If that isn't
> possible, at least having a "hello" regression for a couple of different
> CPU models is needed.
>
> Thanks again for your contribution!
>
> Jason
>
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Re: [gem5-dev] Status of RISC-V patches

2016-10-27 Thread Jason Lowe-Power

Hi Alec,

Thanks for taking the time for writing tests. It's something that we as a
community need to get better at.

To respond to your questions:
- It is completely acceptable for you to include RISC-V only tests. In
fact, I think it's a necessity.
- Focusing just on the "quick" regressions makes sense to me. If you have
one or two longer benchmarks, that would be good, but not required. If you
could stay away from SPEC it would be better. I believe that we can't
distribute the binaries, which makes it a pain for others to run the
regression test.
- Covering corner cases would be amazing, but again, not required. If you
look at gem5's current regression suite, you'll find that we currently
don't have anything like that. So, if it doesn't take you too much time,
this would be a good addition, but just getting coverage of all
instructions would be a step up from all the other ISAs.
- For m5threads, no need to implement it for RISC-V. Although, it looks
like you only need to implement 3 functions, so I don't think it would be
too hard. But that's a project for another day :).

Again, I want to stress that we can't expect you to spend lots of time
writing great regressions. It would be very hypocritical :). Anything is
acceptable. Of course, better regressions mean that RISC-V will be more
usable and more stable.

Cheers,
Jason

On Thu, Oct 27, 2016 at 5:29 PM Alec Roelke  wrote:

> I'll certainly add regressions for "hello" for each of the four models,
> and I'll try to get other "quick" tests done the same way, too.  I won't be
> able to do all of them as m5threads hasn't been implemented for RISC-V, but
> I'll do what I can.  I can also do the "long" ones the same way, if time
> isn't a concern (I noticed some were from SPEC, which could take a long
> time to complete).
>
> Because m5threads hasn't been implemented for RISC-V, and my patches only
> support SE mode, I can't actually test if the atomic instructions work
> properly when used concurrently, but I can at least test that they perform
> the read-modify-write operations properly.  Is it okay if I add a few
> regressions that only work for RISC-V since they'd use assembly calls?  For
> that matter, should I be making sure that the existing regressions cover
> corner cases in instructions, or is it sufficient to see that each
> instruction is represented at least once by them?  I could write some tests
> that check corner cases, but at least some would use assembly calls and
> thus be incompatible with anything other than RISC-V.
>
> On Thu, Oct 27, 2016 at 5:55 PM, Jason Lowe-Power 
> wrote:
>
> Hi Alec,
>
> Thanks again for implementing RISC-V in gem5. It's an incredibly important
> and timely addition!
>
> As far as I can tell, the patches look good. Hopefully some other will
> review them soon as well.
>
> The only thing that's missing that I would really like to have before
> pushing the patches is some regression tests for RISC-V. If you could look
> at http://gem5.org/Regression_Tests and have a go at adding some
> regressions, it would be helpful. It would be *great* if you could make
> sure the regressions cover most of what you've implemented (e.g.,
> multiply/atomic/etc. instructions, Linux syscalls, etc.). If that isn't
> possible, at least having a "hello" regression for a couple of different
> CPU models is needed.
>
> Thanks again for your contribution!
>
> Jason
>
>
>
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[gem5-dev] Status of RISC-V patches

2016-10-27 Thread Jason Lowe-Power

Hi Alec,

Thanks again for implementing RISC-V in gem5. It's an incredibly important
and timely addition!

As far as I can tell, the patches look good. Hopefully some other will
review them soon as well.

The only thing that's missing that I would really like to have before
pushing the patches is some regression tests for RISC-V. If you could look
at http://gem5.org/Regression_Tests and have a go at adding some
regressions, it would be helpful. It would be *great* if you could make
sure the regressions cover most of what you've implemented (e.g.,
multiply/atomic/etc. instructions, Linux syscalls, etc.). If that isn't
possible, at least having a "hello" regression for a couple of different
CPU models is needed.

Thanks again for your contribution!

Jason
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Re: [gem5-dev] Review Request 3627: riscv: [Patch 2/5] Added RISC-V multiply extension RV64M

2016-10-27 Thread Jason Lowe-Power


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---

Ship it!


Seems reasonable to me.

- Jason Lowe-Power


On Sept. 29, 2016, 6:59 p.m., Alec Roelke wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3627/
> ---
> 
> (Updated Sept. 29, 2016, 6:59 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11656:8fa017d0d977
> ---
> riscv: [Patch 2/5] Added RISC-V multiply extension RV64M
> 
> Second of five patches adding RISC-V to GEM5.  This patch adds the
> RV64M extension, which includes integer multiply and divide instructions.
> 
> Patch 1 introduced RISC-V and implemented the base instruction set, RV64I.
> 
> Patch 3 will implement the floating point extensions, RV64FD; patch 4 will
> implement the atomic memory instructions, RV64A; and patch 5 will add
> support for timing, minor, and detailed CPU models that is missing from
> the first four patches.
> 
> [Added mulw instruction that was missed when dividing changes among
> patches.]
> Signed-off by: Alec Roelke
> 
> 
> Diffs
> -
> 
>   src/arch/riscv/isa/decoder.isa PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3627/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Alec Roelke
> 
>

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Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-10-27 Thread Jason Lowe-Power


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---

Ship it!


Sorry for the delay. I finally got everything working and it looks good to me! 
I'll start testing the other patches in the series soon.

- Jason Lowe-Power


On Oct. 21, 2016, 6:12 p.m., Alec Roelke wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3624/
> ---
> 
> (Updated Oct. 21, 2016, 6:12 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11688:f84b3613acf4
> ---
> arch: [Patch 1/5] Added RISC-V base instruction set RV64I
> 
> First of five patches adding RISC-V to GEM5. This patch introduces the
> base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
> The multiply, floating point, and atomic memory instructions will be added
> in additional patches, as well as support for more detailed CPU models.
> The loader is also modified to be able to parse RISC-V ELF files, and a
> "Hello world\!" example for RISC-V is added to test-progs.
> 
> Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
> the floating point (single- and double-precision) extensions, RV64FD;
> patch 4 will implement the atomic memory instructions, RV64A, and patch 5
> will add support for timing, minor, and detailed CPU models that is missing
> from the first four patches (such as handling locked memory).
> 
> [Removed several unused parameters and imports from RiscvInterrupts.py,
> RiscvISA.py, and RiscvSystem.py.]
> [Fixed copyright information in RISC-V files copied from elsewhere that had
> ARM licenses attached.]
> [Reorganized instruction definitions in decoder.isa so that they are sorted
> by opcode in preparation for the addition of ISA extensions M, A, F, D.]
> [Fixed formatting of several files, removed some variables and
> instructions that were missed when moving them to other patches, fixed
> RISC-V Foundation copyright attribution, and fixed history of files
> copied from other architectures using hg copy.]
> [Fixed indentation of switch cases in isa.cc.]
> [Reorganized syscall descriptions in linux/process.cc to remove large
> number of repeated unimplemented system calls and added implmementations
> to functions that have received them since it process.cc was first
> created.]
> [Fixed spacing for some copyright attributions.]
> [Replaced the rest of the file copies using hg copy.]
> [Fixed style check errors and corrected unaligned memory accesses.]
> Signed-off by: Alec Roelke
> 
> 
> Diffs
> -
> 
>   src/arch/riscv/isa/bitfields.isa PRE-CREATION 
>   src/arch/riscv/isa/decoder.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/basic.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/formats.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/mem.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/type.isa PRE-CREATION 
>   src/arch/riscv/isa/formats/unknown.isa PRE-CREATION 
>   src/arch/riscv/isa/includes.isa PRE-CREATION 
>   src/arch/riscv/isa/main.isa PRE-CREATION 
>   src/arch/riscv/isa/operands.isa PRE-CREATION 
>   src/arch/riscv/isa_traits.hh PRE-CREATION 
>   src/arch/riscv/kernel_stats.hh PRE-CREATION 
>   src/arch/riscv/linux/linux.hh PRE-CREATION 
>   src/arch/riscv/linux/linux.cc PRE-CREATION 
>   src/arch/riscv/linux/process.hh PRE-CREATION 
>   src/arch/riscv/linux/process.cc PRE-CREATION 
>   src/arch/riscv/locked_mem.hh PRE-CREATION 
>   src/arch/riscv/microcode_rom.hh PRE-CREATION 
>   src/arch/riscv/mmapped_ipr.hh PRE-CREATION 
>   src/arch/riscv/pagetable.hh PRE-CREATION 
>   src/arch/riscv/pagetable.cc PRE-CREATION 
>   src/arch/riscv/pra_constants.hh PRE-CREATION 
>   src/arch/riscv/system.hh PRE-CREATION 
>   src/arch/riscv/stacktrace.hh PRE-CREATION 
>   src/arch/riscv/process.cc PRE-CREATION 
>   src/arch/riscv/pseudo_inst.hh PRE-CREATION 
>   src/sim/process.cc b3d5f0e9e258 
>   src/base/loader/object_file.hh b3d5f0e9e258 
>   src/arch/riscv/utility.hh PRE-CREATION 
>   src/arch/riscv/tlb.cc PRE-CREATION 
>   src/arch/riscv/system.cc PRE-CREATION 
>   src/arch/riscv/stacktrace.cc PRE-CREATION 
>   src/arch/riscv/remote_gdb.hh PRE-CREATION 
>   src/arch/riscv/remote_gdb.cc PRE-CREATION 
>   src/arch/riscv/registers.hh PRE-CREATION 
>   src/arch/riscv/process.hh PRE-CREATION 
>   src/cpu/BaseCPU.py b3d5f0e9e258 
>   src/arch/riscv/vtophys.hh PRE-CREATION 
>   src/base/loader/elf_object.cc b3d5f0e9e258 
>   src/arch/riscv/types.hh PRE-CREATION 
>   src/arch/riscv/tlb.hh PRE-CREATION 
>   src/arch/riscv/isa.hh PRE-CREATION 
>   src/arch/riscv/isa.cc PRE-CREATION 
>   src/arch/riscv/isa/base.isa PRE-CREATION 
>   src/arch/riscv/decoder.hh PRE-CREATION 
>

Re: [gem5-dev] Review Request 3689: tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)

2016-10-27 Thread Jason Lowe-Power


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---

Ship it!


I'd like to update these tests to do more than 100 "checks". You could do it 
now (line 72 of rubytest-ruby.py). I tested 10 which took ~20 seconds on my 
Skylake machine. Or, I can submit a patch after this is checked in. It's up to 
you.

Thanks for doing this!

- Jason Lowe-Power


On Oct. 27, 2016, 7:50 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3689/
> ---
> 
> (Updated Oct. 27, 2016, 7:50 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11706:e542abbd3730
> ---
> tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)
> 
> This patch avoids compiling ALPHA six times as part of running
> 'util/regress', and instead relis on NULL with different protocols to
> run the rubytest. All we need is the memory system, so there is really
> no need to compile the ISA over and over again.
> 
> The one downside is the removal of running 'hello' for the variuos
> ALPHA and protocol combinations, but if this is a concern we should
> rather beef up the synthetic tests for the variuos protocols.
> 
> 
> Diffs
> -
> 
>   tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simout PRE-CREATION 
>   tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt 
> PRE-CREATION 
>   util/regress c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
>  c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr 
> c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout 
> c38fcdaa5fe5 
>   
> tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
>  c38fcdaa5fe5 
>   tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini 
> c38fcdaa5fe5 
>   tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr 
> c38fcdaa5fe5 
>   tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout 
> c38fcdaa5fe5

[gem5-dev] Branch prediction infrastructure rationale

2016-10-27 Thread Arthur Perais


High guys,

We just noticed some interesting behavior in the branch prediction 
infrastructure (bpred_unit.cc). I was wondering if some of you could 
shed light on it.


When a branch is mispredicted at execute, all younger branches in the 
history of branches are removed. Then, the predictor is updated with the 
actual direction (by calling update(squashed = true) ).


The history is marked as "wasSquashed", so that when it reaches commit, 
a second update does not take place (retireSquashed() is called, rather 
than update(), as a result of wasSquashed being true).


Now, you may know where I am going with this: in all branch predictors, 
the tables are updated when update(squashed = true) is called because 
there is no test against the value of squashed (except a fishy one in 
tournament.cc). This means that update is done speculatively at Execute, 
potentially on the *wrong path*. In other words, the predictor is 
potentially updated with garbage. What should be done is update the 
history with the actual direction at squash time, but *wait for commit 
to do the update*. As it stands, the more you do OoO on the wrong path, 
the worse branch prediction performance you get.


Now it is true that calling update() at squash time is useful if you 
want to fix whatever history you are using, and in that case, it is the 
responsibility of the predictor to test against the value of squashed in 
its update() function. However, the wasSquashed member and 
retireSquashed() function should probably be replaced by a call to 
update(squashed = false). What do you think?


Cheers,

Arthur.


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Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

2016-10-27 Thread Andreas Hansson


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---

Ship it!


thanks for getting this in shape

- Andreas Hansson


On Oct. 27, 2016, 11:25 a.m., Sophiane SENNI wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> ---
> 
> (Updated Oct. 27, 2016, 11:25 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11688:1a792798e845
> ---
> mem: Split the hit_latency into tag_latency and data_latency
> 
> If the cache access mode is parallel, i.e. "sequential_access" parameter
> is set to "False", tags and data are accessed in parallel. Therefore,
> the hit_latency is the maximum latency between tag_latency and
> data_latency. On the other hand, if the cache access mode is
> sequential, i.e. "sequential_access" parameter is set to "True",
> tags and data are accessed sequentially. Therefore, the hit_latency
> is the sum of tag_latency plus data_latency.
> 
> 
> Diffs
> -
> 
>   configs/common/Caches.py 4aac82f10951 
>   configs/common/O3_ARM_v7a.py 4aac82f10951 
>   configs/example/arm/devices.py 4aac82f10951 
>   configs/learning_gem5/part1/caches.py 4aac82f10951 
>   src/mem/cache/Cache.py 4aac82f10951 
>   src/mem/cache/base.hh 4aac82f10951 
>   src/mem/cache/base.cc 4aac82f10951 
>   src/mem/cache/tags/Tags.py 4aac82f10951 
>   src/mem/cache/tags/base.hh 4aac82f10951 
>   src/mem/cache/tags/base.cc 4aac82f10951 
>   src/mem/cache/tags/base_set_assoc.hh 4aac82f10951 
>   src/mem/cache/tags/fa_lru.hh 4aac82f10951 
>   src/mem/cache/tags/fa_lru.cc 4aac82f10951 
> 
> Diff: http://reviews.gem5.org/r/3502/diff/
> 
> 
> Testing
> ---
> 
> Tested using --Debug-flags=Cache
> 
> 
> Thanks,
> 
> Sophiane SENNI
> 
>

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Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

2016-10-27 Thread Sophiane SENNI


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---

(Updated Oct. 27, 2016, 11:25 a.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11688:1a792798e845
---
mem: Split the hit_latency into tag_latency and data_latency

If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.


Diffs (updated)
-

  configs/common/Caches.py 4aac82f10951 
  configs/common/O3_ARM_v7a.py 4aac82f10951 
  configs/example/arm/devices.py 4aac82f10951 
  configs/learning_gem5/part1/caches.py 4aac82f10951 
  src/mem/cache/Cache.py 4aac82f10951 
  src/mem/cache/base.hh 4aac82f10951 
  src/mem/cache/base.cc 4aac82f10951 
  src/mem/cache/tags/Tags.py 4aac82f10951 
  src/mem/cache/tags/base.hh 4aac82f10951 
  src/mem/cache/tags/base.cc 4aac82f10951 
  src/mem/cache/tags/base_set_assoc.hh 4aac82f10951 
  src/mem/cache/tags/fa_lru.hh 4aac82f10951 
  src/mem/cache/tags/fa_lru.cc 4aac82f10951 

Diff: http://reviews.gem5.org/r/3502/diff/


Testing
---

Tested using --Debug-flags=Cache


Thanks,

Sophiane SENNI

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Re: [gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM slave port

2016-10-27 Thread Andreas Hansson



> On Oct. 26, 2016, 7:22 p.m., Andreas Hansson wrote:
> > Somehow the patch is not displaying. Did you use hg postreview?
> 
> Christian Menard wrote:
> Hi Andreas! Thanks for your reviews, I will give them a look soon. I 
> wanted to do some cleaning up anyway as there are still some inconsistencies 
> in master and slave port.
> 
> I uploaded the patches manually since I don't have the postreview 
> extension. Where can I get it? The link on the wiki is broken.

No worries. The link is updated.


- Andreas


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---


On Oct. 26, 2016, 4:26 p.m., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3686/
> ---
> 
> (Updated Oct. 26, 2016, 4:26 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> This patch simplifies the implementation of the SystemC TLM slave port.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_slave_port.hh c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
>   util/tlm/sc_slave_port.cc c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
> 
> Diff: http://reviews.gem5.org/r/3686/diff/
> 
> 
> Testing
> ---
> 
> Example applications are still running.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM slave port

2016-10-27 Thread Christian Menard



> On Oct. 26, 2016, 7:22 p.m., Andreas Hansson wrote:
> > Somehow the patch is not displaying. Did you use hg postreview?

Hi Andreas! Thanks for your reviews, I will give them a look soon. I wanted to 
do some cleaning up anyway as there are still some inconsistencies in master 
and slave port.

I uploaded the patches manually since I don't have the postreview extension. 
Where can I get it? The link on the wiki is broken.


- Christian


---
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---


On Oct. 26, 2016, 4:26 p.m., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3686/
> ---
> 
> (Updated Oct. 26, 2016, 4:26 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> This patch simplifies the implementation of the SystemC TLM slave port.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_slave_port.hh c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
>   util/tlm/sc_slave_port.cc c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
> 
> Diff: http://reviews.gem5.org/r/3686/diff/
> 
> 
> Testing
> ---
> 
> Example applications are still running.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2016-10-27 Thread Cron Daemon

* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer:
 passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer:
 passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer:
 passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer:
 passed.
* build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
passed.
* 
build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level:
 passed.
* 
build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level:
 passed.
* 
build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level:
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level:
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token:
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token:
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token:
 passed.
* build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest: passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory:
 passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: passed.
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token:
 passed.
*

[gem5-dev] Review Request 3689: tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)

2016-10-27 Thread Andreas Hansson


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---

Review request for Default.


Repository: gem5


Description
---

Changeset 11706:e542abbd3730
---
tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)

This patch avoids compiling ALPHA six times as part of running
'util/regress', and instead relis on NULL with different protocols to
run the rubytest. All we need is the memory system, so there is really
no need to compile the ISA over and over again.

The one downside is the removal of running 'hello' for the variuos
ALPHA and protocol combinations, but if this is a concern we should
rather beef up the synthetic tests for the variuos protocols.


Diffs
-

  tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simout PRE-CREATION 
  tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt PRE-CREATION 
  util/regress c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
 c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr 
c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout 
c38fcdaa5fe5 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr 
c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout 
c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr 
c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout 
c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
 c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
 c38fcdaa5fe5 
  tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr 
c38fcdaa5fe5 
  tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout 
c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt 
c38fcdaa5fe5 
  tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini 
c38fcdaa5fe5 
  tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr c38fcdaa5fe5 
  tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout c38fcdaa5fe5 
  tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt 
c38fcdaa5fe5 
  
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/config.ini
 PRE-CREATION 
  tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/simerr 
PRE-CREATION 
  tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/simout 
PRE-CREATION 
  
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/stats.txt 
PRE-CREATION 
  
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/config.ini
 PRE-CREATION 
  
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/simerr
 PRE-CREATION 
  
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/simout
 PRE-CREATION 
  
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/stats.txt
 PRE-CREATION

Re: [gem5-dev] Review Request 3688: alpha: Remove ALPHA tru64 support and associated tests

2016-10-27 Thread Andreas Hansson


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---



src/arch/alpha/kernel_stats.cc 


Could someone skilled in the arts help out with this?

Due to this removal, a number of Linux Tsunami regressions now have 
missing/removed stats.

Was the intention that these syscalls are both for linux and tru64? If so, 
they should be moved or re-added.

Please let me know asap.


- Andreas Hansson


On Oct. 27, 2016, 7:45 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3688/
> ---
> 
> (Updated Oct. 27, 2016, 7:45 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11705:6c2b4e24accf
> ---
> alpha: Remove ALPHA tru64 support and associated tests
> 
> No one appears to be using it, and it is causing build issues
> and increases the development and maintenance effort.
> 
> 
> Diffs
> -
> 
>   tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt 
> c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
>

Re: [gem5-dev] Review Request 3688: alpha: Remove ALPHA tru64 support and associated tests

2016-10-27 Thread Andreas Hansson


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3688/#review8991
---


I don't want this particular part to stall due to the larger discussion around: 
http://reviews.gem5.org/r/3684/. It the tru64 removal is fine with everyone we 
can proceed with this patch and I'll rebase the complete removal for further 
discussion.

- Andreas Hansson


On Oct. 27, 2016, 7:45 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3688/
> ---
> 
> (Updated Oct. 27, 2016, 7:45 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11705:6c2b4e24accf
> ---
> alpha: Remove ALPHA tru64 support and associated tests
> 
> No one appears to be using it, and it is causing build issues
> and increases the development and maintenance effort.
> 
> 
> Diffs
> -
> 
>   tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
>   tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
>   tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt 
> c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out c38fcdaa5fe5 
>   tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini 
> c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
>   tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt c38fcdaa5fe5 
>   tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini c38fcdaa5fe5 
>

[gem5-dev] Review Request 3688: alpha: Remove ALPHA tru64 support and associated tests

2016-10-27 Thread Andreas Hansson


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3688/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11705:6c2b4e24accf
---
alpha: Remove ALPHA tru64 support and associated tests

No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.


Diffs
-

  tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini c38fcdaa5fe5 
  tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
  tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
  tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini 
c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini 
c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
  tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out c38fcdaa5fe5 
  tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout c38fcdaa5fe5 
  tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini c38fcdaa5fe5 
  tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr c38fcdaa5fe5 
  tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout c38fcdaa5fe5 
  tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt c38fcdaa5fe5 
  tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
  tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
  tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
  tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini c38fcdaa5fe5 
  tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr c38fcdaa5fe5 
  tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout c38fcdaa5fe5 
  src/arch/alpha/AlphaSystem.py c38fcdaa5fe5 
  src/arch/alpha/SConscript c38fcdaa5fe5

Re: [gem5-dev] Status of RISC-V patches

Re: [gem5-dev] Status of RISC-V patches

Re: [gem5-dev] Status of RISC-V patches

[gem5-dev] Status of RISC-V patches

Re: [gem5-dev] Review Request 3627: riscv: [Patch 2/5] Added RISC-V multiply extension RV64M

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

Re: [gem5-dev] Review Request 3689: tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)

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Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

Re: [gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM slave port

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

[gem5-dev] Review Request 3689: tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)

Re: [gem5-dev] Review Request 3688: alpha: Remove ALPHA tru64 support and associated tests

Re: [gem5-dev] Review Request 3688: alpha: Remove ALPHA tru64 support and associated tests

[gem5-dev] Review Request 3688: alpha: Remove ALPHA tru64 support and associated tests

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