date:20170123

Re: [gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression --scratch all

2017-01-23 Thread Joel Hestness

Ping! Can someone help us out with fixing up these regressions, or do we
have a plan for how to proceed with them?

I have at least one non-trivial Ruby patch incoming, and I'm worried about
validating its correctness.

  Thanks!
  Joel



On Thu, Dec 29, 2016 at 11:44 AM, Joel Hestness 
wrote:

> Hi Arthur and Jason,
>   I just bisected and tracked down where these regressions changed. It
> looks like changeset 11781:1ae84c76066b
>  on Dec. 21st
> caused the branch predictor to change its baseline prediction accuracy,
> causing a few of the regression tests to show changed stats.
>
>   Can you please let us know if you're able to update the stats to get
> these to pass?
>
>   Thanks!
>   Joel
>
> On Sun, Dec 25, 2016 at 5:03 PM, Cron Daemon 
> wrote:
>
>> * 
>> build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic:
>> FAILED!
>> * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing:
>> CHANGED!
>> * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing:
>> CHANGED!
>> * 
>> build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt:
>> CHANGED!
>> * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3:
>> CHANGED!
>> * 
>> build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual:
>> CHANGED!
>> * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing:
>> CHANGED!
>> * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing:
>> CHANGED!
>> * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing:
>> CHANGED!
>> * 
>> build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
>> CHANGED!
>> * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED!
>> * build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor:
>> CHANGED!
>> * build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing: CHANGED!
>> * build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing:
>> CHANGED!
>> * 
>> build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual:
>> CHANGED!
>> * build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual:
>> CHANGED!
>> * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker:
>> CHANGED!
>> * build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing:
>> CHANGED!
>> * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing:
>> CHANGED!
>> * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3:
>> CHANGED!
>> * build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing: CHANGED!
>> * 
>> build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual:
>> CHANGED!
>> * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor:
>> CHANGED!
>> * build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor:
>> CHANGED!
>> * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual:
>> CHANGED!
>> * build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing: CHANGED!
>> * build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing: CHANGED!
>> * build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing:
>> CHANGED!
>> * build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing:
>> CHANGED!
>> * build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3:
>> CHANGED!
>> * build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing:
>> CHANGED!
>> * build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing:
>> CHANGED!
>> * 
>> build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing:
>> CHANGED!
>> * 
>> build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing:
>> CHANGED!
>> * 
>> build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing:
>> CHANGED!
>> * build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing:
>> CHANGED!
>> * 
>> build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing:
>> CHANGED!
>> * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing:
>> CHANGED!
>> * 
>> build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing:
>> CHANGED!
>> * 
>> build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing:
>> CHANGED!
>> *

[gem5-dev] Bug in x86 stack instructions

2017-01-23 Thread Jason Lowe-Power

To those of you with more x86 ISA implementation knowledge than I have:

I've been working through a bug one of our users found (thanks Sanchayan!).
It looks like current versions of ld use the 0x67 instruction prefix
(address size override) as an optimization instead of using a nop. See
https://www.sourceware.org/ml/binutils/2016-05/msg00323.html.

This causes the call instruction to be decoded with with the "address size
override prefix", which is correct, in a sense. From what I can tell, this
is passed to the call instruction via "-env.dataSize" (see call instruction
implementation below).

def macroop CALL_NEAR_I
{
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call

limm t1, imm
rdip t7
# Check target of call
st t7, ss, [0, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
wrip t7, t1
};

Now, the bug is, according to the x86 manual, "For instructions that
implicitly access the stack segment (SS), the address size for stack
accesses is determined by the D (default) bit in the stack-segment
descriptor. In 64-bit mode, the D bit is ignored, and all stack references
have a 64-bit address size." See
https://support.amd.com/TechDocs/24594.pdf page
9.

Thoughts on how to fix this?

Thanks,
Jason
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[gem5-dev] changeset in gem5: style: [patch 3/22] reduce include dependenci...

2017-01-23 Thread Brandon Potter

changeset 54436a1784dc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=54436a1784dc
description:
style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.

diffstat:

 src/arch/alpha/process.cc  |   1 +
 src/arch/alpha/process.hh  |   1 +
 src/arch/arm/process.cc|   1 +
 src/arch/arm/process.hh|   1 +
 src/arch/mips/process.cc   |   1 +
 src/arch/mips/process.hh   |   1 +
 src/arch/power/interrupts.hh   |   1 +
 src/arch/power/process.cc  |   1 +
 src/arch/power/process.hh  |   1 +
 src/arch/power/remote_gdb.cc   |   2 +
 src/arch/riscv/interrupts.hh   |   1 +
 src/arch/riscv/process.cc  |   1 +
 src/arch/riscv/process.hh  |   1 +
 src/arch/sparc/process.cc  |   1 +
 src/arch/sparc/process.hh  |   1 +
 src/arch/x86/isa_traits.hh |   1 +
 src/arch/x86/pagetable.hh  |   3 +-
 src/arch/x86/process.cc|   1 +
 src/arch/x86/pseudo_inst.cc|   3 +-
 src/arch/x86/system.cc |   7 ---
 src/arch/x86/system.hh |   4 -
 src/arch/x86/tlb.cc|   4 -
 src/arch/x86/tlb.hh|   5 --
 src/arch/x86/utility.cc|   3 +-
 src/arch/x86/utility.hh|   6 --
 src/base/bitfield.hh   |   2 +-
 src/base/bitunion.hh   |   1 -
 src/base/time.cc   |   1 +
 src/base/vnc/vncinput.cc   |   3 +-
 src/cpu/minor/buffers.hh   |   1 +
 src/cpu/testers/directedtest/InvalidateGenerator.cc|   1 +
 src/cpu/testers/directedtest/RubyDirectedTester.cc |   1 +
 src/cpu/testers/directedtest/SeriesRequestGenerator.cc |   1 +
 src/cpu/testers/memtest/memtest.cc |   1 +
 src/cpu/testers/rubytest/Check.cc  |   1 +
 src/cpu/testers/rubytest/CheckTable.cc |   1 +
 src/cpu/testers/rubytest/RubyTester.cc |   1 +
 src/dev/arm/flash_device.cc|   1 +
 src/dev/mc146818.hh|   1 +
 src/dev/net/dist_iface.hh  |   1 +
 src/dev/net/etherbus.cc|   1 +
 src/dev/net/etherswitch.cc |   2 +
 src/gpu-compute/vector_register_file.hh|   1 +
 src/kern/linux/linux.cc|   1 -
 src/kern/linux/linux.hh|   2 +-
 src/mem/cache/prefetch/stride.cc   |   1 +
 src/mem/external_master.cc |   1 +
 src/mem/external_slave.cc  |   1 +
 src/mem/mem_checker.hh |   1 +
 src/mem/multi_level_page_table.hh  |   5 +-
 src/mem/multi_level_page_table_impl.hh |   9 +--
 src/mem/page_table.cc  |   7 +--
 src/mem/page_table.hh  |   3 +-
 src/mem/ruby/network/MessageBuffer.hh  |   1 +
 src/mem/ruby/structures/AbstractReplacementPolicy.cc   |   2 +
 src/mem/se_translating_port_proxy.hh   |   2 +-
 src/mem/simple_mem.cc  |   1 +
 src/python/swig/pyevent.cc |   1 +
 src/sim/SConscript |   3 +
 src/sim/arguments.cc   |   1 -
 src/sim/arguments.hh   |   1 -
 src/sim/byteswap.hh|   1 -
 src/sim/clock_domain.cc|   1 +
 src/sim/clocked_object.hh  |   1 -
 src/sim/cxx_config.hh  |   2 -
 src/sim/cxx_config_ini.cc  |   2 +
 src/sim/cxx_config_ini.hh  |   1 -
 src/sim/cxx_manager.cc |   1 +
 src/sim/drain.hh   |   2 -
 src/sim/dvfs_handler.cc|  26 +++
 src/sim/dvfs_handler.hh|  26

[gem5-dev] changeset in gem5: syscall_emul: [patch 4/22] remove redundant M...

2017-01-23 Thread Brandon Potter

changeset cd7f3a1dbf55 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cd7f3a1dbf55
description:
syscall_emul: [patch 4/22] remove redundant M5_pid field from process

diffstat:

 src/arch/alpha/process.cc |   4 ++--
 src/arch/sparc/faults.cc  |   4 ++--
 src/sim/Process.py|  13 +++--
 src/sim/process.cc|  15 ++-
 src/sim/process.hh|  38 ++
 src/sim/system.cc |   3 ---
 src/sim/system.hh |   8 
 7 files changed, 35 insertions(+), 50 deletions(-)

diffs (243 lines):

diff -r 54436a1784dc -r cd7f3a1dbf55 src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Wed Nov 09 14:27:40 2016 -0600
+++ b/src/arch/alpha/process.cc Wed Nov 09 14:27:40 2016 -0600
@@ -179,7 +179,7 @@
 AlphaLiveProcess::setupASNReg()
 {
 ThreadContext *tc = system->getThreadContext(contextIds[0]);
-tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
+tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
 }
 
 
@@ -187,7 +187,7 @@
 AlphaLiveProcess::loadState(CheckpointIn )
 {
 LiveProcess::loadState(cp);
-// need to set up ASN after unserialization since M5_pid value may
+// need to set up ASN after unserialization since _pid value may
 // come from checkpoint
 setupASNReg();
 }
diff -r 54436a1784dc -r cd7f3a1dbf55 src/arch/sparc/faults.cc
--- a/src/arch/sparc/faults.cc  Wed Nov 09 14:27:40 2016 -0600
+++ b/src/arch/sparc/faults.cc  Wed Nov 09 14:27:40 2016 -0600
@@ -630,7 +630,7 @@
 } else {
 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
 tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
-p->M5_pid /*context id*/, false, entry.pte);
+p->_pid /*context id*/, false, entry.pte);
 }
 }
 
@@ -654,7 +654,7 @@
 } else {
 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
 tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
-p->M5_pid /*context id*/, false, entry.pte);
+p->_pid /*context id*/, false, entry.pte);
 }
 }
 
diff -r 54436a1784dc -r cd7f3a1dbf55 src/sim/Process.py
--- a/src/sim/Process.pyWed Nov 09 14:27:40 2016 -0600
+++ b/src/sim/Process.pyWed Nov 09 14:27:40 2016 -0600
@@ -43,6 +43,13 @@
 kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in SE')
 max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack')
 
+uid = Param.Int(100, 'user id')
+euid = Param.Int(100, 'effective user id')
+gid = Param.Int(100, 'group id')
+egid = Param.Int(100, 'effective group id')
+pid = Param.Int(100, 'process id')
+ppid = Param.Int(99, 'parent process id')
+
 @classmethod
 def export_methods(cls, code):
 code('bool map(Addr vaddr, Addr paddr, int size, bool 
cacheable=true);')
@@ -60,12 +67,6 @@
 cmd = VectorParam.String("command line (executable plus arguments)")
 env = VectorParam.String([], "environment settings")
 cwd = Param.String('', "current working directory")
-uid = Param.Int(100, 'user id')
-euid = Param.Int(100, 'effective user id')
-gid = Param.Int(100, 'group id')
-egid = Param.Int(100, 'effective group id')
-pid = Param.Int(100, 'process id')
-ppid = Param.Int(99, 'parent process id')
 simpoint = Param.UInt64(0, 'simulation point at which to start simulation')
 drivers = VectorParam.EmulatedDriver([], 'Available emulated drivers')
 
diff -r 54436a1784dc -r cd7f3a1dbf55 src/sim/process.cc
--- a/src/sim/process.ccWed Nov 09 14:27:40 2016 -0600
+++ b/src/sim/process.ccWed Nov 09 14:27:40 2016 -0600
@@ -131,12 +131,11 @@
   brk_point(0), stack_base(0), stack_size(0), stack_min(0),
   max_stack_size(params->max_stack_size),
   next_thread_stack_base(0),
-  M5_pid(system->allocatePID()),
   useArchPT(params->useArchPT),
   kvmInSE(params->kvmInSE),
   pTable(useArchPT ?
-static_cast(new ArchPageTable(name(), M5_pid, 
system)) :
-static_cast(new FuncPageTable(name(), M5_pid)) ),
+static_cast(new ArchPageTable(name(), _pid, system)) :
+static_cast(new FuncPageTable(name(), _pid))),
   initVirtMem(system->getSystemPort(), this,
   SETranslatingPortProxy::Always),
   fd_array(make_shared>()),
@@ -147,7 +146,10 @@
 {"cout",   STDOUT_FILENO},
 {"stdout", STDOUT_FILENO},
 {"cerr",   STDERR_FILENO},
-{"stderr", STDERR_FILENO}}
+{"stderr", STDERR_FILENO}},
+  _uid(params->uid), _euid(params->euid),
+  _gid(params->gid), _egid(params->egid),
+  _pid(params->pid), _ppid(params->ppid)
 {
 int sim_fd;
 std::map::iterator it;
@@ -457,7 +459,6 @@
 for (int x = 0; x < fd_array->size(); x++) {
 (*fd_array)[x].serializeSection(cp, csprintf("FDEntry%d", x));
 }
-SERIALIZE_SCALAR(M5_pid);
 
 }
 
@@ -478,7 +479,6

[gem5-dev] RISC-V: Unknown opcode 0x00

2017-01-23 Thread Alec Roelke

Hello,

I'm trying to get the riscv64-linux-gnu-* tools working on gem5 for RISC-V
since right now only the riscv64-unknown-elf-* tools are compatible and
those don't include a lot of Linux headers.

The problem I am encountering is that after returning from a function I
assume is part of libc (the assembly label is __libc_setup_tls), the next
instruction it reads is always 0x, which is undefined in RISC-V and
causes a panic.  For example, when I compile the example "Hello, world"
program with riscv64-linux-gnu-gcc, using the -static and -static-libgcc
flags, here is a snippet of the end of the Exec trace:

 @__libc_setup_tls+456: jalr zero, ra, 0   : IntAlu :
 D=0x0002e2ec
 @__libc_start_main+140: unknown opcode 0x00: No_OpClass :

The value of ra (return address register, just like in MIPS) in the first
line is @__libc_start_main+140 (0x2ddc4), which it appears to correctly
jump to in the second line.  According to the assembly I dumped from the
binary, that should be an actual instruction (lui a5, 0x12, which loads
0x12 into the upper 32 bits of register a5), but gem5 seems to be reading
0x.

Does anyone know what's going on?

Thanks,
Alec Roelke
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Re: [gem5-dev] Review Request 3670: syscall_emul: [patch 4/22] remove redundant M5_pid field from process

2017-01-23 Thread Alexandru Dutu


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3670/#review9297
---

Ship it!


Ship It!

- Alexandru Dutu


On Oct. 17, 2016, 3:14 p.m., Brandon Potter wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3670/
> ---
> 
> (Updated Oct. 17, 2016, 3:14 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11692:ba60e4ae816f
> ---
> syscall_emul: [patch 4/22] remove redundant M5_pid field from process
> 
> 
> Diffs
> -
> 
>   src/sim/system.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/system.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/process.hh 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/sim/Process.py 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/arch/sparc/faults.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
>   src/arch/alpha/process.cc 4a86763c0b30cccba0f56c7f48637a46a4663b06 
> 
> Diff: http://reviews.gem5.org/r/3670/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brandon Potter
> 
>

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Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

2017-01-23 Thread Alec Roelke



> On Jan. 23, 2017, 4:59 p.m., Andreas Hansson wrote:
> > Another option is to remove the stats.txt from the stats results directory. 
> > This will turn the test into a functional-only test.
> > 
> > In fact that may be there better option here as we also don't have to worry 
> > about distributing a new binary.
> 
> Andreas Sandberg wrote:
> If you don't need to diff anything, you can just remove all of the files 
> in the reference directory. In this case, you need to make sure that the 
> directory is created by the version control system by adding an empty file 
> called EMPTY (this is ignored by the test framework). These functional tests 
> succeed as long as gem5 completes with exit code 0 and fail otherwise (e.g., 
> if gem5 aborts). We already use this for some of ARM tests.

I ended up removing all of the output results from the tests but restoring the 
ECALL tests since the output may also be file system dependent (it calls stat 
and fstat and outputs the results to stdout).


- Alec


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3781/#review9294
---


On Jan. 23, 2017, 7:36 p.m., Alec Roelke wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3781/
> ---
> 
> (Updated Jan. 23, 2017, 7:36 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11796:3cec8d75cd13
> ---
> riscv: Remove ECALL tests from insttest
> 
> The system calls tested in rv64i.cpp in RISC-V's insttest suite have
> different behavior depending on the operating system and file system they
> are run on. This patch removes those tests from the regression.
> 
> [Change deletion of ECALL test to block comment.]
> [Restore ECALL test but remove test output to test only for completion
> without error.]
> 
> 
> Diffs
> -
> 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt 
> 97eebddaae84 
>   tests/test-progs/insttest/src/riscv/rv64i.cpp 97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json
>  97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout 
> 97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json 
> 97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini
>  97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout 
> 97eebddaae84 
> 
> Diff: http://reviews.gem5.org/r/3781/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Alec Roelke
> 
>

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Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

2017-01-23 Thread Alec Roelke


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(Updated Jan. 23, 2017, 7:36 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11796:3cec8d75cd13
---
riscv: Remove ECALL tests from insttest

The system calls tested in rv64i.cpp in RISC-V's insttest suite have
different behavior depending on the operating system and file system they
are run on. This patch removes those tests from the regression.

[Change deletion of ECALL test to block comment.]
[Restore ECALL test but remove test output to test only for completion
without error.]


Diffs (updated)
-

  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt 
97eebddaae84 
  tests/test-progs/insttest/src/riscv/rv64i.cpp 97eebddaae84 
  
tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json 
97eebddaae84 
  
tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr 
97eebddaae84 
  tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout 
97eebddaae84 

Diff: http://reviews.gem5.org/r/3781/diff/


Testing
---


Thanks,

Alec Roelke

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Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

2017-01-23 Thread Andreas Sandberg



> On Jan. 23, 2017, 4:59 p.m., Andreas Hansson wrote:
> > Another option is to remove the stats.txt from the stats results directory. 
> > This will turn the test into a functional-only test.
> > 
> > In fact that may be there better option here as we also don't have to worry 
> > about distributing a new binary.

If you don't need to diff anything, you can just remove all of the files in the 
reference directory. In this case, you need to make sure that the directory is 
created by the version control system by adding an empty file called EMPTY 
(this is ignored by the test framework). These functional tests succeed as long 
as gem5 completes with exit code 0 and fail otherwise (e.g., if gem5 aborts). 
We already use this for some of ARM tests.


- Andreas


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---


On Jan. 18, 2017, 4:42 p.m., Alec Roelke wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3781/
> ---
> 
> (Updated Jan. 18, 2017, 4:42 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11796:aaf914ea5a83
> ---
> riscv: Remove ECALL tests from insttest
> 
> The system calls tested in rv64i.cpp in RISC-V's insttest suite have
> different behavior depending on the operating system and file system they
> are run on. This patch removes those tests from the regression.
> 
> [Change deletion of ECALL test to block comment.]
> 
> 
> Diffs
> -
> 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt 
> 97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini
>  97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json
>  97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout 
> 97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt 
> 97eebddaae84 
>   tests/test-progs/insttest/src/riscv/rv64i.cpp 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout 
> 97eebddaae84 
> 
> Diff: http://reviews.gem5.org/r/3781/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Alec Roelke
> 
>

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Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

2017-01-23 Thread Andreas Hansson


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---


Another option is to remove the stats.txt from the stats results directory. 
This will turn the test into a functional-only test.

In fact that may be there better option here as we also don't have to worry 
about distributing a new binary.

- Andreas Hansson


On Jan. 18, 2017, 4:42 p.m., Alec Roelke wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3781/
> ---
> 
> (Updated Jan. 18, 2017, 4:42 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11796:aaf914ea5a83
> ---
> riscv: Remove ECALL tests from insttest
> 
> The system calls tested in rv64i.cpp in RISC-V's insttest suite have
> different behavior depending on the operating system and file system they
> are run on. This patch removes those tests from the regression.
> 
> [Change deletion of ECALL test to block comment.]
> 
> 
> Diffs
> -
> 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt 
> 97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini
>  97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json
>  97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout 
> 97eebddaae84 
>   
> tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt 
> 97eebddaae84 
>   tests/test-progs/insttest/src/riscv/rv64i.cpp 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json 
> 97eebddaae84 
>   tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout 
> 97eebddaae84 
> 
> Diff: http://reviews.gem5.org/r/3781/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Alec Roelke
> 
>

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Re: [gem5-dev] Ideas for sprint projects

2017-01-23 Thread Andreas Hansson

Hi all,

Another medium-sized idea: Embed the generated system SVG in a web page
that can be used to interactively navigate the simulation results

This should be fairly easy for anyone skilled in client-side scripting. It
may even be used to view incremental results while the simulation is
running.

Andreas

On 23/01/2017, 15:57, "gem5-dev on behalf of Andreas Sandberg"
 wrote:

>Hi Everyone,
>
>Thanks for organising this! See below for some of my ideas.
>
>Small projects:
>   * Clean up serialization code for better code reuse (particularly
>container helpers)
>   * Create a separate test classification for CI smoke tests (faster
>than quick)
>
>Medium-sized projects:
>   * New test binaries based on the LLVM test suite
>   * Mini-DSL for param overrides from the command line
>   * Config cleanups. E.g., move some of config/common/ to a m5.config
>name space.
>   * Proper support for pthreads in SE mode
>   * Implement a fast mode in the HDLCD controller to support graphical
>worklaods (e.g., Android) in KVM
>
>Large projects:
>   * Get scons to build basic components only once and share them
>between architectures
>
>
>I'd like to throw cmake in to the build system mix as well. I started
>hacking on a small prototype a while back, but it isn't able to build
>gem5 yet.
>
>
>Cheers,
>Andreas
>
>
>On 17/01/17 16:12, Jason Lowe-Power wrote:
>> Hi gem5 Developers!
>>
>> As you're probably aware, I'm going to be running a gem5 coding sprint
>>in
>> the afternoon after the Learning gem5 tutorial at HPCA on Sunday Feb 5.
>>
>> I'm looking for ideas for small projects that could be started (or even
>> better, completed) in a few hours. Do you have any small bugs that have
>> been bothering you? Any little features that would be nice, but you
>>haven't
>> had the time to work on? Now's the time to get these things done!
>>
>> Also, if you have any bigger projects that you think it would be good
>>for
>> people to chat about in the same room to come up with a plan of attack,
>>we
>> may be able to fit one or two of those in, too.
>>
>> Some examples that I have so far:
>>
>> Little projects:
>> 1. Fix TLB warmup for x86. (See http://reviews.gem5.org/r/3474/)
>> 2. Modify EventWrapper to understand C++11 lambdas so you can pass
>> parameters to simple process() functions without creating a new class.
>> 3. Develop some ISA instruction tests to find out what is implemented
>> correctly and possibly find some bugs. (See RISC-V insttest)
>>
>> Long-term things we may want to discuss:
>> 1. Revamping the test infrastructure
>> 2. Replacing scons, possibly with Bazel (see https://bazel.build/)
>>
>> Please respond with any ideas you have! We definitely won't get to
>> everything, but throwing ideas out there now will give us a large base
>>of
>> options for the coding sprint.
>>
>> Thanks,
>> Jason
>
>IMPORTANT NOTICE: The contents of this email and any attachments are
>confidential and may also be privileged. If you are not the intended
>recipient, please notify the sender immediately and do not disclose the
>contents to any other person, use it for any purpose, or store or copy
>the information in any medium. Thank you.
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Re: [gem5-dev] Review Request 3790: x86: fixed branching computation for branch uops that only changes nupc and not npc

2017-01-23 Thread Tony Gutierrez


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Ship it!


Ship It!

- Tony Gutierrez


On Jan. 23, 2017, 7:39 a.m., Santi Galan wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3790/
> ---
> 
> (Updated Jan. 23, 2017, 7:39 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11801:80af6a1e6beb
> \-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-
> x86: fixed branching() computation for branch uops that only changes nupc and 
> not npc
> 
> When a branch micro-op belongs to a flow and the micro-op does not change the 
> nPC and just updates the nuPC
> (like a 'rep movs' flow), `branching()` function always returns not-taken no 
> matter  actual
> micro-branch outcome. Provided fix adds to the equation  nuPC attribute 
> checking since these kind of branch
> micro-op only updates that pointer.
> 
> This issue has been found while debugging the performance of a copy-loop 
> implemented with `memcopy` function. Without the fix, 'rep movss' internal 
> micro-branch was always predicted as not-taken causing an squash event after 
> every branch micro-branch execution.
> 
> Using the provided test, branch mispredition went from *1922* without the fix 
> to *7*.
> 
> 
> Diffs
> -
> 
>   src/arch/x86/types.hh e47703369039 
> 
> Diff: http://reviews.gem5.org/r/3790/diff/
> 
> 
> Testing
> ---
> 
> I used this command line to evaluate the performance:
> 
> ```
> ./build/X86/gem5.opt configs/example/se.py --cpu-type=detailed --caches 
> --l2cache -c /path/to/binary
> ```
> 
> This is the source code of the binary:
> ```
> #include 
> #include "m5op.h"
> 
> #define SIZE 15*1024
> 
> //arrays are cache aligned
> char a [SIZE] __attribute__((aligned(0x40)));
> char b [SIZE] __attribute__((aligned(0x40)));
> 
> int main ()
> {
> //some warmup
> int i;
> for (i = 0; i < SIZE; ++i)
> {
> a[i] = 1;
> b[i] = 2;
> }
> 
> m5_reset_stats(0, 0);
> memcpy(a, b, SIZE);
> m5_exit(0);
> 
> //keep compiler happy
> return 0;
> }
> ```
> 
> Which was compiled with this makefile:
> 
> ```
> GEM5_PATH=/path/to/gem5
> 
> binary: binary.c $(GEM5_PATH)/util/m5/m5op_x86.S
>   gcc -o $@ $^ -static -I$(GEM5_PATH)/util/m5
> ```
> 
> 
> Thanks,
> 
> Santi Galan
> 
>

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Re: [gem5-dev] Ideas for sprint projects

2017-01-23 Thread Andreas Sandberg


Hi Everyone,

Thanks for organising this! See below for some of my ideas.

Small projects:
  * Clean up serialization code for better code reuse (particularly
container helpers)
  * Create a separate test classification for CI smoke tests (faster
than quick)

Medium-sized projects:
  * New test binaries based on the LLVM test suite
  * Mini-DSL for param overrides from the command line
  * Config cleanups. E.g., move some of config/common/ to a m5.config
name space.
  * Proper support for pthreads in SE mode
  * Implement a fast mode in the HDLCD controller to support graphical
worklaods (e.g., Android) in KVM

Large projects:
  * Get scons to build basic components only once and share them
between architectures


I'd like to throw cmake in to the build system mix as well. I started
hacking on a small prototype a while back, but it isn't able to build
gem5 yet.


Cheers,
Andreas


On 17/01/17 16:12, Jason Lowe-Power wrote:

Hi gem5 Developers!

As you're probably aware, I'm going to be running a gem5 coding sprint in
the afternoon after the Learning gem5 tutorial at HPCA on Sunday Feb 5.

I'm looking for ideas for small projects that could be started (or even
better, completed) in a few hours. Do you have any small bugs that have
been bothering you? Any little features that would be nice, but you haven't
had the time to work on? Now's the time to get these things done!

Also, if you have any bigger projects that you think it would be good for
people to chat about in the same room to come up with a plan of attack, we
may be able to fit one or two of those in, too.

Some examples that I have so far:

Little projects:
1. Fix TLB warmup for x86. (See http://reviews.gem5.org/r/3474/)
2. Modify EventWrapper to understand C++11 lambdas so you can pass
parameters to simple process() functions without creating a new class.
3. Develop some ISA instruction tests to find out what is implemented
correctly and possibly find some bugs. (See RISC-V insttest)

Long-term things we may want to discuss:
1. Revamping the test infrastructure
2. Replacing scons, possibly with Bazel (see https://bazel.build/)

Please respond with any ideas you have! We definitely won't get to
everything, but throwing ideas out there now will give us a large base of
options for the coding sprint.

Thanks,
Jason


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please notify the sender immediately and do not disclose the contents to any 
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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2017-01-23 Thread Cron Daemon

* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: 
CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 CHANGED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 CHANGED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 CHANGED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: 
CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker: 
CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing: CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby: 
CHANGED!*** diff[config.json]: SKIPPED
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby:
 CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby:
 CHANGED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby:
 CHANGED!Maximum error magnitude: +420.00%
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic: 
passed.* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby:
 CHANGED!*** diff[simout]: SKIPPED
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing: 
CHANGED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby:
 CHANGED!
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
CHANGED!
* 
build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
*** diff[simout]: SKIPPED* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 passed.
--- quick/se/00.hello/mips/linux/simple-timing-ruby ---* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 passed.
*

Re: [gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression --scratch all

[gem5-dev] Bug in x86 stack instructions

[gem5-dev] changeset in gem5: style: [patch 3/22] reduce include dependenci...

[gem5-dev] changeset in gem5: syscall_emul: [patch 4/22] remove redundant M...

[gem5-dev] RISC-V: Unknown opcode 0x00

Re: [gem5-dev] Review Request 3670: syscall_emul: [patch 4/22] remove redundant M5_pid field from process

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

Re: [gem5-dev] Ideas for sprint projects

Re: [gem5-dev] Review Request 3790: x86: fixed branching computation for branch uops that only changes nupc and not npc

Re: [gem5-dev] Ideas for sprint projects

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

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