[gem5-dev] Change in gem5/gem5[master]: Merge branch 'master' of https://gem7.googlesource.com/public/gem5

2018-10-26 Thread kodamayu (Gerrit) 
kodamayu has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13795



Change subject: Merge branch 'master' of  
https://gem7.googlesource.com/public/gem5

..

Merge branch 'master' of https://gem7.googlesource.com/public/gem5

Change-Id: Icddcfd54990d94614a3029c069879281a2fdbe67
---
1 file changed, 0 insertions(+), 0 deletions(-)




--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13795
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Icddcfd54990d94614a3029c069879281a2fdbe67
Gerrit-Change-Number: 13795
Gerrit-PatchSet: 1
Gerrit-Owner: kodamayu 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: I missed the header file static_inst.hh

2018-10-26 Thread kodamayu (Gerrit) 
kodamayu has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13797



Change subject: arch-arm: I missed the header file static_inst.hh
..

arch-arm: I missed the header file static_inst.hh

Change-Id: I606888fb7d507ff2fa3de715cb08a4cf061aeb40
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 6216598..f4f3cbb 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -179,7 +179,7 @@
 void printExtendOperand(bool firstOperand, std::ostream ,
 IntRegIndex rm, ArmExtendType type,
 int64_t shiftAmt) const;
-
+void printPFflags(std::ostream , int flag) const;

 void printDataInst(std::ostream , bool withImm) const;
 void printDataInst(std::ostream , bool withImm, bool immShift, bool  
s,


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13797
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I606888fb7d507ff2fa3de715cb08a4cf061aeb40
Gerrit-Change-Number: 13797
Gerrit-PatchSet: 1
Gerrit-Owner: kodamayu 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] ARM build broken with "error: 'printPFflags' was not declared in this scope" since 59e3585a84ef172eba57c9936680c0248f9a97db

2018-10-26 Thread Ciro Santilli 
Build command:

scons  -j  16 --verbose build/ARM/gem5.opt


@Yuetsu: I think you forgot to git add printPFFlags on the .hh 
https://github.com/gem5/gem5/commit/59e3585a84ef172eba57c9936680c0248f9a97db#diff-f37db5a0ac23b11606024c8377f37dd6R327


@all devs: how are plans to do GitHub-like travis CI build check and only allow 
merge is the tests passes? This would save everyone engineering time.


Full error message:


error: 'printPFflags' was not declared in this scope


build/ARM/arch/arm/insts/mem64.cc: In member function 'void 
ArmISA::Memory64::startDisassembly(std::ostream&) const':
build/ARM/arch/arm/insts/mem64.cc:68:30: error: 'printPFflags' was not declared 
in this scope
 printPFflags(os, dest);
  ^
scons: *** [build/ARM/arch/arm/insts/mem64.o] Error 1
build/ARM/arch/arm/insts/static_inst.cc:327:62: error: no 'void 
ArmISA::ArmStaticInst::printPFflags(std::ostream&, int) const' member function 
declared in class 'ArmISA::ArmStaticInst'
 void ArmStaticInst::printPFflags(std::ostream , int flag) const
  ^


___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch, arm: Return s1Req upon fault in s2Lookup

2018-10-26 Thread Anouk Van Laer (Gerrit) 

Hello Giacomo Travaglini, Ciro Santilli,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13782

to review the following change.


Change subject: arch, arm: Return s1Req upon fault in s2Lookup
..

arch, arm: Return s1Req upon fault in s2Lookup

When a s2Lookup object is created, a new request is created, based
upon the original, stage 1 request sent out by the CPU. When a fault
occurs during the second stage of translation, this new request is
returned. This can lead to issues with the O3 CPU. The O3 fetch stage
will not acknowledge the fault as it is a different request than the
one it sent out and does not contain a contextID. This commit
rectifies this.

Change-Id: I21cb7377a59aed9d90d99f048b2106eaf219e93a
Reviewed-by: Ciro Santilli 
Reviewed-by: Giacomo Travaglini 
---
M src/arch/arm/stage2_lookup.cc
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc
index e74ec90..b5e1163 100644
--- a/src/arch/arm/stage2_lookup.cc
+++ b/src/arch/arm/stage2_lookup.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -191,7 +191,8 @@
 mergeTe(req, mode);

 if (fault != NoFault) {
-transState->finish(fault, req, tc, mode);
+// Returning with a fault requires the original request
+transState->finish(fault, s1Req, tc, mode);
 } else if (timing) {
 // Now notify the original stage 1 translation that we finally have
 // a result

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13782
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I21cb7377a59aed9d90d99f048b2106eaf219e93a
Gerrit-Change-Number: 13782
Gerrit-PatchSet: 1
Gerrit-Owner: Anouk Van Laer 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix MOESI_CMP_directory in ports order

2018-10-26 Thread Nikos Nikoleris (Gerrit) 
Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13595 )


Change subject: mem-ruby: Fix MOESI_CMP_directory in ports order
..

mem-ruby: Fix MOESI_CMP_directory in ports order

To avoid deadlocks ruby objects typically prioritize the handling of
responses to all other events. The order in which in_port statements
are written determine the order in which they are handled. This patch
fixes the order of in_order statements for the L2 cache in the
MOESI_CMP_directory.

Change-Id: I62248b0480a88ac2cd945425155f0961a1cf6cb1
Signed-off-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/13595
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/mem/protocol/MOESI_CMP_directory-L2cache.sm
1 file changed, 61 insertions(+), 61 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm  
b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm

index 6d71367..0c00bd9 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -592,6 +592,67 @@
 }
   }

+  // Response Network
+  in_port(responseNetwork_in, ResponseMsg, responseToL2Cache) {
+if (responseNetwork_in.isReady(clockEdge())) {
+  peek(responseNetwork_in, ResponseMsg) {
+assert(in_msg.Destination.isElement(machineID));
+if (in_msg.Type == CoherenceResponseType:ACK) {
+  if (in_msg.SenderMachine == MachineType:L2Cache) {
+trigger(Event:ExtAck, in_msg.addr,
+getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
+  }
+  else {
+trigger(Event:IntAck, in_msg.addr,
+getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
+  }
+} else if (in_msg.Type == CoherenceResponseType:DATA) {
+  trigger(Event:Data, in_msg.addr,
+  getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
+} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
+  trigger(Event:Data_Exclusive, in_msg.addr,
+  getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
+} else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
+  DPRINTF(ProtocolTrace, "Received Unblock from L1 addr: %x\n",  
in_msg.addr);

+  trigger(Event:Unblock, in_msg.addr,
+  getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
+} else if (in_msg.Type == CoherenceResponseType:UNBLOCK_EXCLUSIVE)  
{

+  trigger(Event:Exclusive_Unblock, in_msg.addr,
+  getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
+} else if (in_msg.Type ==  
CoherenceResponseType:WRITEBACK_DIRTY_DATA) {

+  Entry cache_entry := getCacheEntry(in_msg.addr);
+  if (is_invalid(cache_entry) &&
+   L2cache.cacheAvail(in_msg.addr) == false) {
+trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.addr),
+getCacheEntry(L2cache.cacheProbe(in_msg.addr)),
+TBEs[L2cache.cacheProbe(in_msg.addr)]);
+  }
+  else {
+trigger(Event:L1_WBDIRTYDATA, in_msg.addr,
+cache_entry, TBEs[in_msg.addr]);
+  }
+} else if (in_msg.Type ==  
CoherenceResponseType:WRITEBACK_CLEAN_DATA) {

+  Entry cache_entry := getCacheEntry(in_msg.addr);
+  if (is_invalid(cache_entry) &&
+   L2cache.cacheAvail(in_msg.addr) == false) {
+trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.addr),
+getCacheEntry(L2cache.cacheProbe(in_msg.addr)),
+TBEs[L2cache.cacheProbe(in_msg.addr)]);
+  }
+  else {
+trigger(Event:L1_WBCLEANDATA, in_msg.addr,
+cache_entry, TBEs[in_msg.addr]);
+  }
+} else if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
+  trigger(Event:DmaAck, in_msg.addr,
+  getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
+} else {
+  error("Unexpected message");
+}
+  }
+}
+  }
+

   // Request Network
   in_port(requestNetwork_in, RequestMsg, GlobalRequestToL2Cache) {
@@ -661,67 +722,6 @@
   }


-  // Response Network
-  in_port(responseNetwork_in, ResponseMsg, responseToL2Cache) {
-if (responseNetwork_in.isReady(clockEdge())) {
-  peek(responseNetwork_in, ResponseMsg) {
-assert(in_msg.Destination.isElement(machineID));
-if (in_msg.Type == CoherenceResponseType:ACK) {
-  if (in_msg.SenderMachine == MachineType:L2Cache) {
-trigger(Event:ExtAck, in_msg.addr,
-getCacheEntry(in_msg.addr), TBEs[in_msg.addr]);
-  }
-  else {
-trigger(Event:IntAck, in_msg.addr,
-

[gem5-dev] Change in gem5/gem5[master]: arch-arm: We add PRFM PST instruction for arm

2018-10-26 Thread Andreas Sandberg (Gerrit) 
Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13675 )


Change subject: arch-arm: We add PRFM PST instruction for arm
..

arch-arm: We add PRFM PST instruction for arm

Note current PRFM supports only PLD, but PST (prefetch for store) is
also important for latency hiding. We also bug fix in disassembler to
display prfop correctly.

Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13
Signed-off-by: Yuetsu Kodama 
Reviewed-on: https://gem5-review.googlesource.com/c/13675
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Giacomo Travaglini 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/mem64.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/ldr64.isa
M src/mem/cache/base.cc
M src/mem/packet.cc
M src/mem/packet.hh
M src/mem/request.hh
7 files changed, 35 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index fa8fdf0..660e56e 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -64,7 +64,11 @@
 Memory64::startDisassembly(std::ostream ) const
 {
 printMnemonic(os, "", false);
-printIntReg(os, dest);
+if (isDataPrefetch()||isInstPrefetch()){
+printPFflags(os, dest);
+}else{
+printIntReg(os, dest);
+}
 ccprintf(os, ", [");
 printIntReg(os, base);
 }
diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index bd6f115..f245cd4 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -324,6 +324,16 @@
 }
 }

+void ArmStaticInst::printPFflags(std::ostream , int flag) const
+{
+const char *flagtoprfop[]= { "PLD", "PLI", "PST", "Reserved"};
+const char *flagtotarget[] = { "L1", "L2", "L3", "Reserved"};
+const char *flagtopolicy[] = { "KEEP", "STRM"};
+
+ccprintf(os, "%s%s%s", flagtoprfop[(flag>>3)&3],
+ flagtotarget[(flag>>1)&3], flagtopolicy[flag&1]);
+}
+
 void
 ArmStaticInst::printFloatReg(std::ostream , RegIndex reg_idx) const
 {
diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 7c17726..54e50d7 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -74,6 +74,10 @@
 elif self.flavor == "iprefetch":
 self.memFlags.append("Request::PREFETCH")
 self.instFlags = ['IsInstPrefetch']
+elif self.flavor == "mprefetch":
+self.memFlags.append("dest>>3)&3)==2)? \
+ (Request::PF_EXCLUSIVE):(Request::PREFETCH))")
+self.instFlags = ['IsDataPrefetch']
 if self.micro:
 self.instFlags.append("IsMicroop")

@@ -176,7 +180,7 @@
 self.buildEACode()

 # Code that actually handles the access
-if self.flavor in ("dprefetch", "iprefetch"):
+if self.flavor in ("dprefetch", "iprefetch", "mprefetch"):
 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
 elif self.flavor == "fp":
 if self.size in (1, 2, 4):
@@ -365,10 +369,11 @@
 buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp")
 buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp")

-LoadImm64("prfm", "PRFM64_IMM", 8, flavor="dprefetch").emit()
-LoadReg64("prfm", "PRFM64_REG", 8, flavor="dprefetch").emit()
-LoadLit64("prfm", "PRFM64_LIT", 8, literal=True,  
flavor="dprefetch").emit()

-LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="dprefetch").emit()
+LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit()
+LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit()
+LoadLit64("prfm", "PRFM64_LIT", 8, literal=True,
+  flavor="mprefetch").emit()
+LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit()

 LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit()
 LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit()
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index ed23ffd..7bb0e0f 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1663,7 +1663,7 @@

 // should writebacks be included here?  prior code was inconsistent...
 #define SUM_NON_DEMAND(s) \
-(s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
+(s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq] + s[MemCmd::SoftPFExReq])

 demandHits
 .name(name() + ".demand_hits")
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 866bc90..4369e16 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -105,6 +105,9 @@
 /* SoftPFReq */
 { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse),
 SoftPFResp,

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix HVC trapping beahviour

2018-10-26 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13776 )


Change subject: arch-arm: Fix HVC trapping beahviour
..

arch-arm: Fix HVC trapping beahviour

This patch is fixing HVC trapping behaviour, reusing the pseudocode
implementation provided in the arm arm.

Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13776
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc64.isa
1 file changed, 13 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index 2621905..6d40dd9 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -51,10 +51,20 @@

 hvcCode = '''
 SCR scr = Scr64;
+HCR hcr = Hcr64;
+CPSR cpsr = Cpsr;

-if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
-(ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
-fault = disabledFault();
+auto tc = xc->tcBase();
+ExceptionLevel pstate_EL = (ExceptionLevel)(uint8_t)(cpsr.el);
+
+bool unalloc_encod = !ArmSystem::haveEL(tc, EL2) || pstate_EL == EL0 ||
+ (pstate_EL == EL1 && inSecureState(tc));
+
+bool hvc_enable = ArmSystem::haveEL(tc, EL3) ?
+scr.hce : !hcr.hcd;
+
+if (unalloc_encod || !hvc_enable) {
+fault = undefinedFault64(tc, pstate_EL);
 } else {
 fault = std::make_shared(machInst, bits(machInst,  
20, 5));

 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13776
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5
Gerrit-Change-Number: 13776
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1

2018-10-26 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13775 )


Change subject: arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
..

arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1

According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the
CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR,
are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC.

Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13775
Maintainer: Andreas Sandberg 
---
M src/arch/arm/utility.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index e642250..0494c20 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -792,7 +792,7 @@
 break;
   // CPACR, CPTR
   case MISCREG_CPACR_EL1:
-if (el == EL1) {
+if (el == EL1 || el == EL2) {
trapToMon = cptr.tcpac;
 }
 break;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13775
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371
Gerrit-Change-Number: 13775
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Trap to EL2 only if not in Secure State

2018-10-26 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13777 )


Change subject: arch-arm: Trap to EL2 only if not in Secure State
..

arch-arm: Trap to EL2 only if not in Secure State

MRS/MSR Instructions should trap to EL2 only if we are in non-Secure
state since at the current implementation (Armv8.0) there is no Secure
EL2.

Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13777
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
3 files changed, 124 insertions(+), 116 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/insts/data64.isa  
b/src/arch/arm/isa/insts/data64.isa

index 25bcf78..5f2a44c 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -335,7 +335,9 @@

 // Check for traps to hypervisor
 if ((ArmSystem::haveVirtualization(xc->tcBase()) && el <= EL2) &&
-msrMrs64TrapToHyp(flat_idx, el, %s, CptrEl264, Hcr64,  
_vfp_neon)) {

+msrMrs64TrapToHyp(flat_idx, el, %s, CptrEl264, Hcr64,
+  Scr64, cpsr, _vfp_neon)) {
+
 return std::make_shared(
 machInst, is_vfp_neon ? 0x1E0 : imm,
 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 0494c20..f90b899 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -650,127 +650,132 @@
   bool isRead,
   CPTR cptr /* CPTR_EL2 */,
   HCR hcr /* HCR_EL2 */,
+  SCR scr,
+  CPSR cpsr,
   bool * isVfpNeon)
 {
 bool trapToHyp = false;
 *isVfpNeon = false;

-switch (miscReg) {
-  // FP/SIMD regs
-  case MISCREG_FPCR:
-  case MISCREG_FPSR:
-  case MISCREG_FPEXC32_EL2:
-trapToHyp = cptr.tfp;
-*isVfpNeon = true;
-break;
-  // CPACR
-  case MISCREG_CPACR_EL1:
-trapToHyp = cptr.tcpac && el == EL1;
-break;
-  // Virtual memory control regs
-  case MISCREG_SCTLR_EL1:
-  case MISCREG_TTBR0_EL1:
-  case MISCREG_TTBR1_EL1:
-  case MISCREG_TCR_EL1:
-  case MISCREG_ESR_EL1:
-  case MISCREG_FAR_EL1:
-  case MISCREG_AFSR0_EL1:
-  case MISCREG_AFSR1_EL1:
-  case MISCREG_MAIR_EL1:
-  case MISCREG_AMAIR_EL1:
-  case MISCREG_CONTEXTIDR_EL1:
-trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead))
-&& el == EL1;
-break;
-  // TLB maintenance instructions
-  case MISCREG_TLBI_VMALLE1:
-  case MISCREG_TLBI_VAE1_Xt:
-  case MISCREG_TLBI_ASIDE1_Xt:
-  case MISCREG_TLBI_VAAE1_Xt:
-  case MISCREG_TLBI_VALE1_Xt:
-  case MISCREG_TLBI_VAALE1_Xt:
-  case MISCREG_TLBI_VMALLE1IS:
-  case MISCREG_TLBI_VAE1IS_Xt:
-  case MISCREG_TLBI_ASIDE1IS_Xt:
-  case MISCREG_TLBI_VAAE1IS_Xt:
-  case MISCREG_TLBI_VALE1IS_Xt:
-  case MISCREG_TLBI_VAALE1IS_Xt:
-trapToHyp = hcr.ttlb && el == EL1;
-break;
-  // Cache maintenance instructions to the point of unification
-  case MISCREG_IC_IVAU_Xt:
-  case MISCREG_ICIALLU:
-  case MISCREG_ICIALLUIS:
-  case MISCREG_DC_CVAU_Xt:
-trapToHyp = hcr.tpu && el <= EL1;
-break;
-  // Data/Unified cache maintenance instructions to the point of  
coherency

-  case MISCREG_DC_IVAC_Xt:
-  case MISCREG_DC_CIVAC_Xt:
-  case MISCREG_DC_CVAC_Xt:
-trapToHyp = hcr.tpc && el <= EL1;
-break;
-  // Data/Unified cache maintenance instructions by set/way
-  case MISCREG_DC_ISW_Xt:
-  case MISCREG_DC_CSW_Xt:
-  case MISCREG_DC_CISW_Xt:
-trapToHyp = hcr.tsw && el == EL1;
-break;
-  // ACTLR
-  case MISCREG_ACTLR_EL1:
-trapToHyp = hcr.tacr && el == EL1;
-break;
+if (!inSecureState(scr, cpsr) && (el != EL2)) {
+switch (miscReg) {
+  // FP/SIMD regs
+  case MISCREG_FPCR:
+  case MISCREG_FPSR:
+  case MISCREG_FPEXC32_EL2:
+trapToHyp = cptr.tfp;
+*isVfpNeon = true;
+break;
+  // CPACR
+  case MISCREG_CPACR_EL1:
+trapToHyp = cptr.tcpac && el == EL1;
+break;
+  // Virtual memory control regs
+  case MISCREG_SCTLR_EL1:
+  case MISCREG_TTBR0_EL1:
+  case MISCREG_TTBR1_EL1:
+  case MISCREG_TCR_EL1:
+  case MISCREG_ESR_EL1:
+  case MISCREG_FAR_EL1:
+  case MISCREG_AFSR0_EL1:
+  case MISCREG_AFSR1_EL1:
+  case

[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL

2018-10-26 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13779 )


Change subject: arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
..

arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL

While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.

Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13779
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
3 files changed, 67 insertions(+), 7 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index b2761e7..7df2f76 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -266,6 +266,8 @@
 assert(miscRead);
 trap_to_hyp = hcr.tid1 && el == EL1;
 break;
+  case MISCREG_IMPDEF_UNIMPL:
+trap_to_hyp = hcr.tidcp && el == EL1;
   default:
 break;
 }
@@ -330,3 +332,33 @@
 printMiscReg(ss, op1);
 return ss.str();
 }
+
+Fault
+MiscRegImplDefined64::execute(ExecContext *xc,
+  Trace::InstRecord *traceData) const
+{
+auto tc = xc->tcBase();
+const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
+
+Fault fault = trap(tc, miscReg, el, imm);
+
+if (fault != NoFault) {
+return fault;
+
+} else if (warning) {
+warn_once("\tinstruction '%s' unimplemented\n",  
fullMnemonic.c_str());

+return NoFault;
+
+} else {
+return std::make_shared(machInst, false,
+  mnemonic);
+}
+}
+
+std::string
+MiscRegImplDefined64::generateDisassembly(Addr pc,
+  const SymbolTable *symtab) const
+{
+return csprintf("%-10s (implementation defined)",  
fullMnemonic.c_str());

+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 8af488a..f70344b 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -178,4 +178,32 @@
 Addr pc, const SymbolTable *symtab) const override;
 };

+class MiscRegImplDefined64 : public MiscRegOp64
+{
+  protected:
+const std::string fullMnemonic;
+const MiscRegIndex miscReg;
+const uint32_t imm;
+const bool warning;
+
+  public:
+MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst,
+ MiscRegIndex misc_reg, bool misc_read,
+ uint32_t _imm, const std::string full_mnem,
+ bool _warning) :
+MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
+fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
+warning(_warning)
+{
+assert(miscReg == MISCREG_IMPDEF_UNIMPL);
+}
+
+  protected:
+Fault execute(ExecContext *xc,
+  Trace::InstRecord *traceData) const override;
+
+std::string generateDisassembly(
+Addr pc, const SymbolTable *symtab) const override;
+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 26c65ec..3f4e337 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -446,13 +446,13 @@
  read ? "mrs" : "msr",
  op0, op1, crn, crm, op2);

-if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
-return new  
WarnUnimplemented(read ? "mrs" : "msr",
-machInst, full_mnemonic + " treated as  
NOP");

-} else {
-return new  
FailUnimplemented(read ? "mrs" : "msr",

-machInst, full_mnemonic);
-}
+uint32_t iss = msrMrs64IssBuild(
+read, op0, op1, crn, crm, op2, rt);
+
+return new MiscRegImplDefined64(
+read ? "mrs" : "msr",
+machInst, miscReg, read, iss, full_mnemonic,
+miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]);

 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
 if (miscReg == MISCREG_NZCV) {

--
To view, visit

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Refactor AArch64 MSR/MRS trapping

2018-10-26 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13778 )


Change subject: arch-arm: Refactor AArch64 MSR/MRS trapping
..

arch-arm: Refactor AArch64 MSR/MRS trapping

This patch refactors AArch64 MSR/MRS trapping, by moving the trapping
helpers in arch/arm/utility and in the isa code into a MiscRegOp64
class.

This class is the Base class for a generic AArch64 instruction which is
making use of system registers (MiscReg), like MSR,MRS,SYS.  The common
denominator or those instruction is the chance that the system register
access is trapped to an upper Exception level. MiscRegOp64 is providing
that feature.

What do we gain? Other "pseudo" instructions, like access to
implementation defined registers can inherit from this class to make use
of the trapping functionalities even if there is no data movement
between GPRs and system register.

Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13778
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
6 files changed, 276 insertions(+), 230 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 4f66283..8e21bb3 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -39,12 +39,13 @@
 #ifndef __ARCH_ARM_MEM64_HH__
 #define __ARCH_ARM_MEM64_HH__

+#include "arch/arm/insts/misc64.hh"
 #include "arch/arm/insts/static_inst.hh"

 namespace ArmISA
 {

-class SysDC64 : public ArmStaticInst
+class SysDC64 : public MiscRegOp64
 {
   protected:
 IntRegIndex base;
@@ -53,9 +54,10 @@

 SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm)
-: ArmStaticInst(mnem, _machInst, __opClass), base(_base),
-  dest((IntRegIndex)miscReg), imm(_imm)
+: MiscRegOp64(mnem, _machInst, __opClass, false),
+  base(_base), dest((IntRegIndex)miscReg), imm(_imm)
 {}
+
 std::string generateDisassembly(
 Addr pc, const SymbolTable *symtab) const override;
 };
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 5bdf6cb..b2761e7 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -81,6 +81,232 @@
 return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
 }

+Fault
+MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
+  ExceptionLevel el, uint32_t immediate) const
+{
+bool is_vfp_neon = false;
+
+// Check for traps to supervisor (FP/SIMD regs)
+if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) {
+
+return std::make_shared(machInst, 0x1E0,
+EC_TRAPPED_SIMD_FP);
+}
+
+// Check for traps to hypervisor
+if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
+checkEL2Trap(tc, misc_reg, el, _vfp_neon)) {
+
+return std::make_shared(
+machInst, is_vfp_neon ? 0x1E0 : immediate,
+is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
+}
+
+// Check for traps to secure monitor
+if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
+checkEL3Trap(tc, misc_reg, el, _vfp_neon)) {
+
+return std::make_shared(
+machInst,
+is_vfp_neon ? 0x1E0 : immediate,
+is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
+}
+
+return NoFault;
+}
+
+bool
+MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
+  ExceptionLevel el) const
+{
+const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+
+bool trap_to_sup = false;
+switch (misc_reg) {
+  case MISCREG_FPCR:
+  case MISCREG_FPSR:
+  case MISCREG_FPEXC32_EL2:
+if ((el == EL0 && cpacr.fpen != 0x3) ||
+(el == EL1 && !(cpacr.fpen & 0x1)))
+trap_to_sup = true;
+break;
+  default:
+break;
+}
+return trap_to_sup;
+}
+
+bool
+MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
+  ExceptionLevel el, bool * is_vfp_neon) const
+{
+const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+
+bool trap_to_hyp = false;
+*is_vfp_neon = false;
+
+if (!inSecureState(scr, cpsr) && (el != EL2)) {
+switch (misc_reg) {
+  // FP/SIMD regs
+

[gem5-dev] Change in gem5/gem5[master]: arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}

2018-10-26 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13780 )


Change subject: arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}
..

arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}

According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or
15) is implementation defined; this makes it trappable by having
HCR_EL2.TIDCP = 1.

Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13780
Maintainer: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 07123bd..ebe72dd 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1228,6 +1228,11 @@
 break;
 }
 break;
+  case 11:
+  case 15:
+// SYS Instruction with CRn = { 11, 15 }
+// (Trappable by HCR_EL2.TIDCP)
+return MISCREG_IMPDEF_UNIMPL;
 }
 break;
   case 2:

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13780
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef
Gerrit-Change-Number: 13780
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}

2018-10-26 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13780

to review the following change.


Change subject: arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}
..

arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}

According to the arm arm, a SYS instruction (op0 = 1) with CRn = (11 or
15) is implementation defined; this makes it trappable by having
HCR_EL2.TIDCP = 1.

Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 07123bd..ebe72dd 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1228,6 +1228,11 @@
 break;
 }
 break;
+  case 11:
+  case 15:
+// SYS Instruction with CRn = { 11, 15 }
+// (Trappable by HCR_EL2.TIDCP)
+return MISCREG_IMPDEF_UNIMPL;
 }
 break;
   case 2:

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13780
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Idd94ac345fee652ee6f8c0a7eb7b06ac75ec38ef
Gerrit-Change-Number: 13780
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1

2018-10-26 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13775

to review the following change.


Change subject: arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
..

arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1

According to the arm arm, CPTR_EL3.TCPAC traps EL2 accesses to the
CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR,
are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC.

Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/utility.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index e642250..0494c20 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -792,7 +792,7 @@
 break;
   // CPACR, CPTR
   case MISCREG_CPACR_EL1:
-if (el == EL1) {
+if (el == EL1 || el == EL2) {
trapToMon = cptr.tcpac;
 }
 break;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13775
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I637be35b29db39f044dda0c6cc4fe986c9620371
Gerrit-Change-Number: 13775
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Refactor AArch64 MSR/MRS trapping

2018-10-26 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13778

to review the following change.


Change subject: arch-arm: Refactor AArch64 MSR/MRS trapping
..

arch-arm: Refactor AArch64 MSR/MRS trapping

This patch refactors AArch64 MSR/MRS trapping, by moving the trapping
helpers in arch/arm/utility and in the isa code into a MiscRegOp64
class.

This class is the Base class for a generic AArch64 instruction which is
making use of system registers (MiscReg), like MSR,MRS,SYS.  The common
denominator or those instruction is the chance that the system register
access is trapped to an upper Exception level. MiscRegOp64 is providing
that feature.

What do we gain? Other "pseudo" instructions, like access to
implementation defined registers can inherit from this class to make use
of the trapping functionalities even if there is no data movement
between GPRs and system register.

Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/mem64.hh
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
6 files changed, 276 insertions(+), 230 deletions(-)



diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 4f66283..8e21bb3 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -39,12 +39,13 @@
 #ifndef __ARCH_ARM_MEM64_HH__
 #define __ARCH_ARM_MEM64_HH__

+#include "arch/arm/insts/misc64.hh"
 #include "arch/arm/insts/static_inst.hh"

 namespace ArmISA
 {

-class SysDC64 : public ArmStaticInst
+class SysDC64 : public MiscRegOp64
 {
   protected:
 IntRegIndex base;
@@ -53,9 +54,10 @@

 SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm)
-: ArmStaticInst(mnem, _machInst, __opClass), base(_base),
-  dest((IntRegIndex)miscReg), imm(_imm)
+: MiscRegOp64(mnem, _machInst, __opClass, false),
+  base(_base), dest((IntRegIndex)miscReg), imm(_imm)
 {}
+
 std::string generateDisassembly(
 Addr pc, const SymbolTable *symtab) const override;
 };
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 5bdf6cb..b2761e7 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -81,6 +81,232 @@
 return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
 }

+Fault
+MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
+  ExceptionLevel el, uint32_t immediate) const
+{
+bool is_vfp_neon = false;
+
+// Check for traps to supervisor (FP/SIMD regs)
+if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) {
+
+return std::make_shared(machInst, 0x1E0,
+EC_TRAPPED_SIMD_FP);
+}
+
+// Check for traps to hypervisor
+if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
+checkEL2Trap(tc, misc_reg, el, _vfp_neon)) {
+
+return std::make_shared(
+machInst, is_vfp_neon ? 0x1E0 : immediate,
+is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
+}
+
+// Check for traps to secure monitor
+if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
+checkEL3Trap(tc, misc_reg, el, _vfp_neon)) {
+
+return std::make_shared(
+machInst,
+is_vfp_neon ? 0x1E0 : immediate,
+is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
+}
+
+return NoFault;
+}
+
+bool
+MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
+  ExceptionLevel el) const
+{
+const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+
+bool trap_to_sup = false;
+switch (misc_reg) {
+  case MISCREG_FPCR:
+  case MISCREG_FPSR:
+  case MISCREG_FPEXC32_EL2:
+if ((el == EL0 && cpacr.fpen != 0x3) ||
+(el == EL1 && !(cpacr.fpen & 0x1)))
+trap_to_sup = true;
+break;
+  default:
+break;
+}
+return trap_to_sup;
+}
+
+bool
+MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
+  ExceptionLevel el, bool * is_vfp_neon) const
+{
+const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+
+bool trap_to_hyp = false;
+*is_vfp_neon = false;
+
+if (!inSecureState(scr, cpsr) && (el != EL2)) {
+switch (misc_reg) {
+  // FP/SIMD regs
+  case MISCREG_FPCR:
+  case MISCREG_FPSR:
+  case MISCREG_FPEXC32_EL2:
+trap_to_hyp = cptr.tfp;
+

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix HVC trapping beahviour

2018-10-26 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13776

to review the following change.


Change subject: arch-arm: Fix HVC trapping beahviour
..

arch-arm: Fix HVC trapping beahviour

This patch is fixing HVC trapping behaviour, reusing the pseudocode
implementation provided in the arm arm.

Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc64.isa
1 file changed, 13 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index 2621905..6d40dd9 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -51,10 +51,20 @@

 hvcCode = '''
 SCR scr = Scr64;
+HCR hcr = Hcr64;
+CPSR cpsr = Cpsr;

-if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
-(ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
-fault = disabledFault();
+auto tc = xc->tcBase();
+ExceptionLevel pstate_EL = (ExceptionLevel)(uint8_t)(cpsr.el);
+
+bool unalloc_encod = !ArmSystem::haveEL(tc, EL2) || pstate_EL == EL0 ||
+ (pstate_EL == EL1 && inSecureState(tc));
+
+bool hvc_enable = ArmSystem::haveEL(tc, EL3) ?
+scr.hce : !hcr.hcd;
+
+if (unalloc_encod || !hvc_enable) {
+fault = undefinedFault64(tc, pstate_EL);
 } else {
 fault = std::make_shared(machInst, bits(machInst,  
20, 5));

 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13776
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0bc81478400b99d84534c1c8871f894722f547c5
Gerrit-Change-Number: 13776
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Trap to EL2 only if not in Secure State

2018-10-26 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13777

to review the following change.


Change subject: arch-arm: Trap to EL2 only if not in Secure State
..

arch-arm: Trap to EL2 only if not in Secure State

MRS/MSR Instructions should trap to EL2 only if we are in non-Secure
state since at the current implementation (Armv8.0) there is no Secure
EL2.

Change-Id: I93af415fbcbd19a470752adf6afc92e520e9645d
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
3 files changed, 124 insertions(+), 116 deletions(-)



diff --git a/src/arch/arm/isa/insts/data64.isa  
b/src/arch/arm/isa/insts/data64.isa

index 25bcf78..5f2a44c 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -335,7 +335,9 @@

 // Check for traps to hypervisor
 if ((ArmSystem::haveVirtualization(xc->tcBase()) && el <= EL2) &&
-msrMrs64TrapToHyp(flat_idx, el, %s, CptrEl264, Hcr64,  
_vfp_neon)) {

+msrMrs64TrapToHyp(flat_idx, el, %s, CptrEl264, Hcr64,
+  Scr64, cpsr, _vfp_neon)) {
+
 return std::make_shared(
 machInst, is_vfp_neon ? 0x1E0 : imm,
 is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 0494c20..f90b899 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -650,127 +650,132 @@
   bool isRead,
   CPTR cptr /* CPTR_EL2 */,
   HCR hcr /* HCR_EL2 */,
+  SCR scr,
+  CPSR cpsr,
   bool * isVfpNeon)
 {
 bool trapToHyp = false;
 *isVfpNeon = false;

-switch (miscReg) {
-  // FP/SIMD regs
-  case MISCREG_FPCR:
-  case MISCREG_FPSR:
-  case MISCREG_FPEXC32_EL2:
-trapToHyp = cptr.tfp;
-*isVfpNeon = true;
-break;
-  // CPACR
-  case MISCREG_CPACR_EL1:
-trapToHyp = cptr.tcpac && el == EL1;
-break;
-  // Virtual memory control regs
-  case MISCREG_SCTLR_EL1:
-  case MISCREG_TTBR0_EL1:
-  case MISCREG_TTBR1_EL1:
-  case MISCREG_TCR_EL1:
-  case MISCREG_ESR_EL1:
-  case MISCREG_FAR_EL1:
-  case MISCREG_AFSR0_EL1:
-  case MISCREG_AFSR1_EL1:
-  case MISCREG_MAIR_EL1:
-  case MISCREG_AMAIR_EL1:
-  case MISCREG_CONTEXTIDR_EL1:
-trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead))
-&& el == EL1;
-break;
-  // TLB maintenance instructions
-  case MISCREG_TLBI_VMALLE1:
-  case MISCREG_TLBI_VAE1_Xt:
-  case MISCREG_TLBI_ASIDE1_Xt:
-  case MISCREG_TLBI_VAAE1_Xt:
-  case MISCREG_TLBI_VALE1_Xt:
-  case MISCREG_TLBI_VAALE1_Xt:
-  case MISCREG_TLBI_VMALLE1IS:
-  case MISCREG_TLBI_VAE1IS_Xt:
-  case MISCREG_TLBI_ASIDE1IS_Xt:
-  case MISCREG_TLBI_VAAE1IS_Xt:
-  case MISCREG_TLBI_VALE1IS_Xt:
-  case MISCREG_TLBI_VAALE1IS_Xt:
-trapToHyp = hcr.ttlb && el == EL1;
-break;
-  // Cache maintenance instructions to the point of unification
-  case MISCREG_IC_IVAU_Xt:
-  case MISCREG_ICIALLU:
-  case MISCREG_ICIALLUIS:
-  case MISCREG_DC_CVAU_Xt:
-trapToHyp = hcr.tpu && el <= EL1;
-break;
-  // Data/Unified cache maintenance instructions to the point of  
coherency

-  case MISCREG_DC_IVAC_Xt:
-  case MISCREG_DC_CIVAC_Xt:
-  case MISCREG_DC_CVAC_Xt:
-trapToHyp = hcr.tpc && el <= EL1;
-break;
-  // Data/Unified cache maintenance instructions by set/way
-  case MISCREG_DC_ISW_Xt:
-  case MISCREG_DC_CSW_Xt:
-  case MISCREG_DC_CISW_Xt:
-trapToHyp = hcr.tsw && el == EL1;
-break;
-  // ACTLR
-  case MISCREG_ACTLR_EL1:
-trapToHyp = hcr.tacr && el == EL1;
-break;
+if (!inSecureState(scr, cpsr) && (el != EL2)) {
+switch (miscReg) {
+  // FP/SIMD regs
+  case MISCREG_FPCR:
+  case MISCREG_FPSR:
+  case MISCREG_FPEXC32_EL2:
+trapToHyp = cptr.tfp;
+*isVfpNeon = true;
+break;
+  // CPACR
+  case MISCREG_CPACR_EL1:
+trapToHyp = cptr.tcpac && el == EL1;
+break;
+  // Virtual memory control regs
+  case MISCREG_SCTLR_EL1:
+  case MISCREG_TTBR0_EL1:
+  case MISCREG_TTBR1_EL1:
+  case MISCREG_TCR_EL1:
+  case MISCREG_ESR_EL1:
+  case MISCREG_FAR_EL1:
+  case MISCREG_AFSR0_EL1:
+  case MISCREG_AFSR1_EL1:
+  case MISCREG_MAIR_EL1:
+  case MISCREG_AMAIR_EL1:
+  case MISCREG_CONTEXTIDR_EL1:
+trapToHyp = ((hcr.trvm && isRead) ||

[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL

2018-10-26 Thread Giacomo Travaglini (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13779

to review the following change.


Change subject: arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
..

arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL

While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.

Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
3 files changed, 67 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index b2761e7..7df2f76 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -266,6 +266,8 @@
 assert(miscRead);
 trap_to_hyp = hcr.tid1 && el == EL1;
 break;
+  case MISCREG_IMPDEF_UNIMPL:
+trap_to_hyp = hcr.tidcp && el == EL1;
   default:
 break;
 }
@@ -330,3 +332,33 @@
 printMiscReg(ss, op1);
 return ss.str();
 }
+
+Fault
+MiscRegImplDefined64::execute(ExecContext *xc,
+  Trace::InstRecord *traceData) const
+{
+auto tc = xc->tcBase();
+const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
+
+Fault fault = trap(tc, miscReg, el, imm);
+
+if (fault != NoFault) {
+return fault;
+
+} else if (warning) {
+warn_once("\tinstruction '%s' unimplemented\n",  
fullMnemonic.c_str());

+return NoFault;
+
+} else {
+return std::make_shared(machInst, false,
+  mnemonic);
+}
+}
+
+std::string
+MiscRegImplDefined64::generateDisassembly(Addr pc,
+  const SymbolTable *symtab) const
+{
+return csprintf("%-10s (implementation defined)",  
fullMnemonic.c_str());

+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 8af488a..f70344b 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -178,4 +178,32 @@
 Addr pc, const SymbolTable *symtab) const override;
 };

+class MiscRegImplDefined64 : public MiscRegOp64
+{
+  protected:
+const std::string fullMnemonic;
+const MiscRegIndex miscReg;
+const uint32_t imm;
+const bool warning;
+
+  public:
+MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst,
+ MiscRegIndex misc_reg, bool misc_read,
+ uint32_t _imm, const std::string full_mnem,
+ bool _warning) :
+MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
+fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
+warning(_warning)
+{
+assert(miscReg == MISCREG_IMPDEF_UNIMPL);
+}
+
+  protected:
+Fault execute(ExecContext *xc,
+  Trace::InstRecord *traceData) const override;
+
+std::string generateDisassembly(
+Addr pc, const SymbolTable *symtab) const override;
+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 26c65ec..3f4e337 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -446,13 +446,13 @@
  read ? "mrs" : "msr",
  op0, op1, crn, crm, op2);

-if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
-return new  
WarnUnimplemented(read ? "mrs" : "msr",
-machInst, full_mnemonic + " treated as  
NOP");

-} else {
-return new  
FailUnimplemented(read ? "mrs" : "msr",

-machInst, full_mnemonic);
-}
+uint32_t iss = msrMrs64IssBuild(
+read, op0, op1, crn, crm, op2, rt);
+
+return new MiscRegImplDefined64(
+read ? "mrs" : "msr",
+machInst, miscReg, read, iss, full_mnemonic,
+miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]);

 } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
 if (miscReg == MISCREG_NZCV) {

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13779
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings

[gem5-dev] Change in gem5/gem5[master]: tests: Convert CircleBuf unit test to a GTest

2018-10-26 Thread Andreas Sandberg (Gerrit) 
Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13735 )


Change subject: tests: Convert CircleBuf unit test to a GTest
..

tests: Convert CircleBuf unit test to a GTest

Change-Id: I028c6b8d8e0ec06cac3d636689ae647f717096cd
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13735
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
---
M src/base/SConscript
A src/base/circlebuftest.cc
M src/unittest/SConscript
D src/unittest/circlebuf.cc
4 files changed, 121 insertions(+), 122 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/base/SConscript b/src/base/SConscript
index 3065749..3570d15 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -84,6 +84,7 @@

 GTest('addr_range_test', 'addr_range_test.cc')
 GTest('bituniontest', 'bituniontest.cc')
+GTest('CircleBufTest', 'circlebuftest.cc')

 DebugFlag('Annotate', "State machine annotation debugging")
 DebugFlag('AnnotateQ', "State machine annotation queue debugging")
diff --git a/src/base/circlebuftest.cc b/src/base/circlebuftest.cc
new file mode 100644
index 000..9f5679d
--- /dev/null
+++ b/src/base/circlebuftest.cc
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2015, 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include 
+
+#include "base/circlebuf.hh"
+
+const char data[] = {
+0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
+0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
+};
+
+// Basic non-overflow functionality
+TEST(CircleBufTest, BasicReadWriteNoOverflow)
+{
+CircleBuf buf(8);
+char foo[16];
+
+// Write empty buffer, no overflow
+buf.write(data, 8);
+EXPECT_EQ(buf.size(), 8);
+buf.peek(foo, 8);
+EXPECT_EQ(memcmp(foo, data, 8), 0);
+
+// Read 2
+buf.read(foo, 2);
+EXPECT_EQ(memcmp(foo, data, 2), 0);
+EXPECT_EQ(buf.size(), 6);
+buf.read(foo, 6);
+EXPECT_EQ(memcmp(foo, data + 2, 6), 0);
+EXPECT_EQ(buf.size(), 0);
+}
+
+// Basic single write overflow functionality
+TEST(CircleBufTest, SingleWriteOverflow)
+{
+CircleBuf buf(8);
+char foo[16];
+
+buf.write(data, 16);
+EXPECT_EQ(buf.size(), 8);
+buf.peek(foo, 8);
+EXPECT_EQ(memcmp(data + 8, foo, 8), 0);
+}
+
+
+// Multi-write overflow functionality
+TEST(CircleBufTest, MultiWriteOverflow)
+{
+CircleBuf buf(8);
+char foo[16];
+
+// Write, no overflow, write overflow
+buf.write(data, 6);
+buf.write(data + 8, 6);
+EXPECT_EQ(buf.size(), 8);
+buf.peek(foo, 8);
+EXPECT_EQ(memcmp(data + 4, foo, 2), 0);
+EXPECT_EQ(memcmp(data + 8, foo + 2, 6), 0);
+}
+
+// Pointer wrap around
+TEST(CircleBufTest, PointerWrapAround)

[gem5-dev] Change in gem5/gem5[master]: tests: Convert AddrRangeMap unit test to a GTest

2018-10-26 Thread Andreas Sandberg (Gerrit) 
Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13736 )


Change subject: tests: Convert AddrRangeMap unit test to a GTest
..

tests: Convert AddrRangeMap unit test to a GTest

Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13736
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
---
M src/base/SConscript
R src/base/addr_range_map_test.cc
M src/unittest/SConscript
3 files changed, 13 insertions(+), 26 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/base/SConscript b/src/base/SConscript
index 3570d15..d84eba1 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -83,6 +83,7 @@
 Source('stats/text.cc')

 GTest('addr_range_test', 'addr_range_test.cc')
+GTest('AddrRangeMapTest', 'addr_range_map_test.cc')
 GTest('bituniontest', 'bituniontest.cc')
 GTest('CircleBufTest', 'circlebuftest.cc')

diff --git a/src/unittest/rangemaptest.cc b/src/base/addr_range_map_test.cc
similarity index 80%
rename from src/unittest/rangemaptest.cc
rename to src/base/addr_range_map_test.cc
index 88e1c4d..397372c 100644
--- a/src/unittest/rangemaptest.cc
+++ b/src/base/addr_range_map_test.cc
@@ -40,44 +40,31 @@
  * Authors: Ali Saidi
  */

-#include 
-#include 
+#include 

 #include "base/addr_range_map.hh"

-using namespace std;
-
-int
-main()
+// Converted from legacy unit test framework
+TEST(AddrRangeMapTest, LegacyTests)
 {
 AddrRangeMap r;
-
 AddrRangeMap::const_iterator i;

 i = r.insert(RangeIn(10, 40), 5);
-assert(i != r.end());
+ASSERT_NE(i, r.end());
+
 i = r.insert(RangeIn(60, 90), 3);
-assert(i != r.end());
+ASSERT_NE(i, r.end());

-i = r.intersects(RangeIn(20, 30));
-assert(i != r.end());
-cout << i->first.to_string() << " " << i->second << endl;
-
-i = r.contains(RangeIn(55, 55));
-assert(i == r.end());
-
-i = r.intersects(RangeIn(55, 55));
-assert(i == r.end());
+EXPECT_NE(r.intersects(RangeIn(20, 30)), r.end());
+EXPECT_EQ(r.contains(RangeIn(55, 55)), r.end());
+EXPECT_EQ(r.intersects(RangeIn(55, 55)), r.end());

 i = r.insert(RangeIn(0, 12), 1);
-assert(i == r.end());
+EXPECT_EQ(i, r.end());

 i = r.insert(RangeIn(0, 9), 1);
-assert(i != r.end());
+ASSERT_NE(i, r.end());

-i = r.contains(RangeIn(20, 30));
-assert(i != r.end());
-cout << i->first.to_string() << " " << i->second << endl;
-
-return 0;
+EXPECT_NE(r.contains(RangeIn(20, 30)), r.end());
 }
diff --git a/src/unittest/SConscript b/src/unittest/SConscript
index b104932..3f65734 100644
--- a/src/unittest/SConscript
+++ b/src/unittest/SConscript
@@ -35,7 +35,6 @@
 UnitTest('cprintftime', 'cprintftime.cc')
 UnitTest('initest', 'initest.cc')
 UnitTest('nmtest', 'nmtest.cc')
-UnitTest('rangemaptest', 'rangemaptest.cc')
 UnitTest('refcnttest', 'refcnttest.cc')
 UnitTest('strnumtest', 'strnumtest.cc')


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13736
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ifeb0b57c0cda77706691286f78325e50edb31c0d
Gerrit-Change-Number: 13736
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-CC: Abhishek Singh 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Cron /z/m5/regression/do-regression quick

2018-10-26 Thread Cron Daemon 
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
--- quick/se/02.insttest/riscv/linux-rv64d/minor-timing ---* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
Statistics mismatch* 
build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
--- quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic ---* 
build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
*** diff[simerr]: SKIPPED* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: 
CHANGED!*** stat_diff: FAILURE: Statistics mismatch
*** diff[config.ini]: SKIPPED*** diff[simerr]: SKIPPED* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 CHANGED!
*** diff[config.ini]: SKIPPED* 
build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!*** 
stat_diff: FAILURE: Statistics mismatch
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: 
CHANGED!
*** diff[simout]: SKIPPED* 
build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 CHANGED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 CHANGED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 CHANGED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
CHANGED!*** diff[config.ini]: SKIPPED
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
CHANGED!
*