Re: [gem5-dev] Syscall_Emulation for Shared Memory
Hi Maryam,
You need to tell the simulator how many thread contexts it needs at the
beginning of execution. There's no thread scheduler in SE mode like there'd be
in a real operating system. Since clone allows you to dynamically create a lot
of processes, they need to be bound to thread contexts. Since the simulator
doesn't know how many the application needs you need to tell it.
Pass in the -n option to the configs/example/se.py script. You could try
something like -n4 or w/e.
Regards,
Brandon
-Original Message-
From: gem5-dev On Behalf Of Maryam Babaie
Sent: Monday, March 18, 2019 1:56 PM
To: gem5 Developer List
Subject: Re: [gem5-dev] Syscall_Emulation for Shared Memory
Hi all,
I tried a simple program for testing clone system call on gem5 (SE mode, X86).
Eventhough clone is implemented in the list of system calls, via
cloneFunc; but it works like it's not implemented!
As I checked clone system call always returns in the if clause at
src/sim/syscall_emul.hh:1519 :
if (!(ctc = p->findFreeContext())) {
DPRINTF_SYSCALL(Verbose, "clone: no spare thread context in system"
"[cpu %d, thread %d]", tc->cpuId(), tc->threadId());
return -EAGAIN;
}
Obviously, the reason it returns originates from "ctc =
p->findFreeContext()", in which "findFreeContext()" returns nullptr,
p->but I
cant' figure out why it happens.
I appreciate if any one shares their insight in this regard.
Bests,
MB
On Mon, Mar 11, 2019 at 3:39 PM Potter, Brandon
wrote:
> Hi Maryam,
>
> The code that you are looking at is going to change soon. There is a
> changeset on the google reviewboard which will add some fidelity to
> the tracing of mmap/munmaps from the perspective of SE mode (
> https://gem5-review.googlesource.com/c/public/gem5/+/12307). Feel free
> to review it if it's interesting to you.
>
> 1) I don't understand what you are asking.
> 2) The new patch has an implementation.
> 3) We could probably add an implementation that flushes file-backed
> mmaps to the host file. I have never run into a situation where this
> was needed in an application that was being simulated (so it doesn't
> have an implementation).
> 4) It turns out that fork is not used in Linux to create a new
> process. It uses the clone system call instead. (You can verify this
> by using the Linux strace command with your application. You should
> only see a clone call.) You should take a look at the clone implementation.
>
> Regards,
> Brandon
>
> -Original Message-
> From: gem5-dev On Behalf Of Maryam Babaie
> Sent: Friday, March 8, 2019 4:06 PM
> To: m5-...@m5sim.org
> Subject: [gem5-dev] Syscall_Emulation for Shared Memory
>
> Hi all,
> I have some questions regarding the system calls available in SE mode
> on
> gem5 for X86. I appreciate if any one shares their insight about them:
>
> 1. For the mmap syscall, the function "mmapImpl" has been implemented.
> Up-to which extend this function will work properly for mmap syscall?
>
> 2. For munmap syscall, they have put the munmapFunc, but the body of
> the corresponding function is actually empty. So, does this mean it is
> actually not supported on gem5?
>
> 3. msync syscall is flagged as unimplementedFunc. So, does this mean
> that mmap will still work but the writes will not be reflected
> persistently in the region?
>
> 4. Since the fork syscall is also flagged as unimplementedFunc , how
> is the concept of Copy on Write (generally shared pages) able to be
> simulated and handled in gem5?
>
> Regards
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[gem5-dev] cpu-o3: O3 LSQ Generalisation refactor
Dear Giacomo Travaglini, Gabor Dozsa, Regarding your LSQ rewrite commit in January: 51becd2475748fb5515f261254c48827b3b5c2ba Because this is a substantial rewrite, is there any documentation related to how things work now? I'm trying to debug an assert I get with X86 and O3 cpu in lsq_impl.hh. LSQ::SplitDataRequest::finish(const Fault , const RequestPtr , ThreadContext* tc, BaseTLB::Mode mode) _fault.push_back(fault); assert(req == _requests[numTranslatedFragments] || this->isDelayed()); I'm interested in the fix, but I'd also like to know how the new LSQ works because it's related to my work. I can bypass by using the gem5 before the rewrite, but I assume this is something that should be fixed anyway. Thank you, Andrew Zigerelli ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: dev-arm: ambiguous use of getPort()
Andrea Mondelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17469
Change subject: dev-arm: ambiguous use of getPort()
..
dev-arm: ambiguous use of getPort()
The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.
This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)
Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
---
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index f043db2..6235c22 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -132,9 +132,9 @@
}
if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
-parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(),
numBytes,
- event, data,
tc->getCpuPtr()->clockPeriod(),
- req->getFlags());
+parent.getDMAPort().dmaAction(
+MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
+tc->getCpuPtr()->clockPeriod(), req->getFlags());
} else {
// We can't do the DMA access as there's been a problem, so tell
the
// event we're done
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 8787089..69f2f52 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -110,7 +110,7 @@
* is used by the two table walkers, and is exposed externally and
* connected through the stage-one table walker.
*/
-DmaPort& getPort() { return port; }
+DmaPort& getDMAPort() { return port; }
Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
uint8_t *data, int numBytes, Request::Flags flags, bool
isFunctional);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 21257de..d310e9e 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -102,7 +102,7 @@
TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
{
stage2Mmu = m;
-port = >getPort();
+port = >getDMAPort();
masterId = master_id;
}
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index dc3c35b..47c5f96 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1246,7 +1246,7 @@
Port *
TLB::getTableWalkerPort()
{
-return >getPort();
+return >getDMAPort();
}
void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Gerrit-Change-Number: 17469
Gerrit-PatchSet: 1
Gerrit-Owner: Andrea Mondelli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Correct cast of template parameter
Andrea Mondelli has uploaded a new patch set (#3). ( https://gem5-review.googlesource.com/c/public/gem5/+/17308 ) Change subject: dev-arm: Correct cast of template parameter .. dev-arm: Correct cast of template parameter Clang with -Wconstant-conversion is _very_ restrictive on casting. The shift operator results in an incorrect promotion. This patch add a compile-time static cast that remove the error when clang is used. Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 --- M src/arch/arm/isa/insts/sve.isa M src/base/bitfield.hh 2 files changed, 13 insertions(+), 5 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17308 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 Gerrit-Change-Number: 17308 Gerrit-PatchSet: 3 Gerrit-Owner: Andrea Mondelli Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: misc: missing override specifier
Andrea Mondelli has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17468 Change subject: misc: missing override specifier .. misc: missing override specifier Missing specifier of overridden virtual function declared in sim_object.hh Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2 --- M src/cpu/testers/directedtest/RubyDirectedTester.hh M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh M src/cpu/testers/memtest/memtest.hh M src/cpu/testers/rubytest/RubyTester.hh M src/dev/io_device.hh M src/mem/addr_mapper.hh M src/mem/bridge.hh M src/mem/external_master.hh M src/mem/external_slave.hh M src/mem/mem_checker_monitor.hh M src/mem/ruby/network/MessageBuffer.hh M src/mem/ruby/network/Network.hh M src/mem/xbar.hh 13 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 0f51976..68abbcb 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -72,7 +72,7 @@ MasterPort* getCpuPort(int idx); -virtual void init(); +virtual void init() override; void wakeup(); diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh index a18f5bb..af25c69 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh @@ -59,7 +59,7 @@ typedef GarnetSyntheticTrafficParams Params; GarnetSyntheticTraffic(const Params *p); -virtual void init(); +virtual void init() override; // main simulation loop (one cycle) void tick(); diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 8e8f739..b8cdfa5 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -75,7 +75,7 @@ typedef MemTestParams Params; MemTest(const Params *p); -virtual void regStats(); +virtual void regStats() override; Port (const std::string _name, PortID idx=InvalidPortID) override; diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index 2509aa2..210166f 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -103,7 +103,7 @@ MasterPort* getReadableCpuPort(int idx); MasterPort* getWritableCpuPort(int idx); -virtual void init(); +virtual void init() override; void wakeup(); diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index 64d7aa5..a7967e5 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -123,7 +123,7 @@ return dynamic_cast(_params); } -virtual void init(); +virtual void init() override; Port (const std::string _name, PortID idx=InvalidPortID) override; diff --git a/src/mem/addr_mapper.hh b/src/mem/addr_mapper.hh index 6b47cfc..e22cb18 100644 --- a/src/mem/addr_mapper.hh +++ b/src/mem/addr_mapper.hh @@ -65,7 +65,7 @@ Port (const std::string _name, PortID idx=InvalidPortID) override; -virtual void init(); +virtual void init() override; protected: diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index 9066403..9a286c7 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -319,7 +319,7 @@ Port (const std::string _name, PortID idx=InvalidPortID) override; -virtual void init(); +virtual void init() override; typedef BridgeParams Params; diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh index 42ac67c..f105054 100644 --- a/src/mem/external_master.hh +++ b/src/mem/external_master.hh @@ -129,7 +129,7 @@ static void registerHandler(const std::string _name, Handler *handler); -void init(); +void init() override; const MasterID masterId; }; diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh index 7290d63..cfe89b9 100644 --- a/src/mem/external_slave.hh +++ b/src/mem/external_slave.hh @@ -135,7 +135,7 @@ static void registerHandler(const std::string _name, Handler *handler); -void init(); +void init() override; }; diff --git a/src/mem/mem_checker_monitor.hh b/src/mem/mem_checker_monitor.hh index 0564a81..37e72ac 100644 --- a/src/mem/mem_checker_monitor.hh +++ b/src/mem/mem_checker_monitor.hh @@ -73,7 +73,7 @@ Port (const std::string _name, PortID idx=InvalidPortID) override; -virtual void init(); +virtual void init() override; private: diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh index 4e85ac4..05821d5 100644 --- a/src/mem/ruby/network/MessageBuffer.hh +++
[gem5-dev] Change in gem5/gem5[master]: misc: Removed inconsistency in O3* debug msgs
Hello Jason Lowe-Power, Giacomo Travaglini, Bradley Wang, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17248 to look at the new patch set (#6). Change subject: misc: Removed inconsistency in O3* debug msgs .. misc: Removed inconsistency in O3* debug msgs Added consistency in the DEBUG message form, to allow a better parsing. Fixed sn/tid type parameter. Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b --- M src/arch/mips/isa.cc M src/cpu/o3/commit_impl.hh M src/cpu/o3/cpu.cc M src/cpu/o3/decode_impl.hh M src/cpu/o3/fetch_impl.hh M src/cpu/o3/iew_impl.hh M src/cpu/o3/inst_queue_impl.hh M src/cpu/o3/lsq_unit.hh M src/cpu/o3/lsq_unit_impl.hh M src/cpu/o3/mem_dep_unit_impl.hh M src/cpu/o3/rename_impl.hh M src/cpu/o3/rob_impl.hh M src/cpu/pred/bpred_unit.cc 13 files changed, 348 insertions(+), 282 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17248 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b Gerrit-Change-Number: 17248 Gerrit-PatchSet: 6 Gerrit-Owner: Andrea Mondelli Gerrit-Reviewer: Andrea Mondelli Gerrit-Reviewer: Bradley Wang Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5
To make it easier to have a discussion about this proposed API, I copied it into a document over here: https://docs.google.com/document/d/1GBpHjWtjH_AowGqb8pAk9dhWtMdukMALoXmlzwpPgOM/edit?usp=sharing Please take a look when you have a chance. Gabe On Mon, Mar 18, 2019 at 6:51 PM Gabe Black wrote: > Hello again folks. I'm tempted to write up a doc which describes my > thoughts on this, but for the sake of expediency I'm just going to send a > "quick" email for now. (edit: This got pretty long. Maybe I should have put > it in a doc. Too late now, maybe later?) > > TLM DMI socket API: > > When a TLM initiator sends a transaction which eventually gets serviced by > a target, there is an attribute in the generic payload which says whether > or not the value accessed *could* have been accessed by DMI if that had > been requested. It seems to be that at least for some uses of this > mechanism, this is a gating mechanism. If the other guy doesn't say yes to > this, then the initiator won't bother to ask with heavier weight mechanisms. > > Then there's a get_direct_mem_ptr method which also accepts a transaction, > and effectively returns whether there's a DMI-able region which corresponds > to that transaction and a descriptor of that region. > > Finally, there's an invalidate_direct_mem_ptr method which basically > broadcasts backwards to let anybody know who may have a live DMI descriptor > that some region is going away, and they should throw away their > descriptor. Unlike the get_direct_mem_ptr which travels like an access with > one destination, this propogates back to potentially multiple initiators > who could have retrieved a DMI descriptor at some point. > > > Proposed gem5 mechanism: > > There would be a new pair of protocol functions added to the master/slave > memory port pairs, sendAtomicBackdoor/recvAtomicBackdoor. Only the atomic > mechanism is being extended to support backdoor accesses, at least for > right now, because you'd likely use the atomic mode and DMI/backdoors under > the same circumstances, ie when you want to go fast and can sacrafice > accuracy. The sendAtomicBackdoor function would just call the > recvAtomicBackdoor function on its peer. The recvAtomicBackdoor function > would be virtual, and its default implementaiton would be to call vanilla > recvAtomic. > > The same as regular sendAtomic/recvAtomic, except that it also takes a > reference to a pointer to a memory backdoor descriptor. I use the term > backdoor instead of re-using DMI to avoid them being seen as equivalent but > confusingly different, and because the term backdoor is already being used > in gem5. The exact name is up for debate. If the target which services the > atomic requiest could support backdoor accesses, or a link in the chain > wouldn't stop working if it was circumvented (like a cache), then that > pointer is set to point to a backdoor memory descriptor. If not, then it's > left pointing at nullptr. > > The backdoor descriptor itself has a few basic properties (still to be > nailed down) which essentially correspond to the DMI ones, ie start and end > address, pointer to the data, and access priveleges. It also has a list of > callbacks for everyone that has a copy of the descriptor returned one way > or the other. These are registered by the caller when they successfully > receive the descriptor, a step they can skip if they're, for instance, just > checking if there is one but not actually storing it. > > Optionally, there could also be a getMemoryBackdoors function which would > accept a start and end address (or AddrRange) and collect a vector of > backdoor descriptors for the whole system. This could be used when setting > up, for instance, KVM, so that you don't have to manually try to figure out > where the memory is to add into the KVM descriptor. This is largely > separate from/an extension of the other mechanism and can be added later. > > If a backdoor needs to be invalidated, the owner of the backdoor just > needs to go through and call all the callbacks, and when it's done it can > throw away the backdoor. > > > Translation between the two: > > TLM -> gem5 > > When a transaction comes in from TLM, the gem5 side of the bridge would > call sendAtomicBackdoor. That will trickle through to somebody on the gem5 > side which will reply, and optionally pass back a pointer to the backdoor > descriptor. The assumption is that if something is backdoor-able, then it > will have already set up that descriptor and will just hand out pointers to > it as necessary. If the backdoor pointer is set, then the dmi_allowed > attribute will be set. Otherwise the bridge acts as before. > > When get_direct_mem_ptr is called, the bridge will also call > sendAtomicBackdoor, but in that case it will set the NO_ACCESS flag in the > request it creates (or similar) to indicate that the packet shouldn't do > anything when it gets where it's going. When the result comes back, the > backdoor descriptor is used to set
[gem5-dev] Change to the port API
Hi everybody. I just checked in a change which modifies the port API and
may affect code you have which isn't checked in to the main gem5
repository. If you're implementing something which exposes ports and have
implemented the getMasterPort or getSlavePort methods on a MemObject,
porting to the new API should be simple. All you'll need to do is replace
those methods with a new method called getPort with this signature:
Port (const std::string _name, PortID idx=InvalidPortID)
override;
If there's only one of getMasterPort or getSlavePort, you should be able to
just rename the function. If there are both, you can just combine the two
so that if a name either function would recognize is passed in, getPort
returns the same port as the corresponding old function did.
Example:
BaseMasterPort &
getMasterPort(const std::string _name, PortID idx=InvalidPortID)
{
if (if_name == "master")
return masterPort;
return ParentClass::getMasterPort(if_name, idx);
}
BaseSlavePort &
getSlavePort(const std::string _name, PortID idx=InvalidPortID)
{
if (if_name == "slave")
return slavePort;
return ParentClass::getSlavePort(if_name, idx);
}
Would become:
Port &
getPort(const std::string _name, PortID idx=InvalidPortID)
{
if (if_name == "master")
return masterPort;
else if (if_name == "slave")
return slavePort;
return ParentClass::getPort(if_name, idx);
}
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[gem5-dev] Change in gem5/gem5[master]: systemc: Hook up gem5_getPort to the gem5 getPort mechanism.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17229 )
Change subject: systemc: Hook up gem5_getPort to the gem5 getPort mechanism.
..
systemc: Hook up gem5_getPort to the gem5 getPort mechanism.
Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17229
Reviewed-by: Andreas Sandberg
Maintainer: Gabe Black
---
M src/systemc/core/SystemC.py
M src/systemc/core/sc_module.cc
M src/systemc/ext/core/sc_module.hh
3 files changed, 20 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Gabe Black: Looks good to me, approved
diff --git a/src/systemc/core/SystemC.py b/src/systemc/core/SystemC.py
index 649d6d3..74b7cec 100644
--- a/src/systemc/core/SystemC.py
+++ b/src/systemc/core/SystemC.py
@@ -25,7 +25,7 @@
#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from m5.SimObject import SimObject, cxxMethod
# This class represents the systemc kernel. There should be exactly one in
the
# simulation. It receives gem5 SimObject lifecycle callbacks (init,
regStats,
@@ -62,6 +62,10 @@
cxx_class = 'sc_core::sc_module'
cxx_header = 'systemc/ext/core/sc_module.hh'
+@cxxMethod(return_value_policy="reference", cxx_name="gem5_getPort")
+def getPort(self, if_name, iex):
+return None
+
try:
import _m5
except:
diff --git a/src/systemc/core/sc_module.cc b/src/systemc/core/sc_module.cc
index fc98aa3..ba9c76a 100644
--- a/src/systemc/core/sc_module.cc
+++ b/src/systemc/core/sc_module.cc
@@ -31,6 +31,7 @@
#include
#include
+#include "base/logging.hh"
#include "systemc/core/event.hh"
#include "systemc/core/kernel.hh"
#include "systemc/core/module.hh"
@@ -114,6 +115,12 @@
const sc_bind_proxy SC_BIND_PROXY_NIL;
+::Port &
+sc_module::gem5_getPort(const std::string _name, int idx)
+{
+fatal("%s does not have any port named %s\n", name(), if_name);
+}
+
sc_module::~sc_module() { delete _gem5_module; }
void
diff --git a/src/systemc/ext/core/sc_module.hh
b/src/systemc/ext/core/sc_module.hh
index 0c8bd9f..24a1aea 100644
--- a/src/systemc/ext/core/sc_module.hh
+++ b/src/systemc/ext/core/sc_module.hh
@@ -30,6 +30,7 @@
#ifndef __SYSTEMC_CORE_EXT_SC_MODULE_HH__
#define __SYSTEMC_CORE_EXT_SC_MODULE_HH__
+#include
#include
#include "sc_object.hh"
@@ -58,6 +59,9 @@
} // namespace sc_gem5
+// Gem5 prototype
+class Port;
+
namespace sc_core
{
@@ -95,6 +99,10 @@
class sc_module : public sc_object
{
public:
+// Gem5 specific extensions
+virtual ::Port _getPort(const std::string _name, int idx=-1);
+
+ public:
friend class ::sc_gem5::Kernel;
friend class ::sc_gem5::Module;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17229
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Gerrit-Change-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3
Gerrit-Change-Number: 17229
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
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Gerrit-Reviewer: Matthias Jung
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: python: Switch to the new getPort mechanism to connect ports.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17039 )
Change subject: python: Switch to the new getPort mechanism to connect
ports.
..
python: Switch to the new getPort mechanism to connect ports.
This retrieves ports using the getPort method, and connects them using
the bind method on the ports themselves. Any smarts as far as what type
of peers are allowed to connect or how they connect is left up to the
individual bind methods.
Change-Id: Ic640d1fce8af1bed46e5830edc4a8a0f9d66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17039
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/python/m5/params.py
1 file changed, 3 insertions(+), 21 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index ff625e0..5236022 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1943,8 +1943,6 @@
# Call C++ to create corresponding port connection between C++ objects
def ccConnect(self):
-from _m5.pyobject import connectPorts
-
if self.ccConnected: # already done this
return
@@ -1952,27 +1950,11 @@
if not self.peer: # nothing to connect to
return
-# check that we connect a master to a slave
-if self.role == peer.role:
-raise TypeError(
-"cannot connect '%s' and '%s' due to identical
role '%s'" % \
-(peer, self, self.role))
+port = self.simobj.getPort(self.name, self.index)
+peer_port = peer.simobj.getPort(peer.name, peer.index)
+port.bind(peer_port)
-if self.role == 'SLAVE':
-# do nothing and let the master take care of it
-return
-
-try:
-# self is always the master and peer the slave
-connectPorts(self.simobj.getCCObject(), self.name, self.index,
- peer.simobj.getCCObject(), peer.name, peer.index)
-except:
-print("Error connecting port %s.%s to %s.%s" %
- (self.simobj.path(), self.name,
- peer.simobj.path(), peer.name))
-raise
self.ccConnected = True
-peer.ccConnected = True
# A reference to an individual element of a VectorPort... much like a
# PortRef, but has an index.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic640d1fce8af1bed46e5830edc4a8a0f9d66
Gerrit-Change-Number: 17039
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Weiping Liao
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17040 )
Change subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort.
..
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.
Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/generic/tlb.hh
M src/arch/x86/interrupts.hh
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/trace/trace_cpu.cc
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/dev/io_device.cc
M src/dev/io_device.hh
M src/dev/net/Ethernet.py
M src/dev/net/SConscript
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_etherlink.hh
M src/dev/net/etherbus.cc
M src/dev/net/etherbus.hh
M src/dev/net/etherdevice.hh
M src/dev/net/etherlink.cc
M src/dev/net/etherlink.hh
M src/dev/net/etherswitch.cc
M src/dev/net/etherswitch.hh
M src/dev/net/ethertap.cc
M src/dev/net/ethertap.hh
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/ns_gige.cc
M src/dev/net/ns_gige.hh
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/x86/i82094aa.cc
M src/dev/x86/i82094aa.hh
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/lds_state.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.cc
M src/learning_gem5/part2/simple_memobj.hh
M src/mem/addr_mapper.cc
M src/mem/addr_mapper.hh
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/comm_monitor.cc
M src/mem/comm_monitor.hh
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/external_master.cc
M src/mem/external_master.hh
M src/mem/external_slave.cc
M src/mem/external_slave.hh
M src/mem/mem_checker_monitor.cc
M src/mem/mem_checker_monitor.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/mem_object.cc
M src/mem/mem_object.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/Network.hh
R src/mem/ruby/network/dummy_port.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
M src/python/SConscript
M src/python/pybind11/pybind.hh
D src/python/pybind11/pyobject.cc
M src/sim/SConscript
M src/sim/cxx_manager.cc
M src/sim/init.cc
R src/sim/python.cc
M src/sim/system.cc
M src/sim/system.hh
108 files changed, 396 insertions(+), 751 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 1a7b5d3..21257de 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -114,8 +114,8 @@
fatal_if(!tlb, "Table walker must have a valid TLB\n");
}
-BaseMasterPort&
-TableWalker::getMasterPort(const std::string _name, PortID idx)
+Port &
+TableWalker::getPort(const std::string _name, PortID idx)
{
if (if_name == "port") {
if (!isStage2) {
@@ -124,7 +124,7 @@
fatal("Cannot access table walker port through stage-two
walker\n");
}
}
-return MemObject::getMasterPort(if_name, idx);
+return MemObject::getPort(if_name, idx);
}
TableWalker::WalkerState::WalkerState() :
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 57e3aed..8176fc7 100644
--- a/src/arch/arm/table_walker.hh
+++
[gem5-dev] Change in gem5/gem5[master]: mem: Move bind() and unbind() into the Port class.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17038 )
Change subject: mem: Move bind() and unbind() into the Port class.
..
mem: Move bind() and unbind() into the Port class.
These are now pure virtual methods which more specialized port
subclasses will need to implement. The SlavePort class implements them
by ignoring them and then providing parallel functions for the
MasterPort to call. The MasterPort's methods do basically what they
did before, except now bind() uses dynamic cast to check if its peer
is of the appropriate type and also to convert it into that type before
connecting to it.
Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/dev/net/etherint.cc
M src/dev/net/etherint.hh
M src/mem/port.cc
M src/mem/port.hh
M src/sim/port.cc
M src/sim/port.hh
6 files changed, 67 insertions(+), 41 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
diff --git a/src/dev/net/etherint.cc b/src/dev/net/etherint.cc
index 0c5e6b8..b55e625 100644
--- a/src/dev/net/etherint.cc
+++ b/src/dev/net/etherint.cc
@@ -34,6 +34,25 @@
#include "sim/sim_object.hh"
void
+EtherInt::bind(Port )
+{
+EtherInt *p = dynamic_cast();
+if (!p) {
+fatal("Attempt to bind port %s to non-ethernet port %s.",
+name(), peer.name());
+}
+setPeer(p);
+_connected = true;
+}
+
+void
+EtherInt::unbind()
+{
+peer = nullptr;
+_connected = false;
+}
+
+void
EtherInt::setPeer(EtherInt *p)
{
if (peer && peer != p)
diff --git a/src/dev/net/etherint.hh b/src/dev/net/etherint.hh
index 7703220..0486631 100644
--- a/src/dev/net/etherint.hh
+++ b/src/dev/net/etherint.hh
@@ -60,6 +60,9 @@
/** Return port name (for DPRINTF). */
const std::string () const { return portName; }
+void bind(Port ) override;
+void unbind() override;
+
void setPeer(EtherInt *p);
EtherInt* getPeer() { return peer; }
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 6f72bbd..001576f 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -70,12 +70,6 @@
return *_baseSlavePort;
}
-bool
-BaseMasterPort::isConnected() const
-{
-return _baseSlavePort != NULL;
-}
-
BaseSlavePort::BaseSlavePort(const std::string , PortID _id)
: Port(name, _id), _baseMasterPort(NULL)
{
@@ -95,12 +89,6 @@
return *_baseMasterPort;
}
-bool
-BaseSlavePort::isConnected() const
-{
-return _baseMasterPort != NULL;
-}
-
/**
* Master port
*/
@@ -114,24 +102,21 @@
}
void
-MasterPort::bind(BaseSlavePort& slave_port)
+MasterPort::bind(Port )
{
-// bind on the level of the base ports
-_baseSlavePort = _port;
-
-// also attempt to base the slave to the appropriate type
-SlavePort* cast_slave_port = dynamic_cast(_port);
-
-// if this port is compatible, then proceed with the binding
-if (cast_slave_port != NULL) {
-// master port keeps track of the slave port
-_slavePort = cast_slave_port;
-// slave port also keeps track of master port
-_slavePort->bind(*this);
-} else {
-fatal("Master port %s cannot bind to %s\n", name(),
- slave_port.name());
+auto *slave_port = dynamic_cast();
+if (!slave_port) {
+fatal("Attempt to bind port %s to non-slave port %s.",
+name(), peer.name());
}
+// bind on the level of the base ports
+_baseSlavePort = slave_port;
+
+// master port keeps track of the slave port
+_slavePort = slave_port;
+_connected = true;
+// slave port also keeps track of master port
+_slavePort->slaveBind(*this);
}
void
@@ -140,8 +125,9 @@
if (_slavePort == NULL)
panic("Attempting to unbind master port %s that is not
connected\n",
name());
-_slavePort->unbind();
+_slavePort->slaveUnbind();
_slavePort = NULL;
+_connected = false;
_baseSlavePort = NULL;
}
@@ -218,17 +204,19 @@
}
void
-SlavePort::unbind()
+SlavePort::slaveUnbind()
{
_baseMasterPort = NULL;
_masterPort = NULL;
+_connected = false;
}
void
-SlavePort::bind(MasterPort& master_port)
+SlavePort::slaveBind(MasterPort& master_port)
{
_baseMasterPort = _port;
_masterPort = _port;
+_connected = true;
}
Tick
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 77081db..2154da0 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -77,10 +77,7 @@
public:
-virtual void bind(BaseSlavePort& slave_port) = 0;
-virtual void unbind() = 0;
BaseSlavePort& getSlavePort() const;
-bool isConnected() const;
};
@@ -101,7 +98,6 @@
public:
BaseMasterPort& getMasterPort() const;
-
[gem5-dev] Change in gem5/gem5[master]: sim: Add a getPort function to SimObject.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17037 )
Change subject: sim: Add a getPort function to SimObject.
..
sim: Add a getPort function to SimObject.
This will retrieve a Port object from a given SimObject (which might
not be a MemObject) no matter what flavor of Port it is.
Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/python/m5/SimObject.py
M src/sim/sim_object.cc
M src/sim/sim_object.hh
3 files changed, 23 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b74e93a..0e29980 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1642,6 +1642,10 @@
def getValue(self):
return self.getCCObject()
+@cxxMethod(return_value_policy="reference")
+def getPort(self, if_name, idx):
+pass
+
# Create C++ port connections corresponding to the connections in
# _port_refs
def connectPorts(self):
diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index ab92ae5..7b794a0 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -133,6 +133,12 @@
return probeManager;
}
+Port &
+SimObject::getPort(const std::string _name, PortID idx)
+{
+fatal("%s does not have any port named %s\n", name(), if_name);
+}
+
//
// static function: serialize all SimObjects.
//
diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index 42a19bb..5c9bf00 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -56,6 +56,7 @@
#include "sim/drain.hh"
#include "sim/eventq.hh"
#include "sim/eventq_impl.hh"
+#include "sim/port.hh"
#include "sim/serialize.hh"
class EventManager;
@@ -170,6 +171,18 @@
ProbeManager *getProbeManager();
/**
+ * Get a port with a given name and index. This is used at binding time
+ * and returns a reference to a protocol-agnostic port.
+ *
+ * @param if_name Port name
+ * @param idx Index in the case of a VectorPort
+ *
+ * @return A reference to the given port
+ */
+virtual Port (const std::string _name,
+ PortID idx=InvalidPortID);
+
+/**
* startup() is the final initialization call before simulation.
* All state is initialized (including unserialized state, if any,
* such as the curTick() value), so this is the appropriate place to
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1
Gerrit-Change-Number: 17037
Gerrit-PatchSet: 6
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Weiping Liao
Gerrit-MessageType: merged
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