[gem5-dev] Change in gem5/gem5[master]: tests: Added GTests for byteswap.hh
Mahyar Samani has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22080 )
Change subject: tests: Added GTests for byteswap.hh
..
tests: Added GTests for byteswap.hh
In addition to the test, "#include base/logging.hh" was added to the
"byteswap.hh". It is is required to compile the header.
Added tests ByteswapTest.swap_byte64, ByteswapTest.swap_byte32,
ByteswapTest.swap_byte16, ByteswapTest.swap_byte, ByteswapTest.htog,
and ByteswapTest.gtoh. The file byteswap.hh is mostly templates.
Added test for BigEndianGuest and LittleEndianGuest namespaces.
Change-Id: I8870a55594ed439fe9e1fb84f73261d1b1b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22080
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/sim/SConscript
M src/sim/byteswap.hh
A src/sim/byteswap.test.cc
3 files changed, 794 insertions(+), 0 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 72b0f3d..aacdb34 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -77,6 +77,8 @@
Source('clocked_object.cc')
Source('mathexpr.cc')
+GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
+
if env['TARGET_ISA'] != 'null':
SimObject('InstTracer.py')
SimObject('Process.py')
diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index a46f8f5..0b41c67 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -37,6 +37,7 @@
#ifndef __SIM_BYTE_SWAP_HH__
#define __SIM_BYTE_SWAP_HH__
+#include "base/logging.hh"
#include "base/types.hh"
// This lets us figure out what the byte order of the host system is
diff --git a/src/sim/byteswap.test.cc b/src/sim/byteswap.test.cc
new file mode 100644
index 000..ef41437
--- /dev/null
+++ b/src/sim/byteswap.test.cc
@@ -0,0 +1,791 @@
+/*
+ * Copyright (c) 2019 The Regents of the University of California
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Mahyar Samani
+ */
+
+#include
+
+#include "sim/byteswap.hh"
+
+TEST(ByteswapTest, swap_byte64)
+{
+EXPECT_EQ(0x0123456789abcdef, swap_byte64(0xefcdab8967452301));
+EXPECT_EQ(0xfedcba9876543210, swap_byte64(0x1032547698badcfe));
+EXPECT_EQ(0x0b1cb071b77141b1, swap_byte64(0xb14171b771b01c0b));
+EXPECT_EQ(0x, swap_byte64(0x));
+EXPECT_EQ(0x, swap_byte64(0x));
+EXPECT_EQ(0xa0a0a0a0a0a0a0a0, swap_byte64(0xa0a0a0a0a0a0a0a0));
+}
+
+TEST(ByteswapTest, swap_byte32)
+{
+EXPECT_EQ(0x0123cdef, swap_byte32(0xefcd2301));
+EXPECT_EQ(0xfedc3210, swap_byte32(0x1032dcfe));
+EXPECT_EQ(0x0b1c41b1, swap_byte32(0xb1411c0b));
+EXPECT_EQ(0x, swap_byte32(0x));
+EXPECT_EQ(0x, swap_byte32(0x));
+EXPECT_EQ(0xa0a0a0a0, swap_byte32(0xa0a0a0a0));
+}
+
+TEST(ByteswapTest, swap_byte16)
+{
+EXPECT_EQ(0x01ef, swap_byte16(0xef01));
+EXPECT_EQ(0xfe10, swap_byte16(0x10fe));
+EXPECT_EQ(0x0bb1, swap_byte16(0xb10b));
+EXPECT_EQ(0x00ff, swap_byte16(0xff00));
+EXPECT_EQ(0x, swap_byte16(0x));
+EXPECT_EQ(0xa0a0, swap_byte16(0xa0a0));
+}
+
+TEST(ByteswapTest, swap_byte)
+{
+EXPECT_EQ(0x0123456789abcdef, swap_byte((uint64_t)0xefcdab8967452301));
+EXPECT_EQ(0xfedcba9876543210, swap_byte((uint64_t)0x1032547698badcfe));
+
Re: [gem5-dev] ARM semihosting, KVM, fast models, pseudo instructions, and system calls
Nope, it doesn't look like it can. It can intercept BRK and BKPT instructions, but not SVC or HLT, which apparently can also be used for semihosting. Gabe On Fri, Nov 15, 2019 at 2:17 PM Gabe Black wrote: > Unless KVM can intercept SVC instructions somehow? Maybe because they sort > of cause an interrupt? I have my doubts, but I'll look into that since if > it's true it would make life a lot easier. > > Gabe > > On Fri, Nov 15, 2019 at 1:24 PM Gabe Black wrote: > >> >> >> On Fri, Nov 15, 2019 at 4:07 AM Giacomo Travaglini < >> giacomo.travagl...@arm.com> wrote: >> >>> Hi Gabe, >>> >>> Yes, as I was mentioning in >>> https://gem5-review.googlesource.com/c/public/gem5/+/22118/5, if fast >>> models implements arm watchpoints (by writing some self hosted debug >>> registers, >>> and not reying on custom made hooks after the PA is evaluated), those >>> trap on VA matches. >>> >> >> These are not actual architected watchpoints (at least as far as I know), >> these are artificial breakpoints, watchpoints, etc, which are provided by >> the model itself. >> >> >>> >>> I would personally love to see m5 pseudo instructions being implemented >>> with arm semishosting, not only for the FastModel use case. >>> From a m5 pow seems like you would just need to change the macro >>> in util/m5/m5op_arm_A64.S >>> (of course you would have to add the implementation in the semihosting >>> files; how does this work with fast models?) >>> >> >> To implement them in most cases would be easy, but the problem is >> supporting them everywhere. The problem (as I attempted to describe in my >> initial email) is that KVM has no notion of semihosting, and as far as I >> can tell no way to hook the appropriate instructions to intercept them. >> >> To summarize, the options are: >> >> Special instructions: Works only in native CPUs. >> Special memory locations: Works in native CPUs and KVM >> Semihosting: Works in native CPUs and fast models. >> >> There isn't anything that works in all CPUs, meaning there needs to be >> different behavior depending on what CPU you're using at the time. That >> could mean different binaries, or a binary that somehow magically detects >> what it should use, or specifying on the command line, or... >> >> Gabe >> >>> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] ARM semihosting, KVM, fast models, pseudo instructions, and system calls
Unless KVM can intercept SVC instructions somehow? Maybe because they sort of cause an interrupt? I have my doubts, but I'll look into that since if it's true it would make life a lot easier. Gabe On Fri, Nov 15, 2019 at 1:24 PM Gabe Black wrote: > > > On Fri, Nov 15, 2019 at 4:07 AM Giacomo Travaglini < > giacomo.travagl...@arm.com> wrote: > >> Hi Gabe, >> >> Yes, as I was mentioning in >> https://gem5-review.googlesource.com/c/public/gem5/+/22118/5, if fast >> models implements arm watchpoints (by writing some self hosted debug >> registers, >> and not reying on custom made hooks after the PA is evaluated), those >> trap on VA matches. >> > > These are not actual architected watchpoints (at least as far as I know), > these are artificial breakpoints, watchpoints, etc, which are provided by > the model itself. > > >> >> I would personally love to see m5 pseudo instructions being implemented >> with arm semishosting, not only for the FastModel use case. >> From a m5 pow seems like you would just need to change the macro >> in util/m5/m5op_arm_A64.S >> (of course you would have to add the implementation in the semihosting >> files; how does this work with fast models?) >> > > To implement them in most cases would be easy, but the problem is > supporting them everywhere. The problem (as I attempted to describe in my > initial email) is that KVM has no notion of semihosting, and as far as I > can tell no way to hook the appropriate instructions to intercept them. > > To summarize, the options are: > > Special instructions: Works only in native CPUs. > Special memory locations: Works in native CPUs and KVM > Semihosting: Works in native CPUs and fast models. > > There isn't anything that works in all CPUs, meaning there needs to be > different behavior depending on what CPU you're using at the time. That > could mean different binaries, or a binary that somehow magically detects > what it should use, or specifying on the command line, or... > > Gabe > >> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] ARM semihosting, KVM, fast models, pseudo instructions, and system calls
On Fri, Nov 15, 2019 at 4:07 AM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Hi Gabe, > > Yes, as I was mentioning in > https://gem5-review.googlesource.com/c/public/gem5/+/22118/5, if fast > models implements arm watchpoints (by writing some self hosted debug > registers, > and not reying on custom made hooks after the PA is evaluated), those trap > on VA matches. > These are not actual architected watchpoints (at least as far as I know), these are artificial breakpoints, watchpoints, etc, which are provided by the model itself. > > I would personally love to see m5 pseudo instructions being implemented > with arm semishosting, not only for the FastModel use case. > From a m5 pow seems like you would just need to change the macro > in util/m5/m5op_arm_A64.S > (of course you would have to add the implementation in the semihosting > files; how does this work with fast models?) > To implement them in most cases would be easy, but the problem is supporting them everywhere. The problem (as I attempted to describe in my initial email) is that KVM has no notion of semihosting, and as far as I can tell no way to hook the appropriate instructions to intercept them. To summarize, the options are: Special instructions: Works only in native CPUs. Special memory locations: Works in native CPUs and KVM Semihosting: Works in native CPUs and fast models. There isn't anything that works in all CPUs, meaning there needs to be different behavior depending on what CPU you're using at the time. That could mean different binaries, or a binary that somehow magically detects what it should use, or specifying on the command line, or... Gabe > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: base: configurable entrypoint for Raw Images
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/22849 )
Change subject: base: configurable entrypoint for Raw Images
..
base: configurable entrypoint for Raw Images
This patch adds an alternative constructor for raw images
which lets users specify a load address for the blob.
Change-Id: Ib5bd88cbdf79bd40b5f8086b6af83fb8061f9770
Reviewed-by: Giacomo Travaglini
---
M src/base/loader/memory_image.hh
M src/base/loader/raw_image.hh
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/src/base/loader/memory_image.hh
b/src/base/loader/memory_image.hh
index a10daba..dc1a4c8 100644
--- a/src/base/loader/memory_image.hh
+++ b/src/base/loader/memory_image.hh
@@ -1,4 +1,15 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2004 The Regents of The University of Michigan
* All rights reserved.
*
@@ -72,6 +83,11 @@
Segment(_name, 0, _ifd, 0, _ifd->len())
{}
+Segment(const std::string &_name, Addr _base,
+const ImageFileDataPtr &_ifd) :
+Segment(_name, _base, _ifd, 0, _ifd->len())
+{}
+
ImageFileDataPtr ifd;
std::string name;
Addr base = 0;
diff --git a/src/base/loader/raw_image.hh b/src/base/loader/raw_image.hh
index aae82a3..0e825fd 100644
--- a/src/base/loader/raw_image.hh
+++ b/src/base/loader/raw_image.hh
@@ -1,4 +1,15 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -42,10 +53,14 @@
RawImage(ImageFileDataPtr(new ImageFileData(filename)))
{}
+RawImage(ImageFileDataPtr ifd, const Addr load_addr) :
+RawImage(ifd)
+{ entry = load_addr; }
+
MemoryImage
buildImage() const override
{
-return {{ "data", imageData }};
+return {{ "data", entry, imageData }};
}
};
--
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Gerrit-Change-Id: Ib5bd88cbdf79bd40b5f8086b6af83fb8061f9770
Gerrit-Change-Number: 22849
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[gem5-dev] Change in gem5/gem5[master]: sim: kernelExtras if no kernel provided
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/22850 ) Change subject: sim: kernelExtras if no kernel provided .. sim: kernelExtras if no kernel provided kernelExtras facilitates a way for users to provide additional blobs to load into memory. As of now, the creation of the extra images is done independently of the kernel being provided, but the loading is only done if the kernel is present. This patch refactors the loading of extra images to be committed if no kernel is present. Change-Id: I900542e1034ade8d757d01823cfd4a30f0b36734 Reviewed-by: Giacomo Travaglini --- M src/sim/system.cc 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/sim/system.cc b/src/sim/system.cc index f2bbd8c..9f72fdc 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2014,2017-2018 ARM Limited + * Copyright (c) 2011-2014,2017-2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -354,14 +354,14 @@ } // Load program sections into memory kernelImage.write(physProxy); -for (const auto _kernel : kernelExtras) -extra_kernel->buildImage().move(mapper).write(physProxy); DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); DPRINTF(Loader, "Kernel loaded...\n"); } +for (const auto _kernel : kernelExtras) +extra_kernel->buildImage().move(mapper).write(physProxy); } } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22850 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I900542e1034ade8d757d01823cfd4a30f0b36734 Gerrit-Change-Number: 22850 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: dev-arm: device name in AmbaFake accesses
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/22847 )
Change subject: dev-arm: device name in AmbaFake accesses
..
dev-arm: device name in AmbaFake accesses
This patch prints the name of the AmbaFake device being accessed.
This is useful for identifying the device triggering the warning.
Change-Id: I69ca06d5d9bce73d918b8c8b46bb43e92597933b
Reviewed-by: Giacomo Travaglini
---
M src/dev/arm/amba_fake.cc
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/dev/arm/amba_fake.cc b/src/dev/arm/amba_fake.cc
index 9c14140..fb08c4f 100644
--- a/src/dev/arm/amba_fake.cc
+++ b/src/dev/arm/amba_fake.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -63,7 +63,8 @@
pkt->setLE(0);
if (!readId(pkt, ambaId, pioAddr) && !params()->ignore_access)
-panic("Tried to read AmbaFake at offset %#x that doesn't exist\n",
daddr);
+panic("Tried to read AmbaFake %s at offset %#x that doesn't
exist\n",
+ name(), daddr);
pkt->makeAtomicResponse();
return pioDelay;
@@ -76,7 +77,8 @@
Addr daddr = pkt->getAddr() - pioAddr;
if (!params()->ignore_access)
-panic("Tried to write AmbaFake at offset %#x that doesn't
exist\n", daddr);
+panic("Tried to write AmbaFake %s at offset %#x that doesn't
exist\n",
+ name(), daddr);
pkt->makeAtomicResponse();
return pioDelay;
--
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[gem5-dev] Change in gem5/gem5[master]: configs-arm: enable PMU instantiation in CpuCluster
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/22848 ) Change subject: configs-arm: enable PMU instantiation in CpuCluster .. configs-arm: enable PMU instantiation in CpuCluster This patch adds a new method to the CpuCluster object which allows passing the PMU interrupt numbers and events to record for each core. This lets users create CPU clusters with PMUs. Change-Id: Id49fd0aee50f49e4c6fca95e4ee673da3dca73cd Reviewed-by: Giacomo Travaglini --- M configs/example/arm/devices.py 1 file changed, 13 insertions(+), 0 deletions(-) diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 16312eb..ceb36be 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -159,6 +159,19 @@ cpu.connectAllPorts(self.toL2Bus) self.toL2Bus.master = self.l2.cpu_side +def addPMUs(self, ints, events=[]): +assert isinstance(ints, list) and len(ints) == len(self.cpus) +for cpu, pint in zip(self.cpus, ints): +int_cls = ArmPPI if pint < 32 else ArmSPI +for isa in cpu.isa: +isa.pmu = ArmPMU(interrupt=int_cls(num=pint)) +isa.pmu.addArchEvents(cpu=cpu, itb=cpu.itb, dtb=cpu.dtb, + icache=getattr(cpu, 'icache', None), + dcache=getattr(cpu, 'dcache', None), + l2cache=getattr(self, 'l2', None)) +for ev in events: +isa.pmu.addEvent(ev) + def connectMemSide(self, bus): bus.slave try: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22848 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Id49fd0aee50f49e4c6fca95e4ee673da3dca73cd Gerrit-Change-Number: 22848 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Make the Tarmac parsed registers case insensitive
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/22845
to review the following change.
Change subject: arch-arm: Make the Tarmac parsed registers case insensitive
..
arch-arm: Make the Tarmac parsed registers case insensitive
This will make parsing more robust, considering the tarmac
format changes between AA32 and AA64.
Change-Id: I0e4905d70e2e494104706a4c6c75b8169deaecf9
Signed-off-by: Giacomo Travaglini
Reviewed-by: Andreas Sandberg
---
M src/arch/arm/tracers/tarmac_parser.cc
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index ce2300e..42ee852 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -1037,7 +1037,7 @@
regRecord.values.clear();
trace >> buf;
strcpy(regRecord.repr, buf);
-if (buf[0] == 'r' && isdigit(buf[1])) {
+if (std::tolower(buf[0]) == 'r' && isdigit(buf[1])) {
// R register
regRecord.type = REG_R;
int base_index = atoi([1]);
@@ -1063,28 +1063,27 @@
else if (strncmp(pch, "hyp", 3) == 0)
regRecord.index = INTREG_HYP(base_index);
}
-// A64 register names are capitalized in AEM TARMAC, unlike A32
-} else if (buf[0] == 'X' && isdigit(buf[1])) {
+} else if (std::tolower(buf[0]) == 'x' && isdigit(buf[1])) {
// X register (A64)
regRecord.type = REG_X;
regRecord.index = atoi([1]);
-} else if (buf[0] == 's' && isdigit(buf[1])) {
+} else if (std::tolower(buf[0]) == 's' && isdigit(buf[1])) {
// S register
regRecord.type = REG_S;
regRecord.index = atoi([1]);
-} else if (buf[0] == 'd' && isdigit(buf[1])) {
+} else if (std::tolower(buf[0]) == 'd' && isdigit(buf[1])) {
// D register
regRecord.type = REG_D;
regRecord.index = atoi([1]);
-} else if (buf[0] == 'q' && isdigit(buf[1])) {
+} else if (std::tolower(buf[0]) == 'q' && isdigit(buf[1])) {
// Q register
regRecord.type = REG_Q;
regRecord.index = atoi([1]);
-} else if (buf[0] == 'z' && isdigit(buf[1])) {
+} else if (std::tolower(buf[0]) == 'z' && isdigit(buf[1])) {
// Z (SVE vector) register
regRecord.type = REG_Z;
regRecord.index = atoi([1]);
-} else if (buf[0] == 'p' && isdigit(buf[1])) {
+} else if (std::tolower(buf[0]) == 'p' && isdigit(buf[1])) {
// P (SVE predicate) register
regRecord.type = REG_P;
regRecord.index = atoi([1]);
--
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: default MIDR for Armv8 ISA processors
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/22846 )
Change subject: arch-arm: default MIDR for Armv8 ISA processors
..
arch-arm: default MIDR for Armv8 ISA processors
Software such as Trusted Firmware-A checks the MIDR register
to identify which core model is present in the platform.
The previous default value referred to a Cortex-A15 Armv7-A
processor, however when AArch64 is enabled, an Armv8 processor
is expected.
This patch assigns the Cortex-A57 MIDR if AArch64 is enabled.
Change-Id: Id1677a77d2f04843423f7b013405445f3d253399
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/ArmISA.py
M src/arch/arm/isa.cc
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 3c1f7dd..7b71895 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -57,7 +57,11 @@
pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour
specification")
-midr = Param.UInt32(0x410fc0f0, "MIDR value")
+# If no MIDR value is provided, 0x0 is treated by gem5 as follows:
+# When 'highest_el_is_64' (AArch64 support) is:
+# True -> Cortex-A57 TRM r0p0 MIDR is used
+# False -> Cortex-A15 TRM r0p0 MIDR is used
+midr = Param.UInt32(0x0, "MIDR value")
# See section B4.1.89 - B4.1.92 of the ARM ARM
# VMSAv7 support
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 712b430..5433d6a 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -319,9 +319,20 @@
ISA::initID32(const ArmISAParams *p)
{
// Initialize configurable default values
-miscRegs[MISCREG_MIDR] = p->midr;
-miscRegs[MISCREG_MIDR_EL1] = p->midr;
-miscRegs[MISCREG_VPIDR] = p->midr;
+
+uint32_t midr;
+if (p->midr != 0x0)
+midr = p->midr;
+else if (highestELIs64)
+// Cortex-A57 TRM r0p0 MIDR
+midr = 0x410fd070;
+else
+// Cortex-A15 TRM r0p0 MIDR
+midr = 0x410fc0f0;
+
+miscRegs[MISCREG_MIDR] = midr;
+miscRegs[MISCREG_MIDR_EL1] = midr;
+miscRegs[MISCREG_VPIDR] = midr;
miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22846
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id1677a77d2f04843423f7b013405445f3d253399
Gerrit-Change-Number: 22846
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/22844 )
Change subject: mem-cache: Initialize all members of
`QueuedPrefetcher::DeferredPacket`.
..
mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.
Members `tc` and `ongoingTranslation` were uninitialized in the constructor
for
`QueuedPrefetcher::DeferredPacket`. If `ongoingTranslation` is not
initialized to
`false` by default, some translation requests from queued prefetchers are
not
properly handled and executions are nondeterministic.
Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794
Signed-off-by: Isaac Sánchez Barrera
---
M src/mem/cache/prefetch/queued.hh
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mem/cache/prefetch/queued.hh
b/src/mem/cache/prefetch/queued.hh
index ae4c5e4..adcd255 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -80,7 +80,8 @@
*/
DeferredPacket(QueuedPrefetcher *o, PrefetchInfo const , Tick
t,
int32_t prio) : owner(o), pfInfo(pfi), tick(t), pkt(nullptr),
-priority(prio), translationRequest() {
+priority(prio), translationRequest(), tc(nullptr),
+ongoingTranslation(false) {
}
bool operator>(const DeferredPacket& that) const
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22844
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794
Gerrit-Change-Number: 22844
Gerrit-PatchSet: 1
Gerrit-Owner: Isaac Sánchez Barrera
Gerrit-MessageType: newchange
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[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: FAILED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: FAILED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: FAILED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: FAILED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: FAILED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: FAILED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: FAILED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: FAILED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: CHANGED! *
Re: [gem5-dev] ARM semihosting, KVM, fast models, pseudo instructions, and system calls
Hi Gabe, Yes, as I was mentioning in https://gem5-review.googlesource.com/c/public/gem5/+/22118/5, if fast models implements arm watchpoints (by writing some self hosted debug registers, and not reying on custom made hooks after the PA is evaluated), those trap on VA matches. I would personally love to see m5 pseudo instructions being implemented with arm semishosting, not only for the FastModel use case. From a m5 pow seems like you would just need to change the macro in util/m5/m5op_arm_A64.S (of course you would have to add the implementation in the semihosting files; how does this work with fast models?) From: Gabe Black Sent: 15 November 2019 01:46 To: Giacomo Travaglini Cc: gem5 Developer List Subject: Re: [gem5-dev] ARM semihosting, KVM, fast models, pseudo instructions, and system calls FYI I base that not on anything in the documentation (it's never mentioned), but the fact that if I pick an address space that's physical, I get a vague "that didn't work" error from the fast models. Gabe On Thu, Nov 14, 2019 at 5:45 PM Gabe Black mailto:gabebl...@google.com>> wrote: Arg. Unfortunately it looks like you can only set watchpoints based on virtual addresses, not physical addresses. I may still have to go the semihosting hook route, and that means yet another flavor of m5 binary. I think something I'm going to try to tackle is coming up with a way to detect what mechanism to use from within the simulation, which is actually pretty tricky since it may change across checkpoints, CPU switches, etc. Perhaps some sort of coprocessor register or something? It will almost certainly need to be ISA specific. Gabe On Thu, Nov 14, 2019 at 1:38 AM Giacomo Travaglini mailto:giacomo.travagl...@arm.com>> wrote: Hi Gabe, It's good that you've found a solution. Just so you know, semihosting is already implemented in gem5-arm, so it would be easy to extend it in order to support pseudo instructions. Giacomo From: gem5-dev mailto:gem5-dev-boun...@gem5.org>> on behalf of Gabe Black mailto:gabebl...@google.com>> Sent: 14 November 2019 04:55 To: gem5 Developer List mailto:gem5-dev@gem5.org>> Subject: Re: [gem5-dev] ARM semihosting, KVM, fast models, pseudo instructions, and system calls Thinking about this more, it occurs to me it should be possible to set a watchpoint through IRIS which watches for accesses to the m5 device region. That may help solve this issue. Gabe On Wed, Nov 13, 2019 at 8:12 PM Gabe Black mailto:gabebl...@google.com>> wrote: > Hi folks. I'm looking for a way to enable the m5 utility/pseudo > instructions with fast model CPUs, and it's a little more complicated than > I'd initially assumed. > > I knew there was a memory mapped mechanism to support the pseudo > instructions, and that that was added to enable those instructions in KVM > mode. That is done using the finalizePhysical method on the TLBs which > detects accesses within certain ranges, and then redirects them to memory > mapped IPRs (an Alpha-ism) which handle the pseudo instruction. > > The problem with this approach and fast models is that, for starters, the > port to memory comes out of the fast model already collected from all the > cores that make up a cluster. It isn't possible as far as I can tell to > determine which core (and hence which context) a given request came from to > plumb up the "IPR" access correctly. > > Then beyond that, the accesses come out an AMBA flavor of TLM (the systemc > communication mechanism), and those have to be translate first to regular > TLM, and then to gem5's protocol using separate bridge objects. There isn't > anywhere to insert a call to the finalizePhysical call or equivalent to > intercept requests to the psuedo instruction device. > > One possible solution would be to use a mechanism called semihosting which > is supported by the fast models. Basically, using the SVC instruction with > a magic number (SVC is usually used for system calls) will trap into the > simulation mechanism. The value in R0 is supposed to say what service you > want (read from a file, write to stdout, etc), and then additional > parameters are in a blob pointed to by r1. The IRIS API, a debug API we're > using to implement ThreadContexts for the fast models, has an interface to > trap semihosting events, so it should be possible to run semihosting > instructions, capture them with the IRIS interface, and use that (which > knows what ThreadContext is relevant) to implement a call into the pseudo > instructions. > > This *should* work for fast model CPUs, and it shouldn't be difficult to > add into the native gem5 CPUs where we control what all the instructions > do. KVM, on the other hand, is a bit trickier. I've been digging around in > the KVM and QEMU source, and while QEMU says it supports semihosting, I > don't see anything that makes it look like it supports semihosting *and* > KVM at the same time. That may work
