[gem5-dev] Change in gem5/gem5[develop]: cpu: Don't assert on branch target addresses
Hsuan Hsu has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28347 )
Change subject: cpu: Don't assert on branch target addresses
..
cpu: Don't assert on branch target addresses
We should assume a branch target can be any address.
JIRA: https://gem5.atlassian.net/browse/GEM5-483
Change-Id: I6f6da1f9260d6e8978536967dc7fcf1808965db2
Signed-off-by: Hsuan Hsu
Signed-off-by: Howard Wang
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28347
Reviewed-by: Trivikram Reddy
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/pred/ltage.cc
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/tage.cc
M src/cpu/pred/tage_sc_l.cc
5 files changed, 0 insertions(+), 9 deletions(-)
Approvals:
Trivikram Reddy: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/pred/ltage.cc b/src/cpu/pred/ltage.cc
index a2cc56a..68a6db7 100644
--- a/src/cpu/pred/ltage.cc
+++ b/src/cpu/pred/ltage.cc
@@ -95,8 +95,6 @@
LTageBranchInfo* bi = static_cast(bp_history);
-assert(corrTarget != MaxAddr);
-
if (squashed) {
if (tage->isSpeculativeUpdateEnabled()) {
// This restores the global history, then update it
diff --git a/src/cpu/pred/multiperspective_perceptron.cc
b/src/cpu/pred/multiperspective_perceptron.cc
index d081b49..6582197 100644
--- a/src/cpu/pred/multiperspective_perceptron.cc
+++ b/src/cpu/pred/multiperspective_perceptron.cc
@@ -613,7 +613,6 @@
{
assert(bp_history);
MPPBranchInfo *bi = static_cast(bp_history);
-assert(corrTarget != MaxAddr);
if (squashed) {
//delete bi;
return;
diff --git a/src/cpu/pred/multiperspective_perceptron_tage.cc
b/src/cpu/pred/multiperspective_perceptron_tage.cc
index 3ef5f4f..a54f37c 100644
--- a/src/cpu/pred/multiperspective_perceptron_tage.cc
+++ b/src/cpu/pred/multiperspective_perceptron_tage.cc
@@ -605,8 +605,6 @@
assert(bp_history);
MPPTAGEBranchInfo *bi = static_cast(bp_history);
-assert(corrTarget != MaxAddr);
-
if (squashed) {
if (tage->isSpeculativeUpdateEnabled()) {
// This restores the global history, then update it
diff --git a/src/cpu/pred/tage.cc b/src/cpu/pred/tage.cc
index 7906532..d7c50f0 100644
--- a/src/cpu/pred/tage.cc
+++ b/src/cpu/pred/tage.cc
@@ -58,8 +58,6 @@
TageBranchInfo *bi = static_cast(bp_history);
TAGEBase::BranchInfo *tage_bi = bi->tageBranchInfo;
-assert(corrTarget != MaxAddr);
-
if (squashed) {
// This restores the global history, then update it
// and recomputes the folded histories.
diff --git a/src/cpu/pred/tage_sc_l.cc b/src/cpu/pred/tage_sc_l.cc
index de7c2f2..cbd9a45 100644
--- a/src/cpu/pred/tage_sc_l.cc
+++ b/src/cpu/pred/tage_sc_l.cc
@@ -419,8 +419,6 @@
TAGE_SC_L_TAGE::BranchInfo* tage_bi =
static_cast(bi->tageBranchInfo);
-assert(corrTarget != MaxAddr);
-
if (squashed) {
if (tage->isSpeculativeUpdateEnabled()) {
// This restores the global history, then update it
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28347
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6f6da1f9260d6e8978536967dc7fcf1808965db2
Gerrit-Change-Number: 28347
Gerrit-PatchSet: 5
Gerrit-Owner: Hsuan Hsu
Gerrit-Reviewer: Hsuan Hsu
Gerrit-Reviewer: Jairo Balart
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Pau Cabre
Gerrit-Reviewer: Trivikram Reddy
Gerrit-Reviewer: kokoro
Gerrit-CC: Ciro Santilli
Gerrit-CC: Giacomo Travaglini
Gerrit-CC: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Added RELEASE-NOTES.md
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/27807 ) Change subject: misc: Added RELEASE-NOTES.md .. misc: Added RELEASE-NOTES.md These release notes will enable users to keep track of the main changes between gem5 versions. The RELEASE-NOTES.md should also notify the user of any API changes they should be aware of when using this release of gem5. Notes on major changes should be apended to the end of the list as they are added to the repo. Change-Id: If75748306a8086b2abbe2f912dbb2ec9f1a6895f Issue-on: https://gem5.atlassian.net/browse/GEM5-439 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27807 Reviewed-by: Bobby R. Bruce Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- A RELEASE-NOTES.md 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md new file mode 100644 index 000..1a679dd --- /dev/null +++ b/RELEASE-NOTES.md @@ -0,0 +1,10 @@ +# Version 20.0.0.0 + +* Compiling and running gem5 with Python 3 is now fully supported. +* Compiling and running gem5 with GCC 8 and 9 is now supported. +* Scons-based tests have been migrated to the testlib framework. Please consult TESTING.md for more information on how these may be run. +* Support for the ALPHA ISA has been dropped. +* Memory SimObjects can now be initialized using an image file using the image_file parameter. +* The m5 utility has been revamped with a new build system based on scons, tests, and updated and more consistent feature support. +* Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules. +* Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27807 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If75748306a8086b2abbe2f912dbb2ec9f1a6895f Gerrit-Change-Number: 27807 Gerrit-PatchSet: 6 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com> Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] How to prefetch some specified address of store instruction in MinorCPU?
Hello all, I am implementing a data prefetcher that only prefetches the address of some store instructions. My application scenario is that we know which store will reside in the store buffer for a long while. Thus, it is beneficial to perform data prefetching over such sorts of stores. I've checked the existing prefetchers which are used together with cache and configured by python options. Somehow, it is not my goal. Is there someone who could help me out? Thanks, Jianping. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: GCN3 and VIPER integration
Hello Tuan Ta,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28413
to review the following change.
Change subject: mem-ruby: GCN3 and VIPER integration
..
mem-ruby: GCN3 and VIPER integration
This patch modifies the Coalescer and VIPER protocol to support memory
synchronization requests and write-completion responses that are
required by upcoming GCN3 implementation.
VIPER protocol is simplified to be a solely write-through protocol.
Change-Id: Icc3a5beda8550f55f3fb673216056f79e093e25f
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/VIPERCoalescer.cc
M src/mem/ruby/system/VIPERCoalescer.hh
11 files changed, 320 insertions(+), 466 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index f8da4ab..5f05a60 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -392,14 +392,15 @@
action(w_sendResponseWBAck, "w", desc="send WB Ack") {
peek(responseFromNB_in, ResponseMsg) {
-enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
- out_msg.addr := address;
- out_msg.Type := CoherenceResponseType:TDSysWBAck;
- out_msg.Destination.clear();
- out_msg.Destination.add(in_msg.WTRequestor);
- out_msg.Sender := machineID;
- out_msg.MessageSize := MessageSizeType:Writeback_Control;
-}
+ enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
+out_msg.addr := address;
+out_msg.Type := CoherenceResponseType:TDSysWBAck;
+out_msg.Destination.clear();
+out_msg.Destination.add(in_msg.WTRequestor);
+out_msg.Sender := machineID;
+out_msg.MessageSize := MessageSizeType:Writeback_Control;
+out_msg.instSeqNum := in_msg.instSeqNum;
+ }
}
}
@@ -412,6 +413,7 @@
out_msg.Destination.add(in_msg.Requestor);
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Control;
+out_msg.instSeqNum := in_msg.instSeqNum;
}
}
}
@@ -486,6 +488,7 @@
out_msg.Dirty := true;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.writeMask.orMask(in_msg.writeMask);
+out_msg.instSeqNum := in_msg.instSeqNum;
}
}
}
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 4047dc6..3f61791 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -56,9 +56,6 @@
state_declaration(State, desc="TCP Cache States", default="TCP_State_I")
{
I, AccessPermission:Invalid, desc="Invalid";
V, AccessPermission:Read_Only, desc="Valid";
-W, AccessPermission:Read_Write, desc="Written";
-M, AccessPermission:Read_Write, desc="Written and Valid";
-L, AccessPermission:Read_Write, desc="Local access is modifable";
A, AccessPermission:Invalid, desc="Waiting on Atomic";
}
@@ -67,7 +64,6 @@
Load, desc="Load";
Store, desc="Store to L1 (L1 is dirty)";
StoreThrough, desc="Store directly to L2(L1 is clean)";
-StoreLocal, desc="Store to L1 but L1 is clean";
Atomic, desc="Atomic";
Flush, desc="Flush if dirty(wbL1 for Store Release)";
Evict, desc="Evict if clean(invL1 for Load Acquire)";
@@ -264,7 +260,7 @@
if (in_msg.Type == CoherenceResponseType:TDSysResp) {
// disable L1 cache
if (disableL1) {
- trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
+ trigger(Event:Bypass, in_msg.addr, cache_entry, tbe);
} else {
if (is_valid(cache_entry) || L1cache.cacheAvail(in_msg.addr)) {
trigger(Event:TCC_Ack, in_msg.addr, cache_entry, tbe);
@@ -291,18 +287,16 @@
DPRINTF(RubySlicc, "%s\n", in_msg);
if (in_msg.Type == RubyRequestType:LD) {
trigger(Event:Load, in_msg.LineAddress, cache_entry, tbe);
-} else if (in_msg.Type == RubyRequestType:ATOMIC) {
+} else if (in_msg.Type == RubyRequestType:ATOMIC ||
+ in_msg.Type == RubyRequestType:ATOMIC_RETURN ||
+ in_msg.Type == RubyRequestType:ATOMIC_NO_RETURN) {
trigger(Event:Atomic, in_msg.LineAddress, cache_entry, tbe);
} else if (in_msg.Type == RubyRequestType:ST) {
if(disableL1) {
trigger(Event:StoreThrough, in_msg.LineAddress, cache_entry,
tbe);
} else {
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
Hello Tony Gutierrez,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28414
to review the following change.
Change subject: mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
..
mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
This change adds DMA support to the MOESI_AMD_Base-dir.sm,
which is needed to support ROCm apps/GCN3 ISA in the VIPER
ptl. The DMA controller is copied from the MOESI_hammer-dma.sm
with few modifications.
Change-Id: I0cb53abedb7817c88a57c66614e37d1f90603906
---
M src/mem/ruby/protocol/GPU_VIPER.slicc
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
A src/mem/ruby/protocol/MOESI_AMD_Base-dma.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
4 files changed, 499 insertions(+), 6 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER.slicc
b/src/mem/ruby/protocol/GPU_VIPER.slicc
index 45f7f34..0b37ce6 100644
--- a/src/mem/ruby/protocol/GPU_VIPER.slicc
+++ b/src/mem/ruby/protocol/GPU_VIPER.slicc
@@ -2,6 +2,7 @@
include "RubySlicc_interfaces.slicc";
include "MOESI_AMD_Base-msg.sm";
include "MOESI_AMD_Base-dir.sm";
+include "MOESI_AMD_Base-dma.sm";
include "MOESI_AMD_Base-CorePair.sm";
include "GPU_VIPER-TCP.sm";
include "GPU_VIPER-SQC.sm";
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index 6112ec2..e2c5ff5 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -44,6 +44,10 @@
bool useL3OnWT := "False";
Cycles to_memory_controller_latency := 1;
+ // DMA
+ MessageBuffer * requestFromDMA, network="From", virtual_network="1",
vnet_type="request";
+ MessageBuffer * responseToDMA, network="To", virtual_network="3",
vnet_type="request";
+
// From the Cores
MessageBuffer * requestFromCores, network="From", virtual_network="0",
vnet_type="request";
MessageBuffer * responseFromCores, network="From", virtual_network="2",
vnet_type="response";
@@ -63,13 +67,17 @@
// BL is Busy because it's possible for the data only to be in the
network
// in the WB, L3 has sent it and gone on with its business in possibly
I
// state.
+BDR_M, AccessPermission:Backing_Store, desc="DMA read, blocked
waiting for memory";
BS_M, AccessPermission:Backing_Store, desc="blocked
waiting for memory";
BM_M, AccessPermission:Backing_Store, desc="blocked
waiting for memory";
B_M, AccessPermission:Backing_Store, desc="blocked
waiting for memory";
BP, AccessPermission:Backing_Store, desc="blocked
waiting for probes, no need for memory";
+BDR_PM, AccessPermission:Backing_Store, desc="DMA read, blocked
waiting for probes and memory";
BS_PM, AccessPermission:Backing_Store,desc="blocked
waiting for probes and Memory";
BM_PM, AccessPermission:Backing_Store,desc="blocked
waiting for probes and Memory";
B_PM, AccessPermission:Backing_Store,desc="blocked
waiting for probes and Memory";
+BDW_P, AccessPermission:Backing_Store, desc="DMA write, blocked
waiting for probes, no need for memory";
+BDR_Pm, AccessPermission:Backing_Store, desc="DMA read, blocked
waiting for probes, already got memory";
BS_Pm, AccessPermission:Backing_Store,desc="blocked
waiting for probes, already got memory";
BM_Pm, AccessPermission:Backing_Store,desc="blocked
waiting for probes, already got memory";
B_Pm, AccessPermission:Backing_Store,desc="blocked
waiting for probes, already got memory";
@@ -107,6 +115,10 @@
UnblockWriteThrough,desc="Unblock because of writethrough request
finishing";
StaleVicDirty,desc="Core invalidated before VicDirty
processed";
+
+// DMA
+DmaRead,desc="DMA read";
+DmaWrite, desc="DMA write";
}
enumeration(RequestType, desc="To communicate stats from transitions to
recordStats") {
@@ -148,6 +160,7 @@
bool L3Hit, default="false", desc="Was this an L3 hit?";
uint64_t probe_id,desc="probe id for lifetime profiling";
WriteMask writeMask,desc="outstanding write through mask";
+int Len,desc="Length of memory request for DMA";
}
structure(TBETable, external="yes") {
@@ -266,6 +279,8 @@
}
// ** OUT_PORTS **
+ out_port(dmaResponseQueue_out, DMAResponseMsg, responseToDMA);
+
out_port(probeNetwork_out, NBProbeRequestMsg, probeToCore);
out_port(responseNetwork_out, ResponseMsg, responseToCore);
@@ -274,6 +289,23 @@
// ** IN_PORTS **
+ // DMA Ports
+ in_port(dmaRequestQueue_in, DMARequestMsg, requestFromDMA, rank=6) {
+if (dmaRequestQueue_in.isReady(clockEdge())) {
+ peek(dmaRequestQueue_in, DMARequestMsg) {
+TBE tbe :=
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Getting rid of HSA segment and scope
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28411 )
Change subject: mem-ruby: Getting rid of HSA segment and scope
..
mem-ruby: Getting rid of HSA segment and scope
This is protocol and sequencer parts of the bigger GCN3 change.
Author: Tony Gutierrez
Change-Id: I803b4cbb46eeab8462d9af80dd003940a9968b60
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/GPUCoalescer.py
M src/mem/ruby/system/VIPERCoalescer.py
8 files changed, 285 insertions(+), 399 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 9dffe0f..4047dc6 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -298,9 +298,7 @@
trigger(Event:StoreThrough, in_msg.LineAddress, cache_entry,
tbe);
} else {
if (is_valid(cache_entry) ||
L1cache.cacheAvail(in_msg.LineAddress)) {
- if (in_msg.segment == HSASegment:SPILL) {
-trigger(Event:StoreLocal, in_msg.LineAddress, cache_entry,
tbe);
- } else if (WB) {
+ if (WB) {
trigger(Event:Store, in_msg.LineAddress, cache_entry, tbe);
} else {
trigger(Event:StoreThrough, in_msg.LineAddress,
cache_entry, tbe);
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
index a66939c..6d04c76 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
@@ -137,7 +137,6 @@
CoherenceRequestType OriginalType, default="CoherenceRequestType_NA",
desc="Type of request from core fwded through region buffer";
WriteMask writeMask, desc="Write Through Data";
MachineID WTRequestor,desc="Node who initiated the write
through";
- HSAScope scope, default="HSAScope_SYSTEM",
desc="Request Scope";
int wfid, default="0", desc="wavefront id";
bool NoWriteConflict, default="true", desc="write collided
with CAB entry";
int ProgramCounter, desc="PC that accesses to this block";
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 8e17f98..fe2c83b 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -91,26 +91,6 @@
NotPresent, desc="block is NotPresent";
Busy, desc="block is in a transient state, currently invalid";
}
-//HSA scopes
-enumeration(HSAScope, desc="...", default="HSAScope_UNSPECIFIED") {
- UNSPECIFIED, desc="Unspecified scope";
- NOSCOPE, desc="Explictly unscoped";
- WAVEFRONT, desc="Wavefront scope";
- WORKGROUP, desc="Workgroup scope";
- DEVICE, desc="Device scope";
- SYSTEM, desc="System scope";
-}
-
-// HSA segment types
-enumeration(HSASegment, desc="...", default="HSASegment_GLOBAL") {
- GLOBAL, desc="Global segment";
- GROUP,desc="Group segment";
- PRIVATE, desc="Private segment";
- KERNARG, desc="Kernarg segment";
- READONLY, desc="Readonly segment";
- SPILL,desc="Spill segment";
- ARG, desc="Arg segment";
-}
// TesterStatus
enumeration(TesterStatus, desc="...") {
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index fd76289..95a093a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -169,8 +169,6 @@
WriteMask writeMask, desc="Writethrough mask";
DataBlock WTData, desc="Writethrough data block";
int wfid, desc="Writethrough wavefront";
- HSAScope scope,desc="HSA scope";
- HSASegment segment,desc="HSA segment";
PacketPtr pkt, desc="Packet associated with this request";
}
diff --git a/src/mem/ruby/system/GPUCoalescer.cc
b/src/mem/ruby/system/GPUCoalescer.cc
index 4cea30f..19b50ea 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -63,58 +63,6 @@
using namespace std;
-GPUCoalescer *
-RubyGPUCoalescerParams::create()
-{
-return new GPUCoalescer(this);
-}
-
-HSAScope
-reqScopeToHSAScope(const RequestPtr )
-{
-HSAScope accessScope = HSAScope_UNSPECIFIED;
-if (req->isScoped()) {
-if (req->isWavefrontScope()) {
-accessScope = HSAScope_WAVEFRONT;
-} else if (req->isWorkgroupScope()) {
-accessScope = HSAScope_WORKGROUP;
-} else if (req->isDeviceScope()) {
-accessScope = HSAScope_DEVICE;
-} else if (req->isSystemScope()) {
-
[gem5-dev] Change in gem5/gem5[develop]: gpu-compute, configs: Add GCN3 ISA support to GPU model
Hello Tony Gutierrez, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28412 to review the following change. Change subject: gpu-compute, configs: Add GCN3 ISA support to GPU model .. gpu-compute, configs: Add GCN3 ISA support to GPU model Change-Id: I0ead5bcab6fa014e37294c22243831e08dbc5656 --- M configs/common/GPUTLBConfig.py M src/gpu-compute/GPU.py M src/gpu-compute/GPUStaticInstFlags.py M src/gpu-compute/SConscript M src/gpu-compute/compute_unit.cc M src/gpu-compute/compute_unit.hh M src/gpu-compute/dispatcher.cc M src/gpu-compute/dispatcher.hh M src/gpu-compute/exec_stage.cc M src/gpu-compute/exec_stage.hh M src/gpu-compute/fetch_stage.cc M src/gpu-compute/fetch_stage.hh M src/gpu-compute/fetch_unit.cc M src/gpu-compute/fetch_unit.hh M src/gpu-compute/global_memory_pipeline.cc M src/gpu-compute/global_memory_pipeline.hh A src/gpu-compute/gpu_command_processor.cc A src/gpu-compute/gpu_command_processor.hh A src/gpu-compute/gpu_compute_driver.cc A src/gpu-compute/gpu_compute_driver.hh M src/gpu-compute/gpu_dyn_inst.cc M src/gpu-compute/gpu_dyn_inst.hh M src/gpu-compute/gpu_exec_context.cc M src/gpu-compute/gpu_exec_context.hh M src/gpu-compute/gpu_static_inst.cc M src/gpu-compute/gpu_static_inst.hh M src/gpu-compute/gpu_tlb.cc M src/gpu-compute/gpu_tlb.hh A src/gpu-compute/hsa_queue_entry.hh A src/gpu-compute/kernel_code.hh M src/gpu-compute/lds_state.cc M src/gpu-compute/lds_state.hh M src/gpu-compute/local_memory_pipeline.cc M src/gpu-compute/local_memory_pipeline.hh M src/gpu-compute/misc.hh M src/gpu-compute/pool_manager.cc M src/gpu-compute/pool_manager.hh A src/gpu-compute/register_file.cc A src/gpu-compute/register_file.hh A src/gpu-compute/register_manager.cc A src/gpu-compute/register_manager.hh A src/gpu-compute/register_manager_policy.hh M src/gpu-compute/rr_scheduling_policy.hh A src/gpu-compute/scalar_memory_pipeline.cc A src/gpu-compute/scalar_memory_pipeline.hh A src/gpu-compute/scalar_register_file.cc A src/gpu-compute/scalar_register_file.hh M src/gpu-compute/schedule_stage.cc M src/gpu-compute/schedule_stage.hh M src/gpu-compute/scoreboard_check_stage.cc M src/gpu-compute/scoreboard_check_stage.hh M src/gpu-compute/shader.cc M src/gpu-compute/shader.hh M src/gpu-compute/simple_pool_manager.cc M src/gpu-compute/simple_pool_manager.hh A src/gpu-compute/static_register_manager_policy.cc A src/gpu-compute/static_register_manager_policy.hh M src/gpu-compute/tlb_coalescer.cc M src/gpu-compute/tlb_coalescer.hh M src/gpu-compute/vector_register_file.cc M src/gpu-compute/vector_register_file.hh M src/gpu-compute/wavefront.cc M src/gpu-compute/wavefront.hh 63 files changed, 9,892 insertions(+), 3,278 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28412 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0ead5bcab6fa014e37294c22243831e08dbc5656 Gerrit-Change-Number: 28412 Gerrit-PatchSet: 1 Gerrit-Owner: Pouya Fotouhi Gerrit-Reviewer: Tony Gutierrez Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python: Fix compareVersions for python 3.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28309 )
Change subject: python: Fix compareVersions for python 3.
..
python: Fix compareVersions for python 3.
When the internal utility function make_version_list sees a string, it
tries to convert it into a list using the map() function. In python 3,
that returns an iterator. The following call to zip() will consume those
iterators, and then the following calls to len() will die because they
don't work on map iterators.
This is only a problem if all the common components of the version lists
are equal, and the comparison needs to then check if one of the lists
was equal to the other but with more components. When versions are
equal, for instance when compiling with the oldest supported version of
gcc (4.8.0) this error surfaces and breaks our scons build.
A simple fix is to just wrap the call to map() with list() to convert
the iterator to a flat list, making the other logic work as before.
Change-Id: If9dc5cd7fff70c21229ac3dd9a017edeccd26148
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28309
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/python/m5/util/__init__.py
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py
index fd1ea91..98a7a08 100644
--- a/src/python/m5/util/__init__.py
+++ b/src/python/m5/util/__init__.py
@@ -125,7 +125,8 @@
if isinstance(v, (list,tuple)):
return v
elif isinstance(v, string_types):
-return map(lambda x: int(re.match('\d+', x).group()),
v.split('.'))
+return list(map(lambda x: int(re.match('\d+', x).group()),
+v.split('.')))
else:
raise TypeError()
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28309
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If9dc5cd7fff70c21229ac3dd9a017edeccd26148
Gerrit-Change-Number: 28309
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-CC: Earl Ou
Gerrit-CC: Yu-hsin Wang
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix priority of multi compressor
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28367 )
Change subject: mem-cache: Fix priority of multi compressor
..
mem-cache: Fix priority of multi compressor
The priority queue comparator orders such that false gives the
entry a higher priority. Therefore, if it is desired to make
the entry with lowest decompression latency have higher priority,
the comparison must be inverted.
Can be tested with:
MultiCompressor(compressors=[
PerfectCompressor(decompression_latency=1),
PerfectCompressor(decompression_latency=2)])
Where it is expected that compressor0 (the one with decomp lat
of 1) is always chosen.
Change-Id: I44acbf5f51c6e47efdd2a16fba9596935cf2eb69
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28367
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/cache/compressors/multi.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/compressors/multi.cc
b/src/mem/cache/compressors/multi.cc
index 599e059..fe22f5e 100644
--- a/src/mem/cache/compressors/multi.cc
+++ b/src/mem/cache/compressors/multi.cc
@@ -103,7 +103,7 @@
if (lhs_cf == rhs_cf) {
// When they have similar compressed sizes, give the one
// with fastest decompression privilege
-return lhs->decompLat < rhs->decompLat;
+return lhs->decompLat > rhs->decompLat;
}
return lhs_cf < rhs_cf;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28367
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I44acbf5f51c6e47efdd2a16fba9596935cf2eb69
Gerrit-Change-Number: 28367
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: update memory interfaces to support GPU ISA
Hello Tony Gutierrez, Tuan Ta,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28408
to review the following change.
Change subject: mem-ruby: update memory interfaces to support GPU ISA
..
mem-ruby: update memory interfaces to support GPU ISA
This patch deprecates HSA-based memory request types and adds new
types that can be used by real ISA instructions.
Change-Id: Ie107a69d8a35e9de0853f1407392ad01a8b3e930
---
M src/mem/packet.hh
M src/mem/request.hh
M src/mem/ruby/slicc_interface/RubyRequest.hh
3 files changed, 40 insertions(+), 130 deletions(-)
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index d390c00..42d286a 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -110,6 +110,8 @@
SwapResp,
// MessageReq and MessageResp are deprecated.
MemFenceReq = SwapResp + 3,
+MemSyncReq, // memory synchronization request (e.g., cache
invalidate)
+MemSyncResp, // memory synchronization response
MemFenceResp,
CleanSharedReq,
CleanSharedResp,
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 01252bf..2b00dce 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -110,7 +110,7 @@
* STRICT_ORDER flag should be set if such reordering is
* undesirable.
*/
-UNCACHEABLE= 0x0400,
+UNCACHEABLE = 0x0400,
/**
* The request is required to be strictly ordered by CPU
* models and is non-speculative.
@@ -216,35 +216,30 @@
};
/** @} */
-typedef uint32_t MemSpaceConfigFlagsType;
-typedef ::Flags MemSpaceConfigFlags;
+typedef uint64_t CacheCoherenceFlagsType;
+typedef ::Flags CacheCoherenceFlags;
-enum : MemSpaceConfigFlagsType {
-/** Has a synchronization scope been set? */
-SCOPE_VALID= 0x0001,
-/** Access has Wavefront scope visibility */
-WAVEFRONT_SCOPE= 0x0002,
-/** Access has Workgroup scope visibility */
-WORKGROUP_SCOPE= 0x0004,
-/** Access has Device (e.g., GPU) scope visibility */
-DEVICE_SCOPE = 0x0008,
-/** Access has System (e.g., CPU + GPU) scope visibility */
-SYSTEM_SCOPE = 0x0010,
-
-/** Global Segment */
-GLOBAL_SEGMENT = 0x0020,
-/** Group Segment */
-GROUP_SEGMENT = 0x0040,
-/** Private Segment */
-PRIVATE_SEGMENT= 0x0080,
-/** Kergarg Segment */
-KERNARG_SEGMENT= 0x0100,
-/** Readonly Segment */
-READONLY_SEGMENT = 0x0200,
-/** Spill Segment */
-SPILL_SEGMENT = 0x0400,
-/** Arg Segment */
-ARG_SEGMENT= 0x0800,
+/**
+ * These bits are used to set the coherence policy
+ * for the GPU and are encoded in the GCN3 instructions.
+ * See the AMD GCN3 ISA Architecture Manual for more
+ * details.
+ *
+ * SLC: System Level Coherent. Accesses are forced to miss in
+ * the L2 cache and are coherent with system memory.
+ *
+ * GLC: Globally Coherent. Controls how reads and writes are
+ * handled by the L1 cache. Global here referes to the
+ * data being visible globally on the GPU (i.e., visible
+ * to all WGs).
+ *
+ * For atomics, the GLC bit is used to distinguish between
+ * between atomic return/no-return operations.
+ */
+enum : CacheCoherenceFlagsType {
+/** user-policy flags */
+SLC_BIT = 0x0080,
+GLC_BIT = 0x0100,
};
using LocalAccessor =
@@ -305,8 +300,8 @@
/** Flag structure for the request. */
Flags _flags;
-/** Memory space configuraiton flag structure for the request. */
-MemSpaceConfigFlags _memSpaceConfigFlags;
+/** Flags that control how downstream cache system maintains
coherence*/
+CacheCoherenceFlags _cacheCoherenceFlags;
/** Private flags for field validity checking. */
PrivateFlags privateFlags;
@@ -629,10 +624,11 @@
}
void
-setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
+setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
{
+// TODO: do mem_sync_op requests have valid paddr/vaddr?
assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
-_memSpaceConfigFlags.set(extraFlags);
+_cacheCoherenceFlags.set(extraFlags);
}
/** Accessor function for vaddr.*/
@@ -840,82 +836,10 @@
* Accessor functions for the memory space configuration flags and
used by
* GPU ISAs such as the Heterogeneous System Architecture (HSA). Note
that
* these are for testing only; setting extraFlags should be done via
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add codes for pure virtual functions for compilation
Hello Tony Gutierrez,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28409
to review the following change.
Change subject: mem-ruby: Add codes for pure virtual functions for
compilation
..
mem-ruby: Add codes for pure virtual functions for compilation
Change-Id: Ic34f9ccf10ec28d68eed236dc6246e2ae2ef1b89
---
M src/mem/ruby/system/VIPERCoalescer.cc
M src/mem/ruby/system/VIPERCoalescer.hh
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/system/VIPERCoalescer.cc
b/src/mem/ruby/system/VIPERCoalescer.cc
index feb13c5..c00b4f5 100644
--- a/src/mem/ruby/system/VIPERCoalescer.cc
+++ b/src/mem/ruby/system/VIPERCoalescer.cc
@@ -76,6 +76,16 @@
{
}
+void
+VIPERCoalescer::issueRequest(CoalescedRequest* crequest)
+{
+}
+
+void
+VIPERCoalescer::issueMemSyncRequest(PacketPtr pkt)
+{
+}
+
// Analyzes the packet to see if this request can be coalesced.
// If request can be coalesced, this request is added to the reqCoalescer
table
// and makeRequest returns RequestStatus_Issued;
diff --git a/src/mem/ruby/system/VIPERCoalescer.hh
b/src/mem/ruby/system/VIPERCoalescer.hh
index 2b6e86e..48aa18c 100644
--- a/src/mem/ruby/system/VIPERCoalescer.hh
+++ b/src/mem/ruby/system/VIPERCoalescer.hh
@@ -57,6 +57,9 @@
typedef VIPERCoalescerParams Params;
VIPERCoalescer(const Params *);
~VIPERCoalescer();
+
+void issueMemSyncRequest(PacketPtr pkt);
+void issueRequest(CoalescedRequest* crequest);
void wbCallback(Addr address);
void invCallback(Addr address);
RequestStatus makeRequest(PacketPtr pkt);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28409
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic34f9ccf10ec28d68eed236dc6246e2ae2ef1b89
Gerrit-Change-Number: 28409
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez
Gerrit-Reviewer: Tony Gutierrez
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-hsail, gpu-compute: Remove HSAIL related files
Hello Tony Gutierrez, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28410 to review the following change. Change subject: arch-hsail, gpu-compute: Remove HSAIL related files .. arch-hsail, gpu-compute: Remove HSAIL related files Change-Id: Iefba0a38d62da7598bbfe3fe6ff46454d35144b1 --- M MAINTAINERS D build_opts/HSAIL_X86 D src/arch/hsail/Brig.h D src/arch/hsail/Brig_new.hpp D src/arch/hsail/SConscript D src/arch/hsail/SConsopts D src/arch/hsail/gen.py D src/arch/hsail/gpu_decoder.hh D src/arch/hsail/gpu_isa.hh D src/arch/hsail/gpu_types.hh D src/arch/hsail/insts/branch.cc D src/arch/hsail/insts/branch.hh D src/arch/hsail/insts/decl.hh D src/arch/hsail/insts/gpu_static_inst.cc D src/arch/hsail/insts/gpu_static_inst.hh D src/arch/hsail/insts/main.cc D src/arch/hsail/insts/mem.cc D src/arch/hsail/insts/mem.hh D src/arch/hsail/insts/mem_impl.hh D src/arch/hsail/insts/pseudo_inst.cc D src/arch/hsail/operand.cc D src/arch/hsail/operand.hh D src/gpu-compute/brig_object.cc D src/gpu-compute/brig_object.hh D src/gpu-compute/cl_driver.cc D src/gpu-compute/cl_driver.hh D src/gpu-compute/cl_event.hh D src/gpu-compute/condition_register_state.cc D src/gpu-compute/condition_register_state.hh D src/gpu-compute/hsa_code.hh D src/gpu-compute/hsa_kernel_info.hh D src/gpu-compute/hsa_object.cc D src/gpu-compute/hsa_object.hh D src/gpu-compute/hsail_code.cc D src/gpu-compute/hsail_code.hh D src/gpu-compute/kernel_cfg.cc D src/gpu-compute/kernel_cfg.hh D src/gpu-compute/ndrange.hh D src/gpu-compute/qstruct.hh D src/gpu-compute/vector_register_state.cc D src/gpu-compute/vector_register_state.hh 41 files changed, 0 insertions(+), 12,851 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28410 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iefba0a38d62da7598bbfe3fe6ff46454d35144b1 Gerrit-Change-Number: 28410 Gerrit-PatchSet: 1 Gerrit-Owner: Anthony Gutierrez Gerrit-Reviewer: Tony Gutierrez Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: Token port implementation
Anthony Gutierrez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27428 )
Change subject: mem: Token port implementation
..
mem: Token port implementation
Adds a TokenPort which uses tokens for flow control rather than the
standard retry mechanism in gem5. The port is intended to be used
for flow control where speculatively sending packets is not possible.
For example, GPU instructions require this to send memory requests
to the cache coalescer.
Change-Id: Id0d55ab65b7c773e97752b8514a780cdf7d88707
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27428
Reviewed-by: Anthony Gutierrez
Maintainer: Anthony Gutierrez
Tested-by: kokoro
---
M src/mem/SConscript
A src/mem/token_port.cc
A src/mem/token_port.hh
3 files changed, 348 insertions(+), 0 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 2eb64e0..b77dbb1 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -73,6 +73,7 @@
Source('simple_mem.cc')
Source('snoop_filter.cc')
Source('stack_dist_calc.cc')
+Source('token_port.cc')
Source('tport.cc')
Source('xbar.cc')
Source('hmc_controller.cc')
@@ -115,6 +116,7 @@
DebugFlag("DRAMSim2")
DebugFlag('HMCController')
DebugFlag('SerialLink')
+DebugFlag('TokenPort')
DebugFlag("MemChecker")
DebugFlag("MemCheckerMonitor")
diff --git a/src/mem/token_port.cc b/src/mem/token_port.cc
new file mode 100644
index 000..1a8439d
--- /dev/null
+++ b/src/mem/token_port.cc
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2016-2020 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
notice,
+ * this list of conditions and the following disclaimer in the
documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthew Poremba
+ */
+
+
+#include "mem/token_port.hh"
+
+#include "base/trace.hh"
+#include "debug/TokenPort.hh"
+
+void
+TokenMasterPort::bind(Port )
+{
+MasterPort::bind(peer);
+}
+
+void
+TokenMasterPort::recvTokens(int num_tokens)
+{
+panic_if(!tokenManager, "TokenManager not set for %s.\n", name());
+
+tokenManager->recvTokens(num_tokens);
+}
+
+bool
+TokenMasterPort::haveTokens(int num_tokens)
+{
+panic_if(!tokenManager, "TokenManager not set for %s.\n", name());
+
+return tokenManager->haveTokens(num_tokens);
+}
+
+void
+TokenMasterPort::acquireTokens(int num_tokens)
+{
+panic_if(!tokenManager, "TokenManager not set for %s.\n", name());
+
+tokenManager->acquireTokens(num_tokens);
+}
+
+void
+TokenMasterPort::setTokenManager(TokenManager *_tokenManager)
+{
+tokenManager = _tokenManager;
+}
+
+void
+TokenSlavePort::sendTokens(int num_tokens)
+{
+fatal_if(!tokenMasterPort, "Tried sendTokens to non-token master!\n");
+
+// Send tokens to a master
+tokenMasterPort->recvTokens(num_tokens);
+}
+
+void
+TokenSlavePort::bind(Port& peer)
+{
+// TokenSlavePort is allowed to bind to either TokenMasterPort or a
+// MasterPort as fallback. If the type is a MasterPort, tokenMasterPort
+// is set to nullptr to indicate tokens should not be exchanged.
+auto *token_master_port = dynamic_cast();
+auto *master_port = dynamic_cast();
+if (!token_master_port && !master_port) {
+fatal("Attempt to bind port %s to unsupported slave port %s.",
+ name(), peer.name());
+} else if (token_master_port) {
+//
[gem5-dev] Change in gem5/gem5[develop]: mem: Remove infinite queue between Ruby and memory
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28387 )
Change subject: mem: Remove infinite queue between Ruby and memory
..
mem: Remove infinite queue between Ruby and memory
AbstractController sends requests using a QueuedMasterPort which has an
implicit buffer which is unbounded. Remove this by using the tryTiming
interface to query if the memory controller has space available before
sending the memory request. If space is available the request is sent
normally. Otherwise, the request remains in the Ruby MessageBuffer and
the controller wakes periodically to check for space.
This adds tryTiming interface to all of the memory controllers. It is
also added to the NoncoherentXbar because Ruby may place a crossbar
between the AbstractController and memories if there are more memories
than directories.
Change-Id: I8c592af92a1a499a418f34cfee16dd69d84803ad
---
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/noncoherent_xbar.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
8 files changed, 70 insertions(+), 3 deletions(-)
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 0a8479e..cf608ec 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -261,6 +261,23 @@
}
}
+bool
+DRAMCtrl::tryTiming(PacketPtr pkt)
+{
+unsigned size = pkt->getSize();
+unsigned offset = pkt->getAddr() & (burstSize - 1);
+unsigned int dram_pkt_count = divCeil(offset + size, burstSize);
+
+assert(pkt->isRead() || pkt->isWrite());
+if (pkt->isRead() && readQueueFull(dram_pkt_count)) {
+return false;
+} else if (pkt->isWrite() && writeQueueFull(dram_pkt_count)) {
+return false;
+}
+
+return true;
+}
+
Tick
DRAMCtrl::recvAtomic(PacketPtr pkt)
{
@@ -2970,6 +2987,12 @@
return ranges;
}
+bool
+DRAMCtrl::MemoryPort::tryTiming(PacketPtr pkt)
+{
+return memory.tryTiming(pkt);
+}
+
void
DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
{
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 0fe78da..e156185 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -106,6 +106,8 @@
protected:
+bool tryTiming(PacketPtr pkt);
+
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
@@ -1258,6 +1260,7 @@
protected:
+bool tryTiming(PacketPtr pkt);
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr pkt);
diff --git a/src/mem/noncoherent_xbar.hh b/src/mem/noncoherent_xbar.hh
index 86658d0..26b7b57 100644
--- a/src/mem/noncoherent_xbar.hh
+++ b/src/mem/noncoherent_xbar.hh
@@ -128,6 +128,19 @@
{
return xbar.getAddrRanges();
}
+
+bool
+tryTiming(PacketPtr pkt)
+{
+AddrRange addr_range = RangeSize(pkt->getAddr(),
pkt->getSize());
+PortID master_port_id = xbar.findPort(addr_range);
+if (xbar.reqLayers[master_port_id]->layerBusy()) {
+return false;
+}
+
+// Forward the attempt to the master port
+return xbar.masterPorts[master_port_id]->tryTiming(pkt);
+}
};
/**
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 59611ae..b70745a 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -250,12 +250,16 @@
// to make more progress. Make sure it wakes up
scheduleEvent(Cycles(1));
recvTimingResp(pkt);
-} else {
+} else if (memoryPort.tryTiming(pkt)) {
mem_queue->dequeue(clockEdge());
-memoryPort.schedTimingReq(pkt, clockEdge());
+memoryPort.sendTimingReq(pkt);
// Since the queue was popped the controller may be able
// to make more progress. Make sure it wakes up
scheduleEvent(Cycles(1));
+} else {
+delete pkt;
+delete s;
+scheduleEvent(Cycles(1));
}
return true;
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 4161e87..1030a0e 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -66,6 +66,12 @@
}
}
+bool
+SimpleMemory::tryTiming(PacketPtr pkt)
+{
+return !isBusy;
+}
+
Tick
SimpleMemory::recvAtomic(PacketPtr pkt)
{
@@ -271,6 +277,12 @@
return ranges;
}
+bool
+SimpleMemory::MemoryPort::tryTiming(PacketPtr pkt)
+{
+return memory.tryTiming(pkt);
+}
+
Tick
SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
{
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 0bcb15c..3488d74 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -88,6 +88,7 @@
MemoryPort(const std::string& _name, SimpleMemory&
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Add files for arch gcn3 (GPU machine ISA)
Anthony Gutierrez has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28127 ) Change subject: arch-gcn3: Add files for arch gcn3 (GPU machine ISA) .. arch-gcn3: Add files for arch gcn3 (GPU machine ISA) Decoder: gpu_decoder.hh and decoder.cc: The decoder is defined in these files. The decoder is implemented as a lookup table of function pointers where each decode function will decode to a unique ISA instruction, or do some sub-decoding to infer the next decode function to call. The format for each OP encoding is defined in the header file. Registers: registers.[hh|cc] define the special registers and operand selector values, which are used to map operands to registers/special values. many convenience functions are also provides to determine the source/type of an operand, for example vector vs. scalar, register operand vs. constant, etc. GPU ISA: Some special GPU ISA state is maintained in gpu_isa.hh and isa.cc. This class is used to hold some special registers and values that can be used as operands by ISA instructions. Eventually more ISA-specific state should be moved here, and out of the WF class. Vector Operands: The operands for GCN3 instructions are defined in operand.hh. This file defines both scalar and vector operands wth GCN3 specific semantics. The vector operand class is desgned around the generic vec_reg.hh that is already present in gem5. Instructions: The GCN3 instructions are defined and implemented throughout gpu_static_inst.[hh|cc], instructions.[hh|cc], op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions all fall under one of the OP encoding types; for example scalar memory operands are of the type SMEM, vector ALU instructions can be VOP3, VOP2, etc. The base code common to all instructions of a certain OP encoding type is implemented in the OP encodings files, which includes operand information, disassembly methods, encoding type, etc. Each individual ISA isntruction is implemented as a class object in instructions.[hh|cc] and are derived from one of the OP encoding types. The instructions.cc file is primarily for the execute() methods of each individual instruction, and the header file provides the class definition and a few instruction specific API calls. Note that these instruction classes were auto-generated but not using the gem5 ISA description language. A custom ISA description was used and that cannot be released publicly, therefore we are providing them already in C++. Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28127 Reviewed-by: Matt Sinclair Reviewed-by: Jason Lowe-Power Maintainer: Anthony Gutierrez Tested-by: kokoro --- M MAINTAINERS A src/arch/gcn3/SConscript A src/arch/gcn3/SConsopts A src/arch/gcn3/decoder.cc A src/arch/gcn3/gpu_decoder.hh A src/arch/gcn3/gpu_isa.hh A src/arch/gcn3/gpu_types.hh A src/arch/gcn3/insts/gpu_static_inst.cc A src/arch/gcn3/insts/gpu_static_inst.hh A src/arch/gcn3/insts/inst_util.hh A src/arch/gcn3/insts/instructions.cc A src/arch/gcn3/insts/instructions.hh A src/arch/gcn3/insts/op_encodings.cc A src/arch/gcn3/insts/op_encodings.hh A src/arch/gcn3/isa.cc A src/arch/gcn3/operand.hh A src/arch/gcn3/registers.cc A src/arch/gcn3/registers.hh M util/git-commit-msg.py 19 files changed, 139,749 insertions(+), 7 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve Matt Sinclair: Looks good to me, approved Anthony Gutierrez: Looks good to me, approved kokoro: Regressions pass -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28127 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14 Gerrit-Change-Number: 28127 Gerrit-PatchSet: 2 Gerrit-Owner: Anthony Gutierrez Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Tony Gutierrez Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Add HSA device and HSA packet processor
Anthony Gutierrez has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28128 ) Change subject: dev-hsa: Add HSA device and HSA packet processor .. dev-hsa: Add HSA device and HSA packet processor This change adds support for HSA devices, which are DMA devices that have an HSA packet processor (HSAPP). An HSA packet processor model is also included. The HSAPP is a DMA device that matains AQL packet queues and handles extraction of AQL packets, scheduling of AQL queues, and initiates kernel launch for HSA devices. Because these devices directly interact with low-level software and aid in the implementation of the HSA ABI we also include some headers from the ROCm runtime: the hsa.h and kfd_ioctl.h headers. These aid with support ROCm for the HSA devices and drivers. Change-Id: I24305e0337edc6fa555d436697b4e607a1e097d5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28128 Reviewed-by: Matt Sinclair Reviewed-by: Jason Lowe-Power Maintainer: Anthony Gutierrez Maintainer: Jason Lowe-Power Tested-by: kokoro --- M MAINTAINERS A src/dev/hsa/HSADevice.py A src/dev/hsa/HSADriver.py A src/dev/hsa/SConscript A src/dev/hsa/hsa.h A src/dev/hsa/hsa_device.cc A src/dev/hsa/hsa_device.hh A src/dev/hsa/hsa_driver.cc A src/dev/hsa/hsa_driver.hh A src/dev/hsa/hsa_packet.hh A src/dev/hsa/hsa_packet_processor.cc A src/dev/hsa/hsa_packet_processor.hh A src/dev/hsa/hsa_queue.hh A src/dev/hsa/hw_scheduler.cc A src/dev/hsa/hw_scheduler.hh A src/dev/hsa/kfd_ioctl.h 16 files changed, 8,419 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Matt Sinclair: Looks good to me, approved Anthony Gutierrez: Looks good to me, approved kokoro: Regressions pass -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28128 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I24305e0337edc6fa555d436697b4e607a1e097d5 Gerrit-Change-Number: 28128 Gerrit-PatchSet: 2 Gerrit-Owner: Anthony Gutierrez Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Tony Gutierrez Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: configs: add option to set the timeouts for the TCPs and SQCs
Anthony Gutierrez has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28129 )
Change subject: configs: add option to set the timeouts for the TCPs and
SQCs
..
configs: add option to set the timeouts for the TCPs and SQCs
Change-Id: Icff2bd0237ddcc0d21db17208df8e53ff6f43e86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28129
Reviewed-by: Matt Sinclair
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
4 files changed, 63 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matt Sinclair: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index cf2fdbd..26bea0c 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -168,6 +168,11 @@
self.coalescer.max_outstanding_requests = options.simds_per_cu * \
options.wfs_per_simd * \
options.wf_size
+if options.tcp_deadlock_threshold:
+ self.coalescer.deadlock_threshold = \
+options.tcp_deadlock_threshold
+self.coalescer.max_coalesces_per_cycle = \
+options.max_coalesces_per_cycle
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
@@ -240,6 +245,10 @@
self.sequencer.support_data_reqs = False
self.sequencer.is_cpu_sequencer = False
+if options.sqc_deadlock_threshold:
+ self.sequencer.deadlock_threshold = \
+options.sqc_deadlock_threshold
+
self.ruby_system = ruby_system
if options.recycle_latency:
@@ -416,6 +425,8 @@
help="number of TCC directories and banks in the
GPU")
parser.add_option("--TCP_latency", type="int", default=4,
help="TCP latency")
+parser.add_option("--tcp-deadlock-threshold", type='int',
+ help="Set the TCP deadlock threshold to some value")
parser.add_option("--TCC_latency", type="int", default=16,
help="TCC latency")
parser.add_option("--tcc-size", type='string', default='256kB',
@@ -424,6 +435,10 @@
help="tcp size")
parser.add_option("--tcc-dir-factor", type='int', default=4,
help="TCCdir size = factor *(TCPs + TCC)")
+parser.add_option("--sqc-deadlock-threshold", type='int',
+ help="Set the SQC deadlock threshold to some value")
+parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
+ help="Maximum insts that may coalesce in a cycle");
def create_system(options, full_system, system, dma_devices, bootmem,
ruby_system):
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 71238ae..f4ecc41 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -153,6 +153,11 @@
self.coalescer.ruby_system = ruby_system
self.coalescer.support_inst_reqs = False
self.coalescer.is_cpu_sequencer = False
+if options.tcp_deadlock_threshold:
+ self.coalescer.deadlock_threshold = \
+ options.tcp_deadlock_threshold
+self.coalescer.max_coalesces_per_cycle = \
+options.max_coalesces_per_cycle
self.sequencer = RubySequencer()
self.sequencer.version = self.seqCount()
@@ -227,6 +232,9 @@
self.sequencer.ruby_system = ruby_system
self.sequencer.support_data_reqs = False
self.sequencer.is_cpu_sequencer = False
+if options.sqc_deadlock_threshold:
+ self.sequencer.deadlock_threshold = \
+options.sqc_deadlock_threshold
self.ruby_system = ruby_system
@@ -370,6 +378,9 @@
help = "SQC cache size")
parser.add_option("--sqc-assoc", type = 'int', default = 8,
help = "SQC cache assoc")
+parser.add_option("--sqc-deadlock-threshold", type='int',
+ help="Set the SQC deadlock threshold to some value")
+
parser.add_option("--WB_L1", action = "store_true", default = False,
help = "writeback L1")
parser.add_option("--WB_L2", action = "store_true", default = False,
@@ -386,6 +397,11 @@
help = "tcp size")
parser.add_option("--tcp-assoc", type = 'int', default = 16,
help = "tcp assoc")
+parser.add_option("--tcp-deadlock-threshold", type='int',
+ help="Set the TCP deadlock threshold to some value")
+parser.add_option("--max-coalesces-per-cycle", type="int", default=1,
+
[gem5-dev] Change in gem5/gem5[develop]: misc: Add build opts for GCN3 GPU ISA
Anthony Gutierrez has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28130 ) Change subject: misc: Add build opts for GCN3 GPU ISA .. misc: Add build opts for GCN3 GPU ISA Change-Id: I5f2662fe72d876b7bf816b0353aaefb85fc6c1c9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28130 Reviewed-by: Matt Sinclair Reviewed-by: Jason Lowe-Power Maintainer: Anthony Gutierrez Tested-by: kokoro --- A build_opts/GCN3_X86 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Matt Sinclair: Looks good to me, approved Anthony Gutierrez: Looks good to me, approved kokoro: Regressions pass diff --git a/build_opts/GCN3_X86 b/build_opts/GCN3_X86 new file mode 100644 index 000..21e3cf0 --- /dev/null +++ b/build_opts/GCN3_X86 @@ -0,0 +1,5 @@ +PROTOCOL = 'GPU_VIPER' +TARGET_ISA = 'x86' +TARGET_GPU_ISA = 'gcn3' +BUILD_GPU = True +CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU' -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28130 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5f2662fe72d876b7bf816b0353aaefb85fc6c1c9 Gerrit-Change-Number: 28130 Gerrit-PatchSet: 2 Gerrit-Owner: Anthony Gutierrez Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Tony Gutierrez Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix priority of multi compressor
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28367 )
Change subject: mem-cache: Fix priority of multi compressor
..
mem-cache: Fix priority of multi compressor
The priority queue comparator orders such that false gives the
entry a higher priority. Therefore, if it is desired to make
the entry with lowest decompression latency have higher priority,
the comparison must be inverted.
Can be tested with:
MultiCompressor(compressors=[
PerfectCompressor(decompression_latency=1),
PerfectCompressor(decompression_latency=2)])
Where it is expected that compressor0 (the one with decomp lat
of 1) is always chosen.
Change-Id: I44acbf5f51c6e47efdd2a16fba9596935cf2eb69
Signed-off-by: Daniel R. Carvalho
---
M src/mem/cache/compressors/multi.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/cache/compressors/multi.cc
b/src/mem/cache/compressors/multi.cc
index 599e059..fe22f5e 100644
--- a/src/mem/cache/compressors/multi.cc
+++ b/src/mem/cache/compressors/multi.cc
@@ -103,7 +103,7 @@
if (lhs_cf == rhs_cf) {
// When they have similar compressed sizes, give the one
// with fastest decompression privilege
-return lhs->decompLat < rhs->decompLat;
+return lhs->decompLat > rhs->decompLat;
}
return lhs_cf < rhs_cf;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28367
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I44acbf5f51c6e47efdd2a16fba9596935cf2eb69
Gerrit-Change-Number: 28367
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: LL/SC fixes
Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28327
to review the following change.
Change subject: mem-ruby: LL/SC fixes
..
mem-ruby: LL/SC fixes
The implementation for load-linked/store-conditional did not work
correctly for multi-core simulations. Since load-links were treated as
stores, it was not possible for a line to have multiple readers which
often resulted in livelock when using these instructions to implemented
mutexes. This improved implementation treats load-linked instructions
similarly to loads but locks the line after a copy has been fetched
locally. Writes to a monitored address ensure the 'linked' property is
blown away and any subsequent store-conditional will fail.
Change-Id: I3c8b29b66b8200de23cb141bf25bee710d79f844
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 155 insertions(+), 73 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index fd76289..f8de9ed 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -112,6 +124,10 @@
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
+ // ll/sc support
+ void writeCallbackScFail(Addr, DataBlock);
+ bool llscCheckMonitor(Addr);
+
void checkCoherence(Addr);
void evictionCallback(Addr);
void recordRequestType(SequencerRequestType);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 1f538c3..0287e13 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
#include "base/logging.hh"
#include "base/str.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
+#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
#include "debug/ProtocolTrace.hh"
#include "debug/RubySequencer.hh"
@@ -90,6 +91,64 @@
}
void
+Sequencer::llscLoadLinked(const Addr claddr)
+{
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (line) {
+line->setLocked(m_version);
+DPRINTF(LLSC, "LLSC Monitor - inserting load linked - "
+ "addr=0x%lx - cpu=%u\n", claddr, m_version);
+}
+}
+
+void
+Sequencer::llscClearMonitor(const Addr claddr)
+{
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (line && line->isLocked(m_version)) {
+line->clearLocked();
+DPRINTF(LLSC, "LLSC Monitor - clearing due to store - "
+ "addr=0x%lx - cpu=%u\n", claddr, m_version);
+}
+}
+
+bool
+Sequencer::llscStoreConditional(const Addr claddr)
+{
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (!line)
+return false;
+
+DPRINTF(LLSC, "LLSC Monitor - clearing due to "
+ "store conditional - "
+ "addr=0x%lx - cpu=%u\n",
+ claddr, m_version);
+
+if (line->isLocked(m_version)) {
+line->clearLocked();
+return true;
+} else {
+line->clearLocked();
+return false;
+}
+}
+
+bool
+Sequencer::llscCheckMonitor(const Addr address)
+{
+const Addr claddr = makeLineAddress(address);
+AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
+if (!line)
+return false;
+
+if (line->isLocked(m_version)) {
+return true;
+} else {
+return false;
+}
+}
+
+void
Sequencer::wakeup()
{
assert(drainState() != DrainState::Draining);
@@ -203,62 +262,6 @@
}
void
-Sequencer::invalidateSC(Addr address)
-{
-AbstractCacheEntry *e = m_dataCache_ptr->lookup(address);
-// The controller has lost the coherence permissions, hence the lock
-// on the cache line maintained by the cache should be cleared.
-if (e && e->isLocked(m_version)) {
-
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_Level LL/SC improvements
Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28328
to review the following change.
Change subject: mem-ruby: MESI_Three_Level LL/SC improvements
..
mem-ruby: MESI_Three_Level LL/SC improvements
This patch fixes the MESI_Three_Level protocols so that it correctly
informers the Ruby sequencer when a line eviction occurs. Furthermore,
the patch allows the protocol to recognize the 'Store_Conditional'
RubyRequestType and shortcuts this operation if the monitored line
has been cleared from the address monitor. This prevents certain
livelock behaviour in which a line could ping-pong between competing
cores.
The patch establishes a new C/C++ preprocessor definition which allows
the Sequencer to send the 'Store_Conditional' RubyRequestType to
MESI_Three_Level instead of 'ST'. This is a temporary measure until
the other protocols explicitely recognize 'Store_Conditional'.
Change-Id: I27ae041ab0e015a4f54f20df666f9c4873c7583d
---
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/system/SConscript
M src/mem/ruby/system/Sequencer.cc
3 files changed, 77 insertions(+), 23 deletions(-)
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index b74a727..14fb07a 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -121,6 +121,8 @@
Ack,desc="Ack for processor";
WB_Ack,desc="Ack for replacement";
+
+Failed_SC,desc="Store conditional request that will fail";
}
// TYPES
@@ -257,7 +259,8 @@
return Event:Load;
} else if (type == RubyRequestType:IFETCH) {
return Event:Ifetch;
-} else if ((type == RubyRequestType:ST) || (type ==
RubyRequestType:ATOMIC)) {
+} else if ((type == RubyRequestType:ST) || (type ==
RubyRequestType:ATOMIC)
+ || (type == RubyRequestType:Store_Conditional)) {
return Event:Store;
} else {
error("Invalid RubyRequestType");
@@ -349,36 +352,51 @@
}
}
} else {
-
// *** DATA ACCESS ***
Entry Dcache_entry := getDCacheEntry(in_msg.LineAddress);
+
+ // early out for failed store conditionals
+
+ if (in_msg.Type == RubyRequestType:Store_Conditional) {
+ if (!sequencer.llscCheckMonitor(in_msg.LineAddress)) {
+trigger(Event:Failed_SC, in_msg.LineAddress,
+Dcache_entry, TBEs[in_msg.LineAddress]);
+}
+ }
+
if (is_valid(Dcache_entry)) {
// The tag matches for the L0, so the L0 ask the L1 for it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
Dcache_entry, TBEs[in_msg.LineAddress]);
} else {
-
-// Check to see if it is in the OTHER L0
-Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
-if (is_valid(Icache_entry)) {
- // The block is in the wrong L0, put the request on the
queue to the private L1
- trigger(Event:L0_Replacement, in_msg.LineAddress,
- Icache_entry, TBEs[in_msg.LineAddress]);
-}
-
-if (Dcache.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it
- // in the L0 let's see if the L1 has it
- trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Dcache_entry, TBEs[in_msg.LineAddress]);
+// if the request is not valid, the store conditional will fail
+if (in_msg.Type == RubyRequestType:Store_Conditional) {
+// if the line is not valid, it can't be locked
+trigger(Event:Failed_SC, in_msg.LineAddress,
+Dcache_entry, TBEs[in_msg.LineAddress]);
} else {
- // No room in the L1, so we need to make room in the L0
- // Check if the line we want to evict is not locked
- Addr addr := Dcache.cacheProbe(in_msg.LineAddress);
- check_on_cache_probe(mandatoryQueue_in, addr);
- trigger(Event:L0_Replacement, addr,
- getDCacheEntry(addr),
- TBEs[addr]);
+ // Check to see if it is in the OTHER L0
+ Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
+ if (is_valid(Icache_entry)) {
+// The block is in the wrong L0, put the request on the
queue to the private L1
+trigger(Event:L0_Replacement, in_msg.LineAddress,
+Icache_entry, TBEs[in_msg.LineAddress]);
+ }
+
+ if (Dcache.cacheAvail(in_msg.LineAddress)) {
+//
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, mem-ruby, sim: Add missing overrides
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28168 )
Change subject: arch-arm, mem-ruby, sim: Add missing overrides
..
arch-arm, mem-ruby, sim: Add missing overrides
Change-Id: I5ab18960bd61953e6846426adb657818f825
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28168
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/arm/isa.hh
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/Sequencer.hh
M src/sim/kernel_workload.hh
4 files changed, 15 insertions(+), 15 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 5fec2db..b4fbbbf 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -726,14 +726,14 @@
unsigned eCount);
void
-serialize(CheckpointOut ) const
+serialize(CheckpointOut ) const override
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
}
void
-unserialize(CheckpointIn )
+unserialize(CheckpointIn ) override
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 620b5ee..1321173 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -102,9 +102,9 @@
void wakeup(); // Used only for deadlock detection
void printProgress(std::ostream& out) const;
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address, DataBlock& data);
@@ -157,18 +157,18 @@
void recordCPWriteCallBack(MachineID myMachID, MachineID senderMachID);
// Alternate implementations in VIPER Coalescer
-virtual RequestStatus makeRequest(PacketPtr pkt);
+virtual RequestStatus makeRequest(PacketPtr pkt) override;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
bool
-isDeadlockEventScheduled() const
+isDeadlockEventScheduled() const override
{
return deadlockCheckEvent.scheduled();
}
void
-descheduleDeadlockEvent()
+descheduleDeadlockEvent() override
{
deschedule(deadlockCheckEvent);
}
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 0569478..bb2819b 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -86,9 +86,9 @@
// Public Methods
void wakeup(); // Used only for deadlock detection
-void resetStats();
+void resetStats() override;
void collateStats();
-void regStats();
+void regStats() override;
void writeCallback(Addr address,
DataBlock& data,
@@ -106,14 +106,14 @@
const Cycles forwardRequestTime = Cycles(0),
const Cycles firstResponseTime = Cycles(0));
-RequestStatus makeRequest(PacketPtr pkt);
+RequestStatus makeRequest(PacketPtr pkt) override;
bool empty() const;
-int outstandingCount() const { return m_outstanding_count; }
+int outstandingCount() const override { return m_outstanding_count; }
-bool isDeadlockEventScheduled() const
+bool isDeadlockEventScheduled() const override
{ return deadlockCheckEvent.scheduled(); }
-void descheduleDeadlockEvent()
+void descheduleDeadlockEvent() override
{ deschedule(deadlockCheckEvent); }
void print(std::ostream& out) const;
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index 972a539..b88051a 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -98,7 +98,7 @@
}
bool
-insertSymbol(Addr address, const std::string )
+insertSymbol(Addr address, const std::string ) override
{
return kernelSymtab->insert(address, symbol);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28168
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ab18960bd61953e6846426adb657818f825
Gerrit-Change-Number: 28168
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType:
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Removed the unused parameter m_id from VirtualChannel
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28171 )
Change subject: mem-ruby: Removed the unused parameter m_id from
VirtualChannel
..
mem-ruby: Removed the unused parameter m_id from VirtualChannel
Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28171
Reviewed-by: Jason Lowe-Power
Reviewed-by: Srikant Bharadwaj
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/network/garnet2.0/InputUnit.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.cc
M src/mem/ruby/network/garnet2.0/VirtualChannel.hh
3 files changed, 4 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Srikant Bharadwaj: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/garnet2.0/InputUnit.cc
b/src/mem/ruby/network/garnet2.0/InputUnit.cc
index 8fdce06..640e3b4 100644
--- a/src/mem/ruby/network/garnet2.0/InputUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/InputUnit.cc
@@ -52,7 +52,7 @@
// Instantiating the virtual channels
virtualChannels.reserve(m_num_vcs);
for (int i=0; i < m_num_vcs; i++) {
-virtualChannels.emplace_back(i);
+virtualChannels.emplace_back();
}
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
index 3b077d4..a469a84 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
@@ -31,8 +31,8 @@
#include "mem/ruby/network/garnet2.0/VirtualChannel.hh"
-VirtualChannel::VirtualChannel(int id)
- : m_id(id), inputBuffer(), m_vc_state(IDLE_, Cycles(0)),
m_output_port(-1),
+VirtualChannel::VirtualChannel()
+ : inputBuffer(), m_vc_state(IDLE_, Cycles(0)), m_output_port(-1),
m_enqueue_time(INFINITE_), m_output_vc(-1)
{
}
diff --git a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
index 52963c8..752dfb4 100644
--- a/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
+++ b/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
@@ -40,7 +40,7 @@
class VirtualChannel
{
public:
-VirtualChannel(int id);
+VirtualChannel();
~VirtualChannel() = default;
bool need_stage(flit_stage stage, Cycles time);
@@ -89,7 +89,6 @@
uint32_t functionalWrite(Packet *pkt);
private:
-int m_id;
flitBuffer inputBuffer;
std::pair m_vc_state;
int m_output_port;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28171
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Gerrit-Change-Number: 28171
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Srikant Bharadwaj
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Avoid const from member due to ::operator=(...)
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28249 )
Change subject: mem-ruby: Avoid const from member due to
::operator=(...)
..
mem-ruby: Avoid const from member due to ::operator=(...)
Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28249
Reviewed-by: Matthew Poremba
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/Message.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/Message.hh
b/src/mem/ruby/slicc_interface/Message.hh
index 0c2e0aa..1044fe0 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -104,7 +104,7 @@
void setVnet(int net) { vnet = net; }
private:
-const Tick m_time;
+Tick m_time;
Tick m_LastEnqueueTime; // my last enqueue time
Tick m_DelayedTicks; // my delayed cycles
uint64_t m_msg_counter; // FIXME, should this be a 64-bit value?
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Gerrit-Change-Number: 28249
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix inconsistency in variable name
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28172 ) Change subject: arch-arm: Fix inconsistency in variable name .. arch-arm: Fix inconsistency in variable name Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28172 Maintainer: Giacomo Travaglini Tested-by: kokoro --- M src/arch/arm/freebsd/process.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/freebsd/process.cc b/src/arch/arm/freebsd/process.cc index 3955f85..d8a7d68 100644 --- a/src/arch/arm/freebsd/process.cc +++ b/src/arch/arm/freebsd/process.cc @@ -118,7 +118,7 @@ void *holdp = (void *)buf2.bufferPtr(); size_t *holdlenp = (size_t *)buf3.bufferPtr(); -ret = sysctl((int *)hnamep, namelen, holdp, holdlenp, hnewp, newlen); +ret = sysctl((int *)hnamep, nameLen, holdp, holdlenp, hnewp, newlen); buf.copyOut(tc->getVirtProxy()); buf2.copyOut(tc->getVirtProxy()); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28172 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249 Gerrit-Change-Number: 28172 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Downgrade constexpr causing build errors to const
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28167 )
Change subject: arch-arm: Downgrade constexpr causing build errors to const
..
arch-arm: Downgrade constexpr causing build errors to const
Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28167
Tested-by: kokoro
---
M src/arch/arm/aapcs32.hh
1 file changed, 7 insertions(+), 7 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index fd63483..e2e5d09 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -489,12 +489,12 @@
if (state.variadic)
return getArgument(tc, state);
-int index = state.allocate(Float{}, 1);
+const int index = state.allocate(Float{}, 1);
if (index >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Float);
-constexpr int reg = index / lane_per_reg;
-constexpr int lane = index % lane_per_reg;
+const int reg = index / lane_per_reg;
+const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
@@ -558,14 +558,14 @@
if (useBaseABI(state))
return getArgument(tc, state);
-int base = state.allocate(Elem{}, Count);
+const int base = state.allocate(Elem{}, Count);
if (base >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Elem);
HA ha;
for (int i = 0; i < Count; i++) {
-constexpr int index = base + i;
-constexpr int reg = index / lane_per_reg;
-constexpr int lane = index % lane_per_reg;
+const int index = base + i;
+const int reg = index / lane_per_reg;
+const int lane = index % lane_per_reg;
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
--
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Gerrit-Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Gerrit-Change-Number: 28167
Gerrit-PatchSet: 4
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Disable unsupported -Wl,--as-needed in MacOS
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28173 )
Change subject: scons: Disable unsupported -Wl,--as-needed in MacOS
..
scons: Disable unsupported -Wl,--as-needed in MacOS
Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28173
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 4 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 215c0b6..3345148 100755
--- a/SConstruct
+++ b/SConstruct
@@ -359,7 +359,10 @@
main.Append(CCFLAGS=['-I/usr/local/include'])
main.Append(CXXFLAGS=['-I/usr/local/include'])
-main.Append(LINKFLAGS='-Wl,--as-needed')
+# On Mac OS X/Darwin the default linker doesn't support the
+# option --as-needed
+if sys.platform != "darwin":
+main.Append(LINKFLAGS='-Wl,--as-needed')
main['FILTER_PSHLINKFLAGS'] = lambda x: str(x).replace(' -shared', '')
main['PSHLINKFLAGS'] =
main.subst('${FILTER_PSHLINKFLAGS(SHLINKFLAGS)}')
if GetOption('gold_linker'):
--
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Gerrit-Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Gerrit-Change-Number: 28173
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix access modifier in Arm*ProcessBits class
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28248 )
Change subject: arch-arm: Fix access modifier in Arm*ProcessBits class
..
arch-arm: Fix access modifier in Arm*ProcessBits class
Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Reviewed-by: Giacomo Travaglini
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28248
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/arm/freebsd/process.hh
M src/arch/arm/linux/process.hh
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/freebsd/process.hh
b/src/arch/arm/freebsd/process.hh
index ac0092e..d52512a 100644
--- a/src/arch/arm/freebsd/process.hh
+++ b/src/arch/arm/freebsd/process.hh
@@ -39,7 +39,7 @@
class ArmFreebsdProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
index 0662d9f..0c15c28 100644
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -1,5 +1,5 @@
/*
-* Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,7 +47,7 @@
class ArmLinuxProcessBits
{
- protected:
+ public:
struct SyscallABI {};
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Gerrit-Change-Number: 28248
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix function signature inconsistencies in semihosting
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28170 )
Change subject: arch-arm: Fix function signature inconsistencies in
semihosting
..
arch-arm: Fix function signature inconsistencies in semihosting
Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Signed-off-by: Nikos Nikoleris
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28170
Reviewed-by: Gabe Black
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/semihosting.cc
1 file changed, 6 insertions(+), 6 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 7718cd0..7711a86 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -305,7 +305,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callClose(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callClose(ThreadContext *tc, Handle handle)
{
if (handle > files.size()) {
DPRINTF(Semihosting, "Semihosting SYS_CLOSE(%i): Illegal file\n");
@@ -350,7 +350,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callWrite(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callWrite(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -371,7 +371,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callRead(ThreadContext *tc, uint64_t handle, Addr addr,
+ArmSemihosting::callRead(ThreadContext *tc, Handle handle, Addr addr,
size_t size)
{
if (handle > files.size() || !files[handle])
@@ -404,7 +404,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callIsTTY(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callIsTTY(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -418,7 +418,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callSeek(ThreadContext *tc, uint64_t handle, uint64_t pos)
+ArmSemihosting::callSeek(ThreadContext *tc, Handle handle, uint64_t pos)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
@@ -432,7 +432,7 @@
}
ArmSemihosting::RetErrno
-ArmSemihosting::callFLen(ThreadContext *tc, uint64_t handle)
+ArmSemihosting::callFLen(ThreadContext *tc, Handle handle)
{
if (handle > files.size() || !files[handle])
return retError(EBADF);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Gerrit-Change-Number: 28170
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix mismatch between #ifndef and #define in varargs.hh
Nikos Nikoleris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28169 ) Change subject: sim: Fix mismatch between #ifndef and #define in varargs.hh .. sim: Fix mismatch between #ifndef and #define in varargs.hh Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Signed-off-by: Nikos Nikoleris Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28169 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M src/sim/guest_abi/varargs.hh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh index 41e3c62..6a19db8 100644 --- a/src/sim/guest_abi/varargs.hh +++ b/src/sim/guest_abi/varargs.hh @@ -26,7 +26,7 @@ */ #ifndef __SIM_GUEST_ABI_VARARGS_HH__ -#define __SIM_GUEST_ABI_VARRAGS_HH__ +#define __SIM_GUEST_ABI_VARARGS_HH__ #include #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28169 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae Gerrit-Change-Number: 28169 Gerrit-PatchSet: 3 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Inheritance fixes in varargs
Nikos Nikoleris has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28250 )
Change subject: sim: Inheritance fixes in varargs
..
sim: Inheritance fixes in varargs
Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28250
Reviewed-by: Bobby R. Bruce
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/guest_abi/varargs.hh
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/guest_abi/varargs.hh b/src/sim/guest_abi/varargs.hh
index 6a19db8..07ed2a1 100644
--- a/src/sim/guest_abi/varargs.hh
+++ b/src/sim/guest_abi/varargs.hh
@@ -70,6 +70,8 @@
class VarArgsBase : public VarArgsBase
{
public:
+virtual ~VarArgsBase() = default;
+
// The virtual function takes a reference parameter so that the
different
// _getImpl methods can co-exist through overloading.
virtual void _getImpl(First &) = 0;
@@ -126,6 +128,8 @@
// Declare state to pass to the Argument<>::get methods.
ThreadContext *tc;
typename ABI::State state;
+// Make sure base class _getImpl-es don't get hidden by ours.
+using Base::_getImpl;
// Give the "using" statement in our subclass something to refer to.
void _getImpl();
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Gerrit-Change-Number: 28250
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix compareVersions for python 3.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28309 )
Change subject: python: Fix compareVersions for python 3.
..
python: Fix compareVersions for python 3.
When the internal utility function make_version_list sees a string, it
tries to convert it into a list using the map() function. In python 3,
that returns an iterator. The following call to zip() will consume those
iterators, and then the following calls to len() will die because they
don't work on map iterators.
This is only a problem if all the common components of the version lists
are equal, and the comparison needs to then check if one of the lists
was equal to the other but with more components. When versions are
equal, for instance when compiling with the oldest supported version of
gcc (4.8.0) this error surfaces and breaks our scons build.
A simple fix is to just wrap the call to map() with list() to convert
the iterator to a flat list, making the other logic work as before.
Change-Id: If9dc5cd7fff70c21229ac3dd9a017edeccd26148
---
M src/python/m5/util/__init__.py
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py
index fd1ea91..98a7a08 100644
--- a/src/python/m5/util/__init__.py
+++ b/src/python/m5/util/__init__.py
@@ -125,7 +125,8 @@
if isinstance(v, (list,tuple)):
return v
elif isinstance(v, string_types):
-return map(lambda x: int(re.match('\d+', x).group()),
v.split('.'))
+return list(map(lambda x: int(re.match('\d+', x).group()),
+v.split('.')))
else:
raise TypeError()
--
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Gerrit-Branch: develop
Gerrit-Change-Id: If9dc5cd7fff70c21229ac3dd9a017edeccd26148
Gerrit-Change-Number: 28309
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Convert GuestABI example signatures to comments.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28308 )
Change subject: sim: Convert GuestABI example signatures to comments.
..
sim: Convert GuestABI example signatures to comments.
In the base Result and Argument templates, there were private static
functions which weren't meant to be used, but which would act as
documentation for what those functions should look like. They were
marked as private to prevent them from being accidentally used and
causing confusing, hard to debug errors.
Unfortunately, that also meant that those functions exist, and
apparently cause inconsistent problems with SFINAE. I assume if the
functions don't exist at all, then SFINAE will work properly. When
they're private, that seems to cause a substitution failure which
actually is an error which makes the build fail.
Change-Id: I326e9e1d05eafe1b00732ae10264354b07426e74
---
M src/sim/guest_abi/definition.hh
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/sim/guest_abi/definition.hh
b/src/sim/guest_abi/definition.hh
index becdb3c..4928b93 100644
--- a/src/sim/guest_abi/definition.hh
+++ b/src/sim/guest_abi/definition.hh
@@ -57,27 +57,28 @@
template
struct Result
{
- private:
/*
* Store result "ret" into the state accessible through tc. Optionally
* accept "state" in case it holds some signature wide information.
*
* Note that the declaration below is only to document the expected
- * signature and is private so it won't be used by accident.
+ * signature and is commented out so it won't be used by accident.
* Specializations of this Result class should define their own version
- * of this method which actually does something and is public.
+ * of this method which actually does something.
+ *
+ * static void store(ThreadContext *tc, const Ret );
+ * static void store(ThreadContext *tc, const Ret ,
+ * typename ABI::State );
*/
-static void store(ThreadContext *tc, const Ret );
-static void store(ThreadContext *tc, const Ret ,
- typename ABI::State );
/*
* Prepare for a result of type Ret. This might mean, for instance,
* allocating an argument register for a result pointer.
*
* This method can be excluded if no preparation is necessary.
+ *
+ * static void prepare(ThreadContext *tc, typename ABI::State );
*/
-static void prepare(ThreadContext *tc, typename ABI::State );
};
/*
@@ -98,16 +99,18 @@
*
* Like Result::store above, the declaration below is only to document
* the expected method signature.
+ *
+ * static Arg get(ThreadContext *tc, typename ABI::State );
*/
-static Arg get(ThreadContext *tc, typename ABI::State );
/*
* Prepare for an argument of type Arg. This might mean, for instance,
* allocating an argument register for a result pointer.
*
* This method can be excluded if no preparation is necessary.
+ *
+ * static void allocate(ThreadContext *tc, typename ABI::State );
*/
-static void allocate(ThreadContext *tc, typename ABI::State );
};
} // namespace GuestABI
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I326e9e1d05eafe1b00732ae10264354b07426e74
Gerrit-Change-Number: 28308
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add an option to suppress the return value in invokeSimcall.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28288 )
Change subject: sim: Add an option to suppress the return value in
invokeSimcall.
..
sim: Add an option to suppress the return value in invokeSimcall.
Sometimes when using the GuestABI mechanism, gem5 wants to know that a
function was called and with what arguments to do its own processing,
but doesn't want to return its own value since it will still let the
simulated system execute its own function. There are also situations
where gem5 wants to return a value, but not through the normal
mechanism. That happens when, for instance, a gem5 op is triggered by a
memory access, and that access is what should return the value, not a
particular fixed register.
This option is a template parameter rather than a function argument so
that if it's not going to be used, no "Return" type needs to be defined
since it's not present at all in the chain of functions invokeSimcall
expands to.
This will also make it easier to reuse generic ABIs in those situations
without having to make custom wrappers.
Change-Id: I969e78495c8f4e73f4de1a3dfb4d74c9b30f5af5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28288
Reviewed-by: Nikos Nikoleris
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/sim/guest_abi.hh
M src/sim/guest_abi.test.cc
M src/sim/guest_abi/dispatch.hh
3 files changed, 43 insertions(+), 8 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/guest_abi.hh b/src/sim/guest_abi.hh
index 704155b..ea3325f 100644
--- a/src/sim/guest_abi.hh
+++ b/src/sim/guest_abi.hh
@@ -42,7 +42,7 @@
// and write a result (if any) back to. For convenience, the wrapper also
// returns the result of the wrapped function.
-template
+template
Ret
invokeSimcall(ThreadContext *tc,
std::function target)
@@ -51,15 +51,30 @@
// types will be zero initialized.
auto state = GuestABI::initializeState(tc);
GuestABI::prepareForFunction(tc, state);
-return GuestABI::callFrom(tc, state, target);
+return GuestABI::callFrom(tc, state,
target);
+}
+
+template
+Ret
+invokeSimcall(ThreadContext *tc,
+ std::function target)
+{
+return invokeSimcall(tc, target);
+}
+
+template
+Ret
+invokeSimcall(ThreadContext *tc, Ret (*target)(ThreadContext *, Args...))
+{
+return invokeSimcall(
+tc, std::function(target));
}
template
Ret
invokeSimcall(ThreadContext *tc, Ret (*target)(ThreadContext *, Args...))
{
-return invokeSimcall(
-tc, std::function(target));
+return invokeSimcall(tc, target);
}
template
diff --git a/src/sim/guest_abi.test.cc b/src/sim/guest_abi.test.cc
index 6b5d060..8edf5d3 100644
--- a/src/sim/guest_abi.test.cc
+++ b/src/sim/guest_abi.test.cc
@@ -345,6 +345,15 @@
EXPECT_EQ(tc.intResult, tc.DefaultIntResult);
EXPECT_EQ(tc.floatResult, DoubleRetValue + 1.0);
}
+{
+// Disable storing the return value in the ThreadContext.
+ThreadContext tc;
+int ret = invokeSimcall(, testIntRet);
+EXPECT_EQ(ret, IntRetValue);
+EXPECT_EQ(tc.intResult, tc.DefaultIntResult);
+EXPECT_EQ(tc.floatResult, tc.DefaultFloatResult);
+}
+
// 2D returns.
{
diff --git a/src/sim/guest_abi/dispatch.hh b/src/sim/guest_abi/dispatch.hh
index 62cbf29..794fd62 100644
--- a/src/sim/guest_abi/dispatch.hh
+++ b/src/sim/guest_abi/dispatch.hh
@@ -52,8 +52,9 @@
// With no arguments to gather, call the target function and store the
// result.
-template
-static typename std::enable_if::value, Ret>::type
+template
+static typename std::enable_if::value && store_ret,
+Ret>::type
callFrom(ThreadContext *tc, typename ABI::State ,
std::function target)
{
@@ -62,6 +63,15 @@
return ret;
}
+template
+static typename std::enable_if::value && !store_ret,
+Ret>::type
+callFrom(ThreadContext *tc, typename ABI::State ,
+std::function target)
+{
+return target(tc);
+}
+
// With no arguments to gather and nothing to return, call the target
function.
template
static void
@@ -73,7 +83,8 @@
// Recursively gather arguments for target from tc until we get to the base
// case above.
-template
+template
static typename std::enable_if::value, Ret>::type
callFrom(ThreadContext *tc, typename ABI::State ,
std::function target)
@@ -88,7 +99,7 @@
};
// Recursively handle any remaining arguments.
-return callFrom(tc, state, partial);
+return callFrom(tc, state, partial);
}
// Recursively gather arguments for target from tc until we get to the base
--
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