[gem5-dev] Change in gem5/gem5[develop]: arch: Re-add copyrights that were accidentally removed.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/36716 ) Change subject: arch: Re-add copyrights that were accidentally removed. .. arch: Re-add copyrights that were accidentally removed. The partial contents of some files were moved into other files, but the copyright wasn't moved over with them. This propogates the copyright. Change-Id: I8612e88ffb7584b15924cf747f671ca3cdefbe55 --- M src/arch/power/linux/se_workload.cc M src/arch/power/linux/se_workload.hh M src/arch/sparc/linux/se_workload.cc M src/arch/sparc/linux/se_workload.hh M src/arch/x86/linux/se_workload.cc M src/arch/x86/linux/se_workload.hh 6 files changed, 29 insertions(+), 0 deletions(-) diff --git a/src/arch/power/linux/se_workload.cc b/src/arch/power/linux/se_workload.cc index 869b140..7e2b22c 100644 --- a/src/arch/power/linux/se_workload.cc +++ b/src/arch/power/linux/se_workload.cc @@ -1,4 +1,7 @@ /* + * Copyright 2003-2005 The Regents of The University of Michigan + * Copyright 2007-2008 The Florida State University + * Copyright 2009 The University of Edinburgh * Copyright 2020 Google Inc. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/linux/se_workload.hh b/src/arch/power/linux/se_workload.hh index c306b99..ac20e5d 100644 --- a/src/arch/power/linux/se_workload.hh +++ b/src/arch/power/linux/se_workload.hh @@ -1,4 +1,6 @@ /* + * Copyright 2007-2008 The Florida State University + * Copyright 2009 The University of Edinburgh * Copyright 2020 Google Inc. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/sparc/linux/se_workload.cc b/src/arch/sparc/linux/se_workload.cc index 7b652ff..75f74cf 100644 --- a/src/arch/sparc/linux/se_workload.cc +++ b/src/arch/sparc/linux/se_workload.cc @@ -1,4 +1,5 @@ /* + * Copyright 2003-2005 The Regents of The University of Michigan * Copyright 2020 Google Inc. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/sparc/linux/se_workload.hh b/src/arch/sparc/linux/se_workload.hh index a5022d6..60a4be6 100644 --- a/src/arch/sparc/linux/se_workload.hh +++ b/src/arch/sparc/linux/se_workload.hh @@ -1,4 +1,5 @@ /* + * Copyright 2003-2004 The Regents of The University of Michigan * Copyright 2020 Google Inc. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/x86/linux/se_workload.cc b/src/arch/x86/linux/se_workload.cc index 1e56371..f4a71cf 100644 --- a/src/arch/x86/linux/se_workload.cc +++ b/src/arch/x86/linux/se_workload.cc @@ -1,4 +1,15 @@ /* + * Copyright 2007 The Hewlett-Packard Development Company + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright 2020 Google Inc. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/x86/linux/se_workload.hh b/src/arch/x86/linux/se_workload.hh index ee1805c..01d34ec 100644 --- a/src/arch/x86/linux/se_workload.hh +++ b/src/arch/x86/linux/se_workload.hh @@ -1,4 +1,15 @@ /* + * Copyright 2007 The Hewlett-Packard Development Company + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright 2020 Google Inc. * * Redistribution and use in source and binary forms, with or without -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36716 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8612e88ffb7584b15924cf747f671ca3cdefbe55 Gerrit-Change-Number: 36716 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] Change in gem5/gem5[develop]: sim: Add a missing include to sim/syscall_abi.hh.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/36616 ) Change subject: sim: Add a missing include to sim/syscall_abi.hh. .. sim: Add a missing include to sim/syscall_abi.hh. This must have been included indirectly in the past. Change-Id: I8be3a11ca386e420f04d57e51a89c47e6a747e18 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36616 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- M src/sim/syscall_abi.hh 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/sim/syscall_abi.hh b/src/sim/syscall_abi.hh index 5291608..984f0e0 100644 --- a/src/sim/syscall_abi.hh +++ b/src/sim/syscall_abi.hh @@ -28,6 +28,7 @@ #ifndef __SIM_SYSCALL_ABI_HH__ #define __SIM_SYSCALL_ABI_HH__ +#include "base/bitfield.hh" #include "base/types.hh" #include "cpu/thread_context.hh" #include "sim/guest_abi.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36616 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8be3a11ca386e420f04d57e51a89c47e6a747e18 Gerrit-Change-Number: 36616 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: A call for maintainers
We also have our gem5-resources and gem5-website repositories, which we tag with "resources" and "website". Though separate repos, it may be worth adding maintainers for these things as they come up on Gerrit either way. I'm happy to volunteer as a maintainer for both. -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Wed, Oct 21, 2020 at 7:31 PM Gabe Black via gem5-dev wrote: > I think when we first split things into areas for maintainers, we just > went with the top level directories in the source tree. That was a good > first approximation, but I think it will often make sense to break things > down a little differently in practice, particularly with directories like > ext which have a bunch of stuff all lumped together. > > "misc" is sort of a catch all, when no particular category (or many > categories) fit. I don't think it makes a lot of sense to have a maintainer > for misc. Anything that falls under only that probably needs to be given > its own bucket/maintainer, and if it has that tag because it falls under > lots of categories then it's just short hand and we (probably) don't need a > special maintainer for that case. > > Gabe > > On Wed, Oct 21, 2020 at 4:26 PM Hoa Nguyen via gem5-dev > wrote: > >> Hi Jason, >> >> I would like to be a maintainer of testlib, which is in ext/. >> >> I find that the codebase in ext/ itself could be broken down to several >> subcomponents as it consists lots of different projects. >> >> Also, can you elaborate what type of changes fall under the "misc" tag? >> >> Regards, >> Hoa Nguyen >> >> On Fri, Oct 16, 2020, 3:27 PM Jason Lowe-Power via gem5-dev < >> gem5-dev@gem5.org> wrote: >> >>> Hi everyone! >>> >>> As you all are aware, we're pushing to increase the stability of gem5. >>> However, at the same time, we're seeing a significant increase in the rate >>> of gem5 changes. Between gem5-20.0 and gem5-20.1 we had over 650 commits! >>> And, that doesn't count the many changes on gerrit that never got reviewed >>> :(. >>> >>> We need help reviewing! One of the steps we're taking to help with this >>> is to assign specific maintainers to review every patch (automatically). >>> >>> There is a change on gerrit to do this: >>> https://gem5-review.googlesource.com/c/public/gem5/+/34737 Please let >>> us know if there are any comments. >>> >>> In that commit is a new file which specifies the maintainers in a >>> machine-readable format. Now, for the ask: We're looking for volunteers for >>> all of the components that are missing maintainers! Being a maintainer >>> comes with the responsibility of reviewing patches in a timely fashion, but >>> it also means that you can influence the changes in gem5! >>> >>> See >>> https://gem5-review.googlesource.com/c/public/gem5/+/34737/17/util/gerrit_bot/MAINTAINERS.json >>> >>> Specifically, if you would like to become the maintainer for any of the >>> following sub-components, simply reply to this email! Additionally, if you >>> have suggestions for other ways to break down these components, feel free >>> to comment on the changeset linked above. >>> >>> - arch-mips >>> - arch-power >>> - base >>> - cpu >>> - cpu-minor >>> - cpu-o3 >>> - cpu-simple >>> - dev >>> - ext >>> - misc >>> - stats >>> - system >>> >>> Have a great weekend! >>> >>> Cheers, >>> Jason >>> ___ >>> gem5-dev mailing list -- gem5-dev@gem5.org >>> To unsubscribe send an email to gem5-dev-le...@gem5.org >>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >> >> ___ >> gem5-dev mailing list -- gem5-dev@gem5.org >> To unsubscribe send an email to gem5-dev-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Replace any getDTBPtr/getITBPtr usage
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34981 )
Change subject: sim: Replace any getDTBPtr/getITBPtr usage
..
sim: Replace any getDTBPtr/getITBPtr usage
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: Ibd78bef263d186889f4533583ff30f46a0a8643f
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34981
Tested-by: kokoro
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
---
M src/sim/mem_state.cc
1 file changed, 3 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index bcfab78..7adee59 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -30,7 +30,7 @@
#include
-#include "arch/generic/tlb.hh"
+#include "arch/generic/mmu.hh"
#include "debug/Vma.hh"
#include "mem/se_translating_port_proxy.hh"
#include "sim/process.hh"
@@ -258,8 +258,7 @@
* that can flush just part of the address space.
*/
for (auto *tc: _ownerProcess->system->threads) {
-tc->getDTBPtr()->flushAll();
-tc->getITBPtr()->flushAll();
+tc->getMMUPtr()->flushAll();
}
do {
@@ -360,8 +359,7 @@
* that can flush just part of the address space.
*/
for (auto *tc: _ownerProcess->system->threads) {
-tc->getDTBPtr()->flushAll();
-tc->getITBPtr()->flushAll();
+tc->getMMUPtr()->flushAll();
}
do {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34981
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibd78bef263d186889f4533583ff30f46a0a8643f
Gerrit-Change-Number: 34981
Gerrit-PatchSet: 18
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: fix dezip of ubuntu images in long regr
mike upton has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/36615 ) Change subject: tests: fix dezip of ubuntu images in long regr .. tests: fix dezip of ubuntu images in long regr needed to change output open from 'w' to 'wb' to write binary format Change-Id: Ia176d86a8ab8cc083ffc9508e051b667936eca2c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36615 Reviewed-by: Jason Lowe-Power Reviewed-by: Bobby R. Bruce Maintainer: Jason Lowe-Power Maintainer: Bobby R. Bruce Tested-by: kokoro --- M tests/gem5/fixture.py 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py index e8a67b8..467eb43 100644 --- a/tests/gem5/fixture.py +++ b/tests/gem5/fixture.py @@ -297,7 +297,7 @@ gzipped_filename = self.filename + ".gz" urllib.request.urlretrieve(self.url, gzipped_filename) -with open(self.filename, 'w') as outfile: +with open(self.filename, 'wb') as outfile: with gzip.open(gzipped_filename, 'r') as infile: shutil.copyfileobj(infile, outfile) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36615 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia176d86a8ab8cc083ffc9508e051b667936eca2c Gerrit-Change-Number: 36615 Gerrit-PatchSet: 2 Gerrit-Owner: mike upton Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-Reviewer: mike upton Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Replace any getDTBPtr/getITBPtr usage
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34979 )
Change subject: arch-x86: Replace any getDTBPtr/getITBPtr usage
..
arch-x86: Replace any getDTBPtr/getITBPtr usage
The getMMUPtr should be used instead
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I363c2b50abdd5d2d8442ebf5892eaf17c99c129a
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34979
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
---
M src/arch/x86/faults.cc
M src/arch/x86/isa.cc
M src/arch/x86/mmu.hh
M src/arch/x86/remote_gdb.cc
M src/arch/x86/utility.cc
5 files changed, 25 insertions(+), 13 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 36cc47e..a507515 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -42,6 +42,7 @@
#include "arch/x86/generated/decoder.hh"
#include "arch/x86/isa_traits.hh"
+#include "arch/x86/mmu.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
@@ -137,8 +138,7 @@
{
if (FullSystem) {
// Invalidate any matching TLB entries before handling the page
fault.
-tc->getITBPtr()->demapPage(addr, 0);
-tc->getDTBPtr()->demapPage(addr, 0);
+tc->getMMUPtr()->demapPage(addr, 0);
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
X86FaultBase::invoke(tc);
// If something bad happens while trying to enter the page fault
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 1b2504a..8618287 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -29,7 +29,7 @@
#include "arch/x86/isa.hh"
#include "arch/x86/decoder.hh"
-#include "arch/x86/tlb.hh"
+#include "arch/x86/mmu.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "params/X86ISA.hh"
@@ -239,8 +239,7 @@
}
}
if (toggled.pg) {
-dynamic_cast(tc->getITBPtr())->flushAll();
-dynamic_cast(tc->getDTBPtr())->flushAll();
+tc->getMMUPtr()->flushAll();
}
//This must always be 1.
newCR0.et = 1;
@@ -255,15 +254,13 @@
case MISCREG_CR2:
break;
case MISCREG_CR3:
-dynamic_cast(tc->getITBPtr())->flushNonGlobal();
-dynamic_cast(tc->getDTBPtr())->flushNonGlobal();
+static_cast(tc->getMMUPtr())->flushNonGlobal();
break;
case MISCREG_CR4:
{
CR4 toggled = regVal[miscReg] ^ val;
if (toggled.pae || toggled.pse || toggled.pge) {
-dynamic_cast(tc->getITBPtr())->flushAll();
-dynamic_cast(tc->getDTBPtr())->flushAll();
+tc->getMMUPtr()->flushAll();
}
}
break;
diff --git a/src/arch/x86/mmu.hh b/src/arch/x86/mmu.hh
index 4f3411a..70afea3 100644
--- a/src/arch/x86/mmu.hh
+++ b/src/arch/x86/mmu.hh
@@ -39,6 +39,7 @@
#define __ARCH_X86_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/x86/tlb.hh"
#include "params/X86MMU.hh"
@@ -50,6 +51,19 @@
MMU(const X86MMUParams )
: BaseMMU(p)
{}
+
+void
+flushNonGlobal()
+{
+static_cast(itb)->flushNonGlobal();
+static_cast(dtb)->flushNonGlobal();
+}
+
+Walker*
+getDataWalker()
+{
+return static_cast(dtb)->getWalker();
+}
};
} // namespace X86ISA
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 9603b90..2f38fd5f 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -44,6 +44,7 @@
#include
+#include "arch/x86/mmu.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/process.hh"
#include "arch/x86/regs/int.hh"
@@ -68,8 +69,8 @@
RemoteGDB::acc(Addr va, size_t len)
{
if (FullSystem) {
-Walker *walker = dynamic_cast(
-context()->getDTBPtr())->getWalker();
+Walker *walker = dynamic_cast(
+context()->getMMUPtr())->getDataWalker();
unsigned logBytes;
Fault fault = walker->startFunctional(context(), va, logBytes,
BaseTLB::Read);
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 33b9371..7d891af 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -39,6 +39,7 @@
#include "arch/x86/utility.hh"
#include "arch/x86/interrupts.hh"
+#include "arch/x86/mmu.hh"
#include "arch/x86/registers.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/base.hh"
@@ -86,8 +87,7 @@
// CPU switch have different frequencies.
dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
-dest->getITBPtr()->flushAll();
-
[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Replace any getDTBPtr/getITBPtr usage
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34982 )
Change subject: arch-sparc: Replace any getDTBPtr/getITBPtr usage
..
arch-sparc: Replace any getDTBPtr/getITBPtr usage
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34982
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/sparc/faults.cc
M src/arch/sparc/mmu.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
4 files changed, 29 insertions(+), 11 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 33ba921..53e7576 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -30,9 +30,9 @@
#include
+#include "arch/sparc/mmu.hh"
#include "arch/sparc/process.hh"
#include "arch/sparc/se_workload.hh"
-#include "arch/sparc/tlb.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
@@ -669,8 +669,9 @@
// false for syscall emulation mode regardless of whether the
// address is real in preceding code. Not sure sure that this is
// correct, but also not sure if it matters at all.
-dynamic_cast(tc->getITBPtr())->
-insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+static_cast(tc->getMMUPtr())->insertItlbEntry(
+alignedvaddr, partition_id, context_id,
+false, entry.pte);
}
void
@@ -756,8 +757,9 @@
// false for syscall emulation mode regardless of whether the
// address is real in preceding code. Not sure sure that this is
// correct, but also not sure if it matters at all.
-dynamic_cast(tc->getDTBPtr())->
-insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+static_cast(tc->getMMUPtr())->insertDtlbEntry(
+alignedvaddr, partition_id, context_id,
+false, entry.pte);
}
void
diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh
index 39f5008..f784015 100644
--- a/src/arch/sparc/mmu.hh
+++ b/src/arch/sparc/mmu.hh
@@ -39,6 +39,7 @@
#define __ARCH_SPARC_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/sparc/tlb.hh"
#include "params/SparcMMU.hh"
@@ -50,6 +51,22 @@
MMU(const SparcMMUParams )
: BaseMMU(p)
{}
+
+void
+insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real,
+const PageTableEntry& PTE, int entry=-1)
+{
+static_cast(itb)->insert(vpn, partition_id,
+context_id, real, PTE, entry);
+}
+
+void
+insertDtlbEntry(Addr vpn, int partition_id, int context_id, bool real,
+const PageTableEntry& PTE, int entry=-1)
+{
+static_cast(dtb)->insert(vpn, partition_id,
+context_id, real, PTE, entry);
+}
};
} // namespace SparcISA
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 20f316f..9dde4ef 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -33,6 +33,7 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/faults.hh"
#include "arch/sparc/interrupts.hh"
+#include "arch/sparc/mmu.hh"
#include "arch/sparc/registers.hh"
#include "base/bitfield.hh"
#include "base/compiler.hh"
@@ -955,7 +956,7 @@
DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
(uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
-TLB *itb = dynamic_cast(tc->getITBPtr());
+TLB *itb = static_cast(tc->getMMUPtr()->itb);
switch (asi) {
case ASI_LSU_CONTROL_REG:
@@ -1151,7 +1152,7 @@
DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
(uint32_t)asi, va, data);
-TLB *itb = dynamic_cast(tc->getITBPtr());
+TLB *itb = static_cast(tc->getMMUPtr()->itb);
switch (asi) {
case ASI_LSU_CONTROL_REG:
@@ -1388,7 +1389,7 @@
TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{
uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
-TLB *itb = dynamic_cast(tc->getITBPtr());
+TLB *itb = static_cast(tc->getMMUPtr()->itb);
ptrs[0] = MakeTsbPtr(Ps0, tag_access,
c0_tsb_ps0,
c0_config,
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 9291343..4a15b8f 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -49,9 +49,7 @@
class TLB : public BaseTLB
{
-// These faults need to be able to populate the tlb in SE mode.
-friend class FastInstructionAccessMMUMiss;
-friend class FastDataAccessMMUMiss;
+friend class MMU;
// TLB state
protected:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34982
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
[gem5-dev] Change in gem5/gem5[develop]: misc: Fix a parameter name in a DeprecatedParam message
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36635 )
Change subject: misc: Fix a parameter name in a DeprecatedParam message
..
misc: Fix a parameter name in a DeprecatedParam message
Change-Id: Ie84a29e779187effea372c6289688f32a1db075d
Signed-off-by: Hoa Nguyen
---
M src/mem/ruby/system/Sequencer.py
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 0acd87a..0e23fc0 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -52,7 +52,7 @@
"has multiple ports (e.g., I/D ports) all of the ports for
a "
"single CPU can connect to one RubyPort.")
slave= DeprecatedParam(in_ports,
-'`slave` is now called `in_port`')
+'`slave` is now called `in_ports`')
interrupt_out_port = VectorRequestPort("Port to connect to x86
interrupt "
"controller to send the CPU requests from
outside.")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36635
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie84a29e779187effea372c6289688f32a1db075d
Gerrit-Change-Number: 36635
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Simplifying PixelPump
Hi folks. While looking into ways to speed up the ARM HDLCD device, I started looking at how PixelPump was implemented. There is a LOT of events being scheduled, incremental work, etc. It seems to me that while this might all be really flexible and accurate, it probably also has really significant performance overhead. For instance, do we need to keep track of what line of the screen we're on, scheduling and rescheduling events for it, calling a virtual function to notify a subclass, if nobody is actually paying attention? Do we need to convert pixels in small batches of 32? Or could we gather up a whole line (or a whole frame) and convert everything at once? Maybe defer until somebody actually needs to look at the framebuffer and then convert everything outstanding? I think if this was done carefully, the potential speed up would be significant and the loss of fidelity would be minor or none at all. I'm mostly looking at this code for the first time though, so there may be a lot of context I'm missing or things I'm not thinking of. Could someone please let me know if there's more to it than that? Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] event/callback/etc called before simulator exits
Hi folks. To try to speed up simulation, I was thinking of pulling some unidirectional processing (ie things which leave gem5 and don't loop back in) out of the critical path and farm them out to threads. I'm specifically thinking of the code that creates framebuffer images, and potentially code that feeds things to VNC. This is particularly important when the simulation is otherwise sped up with, for instance, KVM or Fast Models. Since some output will be coming from threads which may not be finished when gem5 is ready to exit (or crashes, or ...), I want to be able to ensure that gem5 will wait for them before shutting down. I wouldn't want to lose information that might be critical for debugging a crash because it was being written out asynchronously. Is there any way to hook into something like that? I'd just want to join any threads which are not yet finished running. Or is this something the std::thread implementation will do for us automatically? That would be nice, but I doubt it! Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Replace any getDTBPtr/getITBPtr usage
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34980 )
Change subject: arch-riscv: Replace any getDTBPtr/getITBPtr usage
..
arch-riscv: Replace any getDTBPtr/getITBPtr usage
The getMMUPtr should be used instead
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34980
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/mmu.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/tlb.cc
5 files changed, 25 insertions(+), 10 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index b39005f..5ef68fe 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1848,8 +1848,7 @@
"sfence in user mode or TVM
enabled",
machInst);
}
-xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);
-xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2);
+xc->tcBase()->getMMUPtr()->demapPage(Rs1, Rs2);
}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
0x18: mret({{
if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 16114c9..009f143 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -61,7 +61,7 @@
#include "arch/riscv/decoder.hh"
#include "arch/riscv/faults.hh"
-#include "arch/riscv/tlb.hh"
+#include "arch/riscv/mmu.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
@@ -81,6 +81,7 @@
#include "arch/generic/memhelpers.hh"
#include "arch/riscv/faults.hh"
+#include "arch/riscv/mmu.hh"
#include "arch/riscv/registers.hh"
#include "arch/riscv/utility.hh"
#include "base/condcodes.hh"
diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh
index d10ce13..322f0af 100644
--- a/src/arch/riscv/mmu.hh
+++ b/src/arch/riscv/mmu.hh
@@ -39,6 +39,8 @@
#define __ARCH_RISCV_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/riscv/isa.hh"
+#include "arch/riscv/tlb.hh"
#include "params/RiscvMMU.hh"
@@ -50,6 +52,18 @@
MMU(const RiscvMMUParams )
: BaseMMU(p)
{}
+
+PrivilegeMode
+getMemPriv(ThreadContext *tc, BaseTLB::Mode mode)
+{
+return static_cast(dtb)->getMemPriv(tc, mode);
+}
+
+Walker *
+getDataWalker()
+{
+return static_cast(dtb)->getWalker();
+}
};
} // namespace RiscvISA
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 7da666d..0e4c544 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -134,9 +134,9 @@
#include
+#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/registers.hh"
-#include "arch/riscv/tlb.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "mem/page_table.hh"
@@ -155,15 +155,15 @@
{
if (FullSystem)
{
-TLB *tlb = dynamic_cast(context()->getDTBPtr());
+MMU *mmu = static_cast(context()->getMMUPtr());
unsigned logBytes;
Addr paddr = va;
-PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+PrivilegeMode pmode = mmu->getMemPriv(context(), BaseTLB::Read);
SATP satp = context()->readMiscReg(MISCREG_SATP);
if (pmode != PrivilegeMode::PRV_M &&
satp.mode != AddrXlateMode::BARE) {
-Walker *walker = tlb->getWalker();
+Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(
context(), paddr, logBytes, BaseTLB::Read);
if (fault != NoFault)
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 883a6ca..62517e9 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -35,6 +35,7 @@
#include "arch/riscv/faults.hh"
#include "arch/riscv/fs_workload.hh"
+#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/pra_constants.hh"
@@ -411,13 +412,13 @@
Addr paddr = vaddr;
if (FullSystem) {
-TLB *tlb = dynamic_cast(tc->getDTBPtr());
+MMU *mmu = static_cast(tc->getMMUPtr());
-PrivilegeMode pmode = tlb->getMemPriv(tc, mode);
+PrivilegeMode pmode = mmu->getMemPriv(tc, mode);
SATP satp = tc->readMiscReg(MISCREG_SATP);
if (pmode !=
[gem5-dev] Change in gem5/gem5[develop]: sparc: Remove support for Solaris SE mode.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33996 )
Change subject: sparc: Remove support for Solaris SE mode.
..
sparc: Remove support for Solaris SE mode.
In SPARC and SE mode, system calls are triggered by a trap exception
with the appropriate trap number, and then a handler within the Workload
(formerly the Process) object recognizes the trap number and triggers
the system call.
For Linux, this special handling happens in the Linux specific Workload,
and other types of traps are passed through to the base SPARC SE
Workload class. For Solaris however, no special handling is implemented.
That means that it's actually impossible for a Solaris SE mode program
to actually trigger a system call, and so while there is some code
written for Solaris SE mode, this feature does not actually work at all.
Also, while it's relatively easy to build binaries for Linux on various
architectures using, for instance, the crosstool-ng configs in util/,
there is no ready made option that I could find for building a SPARC
Solaris cross compiler which would run on x86 linux.
Given that the support that exists isn't actually hooked up properly,
SPARC is not one of the most popular ISAs within gem5, Solaris is not a
widely used operating system, we have (to my knowledge) no test binary
to run, and setting up a cross compiler would be non-trivial, it makes
the most sense to me to remove this support.
Change-Id: I896b5abc4bf337bd4e4c06c49de7111a3b2b784c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33996
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/sparc/SConscript
M src/arch/sparc/SparcSeWorkload.py
D src/arch/sparc/solaris/se_workload.cc
D src/arch/sparc/solaris/se_workload.hh
4 files changed, 0 insertions(+), 437 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 7ba6d10..700c076 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -44,7 +44,6 @@
Source('process.cc')
Source('remote_gdb.cc')
Source('se_workload.cc')
-Source('solaris/se_workload.cc')
Source('solaris/solaris.cc')
Source('tlb.cc')
Source('ua2005.cc')
diff --git a/src/arch/sparc/SparcSeWorkload.py
b/src/arch/sparc/SparcSeWorkload.py
index 03d4b73..75327ed 100644
--- a/src/arch/sparc/SparcSeWorkload.py
+++ b/src/arch/sparc/SparcSeWorkload.py
@@ -42,13 +42,3 @@
def _is_compatible_with(cls, obj):
return obj.get_arch() in ('sparc64', 'sparc32') and \
obj.get_op_sys() in ('linux', 'unknown')
-
-class SparcEmuSolaris(SparcSEWorkload):
-type = 'SparcEmuSolaris'
-cxx_header = "arch/sparc/solaris/se_workload.hh"
-cxx_class = 'SparcISA::EmuSolaris'
-
-@classmethod
-def _is_compatible_with(cls, obj):
-return obj.get_arch() in ('sparc64', 'sparc32') and \
-obj.get_op_sys() == 'solaris'
diff --git a/src/arch/sparc/solaris/se_workload.cc
b/src/arch/sparc/solaris/se_workload.cc
deleted file mode 100644
index 9372f15..000
--- a/src/arch/sparc/solaris/se_workload.cc
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- * Copyright 2020 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/solaris/se_workload.hh"
-
-#include
-
-#include "arch/sparc/process.hh"
-#include
