Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34982 )
Change subject: arch-sparc: Replace any getDTBPtr/getITBPtr usage
......................................................................
arch-sparc: Replace any getDTBPtr/getITBPtr usage
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34982
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/sparc/faults.cc
M src/arch/sparc/mmu.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
4 files changed, 29 insertions(+), 11 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 33ba921..53e7576 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -30,9 +30,9 @@
#include <algorithm>
+#include "arch/sparc/mmu.hh"
#include "arch/sparc/process.hh"
#include "arch/sparc/se_workload.hh"
-#include "arch/sparc/tlb.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
@@ -669,8 +669,9 @@
// false for syscall emulation mode regardless of whether the
// address is real in preceding code. Not sure sure that this is
// correct, but also not sure if it matters at all.
- dynamic_cast<TLB *>(tc->getITBPtr())->
- insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+ static_cast<MMU *>(tc->getMMUPtr())->insertItlbEntry(
+ alignedvaddr, partition_id, context_id,
+ false, entry.pte);
}
void
@@ -756,8 +757,9 @@
// false for syscall emulation mode regardless of whether the
// address is real in preceding code. Not sure sure that this is
// correct, but also not sure if it matters at all.
- dynamic_cast<TLB *>(tc->getDTBPtr())->
- insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+ static_cast<MMU *>(tc->getMMUPtr())->insertDtlbEntry(
+ alignedvaddr, partition_id, context_id,
+ false, entry.pte);
}
void
diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh
index 39f5008..f784015 100644
--- a/src/arch/sparc/mmu.hh
+++ b/src/arch/sparc/mmu.hh
@@ -39,6 +39,7 @@
#define __ARCH_SPARC_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/sparc/tlb.hh"
#include "params/SparcMMU.hh"
@@ -50,6 +51,22 @@
MMU(const SparcMMUParams &p)
: BaseMMU(p)
{}
+
+ void
+ insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real,
+ const PageTableEntry& PTE, int entry=-1)
+ {
+ static_cast<TLB*>(itb)->insert(vpn, partition_id,
+ context_id, real, PTE, entry);
+ }
+
+ void
+ insertDtlbEntry(Addr vpn, int partition_id, int context_id, bool real,
+ const PageTableEntry& PTE, int entry=-1)
+ {
+ static_cast<TLB*>(dtb)->insert(vpn, partition_id,
+ context_id, real, PTE, entry);
+ }
};
} // namespace SparcISA
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 20f316f..9dde4ef 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -33,6 +33,7 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/faults.hh"
#include "arch/sparc/interrupts.hh"
+#include "arch/sparc/mmu.hh"
#include "arch/sparc/registers.hh"
#include "base/bitfield.hh"
#include "base/compiler.hh"
@@ -955,7 +956,7 @@
DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
(uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
- TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+ TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
switch (asi) {
case ASI_LSU_CONTROL_REG:
@@ -1151,7 +1152,7 @@
DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
(uint32_t)asi, va, data);
- TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+ TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
switch (asi) {
case ASI_LSU_CONTROL_REG:
@@ -1388,7 +1389,7 @@
TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{
uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
- TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+ TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
ptrs[0] = MakeTsbPtr(Ps0, tag_access,
c0_tsb_ps0,
c0_config,
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 9291343..4a15b8f 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -49,9 +49,7 @@
class TLB : public BaseTLB
{
- // These faults need to be able to populate the tlb in SE mode.
- friend class FastInstructionAccessMMUMiss;
- friend class FastDataAccessMMUMiss;
+ friend class MMU;
// TLB state
protected:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34982
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Gerrit-Change-Number: 34982
Gerrit-PatchSet: 18
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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