[gem5-dev] Change in gem5/gem5[develop]: mem-cache, stats: Stats update for snoop filter
Maryam Babaie has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36355 )
Change subject: mem-cache, stats: Stats update for snoop filter
..
mem-cache, stats: Stats update for snoop filter
Change-Id: I339bbc4268d5b9501421a2a6a76e5267422c87aa
Signed-off-by: Maryam Babaie
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36355
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
2 files changed, 36 insertions(+), 41 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/snoop_filter.cc b/src/mem/snoop_filter.cc
index 7ced30c..d799707 100644
--- a/src/mem/snoop_filter.cc
+++ b/src/mem/snoop_filter.cc
@@ -97,12 +97,12 @@
// updateRequest.
reqLookupResult.retryItem = sf_item;
-totRequests++;
+stats.totRequests++;
if (is_hit) {
if (interested.count() == 1)
-hitSingleRequests++;
+stats.hitSingleRequests++;
else
-hitMultiRequests++;
+stats.hitMultiRequests++;
}
DPRINTF(SnoopFilter, "%s: SF value %x.%x\n",
@@ -207,12 +207,12 @@
SnoopMask interested = (sf_item.holder | sf_item.requested);
-totSnoops++;
+stats.totSnoops++;
if (interested.count() == 1)
-hitSingleSnoops++;
+stats.hitSingleSnoops++;
else
-hitMultiSnoops++;
+stats.hitMultiSnoops++;
// ReadEx and Writes require both invalidation and exlusivity, while
reads
// require neither. Writebacks on the other hand require exclusivity
but
@@ -387,36 +387,26 @@
__func__, sf_item.requested, sf_item.holder);
}
+SnoopFilter::SnoopFilterStats::SnoopFilterStats(Stats::Group *parent):
+Stats::Group(parent),
+ADD_STAT(totRequests,"Total number of requests made to the snoop filter."),
+ADD_STAT(hitSingleRequests,
+ "Number of requests hitting in the snoop filter with a
single "\
+ "holder of the requested data."),
+ADD_STAT(hitMultiRequests,
+ "Number of requests hitting in the snoop filter with
multiple "\
+ "(>1) holders of the requested data."),
+ADD_STAT(totSnoops,"Total number of snoops made to the snoop filter."),
+ADD_STAT(hitSingleSnoops,
+ "Number of snoops hitting in the snoop filter with a
single "\
+ "holder of the requested data."),
+ADD_STAT(hitMultiSnoops,
+ "Number of snoops hitting in the snoop filter with
multiple "\
+ "(>1) holders of the requested data.")
+{}
+
void
SnoopFilter::regStats()
{
SimObject::regStats();
-
-totRequests
-.name(name() + ".tot_requests")
-.desc("Total number of requests made to the snoop filter.");
-
-hitSingleRequests
-.name(name() + ".hit_single_requests")
-.desc("Number of requests hitting in the snoop filter with a
single "\
- "holder of the requested data.");
-
-hitMultiRequests
-.name(name() + ".hit_multi_requests")
-.desc("Number of requests hitting in the snoop filter with
multiple "\
- "(>1) holders of the requested data.");
-
-totSnoops
-.name(name() + ".tot_snoops")
-.desc("Total number of snoops made to the snoop filter.");
-
-hitSingleSnoops
-.name(name() + ".hit_single_snoops")
-.desc("Number of snoops hitting in the snoop filter with a
single "\
- "holder of the requested data.");
-
-hitMultiSnoops
-.name(name() + ".hit_multi_snoops")
-.desc("Number of snoops hitting in the snoop filter with
multiple "\
- "(>1) holders of the requested data.");
}
diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh
index 8150494..abd66a8 100644
--- a/src/mem/snoop_filter.hh
+++ b/src/mem/snoop_filter.hh
@@ -94,7 +94,8 @@
SnoopFilter (const SnoopFilterParams ) :
SimObject(p), reqLookupResult(cachedLocations.end()),
linesize(p.system->cacheLineSize()),
lookupLatency(p.lookup_latency),
-maxEntryCount(p.max_capacity / p.system->cacheLineSize())
+maxEntryCount(p.max_capacity / p.system->cacheLineSize()),
+stats(this)
{
}
@@ -310,13 +311,17 @@
};
/** Statistics */
-Stats::Scalar totRequests;
-Stats::Scalar hitSingleRequests;
-Stats::Scalar hitMultiRequests;
+struct SnoopFilterStats : public Stats::Group {
+SnoopFilterStats(Stats::Group *parent);
-Stats::Scalar totSnoops;
-Stats::Scalar hitSingleSnoops;
-Stats::Scalar hitMultiSnoops;
+Stats::Scalar totRequests;
+Stats::Scalar hitSingleRequests;
+Stats::Scalar hitMultiRequests;
+
+Stats::Scalar totSnoops;
+Stats::Scalar hitSingleSnoops;
+
[gem5-dev] Change in gem5/gem5[develop]: mips: Convert MIPS to use local register index storage.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36880 )
Change subject: mips: Convert MIPS to use local register index storage.
..
mips: Convert MIPS to use local register index storage.
Change-Id: Ib691f3dd666c0877fc53b2f50dbaaf7bb4a6905b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36880
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/mips/isa/formats/basic.isa
M src/arch/mips/isa/formats/mem.isa
2 files changed, 14 insertions(+), 7 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/mips/isa/formats/basic.isa
b/src/arch/mips/isa/formats/basic.isa
index 17d08ef..765dae2 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -35,19 +35,23 @@
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+%(reg_idx_arr_decl)s;
public:
-/// Constructor.
-%(class_name)s(MachInst machInst);
-Fault execute(ExecContext *,
- Trace::InstRecord *) const override;
+/// Constructor.
+%(class_name)s(MachInst machInst);
+Fault execute(ExecContext *,
+ Trace::InstRecord *) const override;
};
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
-%(class_name)s::%(class_name)s(MachInst
machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+%(class_name)s::%(class_name)s(MachInst machInst) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
-%(constructor)s;
+%(set_reg_idx_arr)s;
+%(constructor)s;
}
}};
diff --git a/src/arch/mips/isa/formats/mem.isa
b/src/arch/mips/isa/formats/mem.isa
index a31485d..ac56803 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -129,8 +129,10 @@
*/
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+%(reg_idx_arr_decl)s;
+ public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
@@ -146,6 +148,7 @@
%(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36880
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib691f3dd666c0877fc53b2f50dbaaf7bb4a6905b
Gerrit-Change-Number: 36880
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sparc: Convert SPARC to use local register index storage.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36879 )
Change subject: sparc: Convert SPARC to use local register index storage.
..
sparc: Convert SPARC to use local register index storage.
Once all ISAs are converted, the base StaticInst class will be able to
drop its local arrays, and will no longer need to know what the global
maximum number of source or destination registers is for a given
instruction.
Most of the convertion was very simple and just involved adding tags to
declare and install the register arrays in all the class definitions.
Since SPARC has a relatively simple ISA definition, there weren't many
places that needed to be updated.
The exception was the BlockMem template, which was declaring the microop
classes within the body of the macroop. That was ok when those
declarations didn't need anything other than the name of their parent,
but now they also need to know how big to declare their arrays based on
their actual implementation.
To facilitate that, and to significantly streamline the definition of
the macroop class, the microop class definitions were moved to their own
template, and only the declaration was left in the parent class.
Change-Id: I09e6b1d1041c6a0aeaee63ce5f9a18cf482b6203
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36879
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/sparc/isa/formats/basic.isa
M src/arch/sparc/isa/formats/mem/basicmem.isa
M src/arch/sparc/isa/formats/mem/blockmem.isa
M src/arch/sparc/isa/formats/nop.isa
M src/arch/sparc/isa/formats/priv.isa
5 files changed, 62 insertions(+), 114 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/sparc/isa/formats/basic.isa
b/src/arch/sparc/isa/formats/basic.isa
index 9ab7699..8a3f174 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -31,6 +31,9 @@
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+%(reg_idx_arr_decl)s;
+
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
@@ -45,6 +48,9 @@
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+%(reg_idx_arr_decl)s;
+
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
@@ -60,6 +66,9 @@
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+%(reg_idx_arr_decl)s;
+
public:
// Constructor.
%(class_name)s(const char *mnemonic, ExtMachInst machInst);
@@ -72,6 +81,7 @@
%(class_name)s::%(class_name)s(ExtMachInst machInst) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -81,6 +91,7 @@
%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst
machInst) :
%(base_class)s(mnemonic, machInst, %(op_class)s)
{
+%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa
b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 2850d32..0354478 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -37,6 +37,9 @@
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+%(reg_idx_arr_decl)s;
+
public:
/// Constructor.
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa
b/src/arch/sparc/isa/formats/mem/blockmem.isa
index b79eb3f..fb9cfc4 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -30,120 +30,43 @@
//
def template BlockMemDeclare {{
-/**
- * Static instruction class for a block memory operation
- */
-class %(class_name)s : public %(base_class)s
-{
- public:
-// Constructor
-%(class_name)s(ExtMachInst machInst);
+/**
+ * Static instruction class for a block memory operation
+ */
+class %(class_name)s : public %(base_class)s
+{
+ public:
+// Constructor
+%(class_name)s(ExtMachInst machInst);
- protected:
-class %(class_name)s_0 : public %(base_class)sMicro
-{
- public:
-// Constructor
-%(class_name)s_0(ExtMachInst machInst);
-Fault execute(ExecContext *,
- Trace::InstRecord *) const override;
-Fault initiateAcc(ExecContext *,
- Trace::InstRecord *) const override;
-Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
-};
+ protected:
+class %(class_name)s_0;
+class %(class_name)s_1;
+class %(class_name)s_2;
[gem5-dev] Change in gem5/gem5[develop]: x86: Convert X86 to use local reg index storage.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36883 )
Change subject: x86: Convert X86 to use local reg index storage.
..
x86: Convert X86 to use local reg index storage.
Change-Id: I42bd3e08ebcffe25e2f366be82702b3c04225e92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36883
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/isa/formats/basic.isa
M src/arch/x86/isa/formats/monitor_mwait.isa
M src/arch/x86/isa/microops/debug.isa
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/ldstop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/isa/microops/seqop.isa
M src/arch/x86/isa/microops/specop.isa
10 files changed, 91 insertions(+), 29 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/formats/basic.isa
b/src/arch/x86/isa/formats/basic.isa
index cd9ec9e..32e4087 100644
--- a/src/arch/x86/isa/formats/basic.isa
+++ b/src/arch/x86/isa/formats/basic.isa
@@ -38,25 +38,29 @@
// Basic instruction class declaration template.
def template BasicDeclare {{
-/**
- * Static instruction class for "%(mnemonic)s".
- */
-class %(class_name)s : public %(base_class)s
-{
- public:
-// Constructor.
-%(class_name)s(ExtMachInst machInst);
-Fault execute(ExecContext *, Trace::InstRecord *) const
override;
-};
+/**
+ * Static instruction class for "%(mnemonic)s".
+ */
+class %(class_name)s : public %(base_class)s
+{
+ private:
+%(reg_idx_arr_decl)s;
+
+ public:
+// Constructor.
+%(class_name)s(ExtMachInst machInst);
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+};
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst machInst)
-: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
-{
-%(constructor)s;
-}
+%(class_name)s::%(class_name)s(ExtMachInst machInst) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
}};
// Basic instruction class execute method template.
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa
b/src/arch/x86/isa/formats/monitor_mwait.isa
index 99fc85b..2d25db1 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -47,7 +47,10 @@
def template MwaitDeclare {{
class %(class_name)s : public %(base_class)s
{
-public:
+ private:
+%(reg_idx_arr_decl)s;
+
+ public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
diff --git a/src/arch/x86/isa/microops/debug.isa
b/src/arch/x86/isa/microops/debug.isa
index b7e3a9c..326f245 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -68,19 +68,6 @@
return response.str();
}
};
-
-class MicroDebugFlags : public MicroDebug
-{
- protected:
-uint8_t cc;
-
- public:
-MicroDebugFlags(ExtMachInst _machInst, const char *mnem,
-const char *instMnem, uint64_t setFlags,
-GenericISA::M5DebugFault *_fault, uint8_t _cc);
-
-Fault execute(ExecContext *, Trace::InstRecord *) const override;
-};
}};
output decoder {{
@@ -93,6 +80,24 @@
{}
}};
+def template MicroDebugFlagsDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ private:
+%(reg_idx_arr_decl)s;
+
+ protected:
+uint8_t cc;
+
+ public:
+%(class_name)s(ExtMachInst _machInst, const char *mnem,
+ const char *instMnem, uint64_t setFlags,
+ GenericISA::M5DebugFault *_fault, uint8_t _cc);
+
+Fault execute(ExecContext *, Trace::InstRecord *) const override;
+};
+}};
+
def template MicroDebugFlagsExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
@@ -116,6 +121,7 @@
%(base_class)s(machInst, mnem, instMnem, setFlags, _fault),
cc(_cc)
{
+%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -125,6 +131,8 @@
{"code": "",
"cond_test": "checkCondition(ccFlagBits | cfofBits | \
dfBit | ecfBit | ezfBit,
cc)"})
+
+header_output = MicroDebugFlagsDeclare.subst(iop)
exec_output = MicroDebugFlagsExecute.subst(iop)
decoder_output = MicroDebugFlagsConstructor.subst(iop)
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Update stats of AbstractController and derived classes
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37937 )
Change subject: mem-ruby: Update stats of AbstractController and derived
classes
..
mem-ruby: Update stats of AbstractController and derived classes
Change-Id: Ia125ef0c3e9112ca7fe709e4a1b2bd343042a52f
Signed-off-by: Hoa Nguyen
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
3 files changed, 112 insertions(+), 100 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 1e8d8e0..f8eae37 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -56,7 +56,8 @@
m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
m_mandatory_queue_latency(p.mandatory_queue_latency),
memoryPort(csprintf("%s.memory", name()), this),
- addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
+ addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
+ stats(this)
{
if (m_version == 0) {
// Combine the statistics from all controllers
@@ -68,11 +69,11 @@
void
AbstractController::init()
{
-m_delayHistogram.init(10);
+stats.m_delayHistogram.init(10);
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
-m_delayVCHistogram.push_back(new Stats::Histogram());
-m_delayVCHistogram[i]->init(10);
+stats.m_delayVCHistogram.push_back(new Stats::Histogram(this));
+stats.m_delayVCHistogram[i]->init(10);
}
if (getMemReqQueue()) {
@@ -106,10 +107,10 @@
void
AbstractController::resetStats()
{
-m_delayHistogram.reset();
+stats.m_delayHistogram.reset();
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
-m_delayVCHistogram[i]->reset();
+stats.m_delayVCHistogram[i]->reset();
}
}
@@ -117,19 +118,14 @@
AbstractController::regStats()
{
ClockedObject::regStats();
-
-m_fully_busy_cycles
-.name(name() + ".fully_busy_cycles")
-.desc("cycles for which number of transistions == max transitions")
-.flags(Stats::nozero);
}
void
AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
{
-assert(virtualNetwork < m_delayVCHistogram.size());
-m_delayHistogram.sample(delay);
-m_delayVCHistogram[virtualNetwork]->sample(delay);
+assert(virtualNetwork < stats.m_delayVCHistogram.size());
+stats.m_delayHistogram.sample(delay);
+stats.m_delayVCHistogram[virtualNetwork]->sample(delay);
}
void
@@ -423,3 +419,15 @@
: RequestPort(_name, _controller, id), controller(_controller)
{
}
+
+AbstractController::
+ControllerStats::ControllerStats(Stats::Group *parent)
+: Stats::Group(parent, "Controller"),
+ m_fully_busy_cycles(this, "fully_busy_cycles",
+ "cycles for which number of transistions == max "
+ "transitions"),
+ m_delayHistogram(this, "delay_histogram")
+{
+m_fully_busy_cycles
+.flags(Stats::nozero);
+}
\ No newline at end of file
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 8e19195..7dc2e42 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -151,9 +151,9 @@
MachineID getMachineID() const { return m_machineID; }
RequestorID getRequestorId() const { return m_id; }
-Stats::Histogram& getDelayHist() { return m_delayHistogram; }
+Stats::Histogram& getDelayHist() { return stats.m_delayHistogram; }
Stats::Histogram& getDelayVCHist(uint32_t index)
-{ return *(m_delayVCHistogram[index]); }
+{ return *(stats.m_delayVCHistogram[index]); }
bool respondsTo(Addr addr)
{
@@ -204,14 +204,6 @@
std::unordered_map m_inTrans;
std::unordered_map m_outTrans;
-// Initialized by the SLICC compiler for all combinations of event and
-// states. Only histograms with samples will appear in the stats
-std::vector>>
m_inTransLatHist;
-
-// Initialized by the SLICC compiler for all events.
-// Only histograms with samples will appear in the stats.
-std::vector m_outTransLatHist;
-
/**
* Profiles an event that initiates a protocol transactions for a
specific
* line (e.g. events triggered by incoming request messages).
@@ -241,7 +233,7 @@
{
auto iter = m_inTrans.find(addr);
assert(iter != m_inTrans.end());
-m_inTransLatHist[iter->second.transaction]
+stats.m_inTransLatHist[iter->second.transaction]
[iter->second.state]
[gem5-dev] Change in gem5/gem5[develop]: dev: Set the "status" field of the HDLCD device tree nod to "ok".
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37936 )
Change subject: dev: Set the "status" field of the HDLCD device tree nod
to "ok".
..
dev: Set the "status" field of the HDLCD device tree nod to "ok".
This makes the kernel enable the device.
Change-Id: I2c237b9ba038c5128e2a7e020587ac46ef7b4abd
---
M src/dev/arm/RealView.py
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 1d3b54c..4418ea5 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -516,7 +516,7 @@
pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one
batch")
virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
"in KVM mode")
-_status = "disabled"
+_status = "ok"
encoder = Param.Display(Display1080p(), "Display encoder")
--
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Gerrit-Change-Id: I2c237b9ba038c5128e2a7e020587ac46ef7b4abd
Gerrit-Change-Number: 37936
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev: Set frequency ranges in OSC device tree nodes.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37935 )
Change subject: dev: Set frequency ranges in OSC device tree nodes.
..
dev: Set frequency ranges in OSC device tree nodes.
The existing device tree generation method would the default frequency
as both the min and max frequency when setting up the OSC device tree
nodes. This would sort of work, except it seems that if the kernel
needed to adjust a frequency, it would fail to do so since it would
assume the new frequency was out of range.
Since the existing property is used to set the initial frequency of
those clocks, and because the default, min and max frequencies are all
mostly independent variables (other than obvious ordering restrictions),
two new properties were added, min_freq and max_freq, which are only
there to fill in the frequency range property in the device tree. If
they aren't set, then the device tree generation method falls back to
the old way of using the default frequency as both min and max.
Change-Id: Ie907bd673f8bcb149e69e45c5b486863149b8a68
---
M src/dev/arm/RealView.py
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index bf8e0e6..1d3b54c 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -244,6 +244,10 @@
freq = Param.Clock("Default frequency")
+# These are currently only used for the device tree.
+min_freq = Param.Clock("0t", "Minimum frequency")
+max_freq = Param.Clock("0t", "Maximum frequency")
+
def generateDeviceTree(self, state):
phandle = state.phandle(self)
node = FdtNode("osc@" + format(long(phandle), 'x'))
@@ -251,8 +255,16 @@
node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
[0x1, int(self.device)]))
node.append(FdtPropertyWords("#clock-cells", [0]))
-freq = int(1.0/self.freq.value) # Values are stored as a clock
period
-node.append(FdtPropertyWords("freq-range", [freq, freq]))
+
+minf = self.min_freq if self.min_freq.value else self.freq
+maxf = self.max_freq if self.max_freq.value else self.freq
+
+# Values are stored as a clock period.
+def to_freq(prop):
+return int(1.0 / prop.value)
+
+node.append(FdtPropertyWords("freq-range",
+ [to_freq(minf), to_freq(maxf)]))
node.append(FdtPropertyStrings("clock-output-names",
["oscclk" + str(phandle)]))
node.appendPhandle(self)
@@ -288,10 +300,12 @@
class Temperature(RealViewTemperatureSensor):
site, position, dcc = (0, 0, 0)
-osc_mcc = Osc(device=0, freq="50MHz")
-osc_clcd = Osc(device=1, freq="23.75MHz")
+osc_mcc = Osc(device=0, min_freq="25MHz", max_freq="60MHz",
freq="50MHz")
+osc_clcd = Osc(device=1, min_freq="23.76MHz", max_freq="63.5MHz",
+ freq="23.75MHz")
osc_peripheral = Osc(device=2, freq="24MHz")
-osc_system_bus = Osc(device=4, freq="24MHz")
+osc_system_bus = Osc(device=4, min_freq="2MHz", max_freq="230MHz",
+ freq="24MHz")
# See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
temp_crtl = Temperature(device=0)
@@ -322,11 +336,12 @@
site, position, dcc = (1, 0, 0)
# See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
-osc_cpu = Osc(device=0, freq="60MHz")
-osc_hsbm = Osc(device=4, freq="40MHz")
-osc_pxl = Osc(device=5, freq="23.75MHz")
-osc_smb = Osc(device=6, freq="50MHz")
-osc_sys = Osc(device=7, freq="60MHz")
+osc_cpu = Osc(device=0, min_freq="20MHz", max_freq="60MHz",
freq="60MHz")
+osc_hsbm = Osc(device=4, min_freq="20MHz", max_freq="40MHz",
freq="40MHz")
+osc_pxl = Osc(device=5, min_freq="23.76MHz", max_freq="165MHz",
+ freq="23.75MHz")
+osc_smb = Osc(device=6, min_freq="20MHz", max_freq="50MHz",
freq="50MHz")
+osc_sys = Osc(device=7, min_freq="20MHz", max_freq="20MHz",
freq="60MHz")
osc_ddr = Osc(device=8, freq="40MHz")
def generateDeviceTree(self, state):
--
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[gem5-dev] Change in gem5/gem5[develop]: arm: Use the common pseudoInst dispatch function.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27791 )
Change subject: arm: Use the common pseudoInst dispatch function.
..
arm: Use the common pseudoInst dispatch function.
Instead of manually calling each of the PseudoInst implementations, this
function will automatically pick up new instructions and greatly
simplifies the ARM ISA files.
Change-Id: I6cb94b3d115f50d681ca855f80f9d7d3df6bc470
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27791
Reviewed-by: Bobby R. Bruce
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/decoder/arm.isa
M src/arch/arm/isa/decoder/thumb.isa
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
D src/arch/arm/isa/formats/m5ops.isa
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/isa/insts/m5ops.isa
7 files changed, 32 insertions(+), 682 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/decoder/arm.isa
b/src/arch/arm/isa/decoder/arm.isa
index 838e27b..0349b39 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -119,7 +119,7 @@
0xa, 0xb: VfpData::vfpData();
} // CPNUM
1: decode CPNUM { // 27-24=1110,4 ==1
-0x1: M5ops::m5ops();
+0x1: Gem5Op::gem5op();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
diff --git a/src/arch/arm/isa/decoder/thumb.isa
b/src/arch/arm/isa/decoder/thumb.isa
index c319ec3..1509cc3 100644
--- a/src/arch/arm/isa/decoder/thumb.isa
+++ b/src/arch/arm/isa/decoder/thumb.isa
@@ -82,7 +82,7 @@
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
-0x1: M5ops::m5ops();
+0x1: Gem5Op::gem5op();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
@@ -147,7 +147,7 @@
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
-0x1: M5ops::m5ops();
+0x1: Gem5Op::gem5op();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 9a487ea..a873b1e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -3029,47 +3029,6 @@
}'''
}};
-output decoder {{
-namespace Aarch64
-{
-StaticInstPtr
-decodeGem5Ops(ExtMachInst machInst)
-{
-const uint32_t m5func = bits(machInst, 23, 16);
-switch (m5func) {
- case M5OP_ARM: return new Arm(machInst);
- case M5OP_QUIESCE: return new Quiesce(machInst);
- case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst);
- case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst);
- case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst);
- case M5OP_RPNS: return new Rpns64(machInst);
- case M5OP_WAKE_CPU: return new WakeCPU64(machInst);
- case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
- case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
- case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
- case M5OP_EXIT: return new M5exit64(machInst);
- case M5OP_FAIL: return new M5fail64(machInst);
- case M5OP_SUM: return new M5sum64(machInst);
- case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
- case M5OP_INIT_PARAM: return new Initparam64(machInst);
- case M5OP_RESET_STATS: return new Resetstats64(machInst);
- case M5OP_DUMP_STATS: return new Dumpstats64(machInst);
- case M5OP_DUMP_RESET_STATS: return new
Dumpresetstats64(machInst);
- case M5OP_CHECKPOINT: return new M5checkpoint64(machInst);
- case M5OP_WRITE_FILE: return new M5writefile64(machInst);
- case M5OP_READ_FILE: return new M5readfile64(machInst);
- case M5OP_DEBUG_BREAK: return new M5break(machInst);
- case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
- case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst);
- case M5OP_PANIC: return new M5panic(machInst);
- case M5OP_WORK_BEGIN: return new M5workbegin64(machInst);
- case M5OP_WORK_END: return new M5workend64(machInst);
- default: return new Unknown64(machInst);
-}
-}
[gem5-dev] Change in gem5/gem5[develop]: sim: ScopedCheckpointSection to public for mappingParamIn
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37915 )
Change subject: sim: ScopedCheckpointSection to public for mappingParamIn
..
sim: ScopedCheckpointSection to public for mappingParamIn
In clang, the following error was given:
```
In file included from build/X86/sim/eventq.hh:51:
build/X86/sim/serialize.hh:533:19: error: 'ScopedCheckpointSection' is a
protected member of 'Serializable'
Serializable::ScopedCheckpointSection sec(os, sectionName);
^
build/X86/sim/serialize.hh:175:11: note: declared protected here
class ScopedCheckpointSection {
^
```
The use, at line 533, was introduced in this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/36135
This can be fixed by making ScopedCheckpointSection public.
Change-Id: Ib6ffba18d5e8c37980d4febb548f2405cb45ce8c
---
M src/sim/serialize.hh
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 987bee2..9e25d09 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -171,7 +171,7 @@
*/
class Serializable
{
- protected:
+ public:
class ScopedCheckpointSection {
public:
/**
@@ -224,7 +224,6 @@
void nameOut(CheckpointIn ) {};
};
- public:
/**
* @ingroup api_serialize
*/
--
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Gerrit-Change-Id: Ib6ffba18d5e8c37980d4febb548f2405cb45ce8c
Gerrit-Change-Number: 37915
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36135 )
Change subject: sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING
..
sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING
The motivation for those new methods is to prevent checkpoints from
breaking when new map entries are added.
Change-Id: I0ff8681498bcf669492e6b876ad385fda4673d77
JIRA: https://gem5.atlassian.net/browse/GEM5-661
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36135
Reviewed-by: Richard Cooper
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/sim/serialize.hh
1 file changed, 56 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 51313a4..987bee2 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, 2018 ARM Limited
+ * Copyright (c) 2015, 2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -50,7 +50,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include "base/logging.hh"
@@ -515,6 +517,47 @@
void
objParamIn(CheckpointIn , const std::string , SimObject * );
+/**
+ * Serialize a mapping represented as two arrays: one containing names
+ * and the other containing values.
+ *
+ * @param names array of keys
+ * @param param array of values
+ * @param size size of the names and param arrays
+ */
+template
+void
+mappingParamOut(CheckpointOut , const char* sectionName,
+const char* const names[], const T *param, unsigned size)
+{
+Serializable::ScopedCheckpointSection sec(os, sectionName);
+for (unsigned i = 0; i < size; ++i) {
+paramOut(os, names[i], param[i]);
+}
+}
+
+/**
+ * Restore mappingParamOut. Keys missing from the checkpoint are ignored.
+ */
+template
+void
+mappingParamIn(CheckpointIn , const char* sectionName,
+const char* const names[], T *param, unsigned size)
+{
+Serializable::ScopedCheckpointSection sec(cp, sectionName);
+std::unordered_map name_to_index;
+for (size_t i = 0; i < size; i++) {
+name_to_index[names[i]] = i;
+}
+for (size_t i = 0; i < size; i++) {
+auto& key = names[i];
+T value;
+if (optParamIn(cp, key, value)) {
+param[name_to_index[key]] = value;
+}
+}
+}
+
//
// These macros are streamlined to use in serialize/unserialize
// functions. It's assumed that serialize() has a parameter 'os' for
@@ -646,4 +689,16 @@
objptr = dynamic_cast(sptr); \
} while (0)
+/**
+ * \def SERIALIZE_MAPPING(member, names, size)
+ */
+#define SERIALIZE_MAPPING(member, names, size) \
+mappingParamOut(cp, #member, names, member, size)
+
+/**
+ * \def UNSERIALIZE_MAPPING(member, names, size)
+ */
+#define UNSERIALIZE_MAPPING(member, names, size) \
+mappingParamIn(cp, #member, names, member, size)
+
#endif // __SERIALIZE_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ff8681498bcf669492e6b876ad385fda4673d77
Gerrit-Change-Number: 36135
Gerrit-PatchSet: 8
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: serialize miscregs as a map
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36116 )
Change subject: arch-arm: serialize miscregs as a map
..
arch-arm: serialize miscregs as a map
This will prevent checkpoints from breaking on every miscreg addition.
Before this commit, miscregs were stored as an array:
[system.cpu.isa]
miscRegs=965 0 0 0 0 0 0 0 0 0 0 0 17895697 ...
and after this commit they are stored as a map:
[system.cpu.isa]
[system.cpu.isa.miscRegs]
cpsr=965
spsr=0
spsr_fiq=0
spsr_irq=0
spsr_svc=0
spsr_mon=0
spsr_abt=0
spsr_hyp=0
spsr_und=0
elr_hyp=0
fpsid=0
fpscr=0
mvfr1=17895697
JIRA: https://gem5.atlassian.net/browse/GEM5-661
Change-Id: I4c7206bd9ac1cfb81297d45c8117ff8ae675
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36116
Reviewed-by: Andreas Sandberg
Reviewed-by: Richard Cooper
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/isa.cc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9b1cde3..9b0b957 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2354,14 +2354,14 @@
ISA::serialize(CheckpointOut ) const
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
}
void
ISA::unserialize(CheckpointIn )
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
updateRegMap(tmp_cpsr);
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I4c7206bd9ac1cfb81297d45c8117ff8ae675
Gerrit-Change-Number: 36116
Gerrit-PatchSet: 11
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Re: Compiling gem5 as library for x86 results in error
Many thanks Gabe, I rebuilt completely gem5 and I was able to run the example contained in /util/tlm/ correctly. Michele Il giorno ven 20 nov 2020 alle ore 23:25 Gabe Black ha scritto: > No, that's no related to USE_SYSTEMC=False. That's disabling the systemc > kernel, and the error message is that the system port is not connected. > Even though the names are similar, the system object doesn't have anything > to do with systemc. The system port itself is a port that the system object > (a type of gem5 SimObject) provides which is supposed to connect to the > memory and give components that want to set up memory like kernel loaders, > etc, direct access. If that port is not connected, gem5 assumes that's a > mistake and will error out. You need to make sure it's connected to > something in your configuration. > > Gabe > > On Fri, Nov 20, 2020 at 5:20 AM Michele Marazzi < > michele.marazzi...@gmail.com> wrote: > >> Dear Gabe, >> >> Thanks for your help. >> It does compile with USE_SYSTEMC=False, but unfortunately I suspect I do >> need that part in order to use gem5 as planned. >> >> Indeed, the case scenario is to interface it to a slave memory >> controller. After many tries of different configurations, I keep getting as >> error: >> > panic: System port on system is not connected. >> >> In order to not get out of scope of this ML I guess it's better not to go >> into details about my implementation, but rather to say that also the >> example provided with gem5 (/gem5/util/tlm/build/examples/slave_port/ >> gem5.sc) fails. >> >> I've followed the README explanation, first generating the config, and >> then loading it: >> >> user@pc-10744:~/gem5/util/tlm$ build/examples/slave_port/gem5.sc >>> m5out/config.ini -e 100 -v >>> SystemC 2.3.1-Accellera --- Nov 20 2020 13:20:43 >>> Copyright (c) 1996-2014 by all Contributors, >>> ALL RIGHTS RESERVED >>> Global frequency set at 1 ticks per second >>> >>> EventQueue Dump (cycle 0) >>> >>> >>> >>> panic: System port on system is not connected. >>> Memory Usage: 175632 KBytes >>> Program aborted at tick 0 >>> --- BEGIN LIBC BACKTRACE --- >>> >>> /home/user/gem5/build/X86/libgem5_opt.so(_Z15print_backtracev+0x30)[0x7fcd6722d390] >>> >>> /home/user/gem5/build/X86/libgem5_opt.so(_Z12abortHandleri+0x56)[0x7fcd6723e216] >>> /lib/x86_64-linux-gnu/libc.so.6(+0x46210)[0x7fcd659c3210] >>> /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xcb)[0x7fcd659c318b] >>> /lib/x86_64-linux-gnu/libc.so.6(abort+0x12b)[0x7fcd659a2859] >>> build/examples/slave_port/gem5.sc(+0x2c9a0)[0x56522a0e39a0] >>> >>> /home/user/gem5/build/X86/libgem5_opt.so(_ZN6System4initEv+0xab)[0x7fcd6725ef2b] >>> >>> /home/user/gem5/build/X86/libgem5_opt.so(_ZN16CxxConfigManager13forEachObjectEM9SimObjectFvvE+0x5f)[0x7fcd6722daaf] >>> >>> /home/user/gem5/build/X86/libgem5_opt.so(_ZN16CxxConfigManager11instantiateEb+0xa2)[0x7fcd67233fa2] >>> build/examples/slave_port/gem5.sc(+0x2ba9b)[0x56522a0e2a9b] >>> build/examples/slave_port/gem5.sc(sc_main+0xfa)[0x56522a0cd8f3] >>> build/systemc/libsystemc.so(sc_elab_and_sim+0xe2)[0x7fcd679fcda0] >>> build/systemc/libsystemc.so(main+0x24)[0x7fcd679fcc4e] >>> /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf3)[0x7fcd659a40b3] >>> build/examples/slave_port/gem5.sc(+0x1673e)[0x56522a0cd73e] >>> --- END LIBC BACKTRACE --- >>> Aborted (core dumped) >> >> >> The same happens if I try with a master configuration: >> >> user@pc-10744:~/gem5/util/tlm$ ../../build/X86/gem5.opt >>> conf/tlm_master.py >>> warn: CheckedInt already exists in allParams. This may be caused by the >>> Python 2.7 compatibility layer. >>> warn: Enum already exists in allParams. This may be caused by the Python >>> 2.7 compatibility layer. >>> warn: ScopedEnum already exists in allParams. This may be caused by the >>> Python 2.7 compatibility layer. >>> gem5 Simulator System. http://gem5.org >>> gem5 is copyrighted software; use the --copyright option for details. >>> gem5 version 20.0.0.3 >>> gem5 compiled Nov 20 2020 00:52:43 >>> gem5 started Nov 20 2020 13:30:19 >>> gem5 executing on pc-10744, pid 20674 >>> command line: ../../build/X86/gem5.opt conf/tlm_master.py >>> Global frequency set at 1 ticks per second >>> warn: No dot file generated. Please install pydot to generate the dot >>> file and pdf. >>> fatal: Can't find port handler type 'tlm_master' >>> Memory Usage: 612264 KBytes >> >> >> user@pc-10744:~/gem5/util/tlm$ build/examples/master_port/gem5.sc >>> m5out/config.ini -e 100 -v >>> SystemC 2.3.1-Accellera --- Nov 20 2020 13:20:43 >>> Copyright (c) 1996-2014 by all Contributors, >>> ALL RIGHTS RESERVED >>> Global frequency set at 1 ticks per second >>> >>> EventQueue
