[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Set frequency ranges in OSC device tree nodes.

2020-11-27 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37935 )


Change subject: dev-arm: Set frequency ranges in OSC device tree nodes.
..

dev-arm: Set frequency ranges in OSC device tree nodes.

The existing device tree generation method would use the default
frequency as both the min and max frequency when setting up the OSC
device tree nodes. This would sort of work, except it seems that if
the kernel needed to adjust a frequency, it would fail to do so since
it would assume the new frequency was out of range.

Since the existing property is used to set the initial frequency of
those clocks, and because the default, min and max frequencies are all
mostly independent variables (other than obvious ordering restrictions),
two new properties were added, min_freq and max_freq, which are only
there to fill in the frequency range property in the device tree. If
they aren't set, then the device tree generation method falls back to
the old way of using the default frequency as both min and max.

Change-Id: Ie907bd673f8bcb149e69e45c5b486863149b8a68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37935
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 25 insertions(+), 10 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index bf8e0e6..6f12a8b 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -244,6 +244,10 @@

 freq = Param.Clock("Default frequency")

+# These are currently only used for the device tree.
+min_freq = Param.Clock("0t", "Minimum frequency")
+max_freq = Param.Clock("0t", "Maximum frequency")
+
 def generateDeviceTree(self, state):
 phandle = state.phandle(self)
 node = FdtNode("osc@" + format(long(phandle), 'x'))
@@ -251,8 +255,16 @@
 node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
  [0x1, int(self.device)]))
 node.append(FdtPropertyWords("#clock-cells", [0]))
-freq = int(1.0/self.freq.value) # Values are stored as a clock  
period

-node.append(FdtPropertyWords("freq-range", [freq, freq]))
+
+minf = self.min_freq if self.min_freq.value else self.freq
+maxf = self.max_freq if self.max_freq.value else self.freq
+
+# Values are stored as a clock period.
+def to_freq(prop):
+return int(1.0 / prop.value)
+
+node.append(FdtPropertyWords("freq-range",
+ [to_freq(minf), to_freq(maxf)]))
 node.append(FdtPropertyStrings("clock-output-names",
["oscclk" + str(phandle)]))
 node.appendPhandle(self)
@@ -288,10 +300,12 @@
 class Temperature(RealViewTemperatureSensor):
 site, position, dcc = (0, 0, 0)

-osc_mcc = Osc(device=0, freq="50MHz")
-osc_clcd = Osc(device=1, freq="23.75MHz")
+osc_mcc = Osc(device=0, min_freq="25MHz", max_freq="60MHz",  
freq="50MHz")

+osc_clcd = Osc(device=1, min_freq="23.75MHz", max_freq="63.5MHz",
+   freq="23.75MHz")
 osc_peripheral = Osc(device=2, freq="24MHz")
-osc_system_bus = Osc(device=4, freq="24MHz")
+osc_system_bus = Osc(device=4, min_freq="2MHz", max_freq="230MHz",
+ freq="24MHz")

 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
 temp_crtl = Temperature(device=0)
@@ -322,11 +336,12 @@
 site, position, dcc = (1, 0, 0)

 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
-osc_cpu = Osc(device=0, freq="60MHz")
-osc_hsbm = Osc(device=4, freq="40MHz")
-osc_pxl = Osc(device=5, freq="23.75MHz")
-osc_smb = Osc(device=6, freq="50MHz")
-osc_sys = Osc(device=7, freq="60MHz")
+osc_cpu = Osc(device=0, min_freq="20MHz", max_freq="60MHz",  
freq="60MHz")
+osc_hsbm = Osc(device=4, min_freq="20MHz", max_freq="40MHz",  
freq="40MHz")

+osc_pxl = Osc(device=5, min_freq="23.76MHz", max_freq="165MHz",
+  freq="23.75MHz")
+osc_smb = Osc(device=6, min_freq="20MHz", max_freq="50MHz",  
freq="50MHz")
+osc_sys = Osc(device=7, min_freq="20MHz", max_freq="60MHz",  
freq="60MHz")

 osc_ddr = Osc(device=8, freq="40MHz")

 def generateDeviceTree(self, state):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie907bd673f8bcb149e69e45c5b486863149b8a68
Gerrit-Change-Number: 37935
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer:

[gem5-dev] Change in gem5/gem5[develop]: power: Convert POWER to use local reg index storage.

2020-11-27 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36882 )


Change subject: power: Convert POWER to use local reg index storage.
..

power: Convert POWER to use local reg index storage.

Change-Id: Ieea4ade247f89b23266a383b604c17e740d44e3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36882
Reviewed-by: Sandipan Das 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/power/isa/formats/basic.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/mem.isa
3 files changed, 36 insertions(+), 23 deletions(-)

Approvals:
  Sandipan Das: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/isa/formats/basic.isa  
b/src/arch/power/isa/formats/basic.isa

index 0ccef6a..20d380f 100644
--- a/src/arch/power/isa/formats/basic.isa
+++ b/src/arch/power/isa/formats/basic.isa
@@ -33,19 +33,23 @@
  */
 class %(class_name)s : public %(base_class)s
 {
+  private:
+%(reg_idx_arr_decl)s;
+
   public:
-/// Constructor.
-%(class_name)s(ExtMachInst machInst);
-Fault execute(ExecContext *,
-  Trace::InstRecord *) const override;
+/// Constructor.
+%(class_name)s(ExtMachInst machInst);
+Fault execute(ExecContext *, Trace::InstRecord *) const  
override;

 };
 }};

 // Basic instruction class constructor template.
 def template BasicConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst  
machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

+%(class_name)s::%(class_name)s(ExtMachInst machInst) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 {
-%(constructor)s;
+%(set_reg_idx_arr)s;
+%(constructor)s;
 }
 }};

diff --git a/src/arch/power/isa/formats/integer.isa  
b/src/arch/power/isa/formats/integer.isa

index 3b24927..50badce 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -34,32 +34,38 @@

 // Instruction class constructor template when Rc is set.
 def template IntRcConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst  
machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

-{
-%(constructor)s;
-rcSet = true;
-}
+%(class_name)s::%(class_name)s(ExtMachInst machInst) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+rcSet = true;
+}
 }};


 // Instruction class constructor template when OE is set.
 def template IntOeConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst  
machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

-{
-%(constructor)s;
-oeSet = true;
-}
+%(class_name)s::%(class_name)s(ExtMachInst machInst) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+oeSet = true;
+}
 }};


 // Instruction class constructor template when both Rc and OE are set.
 def template IntRcOeConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst  
machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)

-{
-%(constructor)s;
-rcSet = true;
-oeSet = true;
-}
+%(class_name)s::%(class_name)s(ExtMachInst machInst) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+rcSet = true;
+oeSet = true;
+}
 }};


diff --git a/src/arch/power/isa/formats/mem.isa  
b/src/arch/power/isa/formats/mem.isa

index 1f10a5a..c7be2b1 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -37,8 +37,10 @@
  */
 class %(class_name)s : public %(base_class)s
 {
-  public:
+  private:
+%(reg_idx_arr_decl)s;

+  public:
 /// Constructor.
 %(class_name)s(ExtMachInst machInst);

@@ -54,6 +56,7 @@
 %(class_name)s::%(class_name)s(ExtMachInst machInst)
  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 {
+%(set_reg_idx_arr)s;
 %(constructor)s;
 }
 }};

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieea4ade247f89b23266a383b604c17e740d44e3d
Gerrit-Change-Number: 36882
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Boris

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Change invalidate signature to not const

2020-11-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38115 )



Change subject: mem-cache: Change invalidate signature to not const
..

mem-cache: Change invalidate signature to not const

Allow the replacement policy to be modified when an entry is
invalidated.

Change-Id: I7f5086795dbb93a6fab2b4994c757d509d782d79
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/dueling_rp.cc
M src/mem/cache/replacement_policies/dueling_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/replacement_policies/tree_plru_rp.cc
M src/mem/cache/replacement_policies/tree_plru_rp.hh
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.hh
21 files changed, 17 insertions(+), 24 deletions(-)



diff --git a/src/mem/cache/replacement_policies/base.hh  
b/src/mem/cache/replacement_policies/base.hh

index d5673ec..7d09a4a 100644
--- a/src/mem/cache/replacement_policies/base.hh
+++ b/src/mem/cache/replacement_policies/base.hh
@@ -106,7 +106,7 @@
  * @param replacement_data Replacement data to be invalidated.
  */
 virtual void invalidate(const std::shared_ptr&
-replacement_data) const =  
0;

+replacement_data) = 0;

 /**
  * Update replacement data.
diff --git a/src/mem/cache/replacement_policies/brrip_rp.cc  
b/src/mem/cache/replacement_policies/brrip_rp.cc

index 19cd68d..0a7214d 100644
--- a/src/mem/cache/replacement_policies/brrip_rp.cc
+++ b/src/mem/cache/replacement_policies/brrip_rp.cc
@@ -46,7 +46,6 @@

 void
 BRRIP::invalidate(const std::shared_ptr& replacement_data)
-const
 {
 std::shared_ptr casted_replacement_data =
 std::static_pointer_cast(replacement_data);
diff --git a/src/mem/cache/replacement_policies/brrip_rp.hh  
b/src/mem/cache/replacement_policies/brrip_rp.hh

index 1cabb1f..cafd545 100644
--- a/src/mem/cache/replacement_policies/brrip_rp.hh
+++ b/src/mem/cache/replacement_policies/brrip_rp.hh
@@ -128,7 +128,7 @@
  * @param replacement_data Replacement data to be invalidated.
  */
 void invalidate(const std::shared_ptr&  
replacement_data)
-  const  
override;
+ 
override;


 /**
  * Touch an entry to update its replacement data.
diff --git a/src/mem/cache/replacement_policies/dueling_rp.cc  
b/src/mem/cache/replacement_policies/dueling_rp.cc

index 59c8990..f3cce39 100644
--- a/src/mem/cache/replacement_policies/dueling_rp.cc
+++ b/src/mem/cache/replacement_policies/dueling_rp.cc
@@ -44,8 +44,7 @@
 }

 void
-Dueling::invalidate(
-const std::shared_ptr& replacement_data) const
+Dueling::invalidate(const std::shared_ptr&  
replacement_data)

 {
 std::shared_ptr casted_replacement_data =
 std::static_pointer_cast(replacement_data);
diff --git a/src/mem/cache/replacement_policies/dueling_rp.hh  
b/src/mem/cache/replacement_policies/dueling_rp.hh

index 55627bf..0bd0d95 100644
--- a/src/mem/cache/replacement_policies/dueling_rp.hh
+++ b/src/mem/cache/replacement_policies/dueling_rp.hh
@@ -96,7 +96,7 @@
 ~Dueling() = default;

 void invalidate(const std::shared_ptr&  
replacement_data)
-  const  
override;
+ 
override;
 void touch(const std::shared_ptr& replacement_data)  
const
   
override;
 void reset(const std::shared_ptr& replacement_data)  
const
diff --git a/src/mem/cache/replacement_policies/fifo_rp.cc  
b/src/mem/cache/replacement_policies/fifo_rp.cc

index be28a56..c69c21d 100644
--- a/src/mem/cache/replacement_policies/fifo_rp.cc
+++ b/src/mem/cache/replacement_policies/fifo_rp.cc
@@ -43,7 +43,6 @@

 void
 FIFO::invalidate(const std::shared_ptr& replacement_data)
-const
 {
 // Reset insertion tick
 std::static_pointer_cast(
diff --git a/src/mem/cache/replacement_policies/fifo_rp.hh  
b/src/mem/cache/replacement_policies/fifo_rp.hh

index

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add Signature-Based Hit Predictor replacement policy

2020-11-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38118 )



Change subject: mem-cache: Add Signature-Based Hit Predictor replacement  
policy

..

mem-cache: Add Signature-Based Hit Predictor replacement policy

Add the SHiP Replacement Policy, as described in "SHiP: Signature-
based Hit Predictor for High Performance Caching", by Wu et al.

Instruction Sequence signatures have not been implemented.

Change-Id: I44f00d26eab4c96c9c5bc29740862a87356d30d1
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/SConscript
A src/mem/cache/replacement_policies/ship_rp.cc
A src/mem/cache/replacement_policies/ship_rp.hh
4 files changed, 382 insertions(+), 0 deletions(-)



diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py  
b/src/mem/cache/replacement_policies/ReplacementPolicies.py

index 22b85b0..61378ab 100644
--- a/src/mem/cache/replacement_policies/ReplacementPolicies.py
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -108,6 +108,31 @@
 btp = 100
 num_bits = 1

+class SHiPRP(BRRIPRP):
+type = 'SHiPRP'
+abstract = True
+cxx_class = 'ReplacementPolicy::SHiP'
+cxx_header = "mem/cache/replacement_policies/ship_rp.hh"
+
+shct_size = Param.Unsigned(16384, "Number of SHCT entries")
+# By default any value greater than 0 is enough to change insertion  
policy

+insertion_threshold = Param.Percent(1,
+"Percentage at which an entry changes insertion policy")
+# Always make hits mark entries as last to be evicted
+hit_priority = True
+# Let the predictor decide when to change insertion policy
+btp = 0
+
+class SHiPMemRP(SHiPRP):
+type = 'SHiPMemRP'
+cxx_class = 'ReplacementPolicy::SHiPMem'
+cxx_header = "mem/cache/replacement_policies/ship_rp.hh"
+
+class SHiPPCRP(SHiPRP):
+type = 'SHiPPCRP'
+cxx_class = 'ReplacementPolicy::SHiPPC'
+cxx_header = "mem/cache/replacement_policies/ship_rp.hh"
+
 class TreePLRURP(BaseReplacementPolicy):
 type = 'TreePLRURP'
 cxx_class = 'ReplacementPolicy::TreePLRU'
diff --git a/src/mem/cache/replacement_policies/SConscript  
b/src/mem/cache/replacement_policies/SConscript

index 29152a0..6370052 100644
--- a/src/mem/cache/replacement_policies/SConscript
+++ b/src/mem/cache/replacement_policies/SConscript
@@ -39,5 +39,6 @@
 Source('mru_rp.cc')
 Source('random_rp.cc')
 Source('second_chance_rp.cc')
+Source('ship_rp.cc')
 Source('tree_plru_rp.cc')
 Source('weighted_lru_rp.cc')
diff --git a/src/mem/cache/replacement_policies/ship_rp.cc  
b/src/mem/cache/replacement_policies/ship_rp.cc

new file mode 100644
index 000..eefec43
--- /dev/null
+++ b/src/mem/cache/replacement_policies/ship_rp.cc
@@ -0,0 +1,171 @@
+/**
+ * Copyright (c) 2019, 2020 Inria
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/cache/replacement_policies/ship_rp.hh"
+
+#include "base/logging.hh"
+#include "params/SHiPMemRP.hh"
+#include "params/SHiPPCRP.hh"
+#include "params/SHiPRP.hh"
+
+namespace ReplacementPolicy {
+
+SHiP::SHiPReplData::SHiPReplData(int num_bits)
+  : BRRIPReplData(num_bits), signature(0), outcome(false)
+{
+}
+
+SHiP::SignatureType
+SHiP::SHiPReplData::getSignature() const
+{
+return signature;
+}
+
+void
+SHiP::SHiPReplData::setSignature(SignatureType new_signature)
+{
+signature =

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Use PacketPtr in tags's accessBlock

2020-11-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38116 )



Change subject: mem-cache: Use PacketPtr in tags's accessBlock
..

mem-cache: Use PacketPtr in tags's accessBlock

Pass the packet to the tags, so that the replacement policies
more execution information.

Change-Id: I201884a6d60e3299fc3c9befebbb2e8b64a007f0
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/sector_tags.hh
7 files changed, 18 insertions(+), 21 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 98467ab..6eb8920 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1081,7 +1081,7 @@

 // Access block in the tags
 Cycles tag_latency(0);
-blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency);
+blk = tags->accessBlock(pkt, tag_latency);

 DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
 blk ? "hit " + blk->print() : "miss");
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 5a407a6..2edf74d 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -285,12 +285,11 @@
  * should only be used as such. Returns the tag lookup latency as a  
side

  * effect.
  *
- * @param addr The address to find.
- * @param is_secure True if the target memory space is secure.
+ * @param pkt The packet holding the address to find.
  * @param lat The latency of the tag lookup.
  * @return Pointer to the cache block if found.
  */
-virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles )  
= 0;

+virtual CacheBlk* accessBlock(const PacketPtr pkt, Cycles ) = 0;

 /**
  * Generate the tag from the given address.
diff --git a/src/mem/cache/tags/base_set_assoc.hh  
b/src/mem/cache/tags/base_set_assoc.hh

index b13b007..07e19a5 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -117,14 +117,13 @@
  * should only be used as such. Returns the tag lookup latency as a  
side

  * effect.
  *
- * @param addr The address to find.
- * @param is_secure True if the target memory space is secure.
+ * @param pkt The packet holding the address to find.
  * @param lat The latency of the tag lookup.
  * @return Pointer to the cache block if found.
  */
-CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles ) override
+CacheBlk* accessBlock(const PacketPtr pkt, Cycles ) override
 {
-CacheBlk *blk = findBlock(addr, is_secure);
+CacheBlk *blk = findBlock(pkt->getAddr(), pkt->isSecure());

 // Access all tags in parallel, hence one in each way.  The data  
side
 // either accesses all blocks in parallel, or one block  
sequentially on

diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index e61a280..6fbc485 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -127,17 +127,18 @@
 }

 CacheBlk*
-FALRU::accessBlock(Addr addr, bool is_secure, Cycles )
+FALRU::accessBlock(const PacketPtr pkt, Cycles )
 {
-return accessBlock(addr, is_secure, lat, 0);
+return accessBlock(pkt, lat, 0);
 }

 CacheBlk*
-FALRU::accessBlock(Addr addr, bool is_secure, Cycles ,
+FALRU::accessBlock(const PacketPtr pkt, Cycles ,
CachesMask *in_caches_mask)
 {
 CachesMask mask = 0;
-FALRUBlk* blk = static_cast(findBlock(addr, is_secure));
+FALRUBlk* blk =
+static_cast(findBlock(pkt->getAddr(), pkt->isSecure()));

 // If a cache hit
 if (blk && blk->isValid()) {
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 1d7e45a..550a44b 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -173,19 +173,18 @@
  * cache access and should only be used as such.
  * Returns tag lookup latency and the inCachesMask flags as a side  
effect.

  *
- * @param addr The address to look for.
- * @param is_secure True if the target memory space is secure.
+ * @param pkt The packet holding the address to find.
  * @param lat The latency of the tag lookup.
  * @param in_cache_mask Mask indicating the caches in which the blk  
fits.

  * @return Pointer to the cache block.
  */
-CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles ,
+CacheBlk* accessBlock(const PacketPtr pkt, Cycles ,
   CachesMask *in_cache_mask);

 /**
  * Just a wrapper of above function to conform with the base interface.
  */
-CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles ) override;
+CacheBlk* accessBlock(const PacketPtr pkt, Cycles ) override;

 /**

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Allow sending packet information to replacement policy

2020-11-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38117 )



Change subject: mem-cache: Allow sending packet information to replacement  
policy

..

mem-cache: Allow sending packet information to replacement policy

Some replacement policies can use information such as address or
PC to improve their re-reference prediction.

Change-Id: I412eee09efa2f3511ca1ece76fc2732509df4745
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/dueling_rp.cc
M src/mem/cache/replacement_policies/dueling_rp.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/sector_tags.cc
5 files changed, 50 insertions(+), 7 deletions(-)



diff --git a/src/mem/cache/replacement_policies/base.hh  
b/src/mem/cache/replacement_policies/base.hh

index 7d09a4a..f873926 100644
--- a/src/mem/cache/replacement_policies/base.hh
+++ b/src/mem/cache/replacement_policies/base.hh
@@ -34,6 +34,7 @@
 #include 

 #include "mem/cache/replacement_policies/replaceable_entry.hh"
+#include "mem/packet.hh"
 #include "params/BaseReplacementPolicy.hh"
 #include "sim/sim_object.hh"

@@ -112,17 +113,29 @@
  * Update replacement data.
  *
  * @param replacement_data Replacement data to be touched.
+ * @param pkt Packet that generated this access.
  */
 virtual void touch(const std::shared_ptr&
-replacement_data) const =  
0;

+replacement_data, const PacketPtr pkt)
+{
+touch(replacement_data);
+}
+virtual void touch(const std::shared_ptr&
+replacement_data) const = 0;

 /**
  * Reset replacement data. Used when it's holder is inserted/validated.
  *
  * @param replacement_data Replacement data to be reset.
+ * @param pkt Packet that generated this access.
  */
 virtual void reset(const std::shared_ptr&
-replacement_data) const =  
0;

+replacement_data, const PacketPtr pkt)
+{
+reset(replacement_data);
+}
+virtual void reset(const std::shared_ptr&
+replacement_data) const = 0;

 /**
  * Find replacement victim among candidates.
diff --git a/src/mem/cache/replacement_policies/dueling_rp.cc  
b/src/mem/cache/replacement_policies/dueling_rp.cc

index f3cce39..3e2e604 100644
--- a/src/mem/cache/replacement_policies/dueling_rp.cc
+++ b/src/mem/cache/replacement_policies/dueling_rp.cc
@@ -53,6 +53,16 @@
 }

 void
+Dueling::touch(const std::shared_ptr& replacement_data,
+const PacketPtr pkt)
+{
+std::shared_ptr casted_replacement_data =
+std::static_pointer_cast(replacement_data);
+replPolicyA->touch(casted_replacement_data->replDataA, pkt);
+replPolicyB->touch(casted_replacement_data->replDataB, pkt);
+}
+
+void
 Dueling::touch(const std::shared_ptr& replacement_data)  
const

 {
 std::shared_ptr casted_replacement_data =
@@ -62,6 +72,22 @@
 }

 void
+Dueling::reset(const std::shared_ptr& replacement_data,
+const PacketPtr pkt)
+{
+std::shared_ptr casted_replacement_data =
+std::static_pointer_cast(replacement_data);
+replPolicyA->reset(casted_replacement_data->replDataA, pkt);
+replPolicyB->reset(casted_replacement_data->replDataB, pkt);
+
+// A miss in a set is a sample to the duel. A call to this function
+// implies in the replacement of an entry, which was either caused by
+// a miss, an external invalidation, or the initialization of the table
+// entry (when warming up)
+ 
duelingMonitor.sample(static_cast(casted_replacement_data.get()));

+}
+
+void
 Dueling::reset(const std::shared_ptr& replacement_data)  
const

 {
 std::shared_ptr casted_replacement_data =
diff --git a/src/mem/cache/replacement_policies/dueling_rp.hh  
b/src/mem/cache/replacement_policies/dueling_rp.hh

index 0bd0d95..3077744 100644
--- a/src/mem/cache/replacement_policies/dueling_rp.hh
+++ b/src/mem/cache/replacement_policies/dueling_rp.hh
@@ -97,8 +97,12 @@

 void invalidate(const std::shared_ptr&  
replacement_data)
  
override;

+void touch(const std::shared_ptr& replacement_data,
+const PacketPtr pkt) override;
 void touch(const std::shared_ptr& replacement_data)  
const
   
override;

+void reset(const std::shared_ptr& replacement_data,
+const PacketPtr pkt) override;
 void reset(const std::shared_ptr& replacement_data)  
const
   
override;

 ReplaceableEntry* getVictim(
diff --git a/src/mem/cache/tags/base_set_assoc.hh  
b/src/mem/cache/tags/base_set_assoc.hh

index 07e19a5..38baa6d 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++

[gem5-dev] Change in gem5/gem5[develop]: cpu: MinorCPU not updating cycle counter value

2020-11-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38095 )



Change subject: cpu: MinorCPU not updating cycle counter value
..

cpu: MinorCPU not updating cycle counter value

By not updating the cycle counter value for every tick in the
MinorCPU meant that a read to the associated performance counter
was always returning 0.

For more info check the following email thread in gem5-users:

https://www.mail-archive.com/gem5-users@gem5.org/msg18742.html

Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/minor/cpu.hh
M src/cpu/minor/pipeline.cc
2 files changed, 11 insertions(+), 2 deletions(-)



diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 0e919f33..1e846565 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -181,6 +181,12 @@
 return prio_list;
 }

+/** The tick method in the MinorCPU is simply updating the cycle
+ * counters as the ticking of the pipeline stages is already
+ * handled by the Pipeline object.
+ */
+void tick() { updateCycleCounters(BaseCPU::CPU_STATE_ON); }
+
 /** Interface for stages to signal that they have become active after
  *  a callback or eventq event where the pipeline itself may have
  *  already been idled.  The stage argument should be from the
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index 78c2020..3997c89 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -121,6 +121,9 @@
 void
 Pipeline::evaluate()
 {
+/** We tick the CPU to update the BaseCPU cycle counters */
+cpu.tick();
+
 /* Note that it's important to evaluate the stages in order to allow
  *  'immediate', 0-time-offset TimeBuffer activity to be visible from
  *  later stages to earlier ones in the same cycle */

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38095
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Gerrit-Change-Number: 38095
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Update stats of AbstractController and derived classes

2020-11-27 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38075 )



Change subject: mem-ruby: Update stats of AbstractController and derived  
classes

..

mem-ruby: Update stats of AbstractController and derived classes

Change-Id: Ibe04e33a6cf09b453564592d29293b354d0d33c9
Signed-off-by: Hoa Nguyen 
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
3 files changed, 76 insertions(+), 60 deletions(-)



diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc  
b/src/mem/ruby/slicc_interface/AbstractController.cc

index 1e8d8e0..bf234bd 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -56,7 +56,8 @@
   m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
   m_mandatory_queue_latency(p.mandatory_queue_latency),
   memoryPort(csprintf("%s.memory", name()), this),
-  addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
+  addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
+  stats(this)
 {
 if (m_version == 0) {
 // Combine the statistics from all controllers
@@ -68,11 +69,11 @@
 void
 AbstractController::init()
 {
-m_delayHistogram.init(10);
+stats.m_delayHistogram.init(10);
 uint32_t size = Network::getNumberOfVirtualNetworks();
 for (uint32_t i = 0; i < size; i++) {
-m_delayVCHistogram.push_back(new Stats::Histogram());
-m_delayVCHistogram[i]->init(10);
+stats.m_delayVCHistogram.push_back(new Stats::Histogram(this));
+stats.m_delayVCHistogram[i]->init(10);
 }

 if (getMemReqQueue()) {
@@ -106,10 +107,10 @@
 void
 AbstractController::resetStats()
 {
-m_delayHistogram.reset();
+stats.m_delayHistogram.reset();
 uint32_t size = Network::getNumberOfVirtualNetworks();
 for (uint32_t i = 0; i < size; i++) {
-m_delayVCHistogram[i]->reset();
+stats.m_delayVCHistogram[i]->reset();
 }
 }

@@ -117,19 +118,14 @@
 AbstractController::regStats()
 {
 ClockedObject::regStats();
-
-m_fully_busy_cycles
-.name(name() + ".fully_busy_cycles")
-.desc("cycles for which number of transistions == max transitions")
-.flags(Stats::nozero);
 }

 void
 AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
 {
-assert(virtualNetwork < m_delayVCHistogram.size());
-m_delayHistogram.sample(delay);
-m_delayVCHistogram[virtualNetwork]->sample(delay);
+assert(virtualNetwork < stats.m_delayVCHistogram.size());
+stats.m_delayHistogram.sample(delay);
+stats.m_delayVCHistogram[virtualNetwork]->sample(delay);
 }

 void
@@ -423,3 +419,15 @@
 : RequestPort(_name, _controller, id), controller(_controller)
 {
 }
+
+AbstractController::
+ControllerStats::ControllerStats(Stats::Group *parent)
+: Stats::Group(parent, "Controller"),
+  m_fully_busy_cycles(this, "fully_busy_cycles",
+  "cycles for which number of transistions == max "
+  "transitions"),
+  m_delayHistogram(this, "delay_histogram")
+{
+m_fully_busy_cycles
+.flags(Stats::nozero);
+}
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh  
b/src/mem/ruby/slicc_interface/AbstractController.hh

index 8e19195..ce81de0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -151,9 +151,9 @@
 MachineID getMachineID() const { return m_machineID; }
 RequestorID getRequestorId() const { return m_id; }

-Stats::Histogram& getDelayHist() { return m_delayHistogram; }
+Stats::Histogram& getDelayHist() { return stats.m_delayHistogram; }
 Stats::Histogram& getDelayVCHist(uint32_t index)
-{ return *(m_delayVCHistogram[index]); }
+{ return *(stats.m_delayVCHistogram[index]); }

 bool respondsTo(Addr addr)
 {
@@ -204,14 +204,6 @@
 std::unordered_map m_inTrans;
 std::unordered_map m_outTrans;

-// Initialized by the SLICC compiler for all combinations of event and
-// states. Only histograms with samples will appear in the stats
-std::vector>>  
m_inTransLatHist;

-
-// Initialized by the SLICC compiler for all events.
-// Only histograms with samples will appear in the stats.
-std::vector m_outTransLatHist;
-
 /**
  * Profiles an event that initiates a protocol transactions for a  
specific

  * line (e.g. events triggered by incoming request messages).
@@ -241,10 +233,10 @@
 {
 auto iter = m_inTrans.find(addr);
 assert(iter != m_inTrans.end());
-m_inTransLatHist[iter->second.transaction]
-[iter->second.state]
-[(unsigned)finalState]->sample(
-  ticksToCycles(curTick()

[gem5-dev] Build failed in Jenkins: Compiler-Checks #33

2020-11-27 Thread jenkins-no-reply--- via gem5-dev 
See 


Changes:

[gabe.black] cpu: Access src and dest reg indexes using a pointer to member.

[Bobby R. Bruce] arch-gcn3,misc: Added missing overrides to gpu_thread.hh

[gabe.black] x86: Fix object scope in the CPUID code.

[xiongfei.liao] cpu-minor: this is a bug fix for MinorCPU for thread cloning.

[gabe.black] cpu: Add an StaticInst accessor for setting register index storage.

[gabe.black] arch: Add some format strings to the parser for reg indexes.

[fcrh] systemc: Make tlm/gem5 packet conversion flexible

[giacomo.travaglini] fastmodel: Use BaseMMU in the CortexR52 wrapper

[giacomo.travaglini] fastmodel: Replace xrange with range to be python3 
compliant

[hoanguyen] cpu-minor,stats: Update stats style of MinorCPU

[hoanguyen] cpu-o3,stats: Update stats style for iew and iew_impl

[hoanguyen] cpu-o3,stats: Update stats style of inst_queue & inst_queue_impl

[hoanguyen] cpu-o3,stats: Update stats style for cpu.hh and cpu.cc

[hoanguyen] cpu-o3,stats: Update stats style for mem_dep_unit.hh

[hoanguyen] cpu-simple,stats: Update stats style

[hoanguyen] cpu,stats: Update stats style for base.hh and base.cc

[hoanguyen] dev-arm,stats: Update stats style of src/dev/arm

[hoanguyen] dev,stats: Update stats style of src/dev/net

[hoanguyen] dev,stats: Update stats style for CopyEngine and IdeDisk

[hoanguyen] mem,stats: Update stats style for FALRU

[hoanguyen] mem,stats: Update stats style for mem/probes and mem/qos

[hoanguyen] sim,stats: Update stats style for power_model and thermal_domain

[giacomo.travaglini] python: Fix toBool converter

[hoanguyen] mem-ruby,misc: Fix a parameter name in a DeprecatedParam message

[Jason Lowe-Power] util: Use MAINTAINERS.yaml for valid tags in git hook

[Jason Lowe-Power] util: Relax commit message checker to allow fixups

[giacomo.travaglini] scons, python: Remove SmartDict from python utilities

[giacomo.travaglini] python: Remove SortedDict from python utilities

[hoanguyen] mem-ruby: Fix cache hits being profiled as cache misses

[ciro.santilli] sim: create SERIALIZE_MAPPING and UNSERIALIZE_MAPPING

[ciro.santilli] arch-arm: serialize miscregs as a map

[gabe.black] arm: Use the common pseudoInst dispatch function.

[gabe.black] x86: Convert X86 to use local reg index storage.

[gabe.black] sparc: Convert SPARC to use local register index storage.

[gabe.black] mips: Convert MIPS to use local register index storage.

[mbabaie] mem-cache, stats: Stats update for snoop filter

[Bobby R. Bruce] sim: ScopedCheckpointSection to public for mappingParamIn

[Bobby R. Bruce] tests,misc: Added gem5.fast clang compilation to Kokoro


--
Started by timer
Running as SYSTEM
Building in workspace 
The recommended git tool is: git
No credentials specified
 > git rev-parse --is-inside-work-tree # timeout=10
Fetching changes from the remote Git repository
 > git config remote.origin.url https://gem5.googlesource.com/public/gem5 # 
 > timeout=10
Fetching upstream changes from https://gem5.googlesource.com/public/gem5
 > git --version # timeout=10
 > git --version # 'git version 2.25.1'
 > git fetch --tags --force --progress -- 
 > https://gem5.googlesource.com/public/gem5 
 > +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
 > git rev-parse refs/remotes/origin/origin/develop^{commit} # timeout=10
Checking out Revision 0ff49d741cb7f1541e822722e0c2a34d14d9b289 
(refs/remotes/origin/develop)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f 0ff49d741cb7f1541e822722e0c2a34d14d9b289 # timeout=10
Commit message: "tests,misc: Added gem5.fast clang compilation to Kokoro"
 > git rev-list --no-walk 95a8cf76a5e14fff3039cdd20bc76e8d1f81f833 # timeout=10
[Compiler-Checks] $ /bin/sh -xe /tmp/jenkins4079617977422191720.sh
+ ./util/compiler-tests.sh -j 4
Starting build tests with 'gcc-version-10'...
'gcc-version-10' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-10'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-10'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-10'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-10'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-10'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-10'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-10'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-10'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-10'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-10'...