Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38095 )
Change subject: cpu: MinorCPU not updating cycle counter value
......................................................................
cpu: MinorCPU not updating cycle counter value
By not updating the cycle counter value for every tick in the
MinorCPU meant that a read to the associated performance counter
was always returning 0.
For more info check the following email thread in gem5-users:
https://www.mail-archive.com/gem5-users@gem5.org/msg18742.html
Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/cpu/minor/cpu.hh
M src/cpu/minor/pipeline.cc
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 0e919f33..1e846565 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2014, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -181,6 +181,12 @@
return prio_list;
}
+ /** The tick method in the MinorCPU is simply updating the cycle
+ * counters as the ticking of the pipeline stages is already
+ * handled by the Pipeline object.
+ */
+ void tick() { updateCycleCounters(BaseCPU::CPU_STATE_ON); }
+
/** Interface for stages to signal that they have become active after
* a callback or eventq event where the pipeline itself may have
* already been idled. The stage argument should be from the
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index 78c2020..3997c89 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -121,6 +121,9 @@
void
Pipeline::evaluate()
{
+ /** We tick the CPU to update the BaseCPU cycle counters */
+ cpu.tick();
+
/* Note that it's important to evaluate the stages in order to allow
* 'immediate', 0-time-offset TimeBuffer activity to be visible from
* later stages to earlier ones in the same cycle */
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Gerrit-Change-Number: 38095
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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