[gem5-dev] Change in gem5/gem5[develop]: util: Pass TERM through to commands in the m5 util's scons.

2020-12-03 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27754 )


Change subject: util: Pass TERM through to commands in the m5 util's scons.
..

util: Pass TERM through to commands in the m5 util's scons.

This enables color output from commands since they can detect that the
terminal supports it.

Change-Id: I4bbf400dccb8c6bfe92459a9db812e06e5a69b5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27754
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Pouya Fotouhi 
---
M util/m5/SConstruct
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Pouya Fotouhi: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index 8462cab..3a96103 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -56,6 +56,8 @@

 # Propogate the environment's PATH setting.
 main['ENV']['PATH'] = os.environ['PATH']
+# Pass through terminal information to, for instance, enable color output.
+main['ENV']['TERM'] = os.environ['TERM']

 # Detect some dependencies of some forms of the m5 utility/library.
 main['HAVE_JAVA'] = all(key in main for key in ('JAVAC', 'JAR'))

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4bbf400dccb8c6bfe92459a9db812e06e5a69b5a
Gerrit-Change-Number: 27754
Gerrit-PatchSet: 31
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Pouya Fotouhi 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Add a --debug-build option to the m5 util scons.

2020-12-03 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27753 )


Change subject: util: Add a --debug-build option to the m5 util scons.
..

util: Add a --debug-build option to the m5 util scons.

This enables debug info with -g, and disables optimization with -O0.

Change-Id: I788585c379f048d373c54dc04e7c460914d6912e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27753
Maintainer: Bobby R. Bruce 
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M util/m5/README.md
M util/m5/SConstruct
2 files changed, 15 insertions(+), 2 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/m5/README.md b/util/m5/README.md
index 0e94c28..f1d9bec 100644
--- a/util/m5/README.md
+++ b/util/m5/README.md
@@ -143,6 +143,8 @@

 ## Build options

+### SCons variables
+
 There are some variables which set build options which need to be  
controlled on

 a per ABI level. Currently, these are:

@@ -170,6 +172,10 @@
 host, then you'll need to set an appopriate prefix and may be able to clear
 some other prefix corresponding to that host.

+### SCons command line flags
+
+--debug-build: Compile with the -g option, and -O0.
+
 ## External dependency detection

 In some cases, if an external dependency isn't detected, the build will
diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index e1d7e1d..8462cab 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -42,9 +42,16 @@
 def abspath(d):
 return os.path.abspath(str(d))

+AddOption('--debug-build', dest='debug_build', action='store_true',
+  help='Build with debug info, and disable optimizations.')
+
 # Universal settings.
-main.Append(CXXFLAGS=[ '-O2' ])
-main.Append(CCFLAGS=[ '-O2' ])
+if GetOption('debug_build'):
+main.Append(CXXFLAGS=[ '-O0', '-g' ])
+main.Append(CCFLAGS=[ '-O0', '-g' ])
+else:
+main.Append(CXXFLAGS=[ '-O2' ])
+main.Append(CCFLAGS=[ '-O2' ])
 main.Append(CPPPATH=[ common_include ])

 # Propogate the environment's PATH setting.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I788585c379f048d373c54dc04e7c460914d6912e
Gerrit-Change-Number: 27753
Gerrit-PatchSet: 32
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Pouya Fotouhi 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Jenkins build is back to normal : Compiler-Checks #34

2020-12-03 Thread jenkins-no-reply--- via gem5-dev 
See 

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[gem5-dev] Change in gem5/gem5[develop]: util: Add a README file for the m5 utility.

2020-12-03 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38215 )


Change subject: util: Add a README file for the m5 utility.
..

util: Add a README file for the m5 utility.

This is a fairly comprehensive document which describes how to use the
m5 utility, the various libraries/modules, and the various included
tests.

Change-Id: I63b5c0a50852a57e6d1b2779090308994e5d0f81
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38215
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
A util/m5/README.md
1 file changed, 384 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/m5/README.md b/util/m5/README.md
new file mode 100644
index 000..0e94c28
--- /dev/null
+++ b/util/m5/README.md
@@ -0,0 +1,384 @@
+The m5 utility provides a command line and library interface for gem5
+operations.
+
+These operations are requested by the simulated software through some  
special

+behavior which is recognized by gem5. gem5 will then perform the requested
+operation which is outside the normal behavior of the simulated system.
+
+
+
+# Trigger mechanisms
+
+There are a few different ways the simulated software can let gem5 know it
+wants to perform an operation. Different CPU models have different  
constraints

+depending on how they're implemented, and may not support all of these
+different mechanisms.
+
+   Trigger   | Native  | KVM | Fast Model
+-|-|-|
+ Instruction |   Yes   | |
+ Address | ARM/X86 | Yes |
+ Semihosting |   ARM   | |   Yes
+
+## "Magic" Instructions
+
+This is the oldest trigger mechanism in gem5, and is supported by all of  
the

+CPU models which interpret instructions one at a time using gem5's ISA
+definitions.  It works by co-opting instructions which normally are  
undefined,

+and redefining them to trigger gem5 operations. Exactly what instructions
+these are, how they encode what operation they go with, etc., vary from  
ISA to ISA.

+
+When using the KVM CPU models, the instruction stream is executing on  
actual

+physical hardware which won't treat these instructions specially. They will
+retain their old behavior and, most likely, raise an undefined instruction
+exception if executed.
+
+Other external models, like ARM's Fast Model CPUs, also won't treat these
+instructions specially.
+
+## "Magic" Address Range
+
+This mechanism was added for the KVM CPUs so that they could trigger gem5
+operations without having to recognize special instructions. This trigger  
is

+based on a specially set aside range of physical addresses. When a read or
+write is targetted at that range, instead of a normal device or memory  
access,

+a gem5 operation is triggered.
+
+Depending on the ISA, gem5 native CPUs should support this mechanism (see  
the

+table below).
+
+When using the KVM CPU, the special range of addresses are not registered  
as
+memory, and so the KVM virtual machine will exit when they're accessed.  
gem5

+will have a chance to recognize the special address, and can trigger the
+operation.
+
+When using an external model like ARM's Fast Model CPUs, these external
+accesses will leave the CPU complex, and gem5 will be able to recognize  
them.
+Unfortunately if the CPU has multiple threads of execution, gem5 won't be  
able
+to tell which the access came from. Also, the memory access may not happen  
at a
+precise point in the simulated instruction stream due to binary  
translation.
+The architectural state may not be in a consistent state which is suitable  
to

+extract arguments or inject a return value.
+
+### Default address range
+
+Since x86 has a predictable address space layout, the "magic" address  
range can

+be put in a predictable, default location, which is at 0x.
+
+On other architectures, notably ARM, the address space is less  
predictable, and

+it doesn't make sense to set a default location which won't be valid on all
+configurations.
+
+## Semihosting
+
+This mechanism was added to support ARM's Fast Model CPUs. It extends ARM's
+semihosting support, a mechanism which was already defined to interrupt  
normal

+execution and trigger some sort of behavior in a containing host.
+
+On ISAs which support semihosting (only ARM now, and probably going  
forward),
+gem5 native CPUs can support semihosting instructions, and so should  
support

+the semihosting trigger mechanism.
+
+KVM CPUs use real hardware, and so semihosting instructions will not have
+special behavior and will act like their normal counterparts (HLT, etc.).
+
+
+
+# Building
+
+## Supported ABIs
+
+To build either the command line utility or one of

[gem5-dev] Change in gem5/gem5[develop]: util: Teach the m5 utility's scons how to run unit tests.

2020-12-03 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27752 )


Change subject: util: Teach the m5 utility's scons how to run unit tests.
..

util: Teach the m5 utility's scons how to run unit tests.

This may be directly in the case of native tests, or through a user
level QEMU binary for non-native tests. scons is smart enough to expect
to be able to run native tests always, and non-native tests only if a
qemu binary has been found.

To tell scons to run tests in a particular category, you can use a
command of this form:

scons build/[category]/test/

where category is either an "abi" like sparc or x86, or "native" for
tests which don't do anything target specific and so can be run on the
host.

There will be two directories under .../tests, "bin" and "result". "bin"
is where the test binaries themselves will be built, and "result" is for
the results of running those binaries.

Change-Id: I6450ab4a97169f8a01292d946bfac18008b0430c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27752
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M util/m5/SConstruct
M util/m5/src/abi/aarch64/SConsopts
M util/m5/src/abi/arm/SConsopts
M util/m5/src/abi/sparc/SConsopts
M util/m5/src/abi/thumb/SConsopts
M util/m5/src/abi/x86/SConsopts
6 files changed, 28 insertions(+), 1 deletion(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index bbae8d9..e1d7e1d 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -70,7 +70,21 @@

 if not srcs:
 srcs = [ name + '.cc', name + '.test.cc' ]
-env['GTEST_ENV'].Program('test/%s' % name, srcs, **kwargs)
+test_bin = env['GTEST_ENV'].Program('test/bin/%s' % name, srcs,  
**kwargs)

+
+# The native environment doesn't need QEMU, and doesn't define  
HAVE_QEMU.

+need_qemu_to_run = 'HAVE_QEMU' in env;
+
+# If we can run this test...
+if not need_qemu_to_run or env['HAVE_QEMU']:
+# An XML file which holds the results of the test.
+xml = Dir('test').Dir('result').File('%s.xml' % name)
+# The basic command line for the test.
+cmd = '${SOURCES[0]} --gtest_output=xml:${TARGETS[0]}'
+if need_qemu_to_run:
+# A prefix that runs it in QEMU if necessary.
+cmd = '${QEMU} -L ${QEMU_SYSROOT} -- ' + cmd
+AlwaysBuild(env.Command(xml, test_bin, cmd))

 main.AddMethod(GTest)

@@ -89,6 +103,7 @@
 main['AS'] = '${CROSS_COMPILE}as'
 main['LD'] = '${CROSS_COMPILE}ld'
 main['AR'] = '${CROSS_COMPILE}ar'
+main['QEMU'] = 'qemu-${QEMU_ARCH}'

 class CallType(object):
 def __init__(self, name):
@@ -146,6 +161,13 @@
 env.SConscript(Dir(root).File('SConsopts'),
exports=[ 'env', 'get_abi_opt' ])

+# Check if this version of QEMU is available for running unit  
tests.

+env['HAVE_QEMU'] = env.Detect('${QEMU}') is not None
+if env['HAVE_QEMU'] and env.Detect('${CC}'):
+sysroot_cmd = env.subst('${CC} -print-sysroot')
+sysroot = os.popen(sysroot_cmd).read().strip()
+env['QEMU_SYSROOT'] = sysroot
+
 # Once all the options have been configured, set up build targets  
for

 # this abi.
 abi_dir = build_dir.Dir(env.subst('${ABI}'))
diff --git a/util/m5/src/abi/aarch64/SConsopts  
b/util/m5/src/abi/aarch64/SConsopts

index 010b22e..f55b1a1 100644
--- a/util/m5/src/abi/aarch64/SConsopts
+++ b/util/m5/src/abi/aarch64/SConsopts
@@ -27,6 +27,7 @@

 env['ABI'] = 'aarch64'
 get_abi_opt('CROSS_COMPILE', 'aarch64-linux-gnu-')
+get_abi_opt('QEMU_ARCH', 'aarch64')

 env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
 env['CALL_TYPE']['addr'].impl('m5op_addr.S')
diff --git a/util/m5/src/abi/arm/SConsopts b/util/m5/src/abi/arm/SConsopts
index 4988b71..49762ad 100644
--- a/util/m5/src/abi/arm/SConsopts
+++ b/util/m5/src/abi/arm/SConsopts
@@ -27,6 +27,7 @@

 env['ABI'] = 'arm'
 get_abi_opt('CROSS_COMPILE', 'arm-linux-gnueabihf-')
+get_abi_opt('QEMU_ARCH', 'arm')
 env.Append(CXXFLAGS=[ '-march=armv7-a', '-mfpu=neon' ])

 env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
diff --git a/util/m5/src/abi/sparc/SConsopts  
b/util/m5/src/abi/sparc/SConsopts

index 5f35848..ccadbe6 100644
--- a/util/m5/src/abi/sparc/SConsopts
+++ b/util/m5/src/abi/sparc/SConsopts
@@ -27,6 +27,7 @@

 env['ABI'] = 'sparc'
 get_abi_opt('CROSS_COMPILE', 'sparc64-linux-gnu-')
+get_abi_opt('QEMU_ARCH', 'sparc64')
 env.Append(CXXFLAGS='-m64')

 env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
diff --git a/util/m5/src/abi/thumb/SConsopts  
b/util/m5/src/abi/thumb/SConsopts

index f8956e3..b422634 100644
--- a/util/m5/src/abi/thumb/SConsopts
+++ b/util/m5/src/abi/thumb/SConsopts
@@ -27,6

[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: add resource stalls to MSI protocol

2020-12-03 Thread Gerrit 
Tiago Mück has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38282 )



Change subject: learning-gem5: add resource stalls to MSI protocol
..

learning-gem5: add resource stalls to MSI protocol

This adds resource annotations to some transitions in the MSI protocol
so resource stalls are generated on cache access bank conflicts.

An example of a resource stall handler definition was also added to
the mandatory queue.

Change-Id: I1c6b61292c489e38f372a8a1129b3fda7fb76bb1
---
M configs/learning_gem5/part3/msi_caches.py
M src/learning_gem5/part3/MSI-cache.sm
2 files changed, 95 insertions(+), 9 deletions(-)



diff --git a/configs/learning_gem5/part3/msi_caches.py  
b/configs/learning_gem5/part3/msi_caches.py

index 86adfd5..2d1b1a7 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -134,7 +134,8 @@
 # This is the cache memory object that stores the cache data and  
tags

 self.cacheMemory = RubyCache(size = '16kB',
assoc = 8,
-   start_index_bit =  
self.getBlockSizeBits(system))
+   start_index_bit =  
self.getBlockSizeBits(system),

+   resourceStalls=True)
 self.clk_domain = cpu.clk_domain
 self.send_evictions = self.sendEvicts(cpu)
 self.ruby_system = ruby_system
diff --git a/src/learning_gem5/part3/MSI-cache.sm  
b/src/learning_gem5/part3/MSI-cache.sm

index 843b9b9..12fec5d 100644
--- a/src/learning_gem5/part3/MSI-cache.sm
+++ b/src/learning_gem5/part3/MSI-cache.sm
@@ -294,6 +294,68 @@
 }

  
/*/

+// Definitions of resource allocation types required by transitions
+
+// See 'transition(I, Load, IS_D)' for an example.
+// These are optional annotations which tell SLICC the transition needs
+// the specified resource. If the resource is not available, a resource
+// stall is generated and the transition doesn't execute.
+// Checking and reserving this resource is defined by
+// checkResourceAvailable and recordRequestType.
+enumeration(RequestType, desc="Transition annotations types") {
+DataArrayRead,desc="Read the data array";
+DataArrayWrite,   desc="Write the data array";
+TagArrayRead, desc="Read the data array";
+TagArrayWrite,desc="Write the data array";
+}
+
+// Notice the resourceStalls parameter must be set for the cacheMemory
+// object at configuration time, otherwise these annotations have no
+// effect.
+bool checkResourceAvailable(RequestType request_type, Addr addr) {
+if (request_type == RequestType:DataArrayRead) {
+return cacheMemory.checkResourceAvailable(
+CacheResourceType:DataArray, addr);
+} else if (request_type == RequestType:DataArrayWrite) {
+return cacheMemory.checkResourceAvailable(
+CacheResourceType:DataArray, addr);
+} else if (request_type == RequestType:TagArrayRead) {
+return cacheMemory.checkResourceAvailable(
+CacheResourceType:TagArray, addr);
+} else if (request_type == RequestType:TagArrayWrite) {
+return cacheMemory.checkResourceAvailable(
+CacheResourceType:TagArray, addr);
+} else {
+error("Invalid RequestType type in checkResourceAvailable");
+return true;
+}
+}
+
+// Notice currently there is no support for explicitly releasing the
+// resource. It is assumed the resource is automatically released at  
some
+// point. For the case of cacheMemory, the resource is release after  
the

+// #cycles defined by the tag/data array latency has elapsed.
+void recordRequestType(RequestType request_type, Addr addr) {
+if (request_type == RequestType:DataArrayRead) {
+cacheMemory.recordRequestType(
+CacheRequestType:DataArrayRead, addr);
+} else if (request_type == RequestType:DataArrayWrite) {
+cacheMemory.recordRequestType(
+CacheRequestType:DataArrayWrite, addr);
+} else if (request_type == RequestType:TagArrayRead) {
+cacheMemory.recordRequestType(
+CacheRequestType:TagArrayRead, addr);
+} else if (request_type == RequestType:TagArrayWrite) {
+cacheMemory.recordRequestType(
+CacheRequestType:TagArrayWrite, addr);
+} else {
+error("Invalid RequestType type in checkResourceAvailable");
+}
+}
+
+
+
+ 
/*/

 // Input/output network definitions

 // Output ports. This defines the message types that will flow ocross  
the

[gem5-dev] Change in gem5/gem5[develop]: util: m5term, remove hardcoded superuser install

2020-12-03 Thread Adrian Herrera (Gerrit) via gem5-dev 
Adrian Herrera has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38296 )



Change subject: util: m5term, remove hardcoded superuser install
..

util: m5term, remove hardcoded superuser install

This is a non-standard practice. If the user needs to install the
utility in a privileged directory, it should run "sudo make install"
instead.

Change-Id: I55b7221f2e6215a14b12902ef96221fb35701837
Signed-off-by: Adrian Herrera 
---
M util/term/Makefile
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/util/term/Makefile b/util/term/Makefile
index fd98aae..2242856 100644
--- a/util/term/Makefile
+++ b/util/term/Makefile
@@ -37,7 +37,7 @@

 install: m5term
mkdir -p $(DESTDIR)$(bindir)
-   $(SUDO) install -o root -m 555 m5term $(DESTDIR)$(bindir)
+   install -m 755 m5term $(DESTDIR)$(bindir)

 clean:
@rm -f m5term *~ .#*

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I55b7221f2e6215a14b12902ef96221fb35701837
Gerrit-Change-Number: 38296
Gerrit-PatchSet: 1
Gerrit-Owner: Adrian Herrera 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: m5term, configurable install directories

2020-12-03 Thread Adrian Herrera (Gerrit) via gem5-dev 
Adrian Herrera has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38295 )



Change subject: util: m5term, configurable install directories
..

util: m5term, configurable install directories

Use standard GNU Make install directory variables. Build systems can
configure these to install the utility in custom staging areas.

Change-Id: Ib8d73ec717e1c8c99b24df33e93e1a74cf8aa717
Signed-off-by: Adrian Herrera 
---
M util/term/Makefile
1 file changed, 6 insertions(+), 1 deletion(-)



diff --git a/util/term/Makefile b/util/term/Makefile
index 4aa1c52..fd98aae 100644
--- a/util/term/Makefile
+++ b/util/term/Makefile
@@ -24,6 +24,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+prefix ?= /usr/local
+exec_prefix ?= $(prefix)
+bindir ?= $(exec_prefix)/bin
+
 CFLAGS ?= -g -O0

 default: m5term
@@ -32,7 +36,8 @@
$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LDLIBS)

 install: m5term
-   $(SUDO) install -o root -m 555 m5term /usr/local/bin
+   mkdir -p $(DESTDIR)$(bindir)
+   $(SUDO) install -o root -m 555 m5term $(DESTDIR)$(bindir)

 clean:
@rm -f m5term *~ .#*

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[gem5-dev] Change in gem5/gem5[develop]: util: m5term, fix LDFLAGS, standard make variables

2020-12-03 Thread Adrian Herrera (Gerrit) via gem5-dev 
Adrian Herrera has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38256 )



Change subject: util: m5term, fix LDFLAGS, standard make variables
..

util: m5term, fix LDFLAGS, standard make variables

Enables build systems to provide necessary flags to build m5term.
Useful specially if a different linker is intended to be used.

Change-Id: If7f867cc0965d6ad4627b5421e00a99cc3d64989
Signed-off-by: Adrian Herrera 
---
M util/term/Makefile
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/util/term/Makefile b/util/term/Makefile
index 658b961..4aa1c52 100644
--- a/util/term/Makefile
+++ b/util/term/Makefile
@@ -24,12 +24,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-CCFLAGS= -g -O0
+CFLAGS ?= -g -O0

 default: m5term

 m5term: term.c
-   $(CC) $(LFLAGS) -o $@ $^
+   $(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LDLIBS)

 install: m5term
$(SUDO) install -o root -m 555 m5term /usr/local/bin

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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix setting prefetch bit

2020-12-03 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38176 )


Change subject: mem-cache: Fix setting prefetch bit
..

mem-cache: Fix setting prefetch bit

Commit https://gem5-review.googlesource.com/c/public/gem5/+/35699
had a copy-paste error: when setting the prefetch bit it must
become true.

Change-Id: Ib0abc5141dd65d3c739dc01948a72eb5451884e8
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38176
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/cache/cache_blk.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index 2d866a8..b1038c8 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -251,7 +251,7 @@
 void clearPrefetched() { _prefetched = false; }

 /** Marks this blocks as a recently prefetched block. */
-void setPrefetched() { _prefetched = false; }
+void setPrefetched() { _prefetched = true; }

 /**
  * Get tick at which block's data will be available for access.

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Gerrit-Change-Id: Ib0abc5141dd65d3c739dc01948a72eb5451884e8
Gerrit-Change-Number: 38176
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Use smart pointer for info's storageParams

2020-12-03 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38178 )



Change subject: base: Use smart pointer for info's storageParams
..

base: Use smart pointer for info's storageParams

Previously the storage params were not being deallocated. Make
sure this happens by managing it with smart pointers.

As a side effect, encapsulate this variable to facilitate future
changes.

Change-Id: I4c2496d08241f155793ed35e3463512d9ea06f83
Signed-off-by: Daniel R. Carvalho 
---
M src/base/statistics.cc
M src/base/statistics.hh
M src/base/stats/info.cc
M src/base/stats/info.hh
4 files changed, 43 insertions(+), 21 deletions(-)



diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index bc411f7..844e54a 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -96,7 +96,7 @@
 void
 InfoAccess::setParams(const StorageParams *params)
 {
-info()->storageParams = params;
+info()->setStorageParams(params);
 }

 void
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index b562837..d0d26ca 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -410,7 +410,7 @@

 size_t size = self.size();
 for (off_type i = 0; i < size; ++i)
-self.data(i)->prepare(info->storageParams);
+self.data(i)->prepare(info->getStorageParams());
 }

 void
@@ -421,7 +421,7 @@

 size_t size = self.size();
 for (off_type i = 0; i < size; ++i)
-self.data(i)->reset(info->storageParams);
+self.data(i)->reset(info->getStorageParams());
 }
 };

@@ -520,7 +520,7 @@
 void
 doInit()
 {
-new (storage) Storage(this->info()->storageParams);
+new (storage) Storage(this->info()->getStorageParams());
 this->setInit();
 }

@@ -592,8 +592,8 @@

 bool zero() const { return result() == 0.0; }

-void reset() { data()->reset(this->info()->storageParams); }
-void prepare() { data()->prepare(this->info()->storageParams); }
+void reset() { data()->reset(this->info()->getStorageParams()); }
+void prepare() { data()->prepare(this->info()->getStorageParams()); }
 };

 class ProxyInfo : public ScalarInfo
@@ -918,7 +918,7 @@
 fatal_if(s <= 0, "Storage size must be positive");
 fatal_if(check(), "Stat has already been initialized");

-storage.resize(s, new Storage(this->info()->storageParams));
+storage.resize(s, new Storage(this->info()->getStorageParams()));
 this->setInit();
 }

@@ -1140,7 +1140,7 @@
 info->x = _x;
 info->y = _y;

-storage.resize(x * y, new Storage(info->storageParams));
+storage.resize(x * y, new Storage(info->getStorageParams()));
 this->setInit();

 return self;
@@ -1187,7 +1187,7 @@
 size_type size = this->size();

 for (off_type i = 0; i < size; ++i)
-data(i)->prepare(info->storageParams);
+data(i)->prepare(info->getStorageParams());

 info->cvec.resize(size);
 for (off_type i = 0; i < size; ++i)
@@ -1203,7 +1203,7 @@
 Info *info = this->info();
 size_type size = this->size();
 for (off_type i = 0; i < size; ++i)
-data(i)->reset(info->storageParams);
+data(i)->reset(info->getStorageParams());
 }

 bool
@@ -1259,7 +1259,7 @@
 void
 doInit()
 {
-new (storage) Storage(this->info()->storageParams);
+new (storage) Storage(this->info()->getStorageParams());
 this->setInit();
 }

@@ -1293,7 +1293,7 @@
 prepare()
 {
 Info *info = this->info();
-data()->prepare(info->storageParams, info->data);
+data()->prepare(info->getStorageParams(), info->data);
 }

 /**
@@ -1302,7 +1302,7 @@
 void
 reset()
 {
-data()->reset(this->info()->storageParams);
+data()->reset(this->info()->getStorageParams());
 }

 /**
@@ -1347,7 +1347,7 @@
 fatal_if(s <= 0, "Storage size must be positive");
 fatal_if(check(), "Stat has already been initialized");

-storage.resize(s, new Storage(this->info()->storageParams));
+storage.resize(s, new Storage(this->info()->getStorageParams()));
 this->setInit();
 }

@@ -1392,7 +1392,7 @@
 size_type size = this->size();
 info->data.resize(size);
 for (off_type i = 0; i < size; ++i)
-data(i)->prepare(info->storageParams, info->data[i]);
+data(i)->prepare(info->getStorageParams(), info->data[i]);
 }

 bool
@@ -2213,7 +2213,7 @@
 void
 doInit()
 {
-new (storage) Storage(this->info()->storageParams);
+new (storage) Storage(this->info()->getStorageParams());
 this->setInit();
 }

@@ -2247,7 +2247,7 @@
 prepare()
 {
 Info *info = this->info();
-

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix update of useful prefetches

2020-12-03 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38177 )



Change subject: mem-cache: Fix update of useful prefetches
..

mem-cache: Fix update of useful prefetches

The probe notification must be parsed on every hit, even if
the prefetcher is set not to generate prefetches on accesses.
This fixes the calculation of useful prefetches.

Change-Id: Iff298f7bea11013f411f4ba39dba705fd81a0cd4
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/prefetch/base.cc
1 file changed, 3 insertions(+), 4 deletions(-)



diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 28aaa62..5a34ac6 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -125,6 +125,7 @@
 bool read = pkt->isRead();
 bool inv = pkt->isInvalidate();

+if (!miss && prefetchOnAccess) return false;
 if (pkt->req->isUncacheable()) return false;
 if (fetch && !onInst) return false;
 if (!fetch && !onData) return false;
@@ -236,10 +237,8 @@
 true));
 listeners.push_back(new PrefetchListener(*this, pm, "Fill", true,
  false));
-if (prefetchOnAccess) {
-listeners.push_back(new PrefetchListener(*this, pm, "Hit",  
false,

- false));
-}
+listeners.push_back(new PrefetchListener(*this, pm, "Hit", false,
+ false));
 }
 }


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Gerrit-Change-Id: Iff298f7bea11013f411f4ba39dba705fd81a0cd4
Gerrit-Change-Number: 38177
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Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix setting prefetch bit

2020-12-03 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38176 )



Change subject: mem-cache: Fix setting prefetch bit
..

mem-cache: Fix setting prefetch bit

Commit https://gem5-review.googlesource.com/c/public/gem5/+/35699
had a copy-paste error: when setting the prefetch bit it must
become true.

Change-Id: Ib0abc5141dd65d3c739dc01948a72eb5451884e8
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/cache_blk.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index 2d866a8..b1038c8 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -251,7 +251,7 @@
 void clearPrefetched() { _prefetched = false; }

 /** Marks this blocks as a recently prefetched block. */
-void setPrefetched() { _prefetched = false; }
+void setPrefetched() { _prefetched = true; }

 /**
  * Get tick at which block's data will be available for access.

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[gem5-dev] Change in gem5/gem5[develop]: cpu, sim: Remove unused System::totalNumInst

2020-12-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25305 )


Change subject: cpu, sim: Remove unused System::totalNumInst
..

cpu, sim: Remove unused System::totalNumInst

This counter gets augmented for every executed instruction but it
is not used. It is also overlapping with the

BaseCPU::numSimulatedInsts

A client willing to know the number of simulated instruction should rely
on the interface above.

Change-Id: Ic5c805ac3b2e87bbacb365108d4060f53e044b4e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25305
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/kvm/base.cc
M src/cpu/minor/execute.cc
M src/cpu/o3/cpu.cc
M src/cpu/simple/base.cc
M src/cpu/simple/timing.cc
M src/sim/system.cc
M src/sim/system.hh
7 files changed, 0 insertions(+), 16 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index cb0b4bb..b364d4f 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -766,7 +766,6 @@
 baseStats.numCycles += simCyclesExecuted;;
 stats.committedInsts += instsExecuted;
 ctrInsts += instsExecuted;
-system->totalNumInsts += instsExecuted;

 DPRINTF(KvmRun,
 "KVM: Executed %i instructions in %i cycles "
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 52708ab..3eb7811 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -866,7 +866,6 @@
 thread->numInst++;
 thread->threadStats.numInsts++;
 cpu.stats.numInsts++;
-cpu.system->totalNumInsts++;

 /* Act on events related to instruction counts */
 thread->comInstEventQueue.serviceEvents(thread->numInst);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c67ee64..c910cc4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1474,7 +1474,6 @@
 thread[tid]->numInst++;
 thread[tid]->threadStats.numInsts++;
 cpuStats.committedInsts[tid]++;
-system->totalNumInsts++;

 // Check for instruction-count-based events.
 thread[tid]->comInstEventQueue.serviceEvents(thread[tid]->numInst);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index dc58e0a..7f4797b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -166,7 +166,6 @@
 t_info.numInst++;
 t_info.execContextStats.numInsts++;

-system->totalNumInsts++;
 t_info.thread->funcExeInst++;
 }
 t_info.numOp++;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5e9eb92..0fd83ca 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -148,8 +148,6 @@

 // Reschedule any power gating event (if any)
 schedulePowerGatingEvent();
-
-system->totalNumInsts = 0;
 }

 bool
diff --git a/src/sim/system.cc b/src/sim/system.cc
index d31238c..de4744a 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -229,7 +229,6 @@
   _m5opRange(p.m5ops_base ?
  RangeSize(p.m5ops_base, 0x1) :
  AddrRange(1, 0)), // Create an empty range if disabled
-  totalNumInsts(0),
   redirectPaths(p.redirect_paths)
 {
 if (workload)
@@ -440,12 +439,6 @@
 }

 void
-System::drainResume()
-{
-totalNumInsts = 0;
-}
-
-void
 System::serialize(CheckpointOut ) const
 {
 SERIALIZE_SCALAR(pagePtr);
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 4954af6..ce77f0a 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -592,10 +592,7 @@
 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

-void drainResume() override;
-
   public:
-Counter totalNumInsts;
 std::map, Tick>  lastWorkItemStarted;
 std::map workItemStats;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5c805ac3b2e87bbacb365108d4060f53e044b4e
Gerrit-Change-Number: 25305
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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