[gem5-dev] Build failed in Jenkins: Nightly #195

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[yazakram] arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use

[Andreas.Sandberg] sim: Thermal model style fixes

[Andreas.Sandberg] sim: Don't serialise params in thermal models

[Andreas.Sandberg] python: Fix incorrect prefixes is m5.utils.convert

[gabe.black] arm: Use the "reg" ABI for gem5 ops.

[gabe.black] riscv: Get rid of some unused constants.

[hoanguyen] dev: Fixing EtherDevice stats initialization order


--
[...truncated 909.55 KB...]
 [ CXX] GCN3_X86/mem/cache/compressors/base_dictionary_compressor.cc -> .o
 [LINK]  -> GCN3_X86/systemc/tlm_bridge/lib.o.partial
 [SO PARAM] Base16Delta8 -> GCN3_X86/params/Base16Delta8.hh
 [SO PARAM] Base32Delta16 -> GCN3_X86/params/Base32Delta16.hh
 [SO PARAM] Base32Delta8 -> GCN3_X86/params/Base32Delta8.hh
 [SO PARAM] Base64Delta16 -> GCN3_X86/params/Base64Delta16.hh
 [SO PARAM] Base64Delta32 -> GCN3_X86/params/Base64Delta32.hh
 [SO PARAM] Base64Delta8 -> GCN3_X86/params/Base64Delta8.hh
 [ CXX] GCN3_X86/mem/cache/compressors/base_delta.cc -> .o
 [LINK]  -> GCN3_X86/systemc/dt/bit/lib.o.partial
 [SO PARAM] CPack -> GCN3_X86/params/CPack.hh
 [ CXX] GCN3_X86/mem/cache/compressors/cpack.cc -> .o
 [SO PARAM] FPC -> GCN3_X86/params/FPC.hh
 [ CXX] GCN3_X86/mem/cache/compressors/fpc.cc -> .o
 [SO PARAM] FPCD -> GCN3_X86/params/FPCD.hh
 [ CXX] GCN3_X86/mem/cache/compressors/fpcd.cc -> .o
 [SO PARAM] FrequentValuesCompressor -> 
GCN3_X86/params/FrequentValuesCompressor.hh
 [ CXX] GCN3_X86/mem/cache/compressors/frequent_values.cc -> .o
 [SO PARAM] MultiCompressor -> GCN3_X86/params/MultiCompressor.hh
 [ CXX] GCN3_X86/mem/cache/compressors/multi.cc -> .o
 [SO PARAM] PerfectCompressor -> GCN3_X86/params/PerfectCompressor.hh
 [ CXX] GCN3_X86/mem/cache/compressors/perfect.cc -> .o
 [SO PARAM] RepeatedQwordsCompressor -> 
GCN3_X86/params/RepeatedQwordsCompressor.hh
 [ CXX] GCN3_X86/mem/cache/compressors/repeated_qwords.cc -> .o
 [SO PARAM] ZeroCompressor -> GCN3_X86/params/ZeroCompressor.hh
 [ CXX] GCN3_X86/mem/cache/compressors/zero.cc -> .o
 [ CXX] GCN3_X86/sim/power/power_model.cc -> .o
 [SO PARAM] MathExprPowerModel -> GCN3_X86/params/MathExprPowerModel.hh
 [ CXX] GCN3_X86/sim/power/mathexpr_powermodel.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/ThermalDomain.hh
 [ CXX] GCN3_X86/sim/power/thermal_domain.cc -> .o
 [SO PARAM] ThermalCapacitor -> GCN3_X86/params/ThermalCapacitor.hh
 [SO PARAM] ThermalReference -> GCN3_X86/params/ThermalReference.hh
 [SO PARAM] ThermalResistor -> GCN3_X86/params/ThermalResistor.hh
 [ CXX] GCN3_X86/sim/power/thermal_model.cc -> .o
 [LINK]  -> GCN3_X86/mem/cache/compressors/lib.o.partial
 [SO PARAM] ThermalNode -> GCN3_X86/params/ThermalNode.hh
 [ CXX] GCN3_X86/sim/power/thermal_node.cc -> .o
 [ENUM STR] AddrMap, True -> GCN3_X86/enums/AddrMap.cc
 [ CXX] GCN3_X86/enums/AddrMap.cc -> .o
 [ENUM STR] ByteOrder, True -> GCN3_X86/enums/ByteOrder.cc
 [ CXX] GCN3_X86/enums/ByteOrder.cc -> .o
 [ENUM STR] CDCType, True -> GCN3_X86/enums/CDCType.cc
 [ CXX] GCN3_X86/enums/CDCType.cc -> .o
 [ENUM STR] Characteristic, True -> GCN3_X86/enums/Characteristic.cc
 [ CXX] GCN3_X86/enums/Characteristic.cc -> .o
 [ENUM STR] Clusivity, True -> GCN3_X86/enums/Clusivity.cc
 [ENUM STR] CommitPolicy, True -> GCN3_X86/enums/CommitPolicy.cc
 [ CXX] GCN3_X86/enums/CommitPolicy.cc -> .o
 [ CXX] GCN3_X86/enums/Clusivity.cc -> .o
 [ENUM STR] Enum, True -> GCN3_X86/enums/Enum.cc
 [ENUMDECL] Enum -> GCN3_X86/enums/Enum.hh
 [ CXX] GCN3_X86/enums/Enum.cc -> .o
 [ENUM STR] ExtCharacteristic, True -> GCN3_X86/enums/ExtCharacteristic.cc
 [ CXX] GCN3_X86/enums/ExtCharacteristic.cc -> .o
 [ENUM STR] GPUStaticInstFlags, True -> GCN3_X86/enums/GPUStaticInstFlags.cc
 [ CXX] GCN3_X86/enums/GPUStaticInstFlags.cc -> .o
 [ENUM STR] IdeID, True -> GCN3_X86/enums/IdeID.cc
 [ CXX] GCN3_X86/enums/IdeID.cc -> .o
 [ENUM STR] ImageFormat, True -> GCN3_X86/enums/ImageFormat.cc
 [ CXX] GCN3_X86/enums/ImageFormat.cc -> .o
 [ENUM STR] MemSched, True -> GCN3_X86/enums/MemSched.cc
 [ CXX] GCN3_X86/enums/MemSched.cc -> .o
 [ENUM STR] MemoryMode, True -> GCN3_X86/enums/MemoryMode.cc
 [ CXX] GCN3_X86/enums/MemoryMode.cc -> .o
 [ENUM STR] MessageRandomization, True -> GCN3_X86/enums/MessageRandomization.cc
 [ CXX] GCN3_X86/enums/MessageRandomization.cc -> .o
 [ENUM STR] OpClass, True -> GCN3_X86/enums/OpClass.cc
 [ CXX] GCN3_X86/enums/OpClass.cc -> .o
 [ENUM STR] PMType, True -> GCN3_X86/enums/PMType.cc
 [ CXX] GCN3_X86/enums/PMType.cc -> .o
 [ENUM STR] PageManage, True -> GCN3_X86/enums/PageManage.cc
 [ CXX] GCN3_X86/enums/PageManage.cc -> .o
 [ENUM STR] PrefetchType, True -> GCN3_X86/enums/PrefetchType.cc
 [ CXX] GCN3_X86/enums/PrefetchType.cc -> .o
 [ENUM STR] PwrState, True -> GCN3_X86/enums/PwrState.cc
 [ CXX] 

[gem5-dev] RFC register sets

[Gabe Black via gem5-dev]

The name in the subject line is bad since it has connotations different
from what I'm going for here, but beyond that it probably is the most
accurate name I can think of. Basically what I'm thinking about is how each
register an instruction processes is handled independently, and how it
might be better to group them all together into a single set of registers
and handle them that way.

Lets say we have an instruction that produces result Rd, and consumes
source registers Rs1, Rs2, and Fp1. It would have some sort of data
structure which would have all those elements in it and accessible in a
standard way, like an index for each and a place for each to put their
value, etc.

struct RegInfo
{
RegIdx idx;
// Value from subclass with an appropriately typed member.
}

When an instruction is being created, the basic info would be put into this
structure in a static way based on the instruction's encoding. As the
instruction is processed, renamed, etc, all those registers would be
handled to, for instance, the register flattening function, in a batch. If
that flattening function became virtual in an effort to make the CPUs more
ISA agnostic, then you'd pay the virtual function overhead once instead of
once per register.

Then, when the instruction goes to actually execute, a pre-step would be to
accumulate all the register values into this structure and hand it to the
execute method. The instruction would operate on it, and then fill in
destination values which it would not write back, that would be a post step.

Another nice property this sort of setup would have is that instruction
tracing would get easier and less hacky. Right now the InstRecord
associated with an instruction has a fixed number of slots for register
values, and that's it. If you wanted to really trace an instruction and see
what values its registers had before and after, you could store the entire
structure that held the registers values before and after and then go down
the line and print every registers value if you wanted, without having to
hope they're in the right order, you stored the register that actually
mattered, etc.

This would also potentially be a nice way to store all register values in a
database tracing execution which you could browse through after the fact
meaningfully. You could, for instance, rewind the behavior of an
instruction since you have a register delta of exactly what registers it
changed and to what values. You might need "key frames" now and again to
avoid storing before and after values for all registers, but this could be
a very powerful debugging tool.

Anyway, I haven't done any work on this and don't plan to in the very near
future, but I think it sounds like an idea with a lot of upside. Let me
know what you think.

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Simplify LGKM decrementing for Flat instructions

[Kyle Roarty (Gerrit) via gem5-dev]

Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39396 )


Change subject: gpu-compute: Simplify LGKM decrementing for Flat  
instructions

..

gpu-compute: Simplify LGKM decrementing for Flat instructions

This commit makes it so LGKM count is decremented in a single place
(after completeAcc), which fixes a couple of potential bugs

1. Data is only written by completeAcc, not after initiateAcc. LGKM
count is supposed to be decremented after data is written.
2. LGKM count is now properly decremented for atomics without return

Change-Id: Ic791af3b42e04f7baaa0ce50cb2a2c6286c54f5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39396
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/global_memory_pipeline.cc
1 file changed, 1 insertion(+), 5 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass



diff --git a/src/gpu-compute/global_memory_pipeline.cc  
b/src/gpu-compute/global_memory_pipeline.cc

index 48f767b..2f251e8 100644
--- a/src/gpu-compute/global_memory_pipeline.cc
+++ b/src/gpu-compute/global_memory_pipeline.cc
@@ -130,7 +130,7 @@
 DPRINTF(GPUMem, "CU%d: WF[%d][%d]: Completing global mem  
instr %s\n",

 m->cu_id, m->simdId, m->wfSlotId, m->disassemble());
 m->completeAcc(m);
-if (m->isFlat() && (m->isLoad() || m->isAtomicRet())) {
+if (m->isFlat()) {
 w->decLGKMInstsIssued();
 }
 w->decVMemInstsIssued();
@@ -196,10 +196,6 @@
 mp->disassemble(), mp->seqNum());
 mp->initiateAcc(mp);

-if (mp->isFlat() && mp->isStore()) {
-mp->wavefront()->decLGKMInstsIssued();
-}
-
 if (mp->isStore() && mp->isGlobalSeg()) {
 mp->wavefront()->decExpInstsIssued();
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39396
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic791af3b42e04f7baaa0ce50cb2a2c6286c54f5a
Gerrit-Change-Number: 39396
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix unsigned underflow mishandling.

[Philip Metzler (Gerrit) via gem5-dev]

Philip Metzler has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39496 )


Change subject: base: Fix unsigned underflow mishandling.
..

base: Fix unsigned underflow mishandling.

The second argument in the std::max call is treated as an unsigned value
as all variables are unsigned as well. This will result in an
unsigned underflow, and as such the std::max is a no-op and will result
in the underflowed value.

The `start` and `used` value get corrupted after that, and checks for
`empty` and other stuff downstream break.

Change-Id: I00017e22ba84e65f6b1c596f47d348f342fbc304
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39496
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/circlebuf.hh
M src/base/circlebuf.test.cc
2 files changed, 22 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/circlebuf.hh b/src/base/circlebuf.hh
index bcfa91a..77a05d7 100644
--- a/src/base/circlebuf.hh
+++ b/src/base/circlebuf.hh
@@ -167,7 +167,9 @@
 }

 // How much existing data will be overwritten?
-const size_t overflow = std::max(0, used + len - maxSize);
+const size_t total_bytes = used + len;
+const size_t overflow = total_bytes > maxSize ?
+total_bytes - maxSize : 0;
 // The iterator of the next byte to add.
 auto next_it = buffer.begin() + (start + used) % maxSize;
 // How much there is to copy to the end of the buffer.
diff --git a/src/base/circlebuf.test.cc b/src/base/circlebuf.test.cc
index 6b81b61..2e1f6bd 100644
--- a/src/base/circlebuf.test.cc
+++ b/src/base/circlebuf.test.cc
@@ -130,3 +130,22 @@
 EXPECT_EQ(buf.size(), 0);
 EXPECT_THAT(subArr(foo, 12), ElementsAreArray(data, 12));
 }
+
+// Consume after produce empties queue
+TEST(CircleBufTest, ProduceConsumeEmpty)
+{
+CircleBuf buf(8);
+char foo[1];
+
+// buf is empty to begin with.
+EXPECT_TRUE(buf.empty());
+// Produce one element.
+buf.write(foo, 1);
+EXPECT_FALSE(buf.empty());
+
+// Read it back out.
+buf.read(foo, 1);
+
+// Now the buffer should be empty again.
+EXPECT_TRUE(buf.empty());
+}

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39496
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https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I00017e22ba84e65f6b1c596f47d348f342fbc304
Gerrit-Change-Number: 39496
Gerrit-PatchSet: 3
Gerrit-Owner: Philip Metzler 
Gerrit-Reviewer: Andreas Diavastos 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Philip Metzler 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove Python 2.7 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39584 )



Change subject: python: Remove Python 2.7 compatibility code
..

python: Remove Python 2.7 compatibility code

We don't support Python 2.7 anymore. Remove glue code like the six
dependency and "from __future__" imports from gem5's standard library.

Change-Id: I71834c325f86ff0329b222be87794ead96081f05
Signed-off-by: Andreas Sandberg 
---
M src/python/importer.py
M src/python/m5/SimObject.py
M src/python/m5/__init__.py
M src/python/m5/core.py
M src/python/m5/debug.py
M src/python/m5/event.py
M src/python/m5/ext/__init__.py
M src/python/m5/internal/params.py
M src/python/m5/main.py
M src/python/m5/objects/__init__.py
M src/python/m5/options.py
M src/python/m5/params.py
M src/python/m5/proxy.py
M src/python/m5/simulate.py
M src/python/m5/stats/__init__.py
M src/python/m5/ticks.py
M src/python/m5/trace.py
M src/python/m5/util/__init__.py
M src/python/m5/util/attrdict.py
M src/python/m5/util/code_formatter.py
M src/python/m5/util/convert.py
M src/python/m5/util/dot_writer.py
M src/python/m5/util/fdthelper.py
M src/python/m5/util/grammar.py
M src/python/m5/util/jobfile.py
M src/python/m5/util/multidict.py
M src/python/m5/util/pybind.py
M src/python/m5/util/terminal.py
28 files changed, 32 insertions(+), 133 deletions(-)



diff --git a/src/python/importer.py b/src/python/importer.py
index c29fb7b..b89b4a8 100644
--- a/src/python/importer.py
+++ b/src/python/importer.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 # Simple importer that allows python to import data from a dict of
 # code objects.  The keys are the module path, and the items are the
 # filename and bytecode of the file.
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b47d98d..1697237 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -38,13 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-from six import add_metaclass
-import six
-if six.PY3:
-long = int
-
 import sys
 from types import FunctionType, MethodType, ModuleType
 from functools import wraps
@@ -1178,8 +1171,7 @@
 # The SimObject class is the root of the special hierarchy.  Most of
 # the code in this class deals with the configuration hierarchy itself
 # (parent/child node relationships).
-@add_metaclass(MetaSimObject)
-class SimObject(object):
+class SimObject(object, metaclass=MetaSimObject):
 # Specify metaclass.  Any class inheriting from SimObject will
 # get this metaclass.
 type = 'SimObject'
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 309764d..254d9a6 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 # Import useful subpackages of M5, but *only* when run as an m5
 # script.  This is mostly to keep backward compatibility with existing
 # scripts while allowing new SCons code to operate properly.
diff --git a/src/python/m5/core.py b/src/python/m5/core.py
index 34d54bc..fcbf4aa 100644
--- a/src/python/m5/core.py
+++ b/src/python/m5/core.py
@@ -36,8 +36,5 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from _m5.core import setOutputDir
 from _m5.loader import setInterpDir
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index 6b45b16..10d0980 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from collections import Mapping

 import _m5.debug
diff --git a/src/python/m5/event.py b/src/python/m5/event.py
index 9b5532c..f0230cf 100644
--- a/src/python/m5/event.py
+++ b/src/python/m5/event.py
@@ -38,8 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import m5
 import _m5.event

diff --git a/src/python/m5/ext/__init__.py b/src/python/m5/ext/__init__.py
index f950c98..cdd1f42 100644
--- 

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2 compatibility code in Arm configs

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39581 )



Change subject: configs: Remove Python 2 compatibility code in Arm configs
..

configs: Remove Python 2 compatibility code in Arm configs

Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: If37718ba99def2d6f176604e20d4ebeda75474ad
Signed-off-by: Andreas Sandberg 
---
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/dist_bigLITTLE.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/arm/workloads.py
8 files changed, 1 insertion(+), 31 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 04f60a1..011883b 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -39,9 +39,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index e3cee1e..52613c6 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -35,20 +35,12 @@

 # System components used by the bigLITTLE.py configuration script

-from __future__ import print_function
-from __future__ import absolute_import
-
-import six
-
 import m5
 from m5.objects import *
 m5.util.addToPath('../../')
 from common.Caches import *
 from common import ObjectList

-if six.PY3:
-long = int
-
 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()

@@ -320,7 +312,7 @@
 self.iobridge = Bridge(delay='50ns')
 # Device DMA -> MEM
 mem_range = self.realview._mem_regions[0]
-assert long(mem_range.size()) >= long(Addr(mem_size))
+assert int(mem_range.size()) >= int(Addr(mem_size))
 self.mem_ranges = [
 AddrRange(start=mem_range.start, size=mem_size) ]

diff --git a/configs/example/arm/dist_bigLITTLE.py  
b/configs/example/arm/dist_bigLITTLE.py

index 1d82666..6d35e53 100644
--- a/configs/example/arm/dist_bigLITTLE.py
+++ b/configs/example/arm/dist_bigLITTLE.py
@@ -36,9 +36,6 @@
 # This configuration file extends the example ARM big.LITTLE(tm)
 # configuration to enabe dist-gem5 siulations of big.LITTLE systems.

-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os

diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 090e071..85213ee 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -36,10 +36,6 @@
 # This is an example configuration script for full system simulation of
 # a generic ARM bigLITTLE system.

-
-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os
 import sys
diff --git a/configs/example/arm/fs_power.py  
b/configs/example/arm/fs_power.py

index 72c6292..1c7b6b7 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -36,9 +36,6 @@
 # This configuration file extends the example ARM big.LITTLE(tm)
 # with example power models.

-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os

diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index 8dee137..9d0f0d2 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -38,9 +38,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index 8b1dbd2..23da8e7 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -38,9 +38,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/workloads.py  
b/configs/example/arm/workloads.py

index ce48cdd..1fb9d00 100644
--- a/configs/example/arm/workloads.py
+++ b/configs/example/arm/workloads.py
@@ -34,9 +34,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #

-from __future__ import print_function
-from __future__ import absolute_import
-
 import inspect
 import m5
 from m5.objects import *

--
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To unsubscribe, or 

[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39582 )



Change subject: configs: Weed out old port terminology in Arm examples
..

configs: Weed out old port terminology in Arm examples

Stop using the deprecated port names in Arm example scripts.

Change-Id: I11fea3e0df945ac64075b647766570604b70cad8
Signed-off-by: Andreas Sandberg 
---
M configs/common/MemConfig.py
M configs/example/arm/devices.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/starter_se.py
4 files changed, 20 insertions(+), 19 deletions(-)



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 63301ab..94b1655 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -151,7 +151,7 @@
 system.external_memory = m5.objects.ExternalSlave(
 port_type="tlm_slave",
 port_data=opt_tlm_memory,
-port=system.membus.master,
+port=system.membus.mem_side_ports,
 addr_ranges=system.mem_ranges)
 system.workload.addr_check = False
 return
@@ -269,12 +269,12 @@
 for i in range(len(mem_ctrls)):
 if opt_mem_type == "HMC_2500_1x32":
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar[i/4].master
+mem_ctrls[i].port = xbar[i/4].mem_side_ports
 # Set memory device size. There is an independent controller
 # for each vault. All vaults are same size.
 mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size
 else:
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar.master
+mem_ctrls[i].port = xbar.mem_side_ports

 subsystem.mem_ctrls = mem_ctrls
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 52613c6..9ef4d70 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -151,7 +151,7 @@
 self.l2 = self._l2_type()
 for cpu in self.cpus:
 cpu.connectAllPorts(self.toL2Bus)
-self.toL2Bus.master = self.l2.cpu_side
+self.toL2Bus.mem_side_ports = self.l2.cpu_side

 def addPMUs(self, ints, events=[]):
 """
@@ -181,7 +181,7 @@

 def connectMemSide(self, bus):
 try:
-self.l2.mem_side = bus.slave
+self.l2.mem_side = bus.cpu_side_ports
 except AttributeError:
 for cpu in self.cpus:
 cpu.connectAllPorts(bus)
@@ -223,8 +223,9 @@
 ])

 gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m)
-gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm,  
gem5=system.iobus.slave)

-gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master)
+gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm,
+gem5=system.iobus.cpu_side_ports)
+gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.mem_side_ports)
 gic_g2t.addr_ranges = gic.get_addr_ranges()
 gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm)
 gic.amba_s = gic_t2a.amba
@@ -255,7 +256,7 @@
 self.cpus = [ cpu ]

 a2t = AmbaToTlmBridge64(amba=cpu.amba)
-t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave)
+t2g = TlmToGem5Bridge64(tlm=a2t.tlm,  
gem5=system.membus.cpu_side_ports)

 system.gic_hub.a2t = a2t
 system.gic_hub.t2g = t2g

@@ -330,21 +331,21 @@
 self.realview.attachPciDevice(dev, self.iobus)

 def connect(self):
-self.iobridge.master = self.iobus.slave
-self.iobridge.slave = self.membus.master
+self.iobridge.mem_side_port = self.iobus.cpu_side_ports
+self.iobridge.cpu_side_port = self.membus.mem_side_ports

 if self._caches:
-self.iocache.mem_side = self.membus.slave
-self.iocache.cpu_side = self.iobus.master
+self.iocache.mem_side = self.membus.cpu_side_ports
+self.iocache.cpu_side = self.iobus.mem_side_ports
 else:
-self.dmabridge.master = self.membus.slave
-self.dmabridge.slave = self.iobus.master
+self.dmabridge.mem_side_port = self.membus.cpu_side_ports
+self.dmabridge.cpu_side_port = self.iobus.mem_side_ports

 if hasattr(self.realview.gic, 'cpu_addr'):
 self.gic_cpu_addr = self.realview.gic.cpu_addr
 self.realview.attachOnChipIO(self.membus, self.iobridge)
 self.realview.attachIO(self.iobus)
-self.system_port = self.membus.slave
+self.system_port = self.membus.cpu_side_ports

 def numCpuClusters(self):
 return len(self._clusters)
@@ -377,8 +378,8 @@
 key=lambda c:  
c.clk_domain.clock[0])

 self.l3 = 

[gem5-dev] Change in gem5/gem5[develop]: scons: Remove Python 2.7 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39585 )



Change subject: scons: Remove Python 2.7 compatibility code
..

scons: Remove Python 2.7 compatibility code

Remove the dependency on six and most 'import x from __future__'. A
few instances of imports from the future have been left in place to
ensure that Python 2.7 users still get an error message when invoking
scons.

Change-Id: I366275a6040f0084e91198b5b5c2a648bffbf2d2
Signed-off-by: Andreas Sandberg 
---
M SConstruct
M ext/libelf/SConscript
M ext/systemc/SConscript
M ext/systemc/src/sysc/kernel/SConscript.sc
M site_scons/gem5_scons/__init__.py
M site_scons/site_tools/git.py
M src/SConscript
M src/mem/ruby/SConscript
M src/systemc/tests/SConscript
9 files changed, 5 insertions(+), 26 deletions(-)



diff --git a/SConstruct b/SConstruct
index b5505ff..4cf2f10 100755
--- a/SConstruct
+++ b/SConstruct
@@ -75,8 +75,6 @@
 #
 ###

-from __future__ import print_function
-
 # Global Python includes
 import atexit
 import itertools
diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript
index 3bf5b30..e2cc847 100644
--- a/ext/libelf/SConscript
+++ b/ext/libelf/SConscript
@@ -28,8 +28,6 @@
 #
 # Authors: Nathan Binkert

-from __future__ import print_function
-
 import os, subprocess

 Import('main')
diff --git a/ext/systemc/SConscript b/ext/systemc/SConscript
index cb0c61d..0b6fb0c 100644
--- a/ext/systemc/SConscript
+++ b/ext/systemc/SConscript
@@ -23,8 +23,6 @@
 # Authors: Christian Menard
 #  Matthias Jung

-from __future__ import print_function
-
 import os
 from m5.util.terminal import get_termcap

diff --git a/ext/systemc/src/sysc/kernel/SConscript.sc  
b/ext/systemc/src/sysc/kernel/SConscript.sc

index ac79c2f..0e21f74 100644
--- a/ext/systemc/src/sysc/kernel/SConscript.sc
+++ b/ext/systemc/src/sysc/kernel/SConscript.sc
@@ -23,8 +23,6 @@
 # Authors: Christian Menard
 #  Matthias Jung

-from __future__ import print_function
-
 Import('systemc', 'SystemCSource')

 SystemCSource(
diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index 4208cf1..708002f 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -38,8 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import textwrap
diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index 87738b8..a77cffb 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -38,13 +38,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
 import os
 import sys

 import gem5_scons.util
 from m5.util import readCommand
-from six.moves import input

 git_style_message = """
 You're missing the gem5 style or commit message hook. These hooks help
diff --git a/src/SConscript b/src/SConscript
index b55f485..dc57260 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -37,8 +37,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import array
 import bisect
 import distutils.spawn
@@ -46,7 +44,6 @@
 import imp
 import os
 import re
-import six
 import sys
 import zlib

@@ -144,8 +141,7 @@
 super(SourceMeta, cls).__init__(name, bases, dict)
 cls.all = SourceList()

-@six.add_metaclass(SourceMeta)
-class SourceFile(object):
+class SourceFile(object, metaclass=SourceMeta):
 '''Base object that encapsulates the notion of a source file.
 This includes, the source node, target node, various manipulations
 of those.  A source file also specifies a set of tags which
@@ -157,14 +153,14 @@
 def __init__(self, source, tags=None, add_tags=None, append=None):
 if tags is None:
 tags='gem5 lib'
-if isinstance(tags, six.string_types):
+if isinstance(tags, str):
 tags = set([tags])
 if not isinstance(tags, set):
 tags = set(tags)
 self.tags = tags

 if add_tags:
-if isinstance(add_tags, six.string_types):
+if isinstance(add_tags, str):
 add_tags = set([add_tags])
 if not isinstance(add_tags, set):
 add_tags = set(add_tags)
@@ -266,7 +262,7 @@
 cpp_code(symbol_declaration + ' = {')
 cpp_code.indent()
 step = 16
-for i in six.moves.range(0, len(data), step):
+for i in range(0, len(data), step):
 x = array.array('B', data[i:i+step])
 cpp_code(''.join('%d,' % d for d in x))
 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Don't use deprecated port names

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39583 )



Change subject: cpu: Don't use deprecated port names
..

cpu: Don't use deprecated port names

The BaseCPU has a couple of helper methods that wire up ports using
the deprecated port names. Fix that.

Change-Id: I68452eeef921347e8773d50efd210d2c6844fd90
Signed-off-by: Andreas Sandberg 
---
M src/cpu/BaseCPU.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 025e985..d981570 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -192,13 +192,13 @@

 def connectCachedPorts(self, bus):
 for p in self._cached_ports:
-exec('self.%s = bus.slave' % p)
+exec('self.%s = bus.cpu_side_ports' % p)

 def connectUncachedPorts(self, bus):
 for p in self._uncached_interrupt_response_ports:
-exec('self.%s = bus.master' % p)
+exec('self.%s = bus.mem_side_ports' % p)
 for p in self._uncached_interrupt_request_ports:
-exec('self.%s = bus.slave' % p)
+exec('self.%s = bus.cpu_side_ports' % p)

 def connectAllPorts(self, cached_bus, uncached_bus = None):
 self.connectCachedPorts(cached_bus)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I68452eeef921347e8773d50efd210d2c6844fd90
Gerrit-Change-Number: 39583
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Remove Python 2 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39580 )



Change subject: arch-arm, dev-arm: Remove Python 2 compatibility code
..

arch-arm, dev-arm: Remove Python 2 compatibility code

Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/ArmSystem.py
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/css/MHU.py
5 files changed, 7 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 7ab4b6e..f7d9cd5 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -108,7 +108,7 @@
 # root instead of appended.

 def generateMemNode(mem_range):
-node = FdtNode("memory@%x" % long(mem_range.start))
+node = FdtNode("memory@%x" % int(mem_range.start))
 node.append(FdtPropertyStrings("device_type", ["memory"]))
 node.append(FdtPropertyWords("reg",
 state.addrCells(mem_range.start) +
diff --git a/src/dev/Device.py b/src/dev/Device.py
index af49504..46e992c 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -51,7 +51,7 @@

 def generateBasicPioDeviceNode(self, state, name, pio_addr,
size, interrupts = None):
-node = FdtNode("%s@%x" % (name, long(pio_addr)))
+node = FdtNode("%s@%x" % (name, int(pio_addr)))
 node.append(FdtPropertyWords("reg",
 state.addrCells(pio_addr) +
 state.sizeCells(size) ))
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8fa0edd..81d1f07 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -211,7 +211,7 @@
 idreg = Param.UInt32(0x, "ID Register, SYS_ID")

 def generateDeviceTree(self, state):
-node = FdtNode("sysreg@%x" % long(self.pio_addr))
+node = FdtNode("sysreg@%x" % int(self.pio_addr))
 node.appendCompatible("arm,vexpress-sysreg")
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@

 def generateDeviceTree(self, state):
 phandle = state.phandle(self)
-node = FdtNode("osc@" + format(long(phandle), 'x'))
+node = FdtNode("osc@" + format(int(phandle), 'x'))
 node.appendCompatible("arm,vexpress-osc")
 node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
  [0x1, int(self.device)]))
@@ -595,7 +595,7 @@
 super(MmioSRAM, self).__init__(**kwargs)

 def generateDeviceTree(self, state):
-node = FdtNode("sram@%x" % long(self.range.start))
+node = FdtNode("sram@%x" % int(self.range.start))
 node.appendCompatible(["mmio-sram"])
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.range.start) +
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index f444d64..85c10ad 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -187,7 +187,7 @@
 def generateDeviceTree(self, state):
 reg_addr = self.reg_map.start
 reg_size = self.reg_map.size()
-node = FdtNode("smmuv3@%x" % long(reg_addr))
+node = FdtNode("smmuv3@%x" % int(reg_addr))
 node.appendCompatible("arm,smmu-v3")
 node.append(FdtPropertyWords("reg",
 state.addrCells(reg_addr) +
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
index 878ca22..f5bb7e5 100644
--- a/src/dev/arm/css/MHU.py
+++ b/src/dev/arm/css/MHU.py
@@ -89,7 +89,7 @@
 scp = Param.Scp(Parent.any, "System Control Processor")

 def generateDeviceTree(self, state):
-node = FdtNode("mailbox@%x" % long(self.pio_addr))
+node = FdtNode("mailbox@%x" % int(self.pio_addr))
 node.appendCompatible(["arm,mhu", "arm,primecell"])
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.pio_addr) +

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Gerrit-Change-Number: 39580
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39579 )



Change subject: sim: Consistently use ISO prefixes
..

sim: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Signed-off-by: Andreas Sandberg 
---
M src/sim/Process.py
M src/sim/syscall_emul.hh
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/sim/Process.py b/src/sim/Process.py
index bdcb826..767dbfa 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -44,7 +44,7 @@
 useArchPT = Param.Bool('false', 'maintain an in-memory version of the  
page\

 table in an architecture-specific format')
 kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in  
SE')

-maxStackSize = Param.MemorySize('64MB', 'maximum size of the stack')
+maxStackSize = Param.MemorySize('64MiB', 'maximum size of the stack')

 uid = Param.Int(100, 'user id')
 euid = Param.Int(100, 'effective user id')
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 79cd35a..16fd175 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1824,7 +1824,7 @@
 const ByteOrder bo = OS::byteOrder;
 switch (resource) {
   case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
 rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
 rlp->rlim_cur = htog(rlp->rlim_cur, bo);
 rlp->rlim_max = htog(rlp->rlim_max, bo);
@@ -1867,7 +1867,7 @@
 const ByteOrder bo = OS::byteOrder;
 switch (resource) {
   case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
 rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
 rlp->rlim_cur = htog(rlp->rlim_cur, bo);
 rlp->rlim_max = htog(rlp->rlim_max, bo);

--
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Gerrit-Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Gerrit-Change-Number: 39579
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39562 )



Change subject: cpu: Stop "using namespace std"
..

cpu: Stop "using namespace std"

Change-Id: I1b648914d353672076d903ed581aa61cdd7c1d0f
---
M src/cpu/activity.cc
M src/cpu/base.cc
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu_impl.hh
M src/cpu/exetrace.cc
M src/cpu/func_unit.cc
M src/cpu/inteltrace.cc
M src/cpu/intr_control.cc
M src/cpu/intr_control_noisa.cc
M src/cpu/nativetrace.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/fu_pool.cc
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rob_impl.hh
M src/cpu/pc_event.cc
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/timing.cc
M src/cpu/simple_thread.cc
M src/cpu/static_inst.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/hybrid_gen.cc
M src/cpu/testers/traffic_gen/traffic_gen.cc
30 files changed, 142 insertions(+), 194 deletions(-)



diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc
index 4e8b558..2c8df0e 100644
--- a/src/cpu/activity.cc
+++ b/src/cpu/activity.cc
@@ -33,9 +33,7 @@
 #include "cpu/timebuf.hh"
 #include "debug/Activity.hh"

-using namespace std;
-
-ActivityRecorder::ActivityRecorder(const string , int num_stages,
+ActivityRecorder::ActivityRecorder(const std::string , int num_stages,
 int longest_latency, int activity)
 : _name(name), activityBuffer(longest_latency, 0),
   longestLatency(longest_latency), activityCount(activity),
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 0c998be..af928f1 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -71,11 +71,9 @@
 // Hack
 #include "sim/stat_control.hh"

-using namespace std;
-
 std::unique_ptr BaseCPU::globalStats;

-vector BaseCPU::cpuList;
+std::vector BaseCPU::cpuList;

 // This variable reflects the max number of threads in any CPU.  Be
 // careful to only use it once all the CPUs that you care about have
@@ -156,7 +154,7 @@

 functionTracingEnabled = false;
 if (p.function_trace) {
-const string fname = csprintf("ftrace.%s", name());
+const std::string fname = csprintf("ftrace.%s", name());
 functionTraceStream = simout.findOrCreate(fname)->stream();

 currentFunctionStart = currentFunctionEnd = 0;
@@ -395,7 +393,7 @@
 int size = threadContexts.size();
 if (size > 1) {
 for (int i = 0; i < size; ++i) {
-stringstream namestr;
+std::stringstream namestr;
 ccprintf(namestr, "%s.ctx%d", name(), i);
 threadContexts[i]->regStats(namestr.str());
 }
@@ -404,7 +402,7 @@
 }

 Port &
-BaseCPU::getPort(const string _name, PortID idx)
+BaseCPU::getPort(const std::string _name, PortID idx)
 {
 // Get the right port based on name. This applies to all the
 // subclasses of the base CPU and relies on their implementation
@@ -708,7 +706,7 @@
 auto it = Loader::debugSymbolTable.findNearest(
 pc, currentFunctionEnd);

-string sym_str;
+std::string sym_str;
 if (it == Loader::debugSymbolTable.end()) {
 // no symbol found: use addr as label
 sym_str = csprintf("%#x", pc);
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index ccbc649..8815530 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -52,7 +52,6 @@
 #include "params/CheckerCPU.hh"
 #include "sim/full_system.hh"

-using namespace std;
 using namespace TheISA;

 void
@@ -124,7 +123,7 @@
 }

 void
-CheckerCPU::serialize(ostream ) const
+CheckerCPU::serialize(std::ostream ) const
 {
 }

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 70dc451..733cf1c 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -59,7 +59,6 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"

-using namespace std;
 using namespace TheISA;

 template 
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 4980c91..02ede1a 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -53,7 +53,6 @@
 #include "debug/FmtTicksOff.hh"
 #include "enums/OpClass.hh"

-using namespace std;
 using namespace TheISA;

 namespace Trace {
@@ -70,7 +69,7 @@
 }

 if (Debug::ExecAsid)
-outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
+outs << "A" << std::dec << TheISA::getExecutingAsid(thread) << " ";

 if (Debug::ExecThread)
 outs << "T" << thread->threadId() << " : ";
@@ -100,7 +99,7 @@
 //  Print decoded instruction
 //

-outs << setw(26) << left;
+outs << std::setw(26) << std::left;
 outs << inst->disassemble(cur_pc, ::debugSymbolTable);

 if (ran) {
@@ -150,13 +149,13 @@
 

[gem5-dev] Change in gem5/gem5[develop]: tests: Stop "using namespace std" in unittest/.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39565 )



Change subject: tests: Stop "using namespace std" in unittest/.
..

tests: Stop "using namespace std" in unittest/.

These are the historical "unit test"s, which aren't really unit tests,
they're actually complete builds of gem5 with main functions which run a
fairly specific test instead of a simulation. They test a single unit,
but they do it with all the other units in place and potentially
participating in the test.

Change-Id: Ib0ea68f26091a79992396d932627e4ce180f7825
---
M src/unittest/cprintftime.cc
M src/unittest/nmtest.cc
M src/unittest/stattest.cc
M src/unittest/symtest.cc
4 files changed, 13 insertions(+), 17 deletions(-)



diff --git a/src/unittest/cprintftime.cc b/src/unittest/cprintftime.cc
index f8f1492..a09c4cb 100644
--- a/src/unittest/cprintftime.cc
+++ b/src/unittest/cprintftime.cc
@@ -36,8 +36,6 @@

 #include "base/cprintf.hh"

-using namespace std;
-
 volatile int stop = false;

 void
@@ -56,14 +54,14 @@
 int
 main()
 {
-stringstream result;
+std::stringstream result;
 int iterations = 0;

 signal(SIGALRM, handle_alarm);

 do_test(10);
 while (!stop) {
-stringstream result;
+std::stringstream result;
 ccprintf(result,
  "this is a %s of %d iterations %3.2f %p\n",
  "test", iterations, 51.934, );
diff --git a/src/unittest/nmtest.cc b/src/unittest/nmtest.cc
index f25c5e1..fd24524 100644
--- a/src/unittest/nmtest.cc
+++ b/src/unittest/nmtest.cc
@@ -34,8 +34,6 @@
 #include "base/logging.hh"
 #include "base/str.hh"

-using namespace std;
-
 int
 main(int argc, char *argv[])
 {
@@ -50,7 +48,7 @@
 for (const Loader::Symbol : obj->symtab())
 cprintf("%#x %s\n", symbol.address, symbol.name);
 } else {
-string symbol = argv[2];
+std::string symbol = argv[2];
 Addr address;

 if (symbol[0] == '0' && symbol[1] == 'x') {
diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc
index e58a5a6..650c137 100644
--- a/src/unittest/stattest.cc
+++ b/src/unittest/stattest.cc
@@ -50,7 +50,6 @@
 0 // sentinel is required
 };

-using namespace std;
 using namespace Stats;

 double testfunc();
diff --git a/src/unittest/symtest.cc b/src/unittest/symtest.cc
index 369e1a4..6de3c8d 100644
--- a/src/unittest/symtest.cc
+++ b/src/unittest/symtest.cc
@@ -31,14 +31,13 @@
 #include "base/loader/symtab.hh"
 #include "base/str.hh"

-using namespace std;
-
 void usage(const char *progname);

 void
 usage(const char *progname)
 {
-cout << "Usage: " << progname << "  " << endl;
+std::cout << "Usage: " << progname << "  "
+<< std::endl;

 exit(1);
 }
@@ -52,29 +51,31 @@
 usage(argv[0]);

 if (!symtab.load(argv[1])) {
-cout << "could not load symbol file: " << argv[1] << endl;
+std::cout << "could not load symbol file: " << argv[1] <<  
std::endl;

 exit(1);
 }

-string symbol = argv[2];
+std::string symbol = argv[2];
 Addr address;

 if (!to_number(symbol, address)) {
 auto it = symtab.find(symbol);
 if (it == symtab.end()) {
-cout << "could not find symbol: " << symbol << endl;
+std::cout << "could not find symbol: " << symbol << std::endl;
 exit(1);
 }

-cout << symbol << " -> " << "0x" << hex << it->address << endl;
+std::cout << symbol << " -> " << "0x" << std::hex << it->address <<
+std::endl;
 } else {
 auto it = symtab.find(address);
 if (it == symtab.end()) {
-cout << "could not find address: " << address << endl;
+std::cout << "could not find address: " << address <<  
std::endl;

 exit(1);
 }

-cout << "0x" << hex << address << " -> " << it->name << endl;
+std::cout << "0x" << std::hex << address << " -> " << it->name <<
+std::endl;
 }

 return 0;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib0ea68f26091a79992396d932627e4ce180f7825
Gerrit-Change-Number: 39565
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: Fix building of unittest/stattest.cc.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39564 )



Change subject: tests: Fix building of unittest/stattest.cc.
..

tests: Fix building of unittest/stattest.cc.

This file wasn't including eventq.hh which it happened to be getting
transitively before.

Change-Id: I8ce5572651ddd59160d84794bf5efc90c82d83e6
---
M src/unittest/stattest.cc
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc
index 4030735..e58a5a6 100644
--- a/src/unittest/stattest.cc
+++ b/src/unittest/stattest.cc
@@ -37,6 +37,7 @@
 #include "base/statistics.hh"
 #include "base/types.hh"
 #include "sim/core.hh"
+#include "sim/eventq.hh"
 #include "sim/init.hh"
 #include "sim/stat_control.hh"


--
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[gem5-dev] Change in gem5/gem5[develop]: misc: Stop "using namespace std" in protoio.cc.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39563 )



Change subject: misc: Stop "using namespace std" in protoio.cc.
..

misc: Stop "using namespace std" in protoio.cc.

Change-Id: I4f27979910230860c631b63bb500f87b45c24e33
---
M src/proto/protoio.cc
1 file changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/proto/protoio.cc b/src/proto/protoio.cc
index 691d4ee..72e463b 100644
--- a/src/proto/protoio.cc
+++ b/src/proto/protoio.cc
@@ -39,11 +39,11 @@

 #include "base/logging.hh"

-using namespace std;
 using namespace google::protobuf;

-ProtoOutputStream::ProtoOutputStream(const string& filename) :
-fileStream(filename.c_str(), ios::out | ios::binary | ios::trunc),
+ProtoOutputStream::ProtoOutputStream(const std::string& filename) :
+fileStream(filename.c_str(),
+std::ios::out | std::ios::binary | std::ios::trunc),
 wrappedFileStream(NULL), gzipStream(NULL), zeroCopyStream(NULL)
 {
 if (!fileStream.good())
@@ -98,9 +98,9 @@
 msg.SerializeWithCachedSizes();
 }

-ProtoInputStream::ProtoInputStream(const string& filename) :
-fileStream(filename.c_str(), ios::in | ios::binary),  
fileName(filename),

-useGzip(false),
+ProtoInputStream::ProtoInputStream(const std::string& filename) :
+fileStream(filename.c_str(), std::ios::in | std::ios::binary),
+fileName(filename), useGzip(false),
 wrappedFileStream(NULL), gzipStream(NULL), zeroCopyStream(NULL)
 {
 if (!fileStream.good())
@@ -113,7 +113,7 @@

 // seek to the start of the input file and clear any flags
 fileStream.clear();
-fileStream.seekg(0, ifstream::beg);
+fileStream.seekg(0, std::ifstream::beg);

 createStreams();
 }
@@ -172,7 +172,7 @@
 destroyStreams();
 // seek to the start of the input file and clear any flags
 fileStream.clear();
-fileStream.seekg(0, ifstream::beg);
+fileStream.seekg(0, std::ifstream::beg);
 createStreams();
 }


--
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[gem5-dev] Change in gem5/gem5[develop]: dev: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39578 )



Change subject: dev: Consistently use ISO prefixes
..

dev: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I6ab03934af850494d95a37dcda5c2000794b4d3a
Signed-off-by: Andreas Sandberg 
---
M src/dev/net/Ethernet.py
M src/dev/pci/CopyEngine.py
M src/dev/x86/Pc.py
3 files changed, 20 insertions(+), 19 deletions(-)



diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index dd878e2..e5c5562 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -92,10 +92,11 @@
 type = 'EtherSwitch'
 cxx_header = "dev/net/etherswitch.hh"
 dump = Param.EtherDump(NULL, "dump object")
-fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed  
in bits "

-  "per second")
+fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed  
in "

+  "bits per second")
 interface = VectorEtherInt("Ethernet Interface")
-output_buffer_size = Param.MemorySize('1MB', "size of output port  
buffers")

+output_buffer_size = Param.MemorySize('1MiB',
+  "size of output port buffers")
 delay = Param.Latency('0us', "packet transmit delay")
 delay_var = Param.Latency('0ns', "packet transmit delay variability")
 time_to_live = Param.Latency('10ms', "time to live of MAC address  
maping")

@@ -139,8 +140,8 @@
 cxx_header = "dev/net/i8254xGBe.hh"
 hardware_address = Param.EthernetAddr(NextEthernetAddr,
 "Ethernet Hardware Address")
-rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
-tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
+rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO")
+tx_fifo_size = Param.MemorySize('384KiB', "Size of the tx FIFO")
 rx_desc_cache_size = Param.Int(64,
 "Number of enteries in the rx descriptor cache")
 tx_desc_cache_size = Param.Int(64,
@@ -152,7 +153,7 @@
 SubClassCode = 0x00
 ClassCode = 0x02
 ProgIF = 0x00
-BAR0 = PciMemBar(size='128kB')
+BAR0 = PciMemBar(size='128KiB')
 MaximumLatency = 0x00
 MinimumGrant = 0xff
 InterruptLine = 0x1e
@@ -195,8 +196,8 @@

 rx_delay = Param.Latency('1us', "Receive Delay")
 tx_delay = Param.Latency('1us', "Transmit Delay")
-rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
-tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
+rx_fifo_size = Param.MemorySize('512KiB', "max size of rx fifo")
+tx_fifo_size = Param.MemorySize('512KiB', "max size of tx fifo")

 rx_filter = Param.Bool(True, "Enable Receive Filter")
 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
@@ -218,7 +219,7 @@
 SubClassCode = 0x00
 ClassCode = 0x02
 ProgIF = 0x00
-BARs = (PciIoBar(size='256B'), PciMemBar(size='4kB'))
+BARs = (PciIoBar(size='256B'), PciMemBar(size='4KiB'))
 MaximumLatency = 0x34
 MinimumGrant = 0xb0
 InterruptLine = 0x1e
@@ -232,12 +233,12 @@
 cxx_header = "dev/net/sinic.hh"

 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
-tx_max_copy = Param.MemorySize('16kB', "tx max copy")
+tx_max_copy = Param.MemorySize('16KiB', "tx max copy")
 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
-rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
-rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
-tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
-

[gem5-dev] Change in gem5/gem5[develop]: python: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39577 )



Change subject: python: Consistently use ISO prefixes
..

python: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/params.py
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 45082d7..2b52b93 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -692,7 +692,7 @@

 class MemorySize(CheckedInt):
 cxx_type = 'uint64_t'
-ex_str = '512MB'
+ex_str = '512MiB'
 size = 64
 unsigned = True
 def __init__(self, value):
@@ -704,7 +704,7 @@

 class MemorySize32(CheckedInt):
 cxx_type = 'uint32_t'
-ex_str = '512MB'
+ex_str = '512MiB'
 size = 32
 unsigned = True
 def __init__(self, value):
@@ -724,7 +724,7 @@
 else:
 try:
 # Often addresses are referred to with sizes. Ex: A device
-# base address is at "512MB".  Use toMemorySize() to  
convert
+# base address is at "512MiB".  Use toMemorySize() to  
convert
 # these into addresses. If the address is not specified  
with a
 # "size", an exception will occur and numeric translation  
will

 # proceed below.
@@ -1748,7 +1748,7 @@

 class MemoryBandwidth(float,ParamValue):
 cxx_type = 'float'
-ex_str = "1GB/s"
+ex_str = "1GiB/s"
 cmd_line_settable = True

 def __new__(cls, value):

--
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39576 )



Change subject: arch-arm, dev-arm: Consistently use ISO prefixes
..

arch-arm, dev-arm: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I2d24682d207830f3b7b0ad2ff82b55e082cccb32
Signed-off-by: Andreas Sandberg 
---
M src/mem/AbstractMemory.py
M src/mem/DRAMInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/XBar.py
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/tags/Tags.py
7 files changed, 49 insertions(+), 48 deletions(-)



diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 4c21d52..e1941c3 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -44,9 +44,10 @@
 abstract = True
 cxx_header = "mem/abstract_mem.hh"

-# A default memory size of 128 MB (starting at 0) is used to
+# A default memory size of 128 MiB (starting at 0) is used to
 # simplify the regressions
-range = Param.AddrRange('128MB', "Address range (potentially  
interleaved)")

+range = Param.AddrRange('128MiB',
+"Address range (potentially interleaved)")
 null = Param.Bool(False, "Do not store data, always return zero")

 # All memories are passed to the global physical memory, and
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 85a6092..4f59498 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -259,7 +259,7 @@
 # an 8x8 configuration.
 class DDR3_1600_8x8(DRAMInterface):
 # size of device in bytes
-device_size = '512MB'
+device_size = '512MiB'

 # 8x8 configuration, 8 devices each with an 8-bit interface
 device_bus_width = 8
@@ -268,7 +268,7 @@
 burst_length = 8

 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
-device_rowbuffer_size = '1kB'
+device_rowbuffer_size = '1KiB'

 # 8x8 configuration, so 8 devices
 devices_per_rank = 8
@@ -338,7 +338,7 @@
 # [2] High performance AXI-4.0 based interconnect for extensible smart  
memory

 # cubes (E. Azarkhish et. al)
 # Assumed for the HMC model is a 30 nm technology node.
-# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory  
(4
+# The modelled HMC consists of 4 Gbit layers which sum up to 2GiB of  
memory (4

 # layers).
 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
 # In order to be able to use the same controller used for 2D DRAM  
generations

@@ -354,8 +354,8 @@
 # of the HMC
 class HMC_2500_1x32(DDR3_1600_8x8):
 # size of device
-# two banks per device with each bank 4MB [2]
-device_size = '8MB'
+# two banks per device with each bank 4MiB [2]
+device_size = '8MiB'

 # 1x32 configuration, 1 device with 32 TSVs [2]
 device_bus_width = 32
@@ -458,11 +458,11 @@
 # A single DDR4-2400 x64 channel (one command and address bus), with
 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
 # in an 16x4 configuration.
-# Total channel capacity is 32GB
-# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
+# Total channel capacity is 32GiB
+# 16 devices/rank * 2 ranks/channel * 1GiB/device = 32GiB/channel
 class DDR4_2400_16x4(DRAMInterface):
 # size of device
-device_size = '1GB'
+device_size = '1GiB'

 # 16x4 configuration, 16 devices each with a 4-bit interface
 device_bus_width = 4
@@ -569,14 +569,14 @@
 # A single DDR4-2400 x64 channel (one command and address bus), with
 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
 # in an 8x8 configuration.
-# Total channel capacity is 16GB
-# 8 devices/rank * 2 

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39575 )



Change subject: arch-arm, dev-arm: Consistently use ISO prefixes
..

arch-arm, dev-arm: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I9b47194d26d71c8ebedda6c31a5bac54b600d3bf
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/dev/arm/FlashDevice.py
M src/dev/arm/RealView.py
5 files changed, 49 insertions(+), 49 deletions(-)



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index e445590..8674edc 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -53,10 +53,10 @@
 files_root_dir = Param.String("",
 "Host root directory for files handled by Semihosting")

-mem_reserve = Param.MemorySize("32MB",
+mem_reserve = Param.MemorySize("32MiB",
 "Amount of memory to reserve at the start of the address map.  
This "

 "memory won't be used by the heap reported to an application.");
-stack_size = Param.MemorySize("32MB", "Application stack size");
+stack_size = Param.MemorySize("32MiB", "Application stack size");

 time = Param.Time('01/01/2009',
   "System time to use ('Now' for actual time)")
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index e658b02..7f19adb 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -648,7 +648,7 @@
 MISCREG_TTBR0, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t0sz;
 currState->isUncacheable = currState->ttbcr.irgn0 == 0;
-if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GB
+if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GiB
 start_lookup_level = L2;
 } else if (currState->vaddr >= ttbr1_min) {
 DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
@@ -673,7 +673,7 @@
 MISCREG_TTBR1, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t1sz;
 currState->isUncacheable = currState->ttbcr.irgn1 == 0;
-// Lower limit >= 3 GB
+// Lower limit >= 3 GiB
 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30))
 start_lookup_level = L2;
 } else {
@@ -2379,16 +2379,16 @@
 pageSizes // see DDI 0487A D4-1661
 .init(10)
 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero);
-pageSizes.subname(0, "4K");
-pageSizes.subname(1, "16K");
-pageSizes.subname(2, "64K");
-pageSizes.subname(3, "1M");
-pageSizes.subname(4, "2M");
-pageSizes.subname(5, "16M");
-pageSizes.subname(6, "32M");
-pageSizes.subname(7, "512M");
-pageSizes.subname(8, "1G");
-pageSizes.subname(9, "4TB");
+pageSizes.subname(0, "4KiB");
+pageSizes.subname(1, "16KiB");
+pageSizes.subname(2, "64KiB");
+pageSizes.subname(3, "1MiB");
+pageSizes.subname(4, "2MiB");
+pageSizes.subname(5, "16MiB");
+pageSizes.subname(6, "32MiB");
+pageSizes.subname(7, "512MiB");
+pageSizes.subname(8, "1GiB");
+pageSizes.subname(9, "4TiB");

 requestOrigin
 .init(2,2) // Instruction/Data, requests/completed
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index dbb480e..f4ee552 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -132,7 +132,7 @@
 return (EntryType)(data & 0x3);
 }

-/** Is the page a Supersection (16MB)?*/
+/** Is the page a Supersection (16 MiB)?*/
  

[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39560 )



Change subject: arch-sparc: Stop "using namespace std"
..

arch-sparc: Stop "using namespace std"

Change-Id: I4a1019b5978b08b4999edfe5f65ef7eae06481c2
---
M src/arch/sparc/faults.cc
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/process.cc
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/ua2005.cc
5 files changed, 6 insertions(+), 12 deletions(-)



diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index b480558..a80e649 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -42,8 +42,6 @@
 #include "sim/full_system.hh"
 #include "sim/process.hh"

-using namespace std;
-
 namespace SparcISA
 {

@@ -340,7 +338,7 @@
 tc->setMiscRegNoEffect(MISCREG_TT, tt);

 // Update GL
-tc->setMiscReg(MISCREG_GL, min(GL+1, MaxGL));
+tc->setMiscReg(MISCREG_GL, std::min(GL+1, MaxGL));

 bool priv = pstate.priv; // just save the priv bit
 pstate = 0;
@@ -424,9 +422,9 @@

 // Update the global register level
 if (!gotoHpriv)
-tc->setMiscReg(MISCREG_GL, min(GL + 1, MaxPGL));
+tc->setMiscReg(MISCREG_GL, std::min(GL + 1, MaxPGL));
 else
-tc->setMiscReg(MISCREG_GL, min(GL + 1, MaxGL));
+tc->setMiscReg(MISCREG_GL, std::min(GL + 1, MaxGL));

 // pstate.mm is unchanged
 pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
diff --git a/src/arch/sparc/isa/includes.isa  
b/src/arch/sparc/isa/includes.isa

index da814e3..1cef0fc 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -86,6 +86,5 @@
 #include "sim/sim_exit.hh"

 using namespace SparcISA;
-using namespace std;
 }};

diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index b292c86..0923eeb 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -45,7 +45,6 @@
 #include "sim/syscall_return.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace SparcISA;

 SparcProcess::SparcProcess(const ProcessParams ,
@@ -142,7 +141,7 @@

 std::vector> auxv;

-string filename;
+std::string filename;
 if (argv.size() < 1)
 filename = "";
 else
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index cf91f3d..a2988c6 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -140,7 +140,6 @@
 #include "sim/process.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace SparcISA;

 RemoteGDB::RemoteGDB(System *_system, ThreadContext *c, int _port)
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index b0b9f59..3f33816 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -38,7 +38,6 @@
 #include "sim/system.hh"

 using namespace SparcISA;
-using namespace std;


 void
@@ -66,10 +65,10 @@
 }

 // These functions map register indices to names
-static inline string
+static inline std::string
 getMiscRegName(RegIndex index)
 {
-static string miscRegName[NumMiscRegs] =
+static std::string miscRegName[NumMiscRegs] =
 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
  "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  "stick", "stick_cmpr",

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I4a1019b5978b08b4999edfe5f65ef7eae06481c2
Gerrit-Change-Number: 39560
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39556 )



Change subject: arch-power: Stop "using namespace std"
..

arch-power: Stop "using namespace std"

Change-Id: Iab8acba7c01a873db660304bb85661e75ffbe854
---
M src/arch/power/insts/integer.cc
M src/arch/power/process.cc
M src/arch/power/remote_gdb.cc
M src/arch/power/tlb.cc
4 files changed, 17 insertions(+), 21 deletions(-)



diff --git a/src/arch/power/insts/integer.cc  
b/src/arch/power/insts/integer.cc

index 8522153..febd469 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -28,19 +28,18 @@

 #include "arch/power/insts/integer.hh"

-using namespace std;
 using namespace PowerISA;

-string
+std::string
 IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab)  
const

 {
-stringstream ss;
+std::stringstream ss;
 bool printDest = true;
 bool printSrcs = true;
 bool printSecondSrc = true;

 // Generate the correct mnemonic
-string myMnemonic(mnemonic);
+std::string myMnemonic(mnemonic);

 // Special cases
 if (!myMnemonic.compare("or") && srcRegIdx(0) == srcRegIdx(1)) {
@@ -78,13 +77,13 @@
 }


-string
+std::string
 IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab)  
const

 {
-stringstream ss;
+std::stringstream ss;

 // Generate the correct mnemonic
-string myMnemonic(mnemonic);
+std::string myMnemonic(mnemonic);

 // Special cases
 if (!myMnemonic.compare("addi") && _numSrcRegs == 0) {
@@ -114,11 +113,11 @@
 }


-string
+std::string
 IntShiftOp::generateDisassembly(
 Addr pc, const Loader::SymbolTable *symtab) const
 {
-stringstream ss;
+std::stringstream ss;

 ccprintf(ss, "%-10s ", mnemonic);

@@ -142,11 +141,11 @@
 }


-string
+std::string
 IntRotateOp::generateDisassembly(
 Addr pc, const Loader::SymbolTable *symtab) const
 {
-stringstream ss;
+std::stringstream ss;

 ccprintf(ss, "%-10s ", mnemonic);

diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 9e8d2ad..26d28a8 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -43,7 +43,6 @@
 #include "sim/syscall_return.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace PowerISA;

 PowerProcess::PowerProcess(
@@ -67,9 +66,9 @@
 // Set up region for mmaps. For now, start at bottom of kuseg space.
 Addr mmap_end = 0x7000L;

-memState = make_shared(this, brk_point, stack_base,
- max_stack_size,  
next_thread_stack_base,

- mmap_end);
+memState = std::make_shared(
+this, brk_point, stack_base, max_stack_size,
+next_thread_stack_base, mmap_end);
 }

 void
@@ -85,7 +84,7 @@
 {
 std::vector> auxv;

-string filename;
+std::string filename;
 if (argv.size() < 1)
 filename = "";
 else
@@ -146,7 +145,7 @@
 // A sentry NULL void pointer at the top of the stack.
 int sentry_size = intSize;

-string platform = "v51";
+std::string platform = "v51";
 int platform_size = platform.size() + 1;

 // The aux vectors are put on the stack in two groups. The first group  
are

diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index 661c431..ce9976f 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -143,7 +143,6 @@
 #include "mem/page_table.hh"
 #include "sim/byteswap.hh"

-using namespace std;
 using namespace PowerISA;

 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index dd3b50a..dca8d7b 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -48,7 +48,6 @@
 #include "sim/full_system.hh"
 #include "sim/process.hh"

-using namespace std;
 using namespace PowerISA;

 ///
@@ -168,7 +167,7 @@
 table[Index]=pte;

 // Update fast lookup table
-lookupTable.insert(make_pair(table[Index].VPN, Index));
+lookupTable.insert(std::make_pair(table[Index].VPN, Index));
 }
 }

@@ -209,7 +208,7 @@
 for (int i = 0; i < size; i++) {
 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
 if (table[i].V0 || table[i].V1) {
-lookupTable.insert(make_pair(table[i].VPN, i));
+lookupTable.insert(std::make_pair(table[i].VPN, i));
 }
 }
 }

--
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Gerrit-Change-Id: Iab8acba7c01a873db660304bb85661e75ffbe854
Gerrit-Change-Number: 39556
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Gerrit-MessageType: 

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39557 )



Change subject: arch-x86: Stop "using namespace std"
..

arch-x86: Stop "using namespace std"

Change-Id: I9763177bbd54abc97b99bd54a20a750e0adb5627
---
M src/arch/x86/bios/acpi.cc
M src/arch/x86/bios/e820.cc
M src/arch/x86/bios/intelmp.cc
M src/arch/x86/bios/smbios.cc
M src/arch/x86/isa/includes.isa
M src/arch/x86/process.cc
M src/arch/x86/remote_gdb.cc
M src/arch/x86/types.cc
8 files changed, 16 insertions(+), 26 deletions(-)



diff --git a/src/arch/x86/bios/acpi.cc b/src/arch/x86/bios/acpi.cc
index 5ecb09b..20cf088 100644
--- a/src/arch/x86/bios/acpi.cc
+++ b/src/arch/x86/bios/acpi.cc
@@ -45,8 +45,6 @@
 #include "sim/byteswap.hh"
 #include "sim/sim_object.hh"

-using namespace std;
-
 const char X86ISA::ACPI::RSDP::signature[] = "RSD PTR ";

 X86ISA::ACPI::RSDP::RSDP(const Params ) : SimObject(p), oemID(p.oem_id),
diff --git a/src/arch/x86/bios/e820.cc b/src/arch/x86/bios/e820.cc
index a377703..a22f66c 100644
--- a/src/arch/x86/bios/e820.cc
+++ b/src/arch/x86/bios/e820.cc
@@ -41,7 +41,6 @@
 #include "mem/port_proxy.hh"
 #include "sim/byteswap.hh"

-using namespace std;
 using namespace X86ISA;

 template
diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc
index 6378c48..ba9ba20 100644
--- a/src/arch/x86/bios/intelmp.cc
+++ b/src/arch/x86/bios/intelmp.cc
@@ -63,8 +63,6 @@
 #include "params/X86IntelMPBusHierarchy.hh"
 #include "params/X86IntelMPCompatAddrSpaceMod.hh"

-using namespace std;
-
 const char X86ISA::IntelMP::FloatingPointer::signature[] = "_MP_";

 template
@@ -83,7 +81,7 @@
 }

 uint8_t
-writeOutString(PortProxy& proxy, Addr addr, string str, int length)
+writeOutString(PortProxy& proxy, Addr addr, std::string str, int length)
 {
 char cleanedString[length + 1];
 cleanedString[length] = 0;
@@ -210,7 +208,7 @@
 proxy.writeBlob(addr + 43, , 1);
 checkSum += reserved;

-vector::iterator baseEnt;
+std::vector::iterator baseEnt;
 uint16_t offset = 44;
 for (baseEnt = baseEntries.begin();
 baseEnt != baseEntries.end(); baseEnt++) {
@@ -220,7 +218,7 @@
 // We've found the end of the base table this point.
 checkSum += writeOutField(proxy, addr + 4, offset);

-vector::iterator extEnt;
+std::vector::iterator extEnt;
 uint16_t extOffset = 0;
 uint8_t extCheckSum = 0;
 for (extEnt = extEntries.begin();
diff --git a/src/arch/x86/bios/smbios.cc b/src/arch/x86/bios/smbios.cc
index afe0f15..ead87cf 100644
--- a/src/arch/x86/bios/smbios.cc
+++ b/src/arch/x86/bios/smbios.cc
@@ -48,8 +48,6 @@
 #include "params/X86SMBiosSMBiosTable.hh"
 #include "sim/byteswap.hh"

-using namespace std;
-
 const char X86ISA::SMBios::SMBiosTable::SMBiosHeader::anchorString[]  
= "_SM_";

 const uint8_t X86ISA::SMBios::SMBiosTable::
 SMBiosHeader::formattedArea[] = {0,0,0,0,0};
@@ -128,7 +126,7 @@
 }

 int
-X86ISA::SMBios::SMBiosStructure::addString(const string _string)
+X86ISA::SMBios::SMBiosStructure::addString(const std::string _string)
 {
 stringFields = true;
 // If a string is empty, treat it as not existing. The index for empty
@@ -139,7 +137,7 @@
 return strings.size();
 }

-string
+std::string
 X86ISA::SMBios::SMBiosStructure::readString(int n)
 {
 assert(n > 0 && n <= strings.size());
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index d2098c3..3bd7872 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -126,6 +126,5 @@
 #include "sim/sim_exit.hh"

 using namespace X86ISA;
-using namespace std;
 }};

diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 03e8641..925c836 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -65,7 +65,6 @@
 #include "sim/syscall_return.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace X86ISA;

 template class MultiLevelPageTable,
@@ -112,9 +111,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0x77FFF000ULL;

-memState = make_shared(this, brk_point, stack_base,
- max_stack_size,  
next_thread_stack_base,

- mmap_end);
+memState = std::make_shared(
+this, brk_point, stack_base, max_stack_size,
+next_thread_stack_base, mmap_end);
 }


@@ -139,9 +138,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0xB7FFF000ULL;

-memState = make_shared(this, brk_point, stack_base,
- max_stack_size,  
next_thread_stack_base,

- mmap_end);
+memState = std::make_shared(
+this, brk_point, stack_base, max_stack_size,
+next_thread_stack_base, mmap_end);
 }

 void
@@ -714,7 +713,7 @@

 std::vector> auxv = extraAuxvs;

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39561 )



Change subject: arch-arm: Stop "using namespace std"
..

arch-arm: Stop "using namespace std"

Change-Id: If0f373bdaadce81c5ebbc37b03810335c42dd10a
---
M src/arch/arm/insts/macromem.cc
M src/arch/arm/insts/mem.cc
M src/arch/arm/insts/mem64.cc
M src/arch/arm/linux/process.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/pauth_helpers.cc
M src/arch/arm/process.cc
M src/arch/arm/qarma.cc
M src/arch/arm/remote_gdb.cc
M src/arch/arm/self_debug.cc
M src/arch/arm/system.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_parser.cc
13 files changed, 45 insertions(+), 60 deletions(-)



diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 1ce9705..e20aef9 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -45,7 +45,6 @@
 #include "arch/arm/generated/decoder.hh"
 #include "arch/arm/insts/neon64_mem.hh"

-using namespace std;
 using namespace ArmISAInst;

 namespace ArmISA
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index e44fc96..8ee3f49 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -42,8 +42,6 @@

 #include "base/loader/symtab.hh"

-using namespace std;
-
 namespace ArmISA
 {

@@ -75,10 +73,10 @@
 }
 }

-string
+std::string
 RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab)  
const

 {
-stringstream ss;
+std::stringstream ss;
 switch (mode) {
   case DecrementAfter:
 printMnemonic(ss, "da");
@@ -100,10 +98,10 @@
 return ss.str();
 }

-string
+std::string
 SrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab)  
const

 {
-stringstream ss;
+std::stringstream ss;
 switch (mode) {
   case DecrementAfter:
 printMnemonic(ss, "da");
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index a12c330..1b02c41 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -41,8 +41,6 @@
 #include "base/loader/symtab.hh"
 #include "mem/request.hh"

-using namespace std;
-
 namespace ArmISA
 {

diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 7f86c24..cba3d14 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -54,7 +54,6 @@
 #include "sim/syscall_emul.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace ArmISA;

 const Addr ArmLinuxProcess32::commPage = 0x;
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index b5af9b6..5dfbd48 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -333,8 +333,6 @@
 return MISCREG_CP14_UNIMPL;
 }

-using namespace std;
-
 MiscRegIndex
 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 {
@@ -3393,7 +3391,7 @@
 return MISCREG_UNKNOWN;
 }

-bitset miscRegInfo[NUM_MISCREGS]; // initialized below
+std::bitset miscRegInfo[NUM_MISCREGS]; // initialized  
below


 void
 ISA::initializeMiscRegMetadata()
diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 7424eb3..aa93384 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -41,7 +41,6 @@
 #include "base/bitfield.hh"

 using namespace ArmISA;
-using namespace std;

 bool
 ArmISA::calculateTBI(ThreadContext* tc, ExceptionLevel el,
@@ -101,11 +100,11 @@
 using64k  = el == EL2 ? tcr2.tg0 == 0x1 : tcr3.tg0 == 0x1 ;
 }
 uint32_t max_limit_tsz_field = using64k ? 47 : 48;
-tsz_field = min(tsz_field, max_limit_tsz_field);
+tsz_field = std::min(tsz_field, max_limit_tsz_field);
 const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);

 uint32_t tszmin = (using64k && (bool)mm_fr2.varange) ? 12 : 16;
-tsz_field = max(tsz_field, tszmin);
+tsz_field = std::max(tsz_field, tszmin);

 return (64-tsz_field);
 }
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 6f37d11..86bc8e2 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -55,7 +55,6 @@
 #include "sim/syscall_return.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace ArmISA;

 ArmProcess::ArmProcess(const ProcessParams ,
@@ -78,9 +77,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0x4000L;

-memState = make_shared(this, brk_point, stack_base,
- max_stack_size,  
next_thread_stack_base,

- mmap_end);
+memState = std::make_shared(
+this, brk_point, stack_base, max_stack_size,
+next_thread_stack_base, mmap_end);
 }

 ArmProcess64::ArmProcess64(
@@ -94,9 +93,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0x40L;

-memState = make_shared(this, brk_point, stack_base,
-  

[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39559 )



Change subject: arch-mips: Stop "using namespace std"
..

arch-mips: Stop "using namespace std"

Change-Id: I0ad5ad71d8ba2d7c050d3f368341ce98d3f87a90
---
M src/arch/mips/dsp.cc
M src/arch/mips/isa/formats/branch.isa
M src/arch/mips/isa/formats/dsp.isa
M src/arch/mips/isa/formats/int.isa
M src/arch/mips/isa/formats/util.isa
M src/arch/mips/process.cc
M src/arch/mips/remote_gdb.cc
M src/arch/mips/tlb.cc
M src/arch/mips/utility.cc
9 files changed, 8 insertions(+), 16 deletions(-)



diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index 9b0f098..73babf1 100644
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -35,7 +35,6 @@
 #include "sim/serialize.hh"

 using namespace MipsISA;
-using namespace std;

 int32_t
 MipsISA::bitrev(int32_t value)
diff --git a/src/arch/mips/isa/formats/branch.isa  
b/src/arch/mips/isa/formats/branch.isa

index 42a0dea..09bab47 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -34,7 +34,6 @@
 output header {{

 #include 
-using namespace std;

 /**
  * Base class for instructions whose disassembly is not purely a
diff --git a/src/arch/mips/isa/formats/dsp.isa  
b/src/arch/mips/isa/formats/dsp.isa

index 12af2d6..fc08956 100644
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -32,7 +32,6 @@
 //
 output header {{
 #include 
-using namespace std;
 /**
  * Base class for integer operations.
  */
diff --git a/src/arch/mips/isa/formats/int.isa  
b/src/arch/mips/isa/formats/int.isa

index f47e728..35bbef6 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -32,7 +32,6 @@
 //
 output header {{
 #include 
-using namespace std;
 /**
  * Base class for integer operations.
  */
diff --git a/src/arch/mips/isa/formats/util.isa  
b/src/arch/mips/isa/formats/util.isa

index 39ece7a..3870955 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -80,7 +80,7 @@

 std::string inst2string(MachInst machInst)
 {
-string str = "";
+std::string str = "";
 uint32_t mask = 0x8000;

 for(int i=0; i < 32; i++) {
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 44f4f32..e2f2bb9 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -42,7 +42,6 @@
 #include "sim/syscall_return.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace MipsISA;

 MipsProcess::MipsProcess(const ProcessParams ,
@@ -68,9 +67,9 @@
 // Set up region for mmaps.  Start it 1GB above the top of the heap.
 Addr mmap_end = brk_point + 0x4000L;

-memState = make_shared(this, brk_point, stack_base,
- max_stack_size,  
next_thread_stack_base,

- mmap_end);
+memState = std::make_shared(
+this, brk_point, stack_base, max_stack_size,
+next_thread_stack_base, mmap_end);
 }

 void
@@ -126,7 +125,7 @@
 int auxv_array_size = intSize * 2 * (auxv.size() + 1);

 int arg_data_size = 0;
-for (vector::size_type i = 0; i < argv.size(); ++i) {
+for (std::vector::size_type i = 0; i < argv.size(); ++i) {
 arg_data_size += argv[i].size() + 1;
 }

@@ -134,7 +133,7 @@
 int aux_data_size = numRandomBytes;

 int env_data_size = 0;
-for (vector::size_type i = 0; i < envp.size(); ++i) {
+for (std::vector::size_type i = 0; i < envp.size(); ++i) {
 env_data_size += envp[i].size() + 1;
 }

diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index bd9a40f..9d71792 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -143,7 +143,6 @@
 #include "mem/page_table.hh"
 #include "sim/full_system.hh"

-using namespace std;
 using namespace MipsISA;

 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 3ceb1ae..5373ba9 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -46,7 +46,6 @@
 #include "params/MipsTLB.hh"
 #include "sim/process.hh"

-using namespace std;
 using namespace MipsISA;

 ///
@@ -169,7 +168,7 @@
 }
 table[Index]=pte;
 // Update fast lookup table
-lookupTable.insert(make_pair(table[Index].VPN, Index));
+lookupTable.insert(std::make_pair(table[Index].VPN, Index));
 }
 }

@@ -211,7 +210,7 @@
 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
 table[i].unserialize(cp);
 if (table[i].V0 || table[i].V1) {
-lookupTable.insert(make_pair(table[i].VPN, i));
+lookupTable.insert(std::make_pair(table[i].VPN, i));
 }
 }
 }
diff --git 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix float point test fail in Riscv-test

[Kai Ren (Gerrit) via gem5-dev]

Kai Ren has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39357 )



Change subject: arch-riscv: Fix float point test fail in Riscv-test
..

arch-riscv: Fix float point test fail in Riscv-test

Using SoftFloat Package to reinplement Riscv FPops.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-373

Change-Id: Ic96e6c8adec0713bdbd744d581c750034b88246c
---
A ext/softfloat/SConscript
A ext/softfloat/f128_add.c
A ext/softfloat/f128_classify.c
A ext/softfloat/f128_div.c
A ext/softfloat/f128_eq.c
A ext/softfloat/f128_eq_signaling.c
A ext/softfloat/f128_isSignalingNaN.c
A ext/softfloat/f128_le.c
A ext/softfloat/f128_le_quiet.c
A ext/softfloat/f128_lt.c
A ext/softfloat/f128_lt_quiet.c
A ext/softfloat/f128_mul.c
A ext/softfloat/f128_mulAdd.c
A ext/softfloat/f128_rem.c
A ext/softfloat/f128_roundToInt.c
A ext/softfloat/f128_sqrt.c
A ext/softfloat/f128_sub.c
A ext/softfloat/f128_to_f16.c
A ext/softfloat/f128_to_f32.c
A ext/softfloat/f128_to_f64.c
A ext/softfloat/f128_to_i32.c
A ext/softfloat/f128_to_i32_r_minMag.c
A ext/softfloat/f128_to_i64.c
A ext/softfloat/f128_to_i64_r_minMag.c
A ext/softfloat/f128_to_ui32.c
A ext/softfloat/f128_to_ui32_r_minMag.c
A ext/softfloat/f128_to_ui64.c
A ext/softfloat/f128_to_ui64_r_minMag.c
A ext/softfloat/f16_add.c
A ext/softfloat/f16_div.c
A ext/softfloat/f16_eq.c
A ext/softfloat/f16_eq_signaling.c
A ext/softfloat/f16_isSignalingNaN.c
A ext/softfloat/f16_le.c
A ext/softfloat/f16_le_quiet.c
A ext/softfloat/f16_lt.c
A ext/softfloat/f16_lt_quiet.c
A ext/softfloat/f16_mul.c
A ext/softfloat/f16_mulAdd.c
A ext/softfloat/f16_rem.c
A ext/softfloat/f16_roundToInt.c
A ext/softfloat/f16_sqrt.c
A ext/softfloat/f16_sub.c
A ext/softfloat/f16_to_f128.c
A ext/softfloat/f16_to_f32.c
A ext/softfloat/f16_to_f64.c
A ext/softfloat/f16_to_i32.c
A ext/softfloat/f16_to_i32_r_minMag.c
A ext/softfloat/f16_to_i64.c
A ext/softfloat/f16_to_i64_r_minMag.c
A ext/softfloat/f16_to_ui32.c
A ext/softfloat/f16_to_ui32_r_minMag.c
A ext/softfloat/f16_to_ui64.c
A ext/softfloat/f16_to_ui64_r_minMag.c
A ext/softfloat/f32_add.c
A ext/softfloat/f32_classify.c
A ext/softfloat/f32_div.c
A ext/softfloat/f32_eq.c
A ext/softfloat/f32_eq_signaling.c
A ext/softfloat/f32_isSignalingNaN.c
A ext/softfloat/f32_le.c
A ext/softfloat/f32_le_quiet.c
A ext/softfloat/f32_lt.c
A ext/softfloat/f32_lt_quiet.c
A ext/softfloat/f32_mul.c
A ext/softfloat/f32_mulAdd.c
A ext/softfloat/f32_rem.c
A ext/softfloat/f32_roundToInt.c
A ext/softfloat/f32_sqrt.c
A ext/softfloat/f32_sub.c
A ext/softfloat/f32_to_f128.c
A ext/softfloat/f32_to_f16.c
A ext/softfloat/f32_to_f64.c
A ext/softfloat/f32_to_i32.c
A ext/softfloat/f32_to_i32_r_minMag.c
A ext/softfloat/f32_to_i64.c
A ext/softfloat/f32_to_i64_r_minMag.c
A ext/softfloat/f32_to_ui32.c
A ext/softfloat/f32_to_ui32_r_minMag.c
A ext/softfloat/f32_to_ui64.c
A ext/softfloat/f32_to_ui64_r_minMag.c
A ext/softfloat/f64_add.c
A ext/softfloat/f64_classify.c
A ext/softfloat/f64_div.c
A ext/softfloat/f64_eq.c
A ext/softfloat/f64_eq_signaling.c
A ext/softfloat/f64_isSignalingNaN.c
A ext/softfloat/f64_le.c
A ext/softfloat/f64_le_quiet.c
A ext/softfloat/f64_lt.c
A ext/softfloat/f64_lt_quiet.c
A ext/softfloat/f64_mul.c
A ext/softfloat/f64_mulAdd.c
A ext/softfloat/f64_rem.c
A ext/softfloat/f64_roundToInt.c
A ext/softfloat/f64_sqrt.c
A ext/softfloat/f64_sub.c
A ext/softfloat/f64_to_f128.c
A ext/softfloat/f64_to_f16.c
A ext/softfloat/f64_to_f32.c
A ext/softfloat/f64_to_i32.c
A ext/softfloat/f64_to_i32_r_minMag.c
A ext/softfloat/f64_to_i64.c
A ext/softfloat/f64_to_i64_r_minMag.c
A ext/softfloat/f64_to_ui32.c
A ext/softfloat/f64_to_ui32_r_minMag.c
A ext/softfloat/f64_to_ui64.c
A ext/softfloat/f64_to_ui64_r_minMag.c
A ext/softfloat/i32_to_f128.c
A ext/softfloat/i32_to_f16.c
A ext/softfloat/i32_to_f32.c
A ext/softfloat/i32_to_f64.c
A ext/softfloat/i64_to_f128.c
A ext/softfloat/i64_to_f16.c
A ext/softfloat/i64_to_f32.c
A ext/softfloat/i64_to_f64.c
A ext/softfloat/internals.h
A ext/softfloat/platform.h
A ext/softfloat/primitiveTypes.h
A ext/softfloat/primitives.h
A ext/softfloat/s_add128.c
A ext/softfloat/s_add256M.c
A ext/softfloat/s_addCarryM.c
A ext/softfloat/s_addComplCarryM.c
A ext/softfloat/s_addM.c
A ext/softfloat/s_addMagsF128.c
A ext/softfloat/s_addMagsF16.c
A ext/softfloat/s_addMagsF32.c
A ext/softfloat/s_addMagsF64.c
A ext/softfloat/s_approxRecip32_1.c
A ext/softfloat/s_approxRecipSqrt32_1.c
A ext/softfloat/s_approxRecipSqrt_1Ks.c
A ext/softfloat/s_approxRecip_1Ks.c
A ext/softfloat/s_commonNaNToF128UI.c
A ext/softfloat/s_commonNaNToF16UI.c
A ext/softfloat/s_commonNaNToF32UI.c
A ext/softfloat/s_commonNaNToF64UI.c
A ext/softfloat/s_compare128M.c
A ext/softfloat/s_compare96M.c
A ext/softfloat/s_countLeadingZeros16.c
A ext/softfloat/s_countLeadingZeros32.c
A ext/softfloat/s_countLeadingZeros64.c
A ext/softfloat/s_countLeadingZeros8.c
A ext/softfloat/s_eq128.c
A ext/softfloat/s_f128UIToCommonNaN.c
A 

[gem5-dev] Change in gem5/gem5[develop]: base: Style fixes in cprintf related files.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39535 )



Change subject: base: Style fixes in cprintf related files.
..

base: Style fixes in cprintf related files.

Fix braces, capitalization, missing line breaks, and remove mostly
useless "using namespace std"s.

Change-Id: I1210dd3b918e7cba8e576cbbdf47aa986d9278e6
---
M src/base/cprintf.cc
M src/base/cprintf.hh
M src/base/cprintf_formats.hh
3 files changed, 252 insertions(+), 192 deletions(-)



diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc
index e7336a8..572fc40 100644
--- a/src/base/cprintf.cc
+++ b/src/base/cprintf.cc
@@ -35,26 +35,25 @@

 #include "base/compiler.hh"

-using namespace std;
-
-namespace cp {
+namespace cp
+{

 Print::Print(std::ostream , const std::string )
 : stream(stream), format(format.c_str()), ptr(format.c_str()),  
cont(false)

 {
-saved_flags = stream.flags();
-saved_fill = stream.fill();
-saved_precision = stream.precision();
-saved_width = stream.width();
+savedFlags = stream.flags();
+savedFill = stream.fill();
+savedPrecision = stream.precision();
+savedWidth = stream.width();
 }

 Print::Print(std::ostream , const char *format)
 : stream(stream), format(format), ptr(format), cont(false)
 {
-saved_flags = stream.flags();
-saved_fill = stream.fill();
-saved_precision = stream.precision();
-saved_width = stream.width();
+savedFlags = stream.flags();
+savedFill = stream.fill();
+savedPrecision = stream.precision();
+savedWidth = stream.width();
 }

 Print::~Print()
@@ -72,7 +71,7 @@
 switch (*ptr) {
   case '%':
 if (ptr[1] != '%') {
-process_flag();
+processFlag();
 return;
 }
 stream.put('%');
@@ -99,7 +98,7 @@
 }

 void
-Print::process_flag()
+Print::processFlag()
 {
 bool done = false;
 bool end_number = false;
@@ -114,17 +113,18 @@
 if (*ptr >= '0' && *ptr <= '9') {
 if (end_number)
 continue;
-} else if (number > 0)
+} else if (number > 0) {
 end_number = true;
+}

 switch (*ptr) {
   case 's':
-fmt.format = Format::string;
+fmt.format = Format::String;
 done = true;
 break;

   case 'c':
-fmt.format = Format::character;
+fmt.format = Format::Character;
 done = true;
 break;

@@ -132,8 +132,8 @@
 continue;

   case 'p':
-fmt.format = Format::integer;
-fmt.base = Format::hex;
+fmt.format = Format::Integer;
+fmt.base = Format::Hex;
 fmt.alternate_form = true;
 done = true;
 break;
@@ -142,21 +142,21 @@
 fmt.uppercase = true;
 M5_FALLTHROUGH;
   case 'x':
-fmt.base = Format::hex;
-fmt.format = Format::integer;
+fmt.base = Format::Hex;
+fmt.format = Format::Integer;
 done = true;
 break;

   case 'o':
-fmt.base = Format::oct;
-fmt.format = Format::integer;
+fmt.base = Format::Oct;
+fmt.format = Format::Integer;
 done = true;
 break;

   case 'd':
   case 'i':
   case 'u':
-fmt.format = Format::integer;
+fmt.format = Format::Integer;
 done = true;
 break;

@@ -164,8 +164,8 @@
 fmt.uppercase = true;
 M5_FALLTHROUGH;
   case 'g':
-fmt.format = Format::floating;
-fmt.float_format = Format::best;
+fmt.format = Format::Floating;
+fmt.floatFormat = Format::Best;
 done = true;
 break;

@@ -173,14 +173,14 @@
 fmt.uppercase = true;
 M5_FALLTHROUGH;
   case 'e':
-fmt.format = Format::floating;
-fmt.float_format = Format::scientific;
+fmt.format = Format::Floating;
+fmt.floatFormat = Format::Scientific;
 done = true;
 break;

   case 'f':
-fmt.format = Format::floating;
-fmt.float_format = Format::fixed;
+fmt.format = Format::Floating;
+fmt.floatFormat = Format::Fixed;
 done = true;
 break;

@@ -190,19 +190,19 @@
 break;

   case '#':
-fmt.alternate_form = true;
+fmt.alternateForm = true;
 break;

   case '-':
-fmt.flush_left = true;
+fmt.flushLeft = true;
 break;

   case '+':
-fmt.print_sign = true;
+fmt.printSign = true;
 break;

   case ' ':
-  

[gem5-dev] Change in gem5/gem5[develop]: base: Stop "using namespace std".

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39536 )



Change subject: base: Stop "using namespace std".
..

base: Stop "using namespace std".

As the std namespace expands, it becomes more and more likely that
blanketly importing all its symbols will cause a collision. Also, when
it was imported, the std:: was used or left off arbitrarily, sometimes
inconsistently even in the same function signature.

Change-Id: Ie30cbab154b00c60433908a206c229230d2b109f
---
M src/base/bitunion.test.cc
M src/base/cprintf.cc
M src/base/cprintf.hh
M src/base/fiber.cc
M src/base/hostinfo.cc
M src/base/inet.cc
M src/base/inifile.cc
M src/base/inifile.test.cc
M src/base/loader/symtab.cc
M src/base/match.cc
M src/base/output.cc
M src/base/pollevent.cc
M src/base/refcnt.test.cc
M src/base/remote_gdb.cc
M src/base/socket.cc
M src/base/statistics.cc
M src/base/stats/text.cc
M src/base/str.cc
M src/base/time.cc
M src/base/vnc/vncinput.cc
M src/base/vnc/vncserver.cc
21 files changed, 203 insertions(+), 230 deletions(-)



diff --git a/src/base/bitunion.test.cc b/src/base/bitunion.test.cc
index 77897f5..5a80a57 100644
--- a/src/base/bitunion.test.cc
+++ b/src/base/bitunion.test.cc
@@ -34,9 +34,8 @@
 #include "base/bitunion.hh"
 #include "base/cprintf.hh"

-using namespace std;
-
-namespace {
+namespace
+{

 BitUnion64(SixtyFour)
 Bitfield<39, 32> byte5;
diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc
index 572fc40..580a77c 100644
--- a/src/base/cprintf.cc
+++ b/src/base/cprintf.cc
@@ -34,6 +34,7 @@
 #include 

 #include "base/compiler.hh"
+#include "base/logging.hh"

 namespace cp
 {
@@ -79,13 +80,13 @@
 break;

   case '\n':
-stream << endl;
+stream << std::endl;
 ++ptr;
 break;
   case '\r':
 ++ptr;
 if (*ptr != '\n')
-stream << endl;
+stream << std::endl;
 break;

   default:
@@ -106,7 +107,7 @@
 int number = 0;

 stream.fill(' ');
-stream.flags((ios::fmtflags)0);
+stream.flags((std::ios::fmtflags)0);

 while (!done) {
 ++ptr;
@@ -134,7 +135,7 @@
   case 'p':
 fmt.format = Format::Integer;
 fmt.base = Format::Hex;
-fmt.alternate_form = true;
+fmt.alternateForm = true;
 done = true;
 break;

@@ -262,9 +263,9 @@
 // specified a . but not a float, set width
 fmt.width = fmt.precision;
 // precision requries digits for width, must fill with 0
-fmt.fill_zero = true;
+fmt.fillZero = true;
 } else if ((fmt.format == Format::Floating) && !have_precision  
&&

-fmt.fill_zero) {
+fmt.fillZero) {
 // ambiguous case, matching printf
 fmt.precision = fmt.width;
 }
@@ -290,13 +291,13 @@
 break;

   case '\n':
-stream << endl;
+stream << std::endl;
 ++ptr;
 break;
   case '\r':
 ++ptr;
 if (*ptr != '\n')
-stream << endl;
+stream << std::endl;
 break;

   default:
diff --git a/src/base/cprintf.hh b/src/base/cprintf.hh
index 51531f4..39d9261 100644
--- a/src/base/cprintf.hh
+++ b/src/base/cprintf.hh
@@ -48,7 +48,7 @@
 const char *ptr;
 bool cont;

-std::ios::fmtflags saved_flags;
+std::ios::fmtflags savedFlags;
 char savedFill;
 int savedPrecision;
 int savedWidth;
diff --git a/src/base/fiber.cc b/src/base/fiber.cc
index fe1bad0..e414bd2 100644
--- a/src/base/fiber.cc
+++ b/src/base/fiber.cc
@@ -48,8 +48,6 @@

 #include "base/logging.hh"

-using namespace std;
-
 namespace
 {

diff --git a/src/base/hostinfo.cc b/src/base/hostinfo.cc
index be3d46f..e835a10 100644
--- a/src/base/hostinfo.cc
+++ b/src/base/hostinfo.cc
@@ -49,9 +49,7 @@
 #include "base/str.hh"
 #include "base/types.hh"

-using namespace std;
-
-string
+std::string
 __get_hostname()
 {
 char host[256];
@@ -60,10 +58,10 @@
 return host;
 }

-string &
+std::string &
 hostname()
 {
-static string hostname = __get_hostname();
+static std::string hostname = __get_hostname();
 return hostname;
 }

diff --git a/src/base/inet.cc b/src/base/inet.cc
index 6be4e26..1d556c5 100644
--- a/src/base/inet.cc
+++ b/src/base/inet.cc
@@ -50,12 +50,12 @@
 #include "base/logging.hh"
 #include "base/types.hh"

-using namespace std;
-namespace Net {
+namespace Net
+{

 EthAddr::EthAddr()
 {
-memset(data, 0, ETH_ADDR_LEN);
+std::memset(data, 0, ETH_ADDR_LEN);
 }

 EthAddr::EthAddr(const uint8_t ea[ETH_ADDR_LEN])
@@ -97,13 +97,13 @@
 int bytes[ETH_ADDR_LEN == 6 ? ETH_ADDR_LEN : -1];
 if (sscanf(addr.c_str(), 

[gem5-dev] Change in gem5/gem5[develop]: sim: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39537 )



Change subject: sim: Stop "using namespace std"
..

sim: Stop "using namespace std"

Change-Id: Ic641cb82a069ccb2b185d74a3b49a96b27111035
---
M src/sim/core.cc
M src/sim/debug.cc
M src/sim/eventq.cc
M src/sim/init.cc
M src/sim/init_signals.cc
M src/sim/process.cc
M src/sim/pseudo_inst.cc
M src/sim/serialize.cc
M src/sim/sim_events.cc
M src/sim/sim_object.cc
M src/sim/stat_control.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/sim/system.cc
14 files changed, 72 insertions(+), 89 deletions(-)



diff --git a/src/sim/core.cc b/src/sim/core.cc
index ace699a..928e6c8 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -39,8 +39,6 @@
 #include "base/output.hh"
 #include "sim/eventq.hh"

-using namespace std;
-
 namespace Gem5Internal
 {

@@ -125,7 +123,7 @@
 Tick getClockFrequency() { return _ticksPerSecond; }

 void
-setOutputDir(const string )
+setOutputDir(const std::string )
 {
 simout.setDirectory(dir);
 }
@@ -159,6 +157,6 @@
 exitCallbacks().process();
 exitCallbacks().clear();

-cout.flush();
+std::cout.flush();
 }

diff --git a/src/sim/debug.cc b/src/sim/debug.cc
index b2b3d45..4144caf 100644
--- a/src/sim/debug.cc
+++ b/src/sim/debug.cc
@@ -40,8 +40,6 @@
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"

-using namespace std;
-
 //
 // Debug event: place a breakpoint on the process function and
 // schedule the event to break at a particular cycle
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index adce51e..3e99683 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -43,8 +43,6 @@
 #include "debug/Checkpoint.hh"
 #include "sim/core.hh"

-using namespace std;
-
 Tick simQuantum = 0;

 //
@@ -54,7 +52,7 @@
 // cycle, before the pipeline simulation is performed.
 //
 uint32_t numMainEventQueues = 0;
-vector mainEventQueue;
+std::vector mainEventQueue;
 __thread EventQueue *_curEventQueue = NULL;
 bool inParallelMode = false;

@@ -419,7 +417,7 @@
 }
 }

-EventQueue::EventQueue(const string )
+EventQueue::EventQueue(const std::string )
 : objName(n), head(NULL), _curTick(0)
 {
 }
diff --git a/src/sim/init.cc b/src/sim/init.cc
index 73d4dbd..6abb0e1 100644
--- a/src/sim/init.cc
+++ b/src/sim/init.cc
@@ -65,7 +65,6 @@

 #endif

-using namespace std;
 namespace py = pybind11;

 // The python library is totally messed up with respect to constness,
@@ -81,16 +80,16 @@
 {
 // if we've added the importer keep track of it because we need it
 // to bootstrap.
-if (string(modpath) == string("importer"))
+if (std::string(modpath) == std::string("importer"))
 importer = this;
 else
 getList().push_back(this);
 }

-list &
+std::list &
 EmbeddedPython::getList()
 {
-static list the_list;
+static std::list the_list;
 return the_list;
 }

@@ -142,8 +141,8 @@

 // Load the rest of the embedded python files into the embedded
 // python importer
-list::iterator i = getList().begin();
-list::iterator end = getList().end();
+std::list::iterator i = getList().begin();
+std::list::iterator end = getList().end();
 for (; i != end; ++i)
 if (!(*i)->addModule())
 return 1;
diff --git a/src/sim/init_signals.cc b/src/sim/init_signals.cc
index 305f0cf..db82682 100644
--- a/src/sim/init_signals.cc
+++ b/src/sim/init_signals.cc
@@ -61,8 +61,6 @@
 #include "sim/core.hh"
 #include "sim/eventq.hh"

-using namespace std;
-
 // Use an separate stack for fatal signal handlers
 static uint8_t fatalSigStack[2 * SIGSTKSZ];

@@ -146,7 +144,8 @@
 {
 const EventQueue *const eq(curEventQueue());
 if (eq) {
-ccprintf(cerr, "Program aborted at tick %llu\n", eq->getCurTick());
+ccprintf(std::cerr, "Program aborted at tick %llu\n",
+eq->getCurTick());
 } else {
 STATIC_ERR("Program aborted\n\n");
 }
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 7819820..ac95b41 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -67,7 +67,6 @@
 #include "sim/syscall_desc.hh"
 #include "sim/system.hh"

-using namespace std;
 using namespace TheISA;

 namespace
@@ -127,7 +126,8 @@
   _gid(params.gid), _egid(params.egid),
   _pid(params.pid), _ppid(params.ppid),
   _pgid(params.pgid), drivers(params.drivers),
-  fds(make_shared(params.input, params.output,  
params.errout)),

+  fds(std::make_shared(
+  params.input, params.output, params.errout)),
   childClearTID(0),
   ADD_STAT(numSyscalls, "Number of system calls")
 {
@@ -189,7 +189,7 @@
  * Duplicate the process memory address space. The state needs to  
be

  * copied over (rather than using pointers to share everything).
  */
-typedef std::vector> MapVec;
+typedef std::vector> MapVec;
 MapVec mappings;
 

[gem5-dev] Change in gem5/gem5[develop]: dev: Stop "using namespace std"

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39538 )



Change subject: dev: Stop "using namespace std"
..

dev: Stop "using namespace std"

Change-Id: I317df9b566936445c3a02c28ed37146a16610454
---
M src/dev/baddev.cc
M src/dev/intel_8254_timer.cc
M src/dev/isa_fake.cc
M src/dev/mc146818.cc
M src/dev/mips/malta.cc
M src/dev/mips/malta_cchip.cc
M src/dev/mips/malta_io.cc
M src/dev/net/dist_etherlink.cc
M src/dev/net/dist_iface.cc
M src/dev/net/etherbus.cc
M src/dev/net/etherlink.cc
M src/dev/net/etherpkt.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/pktfifo.cc
M src/dev/net/sinic.cc
M src/dev/net/tcp_iface.cc
M src/dev/platform.cc
M src/dev/serial/terminal.cc
M src/dev/serial/uart8250.cc
M src/dev/sparc/dtod.cc
M src/dev/sparc/t1000.cc
M src/dev/storage/disk_image.cc
M src/dev/storage/simple_disk.cc
24 files changed, 67 insertions(+), 113 deletions(-)



diff --git a/src/dev/baddev.cc b/src/dev/baddev.cc
index 3a64212..f291459 100644
--- a/src/dev/baddev.cc
+++ b/src/dev/baddev.cc
@@ -38,8 +38,6 @@
 #include "params/BadDevice.hh"
 #include "sim/system.hh"

-using namespace std;
-
 BadDevice::BadDevice(const Params )
 : BasicPioDevice(p, 0x10), devname(p.devicename)
 {
diff --git a/src/dev/intel_8254_timer.cc b/src/dev/intel_8254_timer.cc
index 7877c91..a2ba7a4 100644
--- a/src/dev/intel_8254_timer.cc
+++ b/src/dev/intel_8254_timer.cc
@@ -31,9 +31,7 @@
 #include "base/logging.hh"
 #include "debug/Intel8254Timer.hh"

-using namespace std;
-
-Intel8254Timer::Intel8254Timer(EventManager *em, const string ,
+Intel8254Timer::Intel8254Timer(EventManager *em, const std::string ,
 Counter *counter0, Counter *counter1, Counter *counter2) :
 EventManager(em), _name(name)
 {
@@ -42,7 +40,7 @@
 counter[2] = counter2;
 }

-Intel8254Timer::Intel8254Timer(EventManager *em, const string ) :
+Intel8254Timer::Intel8254Timer(EventManager *em, const std::string ) :
 EventManager(em), _name(name)
 {
 counter[0] = new Counter(this, name + ".counter0", 0);
@@ -68,7 +66,7 @@
 }

 void
-Intel8254Timer::serialize(const string , CheckpointOut ) const
+Intel8254Timer::serialize(const std::string , CheckpointOut ) const
 {
 // serialize the counters
 counter[0]->serialize(base + ".counter0", cp);
@@ -77,7 +75,7 @@
 }

 void
-Intel8254Timer::unserialize(const string , CheckpointIn )
+Intel8254Timer::unserialize(const std::string , CheckpointIn )
 {
 // unserialze the counters
 counter[0]->unserialize(base + ".counter0", cp);
@@ -94,7 +92,7 @@
 }

 Intel8254Timer::Counter::Counter(Intel8254Timer *p,
-const string , unsigned int _num)
+const std::string , unsigned int _num)
 : _name(name), num(_num), event(this), running(false),
   initial_count(0), latched_count(0), period(0), mode(0),
   output_high(false), latch_on(false), read_byte(LSB),
@@ -225,7 +223,8 @@
 }

 void
-Intel8254Timer::Counter::serialize(const string , CheckpointOut )  
const

+Intel8254Timer::Counter::serialize(
+const std::string , CheckpointOut ) const
 {
 paramOut(cp, base + ".initial_count", initial_count);
 paramOut(cp, base + ".latched_count", latched_count);
@@ -243,7 +242,7 @@
 }

 void
-Intel8254Timer::Counter::unserialize(const string , CheckpointIn )
+Intel8254Timer::Counter::unserialize(const std::string , CheckpointIn  
)

 {
 paramIn(cp, base + ".initial_count", initial_count);
 paramIn(cp, base + ".latched_count", latched_count);
diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc
index b441120..0132ddc 100644
--- a/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@ -38,8 +38,6 @@
 #include "mem/packet_access.hh"
 #include "sim/system.hh"

-using namespace std;
-
 IsaFake::IsaFake(const Params )
 : BasicPioDevice(p, p.ret_bad_addr ? 0 : p.pio_size)
 {
diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc
index 3ea1d0d..5e76a23 100644
--- a/src/dev/mc146818.cc
+++ b/src/dev/mc146818.cc
@@ -39,8 +39,6 @@
 #include "debug/MC146818.hh"
 #include "dev/rtcreg.h"

-using namespace std;
-
 static uint8_t
 bcdize(uint8_t val)
 {
@@ -87,8 +85,8 @@
 }
 }

-MC146818::MC146818(EventManager *em, const string , const struct tm time,
-   bool bcd, Tick frequency)
+MC146818::MC146818(EventManager *em, const std::string ,
+const struct tm time, bool bcd, Tick frequency)
 : EventManager(em), _name(n), event(this, frequency), tickEvent(this)
 {
 memset(clock_data, 0, sizeof(clock_data));
@@ -262,7 +260,7 @@
 }

 void
-MC146818::serialize(const string , CheckpointOut ) const
+MC146818::serialize(const std::string , CheckpointOut ) const
 {
 uint8_t regA_serial(stat_regA);
 uint8_t regB_serial(stat_regB);
@@ -282,7 +280,7 @@
 }

 void
-MC146818::unserialize(const string , CheckpointIn )
+MC146818::unserialize(const std::string , CheckpointIn )
 {
 uint8_t tmp8;

diff --git