[gem5-dev] Build failed in Jenkins: nightly #318

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[gabe.black] cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.

[gabe.black] base: Stop using macros in base/socket.test.cc.

[gabe.black] cpu: Drop the DynInstPtr types from O3CPUImpl.

[gabe.black] cpu: Remove the O3CPU type from the O3CPUImpl.

[gabe.black] cpu: Remove comm types from O3CPUImpl.

[gabe.black] cpu: Remove the MemDepPred template parameter from MemDepUnit.

[gabe.black] cpu: De-templatize the O3 MemDepUnit.

[gabe.black] cpu: De-templatize the O3 ROB.

[Bobby R. Bruce] mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

[gabe.black] arch-riscv: When an inst generates a fault, return it immediately.

[gabe.black] cpu: De-templatize O3's LSQUnit.

[gabe.black] cpu: De-templatize the O3 InstructionQueue.

[gabe.black] cpu: De-templatize the O3 DefaultFetch.

[gabe.black] cpu: De-templatize the O3 DefaultDecode.

[gabe.black] cpu: De-templatize the O3 LSQ.

[gabe.black] cpu: De-templatize the O3 DefaultIEW.

[gabe.black] cpu: De-templatize the O3 DefaultRename.

[gabe.black] cpu: De-templatize the O3 DefaultCommit.

[gabe.black] cpu: De-templatize the O3ThreadContext.

[gabe.black] cpu: Delete the unnecessary BaseO3CPU class.

[gabe.black] cpu: De-templatize the FullO3CPU class.

[gabe.black] cpu: De-templatize the O3ThreadState.

[gabe.black] cpu: Delete the now unused cpu/o3/impl.hh.


--
[...truncated 491.59 KB...]
[ RUN  ] CyclesTest.PrefixDecrement
[   OK ] CyclesTest.PrefixDecrement (0 ms)
[ RUN  ] CyclesTest.InPlaceAddition
[   OK ] CyclesTest.InPlaceAddition (0 ms)
[ RUN  ] CyclesTest.GreaterThanLessThan
[   OK ] CyclesTest.GreaterThanLessThan (0 ms)
[ RUN  ] CyclesTest.AddCycles
[   OK ] CyclesTest.AddCycles (0 ms)
[ RUN  ] CyclesTest.SubtractCycles
[   OK ] CyclesTest.SubtractCycles (0 ms)
[ RUN  ] CyclesTest.ShiftRight
[   OK ] CyclesTest.ShiftRight (0 ms)
[ RUN  ] CyclesTest.ShiftLeft
[   OK ] CyclesTest.ShiftLeft (0 ms)
[ RUN  ] CyclesTest.OutStream
[   OK ] CyclesTest.OutStream (0 ms)
[--] 10 tests from CyclesTest (0 ms total)

[--] 5 tests from MicroPCTest
[ RUN  ] MicroPCTest.CheckMicroPCRomBit
[   OK ] MicroPCTest.CheckMicroPCRomBit (0 ms)
[ RUN  ] MicroPCTest.RomMicroPCTest
[   OK ] MicroPCTest.RomMicroPCTest (0 ms)
[ RUN  ] MicroPCTest.NormalMicroPCTest
[   OK ] MicroPCTest.NormalMicroPCTest (0 ms)
[ RUN  ] MicroPCTest.IsRomMicroPCTest
[   OK ] MicroPCTest.IsRomMicroPCTest (0 ms)
[ RUN  ] MicroPCTest.IsNotRomMicroPCTest
[   OK ] MicroPCTest.IsNotRomMicroPCTest (0 ms)
[--] 5 tests from MicroPCTest (0 ms total)

[--] 4 tests from TypesTest
[ RUN  ] TypesTest.FloatToBits32
[   OK ] TypesTest.FloatToBits32 (0 ms)
[ RUN  ] TypesTest.floatToBits64
[   OK ] TypesTest.floatToBits64 (0 ms)
[ RUN  ] TypesTest.floatsToBitsDoubleInput
[   OK ] TypesTest.floatsToBitsDoubleInput (0 ms)
[ RUN  ] TypesTest.floatsToBitsFloatInput
[   OK ] TypesTest.floatsToBitsFloatInput (0 ms)
[--] 4 tests from TypesTest (0 ms total)

[--] Global test environment tear-down
[==] 19 tests from 3 test suites ran. (1 ms total)
[  PASSED  ] 19 tests.
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 2 tests from 1 test suite.
[--] Global test environment set-up.
[--] 2 tests from UncontendedMutex
[ RUN  ] UncontendedMutex.Lock
build/NULL/sim/byteswap.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/sim/byteswap.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 8 tests from 1 test suite.
[--] Global test environment set-up.
[--] 8 tests from ByteswapTest
[ RUN  ] ByteswapTest.swap_byte64
[   OK ] ByteswapTest.swap_byte64 (0 ms)
[ RUN  ] ByteswapTest.swap_byte32
[   OK ] ByteswapTest.swap_byte32 (0 ms)
[ RUN  ] ByteswapTest.swap_byte16
[   OK ] ByteswapTest.swap_byte16 (0 ms)
[ RUN  ] ByteswapTest.swap_byte
[   OK ] ByteswapTest.swap_byte (0 ms)
[ RUN  ] ByteswapTest.htog
[   OK ] ByteswapTest.htog (0 ms)
[ RUN  ] ByteswapTest.gtoh
[   OK ] ByteswapTest.gtoh (0 ms)
[ RUN  ] ByteswapTest.betole
[   OK ] ByteswapTest.betole (0 ms)
[ RUN  ] ByteswapTest.letobe
[   OK ] ByteswapTest.letobe (0 ms)
[--] 8 tests from ByteswapTest (0 ms total)

[--] Global test environment tear-down
[==] 8 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 8 tests.
build/NULL/sim/guest_abi.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/sim/guest_abi.test.xml
build/NULL/sim/proxy_ptr.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/sim/proxy_ptr.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 7 tests from 1 test suite.
[--] Global 

[gem5-dev] test breakage for GCN3 on ToT?

[Gabe Black via gem5-dev]

Hey folks, I'm trying to test a change of mine, and it looks like the tests
are broken on ToT for GCN3? Not sure if it's just something that's out of
whack on my system, or if incompatible patches passed each other on gerrit.

I'm attempting to bisect where things went wrong, but I wouldn't complain
if anyone else wants to try to figure it out too.

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Work around a bug in g++ 6 and 7.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45820 )


Change subject: arch-x86: Work around a bug in g++ 6 and 7.
..

arch-x86: Work around a bug in g++ 6 and 7.

These versions of g++ don't handle parameter pack expansion correctly
when there is a parameter pack defined at the class level and then one
which is defined by the constructor itself. Even though it knows what
the outter parameter pack contains, it still re-assigns it to be empty
and puts all arguments into the later parameter pack.

To work around this problem, we will explicitly put the class level
parameters into a tuple, which we then have to go through extra
acrobatics to explode and pass into base class constructors.

That also means that in all subclasses, the arguments which go into the
tuple need to be wrapped in {}s to group them into constructor arguments
for the tuple.

Change-Id: I3139eebd7042b02f50862d88be5c940583a2a809
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45820
Maintainer: Gabe Black 
Maintainer: Bobby R. Bruce 
Reviewed-by: Matt Sinclair 
Reviewed-by: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/x86/insts/microldstop.hh
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/insts/microspecop.hh
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/isa/microops/seqop.isa
M src/arch/x86/isa/microops/specop.isa
9 files changed, 33 insertions(+), 16 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/insts/microldstop.hh  
b/src/arch/x86/insts/microldstop.hh

index 067e5bd..8ce458b 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -39,6 +39,8 @@
 #ifndef __ARCH_X86_INSTS_MICROLDSTOP_HH__
 #define __ARCH_X86_INSTS_MICROLDSTOP_HH__

+#include 
+
 #include "arch/x86/insts/microop.hh"
 #include "arch/x86/insts/microop_args.hh"
 #include "arch/x86/ldstflags.hh"
@@ -89,7 +91,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-_data, { _scale, _index, _base, _disp, _segment },
+{ _data, { _scale, _index, _base, _disp, _segment } },
 data_size, address_size, mem_flags | _segment.index)
 {}
 };
@@ -108,7 +110,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-_data, { _scale, _index, _base, _disp, _segment },
+{ _data, { _scale, _index, _base, _disp, _segment } },
 data_size, address_size, mem_flags | _segment.index)
 {}
 };
@@ -126,7 +128,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-{ _scale, _index, _base, _disp, _segment },
+{ { _scale, _index, _base, _disp, _segment } },
 data_size, address_size, mem_flags | _segment.index)
 {}
 };
@@ -148,7 +150,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-data_low, data_hi, { _scale, _index, _base, _disp, _segment },
+{ data_low, data_hi, { _scale, _index, _base, _disp, _segment  
} },

 data_size, address_size, mem_flags | _segment.index)
 {}
 };
diff --git a/src/arch/x86/insts/microop_args.hh  
b/src/arch/x86/insts/microop_args.hh

index 3a9cb06..f810a74 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -31,6 +31,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 #include "arch/x86/insts/static_inst.hh"
 #include "arch/x86/regs/int.hh"
@@ -338,13 +340,26 @@
 template 
 class InstOperands : public Base, public Operands...
 {
+  private:
+using ArgTuple = std::tuple;
+
+template 
+InstOperands(std::index_sequence, ExtMachInst mach_inst,
+const char *mnem, const char *inst_mnem, uint64_t set_flags,
+OpClass op_class, GEM5_VAR_USED ArgTuple args,
+CTorArgs... ctor_args) :
+Base(mach_inst, mnem, inst_mnem, set_flags, op_class,  
ctor_args...),

+Operands(this, std::get(args))...
+{}
+
   protected:
 template 
 InstOperands(ExtMachInst mach_inst, const char *mnem,
 const char *inst_mnem, uint64_t set_flags, OpClass op_class,
-typename Operands::ArgType... args, CTorArgs... ctor_args) :
-Base(mach_inst, mnem, inst_mnem, set_flags, op_class,  
ctor_args...),

-Operands(this, args)...
+

[gem5-dev] Change in gem5/gem5[develop]: base: Initialize some variables in the wide multiply helpers.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45819 )


Change subject: base: Initialize some variables in the wide multiply  
helpers.

..

base: Initialize some variables in the wide multiply helpers.

Not initializing them seems to upset older versions of g++.

Change-Id: Ib3de0460463f2fe514175484c49e1df68dacb4d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45819
Reviewed-by: Daniel Carvalho 
Reviewed-by: Matt Sinclair 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/intmath.hh
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index 4be4a3b..78d0795 100644
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -228,7 +228,7 @@
 static constexpr std::pair,  
std::make_unsigned_t>

 mulUnsigned(std::make_unsigned_t val_a, std::make_unsigned_t val_b)
 {
-std::make_unsigned_t hi, low;
+std::make_unsigned_t hi{}, low{};
 mulUnsigned(hi, low, val_a, val_b);
 return {hi, low};
 };
@@ -237,7 +237,7 @@
 static constexpr std::pair, std::make_signed_t>
 mulSigned(std::make_signed_t val_a, std::make_signed_t val_b)
 {
-std::make_signed_t hi, low;
+std::make_signed_t hi{}, low{};
 mulSigned(hi, low, val_a, val_b);
 return {hi, low};
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib3de0460463f2fe514175484c49e1df68dacb4d3
Gerrit-Change-Number: 45819
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] gem5 Minor release: Candidate patches

[Bobby Bruce via gem5-dev]

Dear all,

I'm getting ready to go for our first gem5 minor release, consisting of bug
fixes but no functionality/API changes. I've cherry-picked some candidates
that have already been reviewed and merged on the develop branch. These can
be found in this relation-chain:
https://gem5-review.googlesource.com/c/public/gem5/+/45829.

I'm currently running our usual suite of compiler, nightly, and weekly
tests on these, but I'd appreciate a thorough review. While I'm fairly
confident most of these are simple bug fixes, I'd appreciate confirmation.

I will not merge a patch until I get sign-off from an original author (out
of respect, and to validate I'm not doing something silly). To be clear, if
merged into the minor-release-staging-v21-0-1branch on Gerrit, it will be
part of the gem5 v21.0.1 minor release.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net
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[gem5-dev] Change in gem5/gem5[develop]: arch: Rename freebsd loader variables as freebsdLoader

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45423 )


Change subject: arch: Rename freebsd loader variables as freebsdLoader
..

arch: Rename freebsd loader variables as freebsdLoader

Pave the way for a loader namespace.

Change-Id: Ief6f54cc49840fb6c156d56ba3da52dc0a995ac8
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45423
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/arm/freebsd/se_workload.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/freebsd/se_workload.cc  
b/src/arch/arm/freebsd/se_workload.cc

index 12f966e..5e52485 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -71,7 +71,7 @@
 }
 };

-FreebsdLoader loader;
+FreebsdLoader freebsdLoader;

 } // anonymous namespace




2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief6f54cc49840fb6c156d56ba3da52dc0a995ac8
Gerrit-Change-Number: 45423
Gerrit-PatchSet: 6
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Rename prefetch variable as isPrefetch

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45409 )


Change subject: gpu-compute: Rename prefetch variable as isPrefetch
..

gpu-compute: Rename prefetch variable as isPrefetch

Pave the way for a prefetch namespace.

Change-Id: I4372abb5603eb6a920f7ff127cde54cb24e31377
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45409
Tested-by: kokoro 
Reviewed-by: Matthew Poremba 
Reviewed-by: Matt Sinclair 
Maintainer: Matthew Poremba 
Maintainer: Matt Sinclair 
---
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/tlb_coalescer.cc
3 files changed, 14 insertions(+), 14 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index dfe9a48..edd839f 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -676,7 +676,7 @@
 TranslationState *sender_state =
 safe_cast(pkt->senderState);

-bool update_stats = !sender_state->prefetch;
+bool update_stats = !sender_state->isPrefetch;
 ThreadContext * tmp_tc = sender_state->tc;

 DPRINTF(GPUTLB, "Translation req. for virt. page addr %#x\n",
@@ -891,7 +891,7 @@
 safe_cast(pkt->senderState);

 int req_cnt = tmp_sender_state->reqCnt.back();
-bool update_stats = !tmp_sender_state->prefetch;
+bool update_stats = !tmp_sender_state->isPrefetch;


 if (outcome == TLB_HIT) {
@@ -1102,7 +1102,7 @@
  * This feature could be used to explore security issues around
  * speculative memory accesses.
  */
-if (!sender_state->prefetch && sender_state->tlbEntry)
+if (!sender_state->isPrefetch && sender_state->tlbEntry)
 pagingProtectionChecks(tc, pkt, local_entry, mode);

 int page_size = local_entry->size();
@@ -1124,7 +1124,7 @@
 safe_cast(pkt->senderState);

 ThreadContext *tc = sender_state->tc;
-bool update_stats = !sender_state->prefetch;
+bool update_stats = !sender_state->isPrefetch;

 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
 X86ISA::PageBytes);
@@ -1154,7 +1154,7 @@
 // there is a TLB below -> propagate down the TLB hierarchy
 tlb->memSidePort[0]->sendFunctional(pkt);
 // If no valid translation from a prefetch, then just  
return

-if (sender_state->prefetch && !pkt->req->hasPaddr())
+if (sender_state->isPrefetch && !pkt->req->hasPaddr())
 return;
 } else {
 // Need to access the page table and update the TLB
@@ -1175,7 +1175,7 @@
 pte = p->pTable->lookup(vaddr);
 }

-if (!sender_state->prefetch) {
+if (!sender_state->isPrefetch) {
 // no PageFaults are permitted after
 // the second page table lookup
 assert(pte);
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 1df907b..b678f6b 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -293,7 +293,7 @@
 */
 TlbEntry *tlbEntry;
 // Is this a TLB prefetch request?
-bool prefetch;
+bool isPrefetch;
 // When was the req for this translation issued
 uint64_t issueTime;
 // Remember where this came from
@@ -307,10 +307,10 @@
 Packet::SenderState *saved;

 TranslationState(Mode tlb_mode, ThreadContext *_tc,
- bool _prefetch=false,
+ bool is_prefetch=false,
  Packet::SenderState *_saved=nullptr)
 : tlbMode(tlb_mode), tc(_tc), tlbEntry(nullptr),
-  prefetch(_prefetch), issueTime(0),
+  isPrefetch(is_prefetch), issueTime(0),
   hitLevel(0),saved(_saved) { }
 };

diff --git a/src/gpu-compute/tlb_coalescer.cc  
b/src/gpu-compute/tlb_coalescer.cc

index 08f0f95..ea754c1 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -127,7 +127,7 @@
 // when we can coalesce a packet update the reqCnt
 // that is the number of packets represented by
 // this coalesced packet
-if (!incoming_state->prefetch)
+if (!incoming_state->isPrefetch)
 coalesced_state->reqCnt.back() += incoming_state->reqCnt.back();

 return true;
@@ -170,7 +170,7 @@

 // we are sending the packet back, so pop the reqCnt associated
 // with this level in 

[gem5-dev] Change in gem5/gem5[develop]: arch: Rename some linux loader variables as linuxLoader

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45422 )


Change subject: arch: Rename some linux loader variables as linuxLoader
..

arch: Rename some linux loader variables as linuxLoader

Pave the way for a loader namespace.

Change-Id: Ie7c811e74424063ff773569e7ad9df9dde166d4f
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45422
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/arm/linux/se_workload.cc
M src/arch/mips/linux/se_workload.cc
M src/arch/power/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.cc
M src/arch/sparc/linux/se_workload.cc
M src/arch/x86/linux/se_workload.cc
6 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/linux/se_workload.cc  
b/src/arch/arm/linux/se_workload.cc

index da523fb..8080b2b 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -85,7 +85,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/mips/linux/se_workload.cc  
b/src/arch/mips/linux/se_workload.cc

index 2edb764..2c6b9d5 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -64,7 +64,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/power/linux/se_workload.cc  
b/src/arch/power/linux/se_workload.cc

index 864468f..90add2f 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -64,7 +64,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/riscv/linux/se_workload.cc  
b/src/arch/riscv/linux/se_workload.cc

index a59423e..7ffc5f6 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -68,7 +68,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/sparc/linux/se_workload.cc  
b/src/arch/sparc/linux/se_workload.cc

index 848f64b..1659163 100644
--- a/src/arch/sparc/linux/se_workload.cc
+++ b/src/arch/sparc/linux/se_workload.cc
@@ -66,7 +66,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/x86/linux/se_workload.cc  
b/src/arch/x86/linux/se_workload.cc

index f6f9d9a..66e4763 100644
--- a/src/arch/x86/linux/se_workload.cc
+++ b/src/arch/x86/linux/se_workload.cc
@@ -81,7 +81,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace




2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Change-Number: 45422
Gerrit-PatchSet: 6
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: util-docker: Use python3 by default for Ubuntu 18.04 docker images

[Bobby R. Bruce (Gerrit) via gem5-dev]

Attention is currently required from: Hoa Nguyen, Jason Lowe-Power.
Hello kokoro, Hoa Nguyen, Jason Lowe-Power,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/45826

to review the following change.


Change subject: util-docker: Use python3 by default for Ubuntu 18.04 docker  
images

..

util-docker: Use python3 by default for Ubuntu 18.04 docker images

gem5 dropped the support for python2. This change sets python3
to have a higher priority than python2 in the Ubuntu 18.04 docker
images. This is done so that gem5 will be compiled and tested
in the python3 environment by default.

JIRA: https://gem5.atlassian.net/browse/GEM5-958

Signed-off-by: Hoa Nguyen 
Change-Id: I11ffb06697ecf4cebf9f98b611641faa42805547
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45125
Maintainer: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
M util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
2 files changed, 6 insertions(+), 0 deletions(-)



diff --git a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile

index 2403a50..775e549 100644
--- a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile
@@ -32,3 +32,6 @@
 libprotobuf-dev protobuf-compiler libprotoc-dev  
libgoogle-perftools-dev \

 python3-dev python3 python3-six doxygen libboost-all-dev \
 libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config
+
+RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

+RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1
diff --git a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile

index 5ec6784..53a7d92 100644
--- a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
@@ -30,3 +30,6 @@
 RUN apt -y upgrade
 RUN apt -y install build-essential scons zlib1g-dev m4 python3-dev python3  
\

 python3-six
+
+RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

+RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1

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Gerrit-Change-Number: 45826
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: util: Fix cpt_upgrader format string

[Bobby R. Bruce (Gerrit) via gem5-dev]

Attention is currently required from: Giacomo Travaglini, Jason Lowe-Power.
Hello kokoro, Giacomo Travaglini, Jason Lowe-Power,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/45824

to review the following change.


Change subject: util: Fix cpt_upgrader format string
..

util: Fix cpt_upgrader format string

Change-Id: I9d15316f199b20976420c35d2c79dd13cc9db9ee
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44510
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/cpt_upgrader.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 15dc2ab..5331c49 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -126,7 +126,7 @@
 sys.exit(1)
 Upgrader.untag_set.add(self.tag)
 else:
-print("Error: no upgrader or downgrader method for".format(
+print("Error: no upgrader or downgrader method for {}".format(
 self.tag))
 sys.exit(1)


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Gerrit-Change-Number: 45824
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: dev: Fix GCN3_X86 builds on aarch64 host

[Bobby R. Bruce (Gerrit) via gem5-dev]

Attention is currently required from: Giacomo Travaglini, Gabe Black.
Hello kokoro, Giacomo Travaglini, Gabe Black,

I'd like you to do a code review.
Please visit

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to review the following change.


Change subject: dev: Fix GCN3_X86 builds on aarch64 host
..

dev: Fix GCN3_X86 builds on aarch64 host

Signed-off-by: Giacomo Travaglini 
Change-Id: Ic826f0cb46e07b9b5135eee1e518bc13f3d978a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44485
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/hsa/hsa.h
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/dev/hsa/hsa.h b/src/dev/hsa/hsa.h
index f7d15ba..1c1f340 100644
--- a/src/dev/hsa/hsa.h
+++ b/src/dev/hsa/hsa.h
@@ -80,7 +80,7 @@
 // Try to detect CPU endianness
 #if !defined(LITTLEENDIAN_CPU) && !defined(BIGENDIAN_CPU)
 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || \
-defined(_M_X64)
+defined(_M_X64) || defined(__aarch64__)
 #define LITTLEENDIAN_CPU
 #endif
 #endif

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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

[Bobby R. Bruce (Gerrit) via gem5-dev]

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Please visit

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to review the following change.


Change subject: mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache
..

mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

This check always equated to False. It should be an 'or' not an 'and'
comparison.

The Clang 11 compiler threw an "overlapping comparisons always evaluate
to false" error for the code generaed from this.

Change-Id: I299dc6fa8206d5e85d59ba8353bf16102b8e5e1b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45799
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm  
b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm

index 5c3d5f7..c9fe135 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
@@ -358,7 +358,7 @@
   }

   // You have at least half the token in O-like states
-  if (state == State:O && state == State:OM) {
+  if (state == State:O || state == State:OM) {
 assert(cache_entry.Tokens > (max_tokens() / 2));
   }


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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: systemc: Fix verify.py and make it python 3 compatible

[Bobby R. Bruce (Gerrit) via gem5-dev]

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Change subject: systemc: Fix verify.py and make it python 3 compatible
..

systemc: Fix verify.py and make it python 3 compatible

1. The logger behavior change breaks verify.py.
commit 8deb205ea10d6cee0b58c46e097be46c784ed345
Author: Daniel Carvalho 
Date:   Wed Mar 3 16:49:05 2021 -0300

base: Add LOC to Loggers

Printing the line and the file that triggered a log
is useful for debugging.

Change-Id: I74e0637b2943049134bd3e9a4bc6cab3766591a9
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42141
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 

2. Use bytes diff in LogChecker.
In Python3, string is required to be in a certain encoding, while in  
Python2,

it is not. In the testcase, misc/cae_test/general/bitwise/or/datatypes,
it contains some invalid codepoint of utf-8, we need diff the log with
bytes in Pyhton3.

3. Python3 compatible.
* dict.iteritems -> dict.items
* remove object base class
* use `except as` when catching exceptions
* handle map and filter behavior change

Test with

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt --phase verify --result-file

Change-Id: Ibf5b99d08a948387cf6162c476c294c49a7dac0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44465
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/systemc/tests/verify.py
1 file changed, 47 insertions(+), 30 deletions(-)



diff --git a/src/systemc/tests/verify.py b/src/systemc/tests/verify.py
index 6b4cf5c..95812f4 100755
--- a/src/systemc/tests/verify.py
+++ b/src/systemc/tests/verify.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2.7
+#!/usr/bin/env python
 #
 # Copyright 2018 Google, Inc.
 #
@@ -58,14 +58,14 @@



-class Test(object):
+class Test():
 def __init__(self, target, suffix, build_dir, props):
 self.target = target
 self.suffix = suffix
 self.build_dir = build_dir
 self.props = {}

-for key, val in props.iteritems():
+for key, val in props.items():
 self.set_prop(key, val)

 def set_prop(self, key, val):
@@ -107,7 +107,7 @@

 super(TestPhaseMeta, cls).__init__(name, bases, d)

-class TestPhaseBase(object, metaclass=TestPhaseMeta):
+class TestPhaseBase(metaclass=TestPhaseMeta):
 abstract = True

 def __init__(self, main_args, *args):
@@ -169,7 +169,7 @@
 os.makedirs(test.m5out_dir())
 try:
 subprocess.check_call(cmd, cwd=os.path.dirname(test.dir()))
-except subprocess.CalledProcessError, error:
+except subprocess.CalledProcessError as error:
 returncode = error.returncode
 else:
 returncode = 0
@@ -180,14 +180,14 @@

 runnable = filter(lambda t: not t.compile_only, tests)
 if j == 1:
-map(run_test, runnable)
+list(map(run_test, runnable))
 else:
 tp = multiprocessing.pool.ThreadPool(j)
-map(lambda t: tp.apply_async(run_test, (t,)), runnable)
+list(map(lambda t: tp.apply_async(run_test, (t,)), runnable))
 tp.close()
 tp.join()

-class Checker(object):
+class Checker():
 def __init__(self, ref, test, tag):
 self.ref = ref
 self.test = test
@@ -215,6 +215,13 @@
 super(DiffingChecker, self).__init__(ref, test, tag)
 self.out_dir = out_dir

+def is_bytes_mode(self):
+return False
+
+def do_diff(self, ref_lines, test_lines, ref_file, test_file):
+return difflib.unified_diff(ref_lines, test_lines,
+fromfile=ref_file, tofile=test_file)
+
 def diffing_check(self, ref_lines, test_lines):
 test_file = os.path.basename(self.test)
 ref_file = os.path.basename(self.ref)
@@ -222,11 +229,10 @@
 diff_file = '.'.join([ref_file, 'diff'])
 diff_path = os.path.join(self.out_dir, diff_file)
 if test_lines != ref_lines:
-with open(diff_path, 'w') as diff_f:
-for line in difflib.unified_diff(
-ref_lines, test_lines,
-fromfile=ref_file,
-tofile=test_file):
+flag = 'wb' if self.is_bytes_mode() else 'w'
+with open(diff_file, flag) as diff_f:
+for line in self.do_diff(ref_lines, test_lines,
+ ref_file, test_file):
   

[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: configs: restore_simpoint_checkpoint should be a boolean

[Bobby R. Bruce (Gerrit) via gem5-dev]

Attention is currently required from: Daniel Carvalho, Giacomo Travaglini,  
Jason Lowe-Power.

Hello kokoro, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/45825

to review the following change.


Change subject: configs: restore_simpoint_checkpoint should be a boolean
..

configs: restore_simpoint_checkpoint should be a boolean

The --restore_simpoint_checkpoint option is a boolean;
however if no default value is supplied, optparse sets the
default value to None

This is not valid for argparse. Argparse recognizes the store_true
action and it is automatically treating the option as a boolean,
hence providing a default=False instead of default=None

Change-Id: I6b09edf6911be71a06001730be1232a1b5c8482c
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44765
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/Options.py
M configs/common/Simulation.py
2 files changed, 2 insertions(+), 1 deletion(-)



diff --git a/configs/common/Options.py b/configs/common/Options.py
index c48bfe6..b833531 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -305,6 +305,7 @@
 parser.add_option("--take-simpoint-checkpoints", action="store",  
type="string",

 help="")
 parser.add_option("--restore-simpoint-checkpoint", action="store_true",
+default=False,
 help="restore from a simpoint checkpoint taken with " +
  "--take-simpoint-checkpoints")

diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 067bc01..3b9efc0 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -710,7 +710,7 @@
 takeSimpointCheckpoints(simpoints, interval_length, cptdir)

 # Restore from SimPoint checkpoints
-elif options.restore_simpoint_checkpoint != None:
+elif options.restore_simpoint_checkpoint:
 restoreSimpointCheckpoint()

 else:

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Gerrit-Change-Number: 45825
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: fastmodel: Fix scx_get_parameter_list for ARM fastmodels.

[Bobby R. Bruce (Gerrit) via gem5-dev]

Attention is currently required from: Gabe Black.
Hello kokoro, Gabe Black,

I'd like you to do a code review.
Please visit

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to review the following change.


Change subject: fastmodel: Fix scx_get_parameter_list for ARM fastmodels.
..

fastmodel: Fix scx_get_parameter_list for ARM fastmodels.

The first non-critical piece of this CL removes the unused self
from the Python function signature.

Then also includes "stl.h" from pybind11 to allow the
implicit conversion from std::map
to a Python dict (otherwise there will be a runtime (not compile time)
error when calling the function.

As the current implementation always throws an error because of the
missing stl.h I don't believe anyone is using this function, and as such
it should be safe to just change the signature of
scx_get_parameter_list.

Change-Id: Ib3202b2d4d1b8418a4adf54739fe389d4ee07743
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45622
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/arm_fast_model.py
M src/python/pybind11/pybind.hh
2 files changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/fastmodel/arm_fast_model.py  
b/src/arch/arm/fastmodel/arm_fast_model.py

index 3b9c7cb..c9d1113 100644
--- a/src/arch/arm/fastmodel/arm_fast_model.py
+++ b/src/arch/arm/fastmodel/arm_fast_model.py
@@ -77,7 +77,7 @@
 _m5.arm_fast_model.scx_get_parameter(name, value)
 return value

-def scx_get_parameter_list(self):
+def scx_get_parameter_list():
 return _m5.arm_fast_model.scx_get_parameter_list()

 def scx_set_cpi_file(cpi_file_path):
diff --git a/src/python/pybind11/pybind.hh b/src/python/pybind11/pybind.hh
index cdf18bc..256120e 100644
--- a/src/python/pybind11/pybind.hh
+++ b/src/python/pybind11/pybind.hh
@@ -39,6 +39,7 @@
 #define __PYTHON_PYBIND11_PYBIND_HH__

 #include "pybind11/pybind11.h"
+#include "pybind11/stl.h"

 void pybind_init_core(pybind11::module_ _native);
 void pybind_init_debug(pybind11::module_ _native);

--
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Gerrit-Change-Number: 45827
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: arch-arm: Fix FEAT_VMID16 for Self Hosted debug

[Bobby R. Bruce (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper, Giacomo Travaglini.
Hello Richard Cooper, kokoro, Giacomo Travaglini,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/45828

to review the following change.


Change subject: arch-arm: Fix FEAT_VMID16 for Self Hosted debug
..

arch-arm: Fix FEAT_VMID16 for Self Hosted debug

The existing code was querying the vmidbits but it was not checking the
VTCR_EL2.VS bit, which dynamically enables/disables VMID16

Signed-off-by: Giacomo Travaglini 
Change-Id: Id1e7df758a636267173c4fcd4db99e5834f21ee9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45659
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 12 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 86e4ae5..f1b21b4 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2021 Arm Limited
  * Copyright (c) 2019 Metempsy Technology LSC
  * All rights reserved
  *
@@ -452,15 +453,18 @@
 bool
 BrkPoint::testVMIDMatch(ThreadContext *tc)
 {
+const bool vs = ((VTCR_t)(tc->readMiscReg(MISCREG_VTCR_EL2))).vs;
+
 uint32_t vmid_index = 55;
-if (VMID16enabled)
+if (VMID16enabled && vs)
 vmid_index = 63;
 ExceptionLevel el = currEL(tc);
 if (el == EL2)
 return false;

-uint32_t vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), vmid_index,  
48);

-uint32_t v = getVMIDfromReg(tc);
+vmid_t vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), vmid_index, 48);
+vmid_t v = getVMIDfromReg(tc, vs);
+
 return (v == vmid);
 }

@@ -520,11 +524,11 @@
 return v && SelfDebug::securityStateMatch(tc, ssc, hmc || !aarch32);
 }

-uint32_t
-BrkPoint::getVMIDfromReg(ThreadContext *tc)
+vmid_t
+BrkPoint::getVMIDfromReg(ThreadContext *tc, bool vs)
 {
 uint32_t vmid_index = 39;
-if (VMID16enabled)
+if (VMID16enabled && vs)
 vmid_index = 47;
 return bits(tc->readMiscReg(valRegIndex), vmid_index, 32);
 }
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 2ae2f8e..e02e27d 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2021 Arm Limited
  * Copyright (c) 2019 Metempsy Technology LSC
  * All rights reserved
  *
@@ -103,7 +104,7 @@
 }


-inline uint32_t getVMIDfromReg(ThreadContext *tc);
+vmid_t getVMIDfromReg(ThreadContext *tc, bool vs);

   public:
 bool testAddrMatch(ThreadContext *tc, Addr pc, uint8_t bas);

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Gerrit-Change-Number: 45828
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: systemc: Eliminate ClockTick duplicated name warning

[Bobby R. Bruce (Gerrit) via gem5-dev]

Attention is currently required from: Gabe Black.
Hello kokoro, Gabe Black,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/45821

to review the following change.


Change subject: systemc: Eliminate ClockTick duplicated name warning
..

systemc: Eliminate ClockTick duplicated name warning

In systemc, a module name is consist of hierarchy names with dot
separated. The basename is the last part of the module name. Because
lack of hierarchy information, it's a chance that the basename is
duplicated. Although, ClockTick is using sc_gen_unique_name to solve
this, the warning from sc_gen_unique_name is annoying. To solve this
completely, we should use the full module name to construct the name of
ClockTick.

Change-Id: Ie664fe4757a05f72860be49c3a9d1172f824eb2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44425
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/systemc/channel/sc_clock.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/systemc/channel/sc_clock.cc  
b/src/systemc/channel/sc_clock.cc

index 137a7a1..bf48b82 100644
--- a/src/systemc/channel/sc_clock.cc
+++ b/src/systemc/channel/sc_clock.cc
@@ -54,7 +54,7 @@
 ClockTick(::sc_core::sc_clock *clock, bool to,
 ::sc_core::sc_time _period) :
 ScEvent([this]() { tick(); }),
-_period(_period), name(clock->basename()), p(nullptr),
+_period(_period), name(clock->name()), p(nullptr),
 funcWrapper(clock, to ? &::sc_core::sc_clock::tickUp :
 &::sc_core::sc_clock::tickDown)
 {

--
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Gerrit-Change-Number: 45821
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: dev: Rename Ps2 namespace as ps2

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45390 )


Change subject: dev: Rename Ps2 namespace as ps2
..

dev: Rename Ps2 namespace as ps2

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Ps2 became ::ps2.

Change-Id: I6630a0817ee4aa724ce4e76edac164c28a583d61
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45390
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/dev/ps2/device.cc
M src/dev/ps2/keyboard.cc
M src/dev/ps2/mouse.cc
M src/dev/ps2/touchkit.cc
M src/dev/ps2/types.cc
M src/dev/ps2/types.hh
6 files changed, 63 insertions(+), 58 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index 47eb026..b9dfafb 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -119,5 +119,5 @@
 void
 PS2Device::sendAck()
 {
-send(Ps2::Ack);
+send(ps2::Ack);
 }
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index d62ec44..86771f6 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -75,36 +75,36 @@
 PS2Keyboard::recv(const std::vector )
 {
 switch (data[0]) {
-  case Ps2::ReadID:
+  case ps2::ReadID:
 DPRINTF(PS2, "Got keyboard read ID command.\n");
 sendAck();
-send(Ps2::Keyboard::ID);
+send(ps2::Keyboard::ID);
 return true;
-  case Ps2::Enable:
+  case ps2::Enable:
 DPRINTF(PS2, "Enabling the keyboard.\n");
 enabled = true;
 sendAck();
 return true;
-  case Ps2::Disable:
+  case ps2::Disable:
 DPRINTF(PS2, "Disabling the keyboard.\n");
 enabled = false;
 sendAck();
 return true;
-  case Ps2::DefaultsAndDisable:
+  case ps2::DefaultsAndDisable:
 DPRINTF(PS2, "Disabling and resetting the keyboard.\n");
 enabled = false;
 sendAck();
 return true;
-  case Ps2::Reset:
+  case ps2::Reset:
 DPRINTF(PS2, "Resetting keyboard.\n");
 enabled = true;
 sendAck();
-send(Ps2::SelfTestPass);
+send(ps2::SelfTestPass);
 return true;
-  case Ps2::Resend:
+  case ps2::Resend:
 panic("Keyboard resend unimplemented.\n");

-  case Ps2::Keyboard::LEDWrite:
+  case ps2::Keyboard::LEDWrite:
 if (data.size() == 1) {
 DPRINTF(PS2, "Got LED write command.\n");
 sendAck();
@@ -118,11 +118,11 @@
 sendAck();
 return true;
 }
-  case Ps2::Keyboard::DiagnosticEcho:
+  case ps2::Keyboard::DiagnosticEcho:
 panic("Keyboard diagnostic echo unimplemented.\n");
-  case Ps2::Keyboard::AlternateScanCodes:
+  case ps2::Keyboard::AlternateScanCodes:
 panic("Accessing alternate scan codes unimplemented.\n");
-  case Ps2::Keyboard::TypematicInfo:
+  case ps2::Keyboard::TypematicInfo:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting typematic info.\n");
 sendAck();
@@ -132,20 +132,20 @@
 sendAck();
 return true;
 }
-  case Ps2::Keyboard::AllKeysToTypematic:
+  case ps2::Keyboard::AllKeysToTypematic:
 panic("Setting all keys to typemantic unimplemented.\n");
-  case Ps2::Keyboard::AllKeysToMakeRelease:
+  case ps2::Keyboard::AllKeysToMakeRelease:
 panic("Setting all keys to make/release unimplemented.\n");
-  case Ps2::Keyboard::AllKeysToMake:
+  case ps2::Keyboard::AllKeysToMake:
 panic("Setting all keys to make unimplemented.\n");
-  case Ps2::Keyboard::AllKeysToTypematicMakeRelease:
+  case ps2::Keyboard::AllKeysToTypematicMakeRelease:
 panic("Setting all keys to "
 "typematic/make/release unimplemented.\n");
-  case Ps2::Keyboard::KeyToTypematic:
+  case ps2::Keyboard::KeyToTypematic:
 panic("Setting a key to typematic unimplemented.\n");
-  case Ps2::Keyboard::KeyToMakeRelease:
+  case ps2::Keyboard::KeyToMakeRelease:
 panic("Setting a key to make/release unimplemented.\n");
-  case Ps2::Keyboard::KeyToMakeOnly:
+  case ps2::Keyboard::KeyToMakeOnly:
 panic("Setting key to make only unimplemented.\n");
   default:
 panic("Unknown keyboard command %#02x.\n", data[0]);
@@ -159,7 +159,7 @@

 // convert the X11 keysym into ps2 codes and update the shift
 // state (shiftDown)
-Ps2::keySymToPs2(key, down, shiftDown, keys);
+ps2::keySymToPs2(key, down, shiftDown, keys);

 // Drop key presses if the keyboard hasn't been enabled by the
 // host. We do that after translating the key code to ensure that
diff --git a/src/dev/ps2/mouse.cc 

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename Sinic namespace as sinic

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45385 )


Change subject: dev: Rename Sinic namespace as sinic
..

dev: Rename Sinic namespace as sinic

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Sinic became ::sinic.

Change-Id: I0a28089cc9f8f65b33101b4791d67c2f82b85059
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45385
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/dev/net/Ethernet.py
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/net/sinicreg.hh
4 files changed, 14 insertions(+), 7 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index 53cc035..dc29ce6 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -229,7 +229,7 @@

 class Sinic(EtherDevBase):
 type = 'Sinic'
-cxx_class = 'Sinic::Device'
+cxx_class = 'sinic::Device'
 cxx_header = "dev/net/sinic.hh"

 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index b893b49..e0fed58 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -45,7 +45,9 @@

 using namespace Net;

-namespace Sinic {
+GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
+namespace sinic
+{

 const char *RxStateStrings[] =
 {
@@ -1486,4 +1488,4 @@

 }

-} // namespace Sinic
+} // namespace sinic
diff --git a/src/dev/net/sinic.hh b/src/dev/net/sinic.hh
index 2230a77..750b682 100644
--- a/src/dev/net/sinic.hh
+++ b/src/dev/net/sinic.hh
@@ -29,6 +29,7 @@
 #ifndef __DEV_NET_SINIC_HH__
 #define __DEV_NET_SINIC_HH__

+#include "base/compiler.hh"
 #include "base/inet.hh"
 #include "base/statistics.hh"
 #include "dev/io_device.hh"
@@ -41,7 +42,9 @@
 #include "params/Sinic.hh"
 #include "sim/eventq.hh"

-namespace Sinic {
+GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
+namespace sinic
+{

 class Interface;
 class Base : public EtherDevBase
@@ -319,6 +322,6 @@
 virtual void sendDone() { dev->transferDone(); }
 };

-} // namespace Sinic
+} // namespace sinic

 #endif // __DEV_NET_SINIC_HH__
diff --git a/src/dev/net/sinicreg.hh b/src/dev/net/sinicreg.hh
index 97154db..55fca69 100644
--- a/src/dev/net/sinicreg.hh
+++ b/src/dev/net/sinicreg.hh
@@ -52,7 +52,9 @@
 static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
 { return (reg & ~NAME) | ((val << OFFSET) & NAME); }

-namespace Sinic {
+GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
+namespace sinic
+{
 namespace Regs {

 static const int VirtualShift = 8;
@@ -232,6 +234,6 @@
 return true;
 }

-} // namespace Sinic
+} // namespace sinic

 #endif // __DEV_NET_SINICREG_HH__



3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0a28089cc9f8f65b33101b4791d67c2f82b85059
Gerrit-Change-Number: 45385
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Rename TxdOp namespace as txd_op

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45386 )


Change subject: dev: Rename TxdOp namespace as txd_op
..

dev: Rename TxdOp namespace as txd_op

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

iGbReg::TxdOp became iGbReg::txd_op.

Change-Id: I737205a3d29ffc0d96da72ba9fc6829939970957
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45386
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe_defs.hh
2 files changed, 49 insertions(+), 45 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 30e38f0..73bea7a 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -1519,7 +1519,7 @@
 DPRINTF(EthernetDesc, "Checking and  processing context  
descriptors\n");


 while (!useTso && unusedCache.size() &&
-   TxdOp::isContext(unusedCache.front())) {
+   txd_op::isContext(unusedCache.front())) {
 DPRINTF(EthernetDesc, "Got context descriptor type...\n");

 desc = unusedCache.front();
@@ -1528,19 +1528,19 @@


 // is this going to be a tcp or udp packet?
-isTcp = TxdOp::tcp(desc) ? true : false;
+isTcp = txd_op::tcp(desc) ? true : false;

 // setup all the TSO variables, they'll be ignored if we don't use
 // tso for this connection
-tsoHeaderLen = TxdOp::hdrlen(desc);
-tsoMss  = TxdOp::mss(desc);
+tsoHeaderLen = txd_op::hdrlen(desc);
+tsoMss  = txd_op::mss(desc);

-if (TxdOp::isType(desc, TxdOp::TXD_CNXT) && TxdOp::tse(desc)) {
+if (txd_op::isType(desc, txd_op::TXD_CNXT) && txd_op::tse(desc)) {
 DPRINTF(EthernetDesc, "TCP offload enabled for packet hdrlen: "
-"%d mss: %d paylen %d\n", TxdOp::hdrlen(desc),
-TxdOp::mss(desc), TxdOp::getLen(desc));
+"%d mss: %d paylen %d\n", txd_op::hdrlen(desc),
+txd_op::mss(desc), txd_op::getLen(desc));
 useTso = true;
-tsoTotalLen = TxdOp::getLen(desc);
+tsoTotalLen = txd_op::getLen(desc);
 tsoLoadedHeader = false;
 tsoDescBytesUsed = 0;
 tsoUsedLen = 0;
@@ -1550,7 +1550,7 @@
 tsoCopyBytes = 0;
 }

-TxdOp::setDd(desc);
+txd_op::setDd(desc);
 unusedCache.pop_front();
 usedCache.push_back(desc);
 }
@@ -1559,13 +1559,13 @@
 return;

 desc = unusedCache.front();
-if (!useTso && TxdOp::isType(desc, TxdOp::TXD_ADVDATA) &&
-TxdOp::tse(desc)) {
+if (!useTso && txd_op::isType(desc, txd_op::TXD_ADVDATA) &&
+txd_op::tse(desc)) {
 DPRINTF(EthernetDesc, "TCP offload(adv) enabled for packet "
 "hdrlen: %d mss: %d paylen %d\n",
-tsoHeaderLen, tsoMss, TxdOp::getTsoLen(desc));
+tsoHeaderLen, tsoMss, txd_op::getTsoLen(desc));
 useTso = true;
-tsoTotalLen = TxdOp::getTsoLen(desc);
+tsoTotalLen = txd_op::getTsoLen(desc);
 tsoLoadedHeader = false;
 tsoDescBytesUsed = 0;
 tsoUsedLen = 0;
@@ -1577,10 +1577,10 @@
 if (useTso && !tsoLoadedHeader) {
 // we need to fetch a header
 DPRINTF(EthernetDesc, "Starting DMA of TSO header\n");
-assert(TxdOp::isData(desc) && TxdOp::getLen(desc) >= tsoHeaderLen);
+assert(txd_op::isData(desc) && txd_op::getLen(desc) >=  
tsoHeaderLen);

 pktWaiting = true;
 assert(tsoHeaderLen <= 256);
-igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)),
+igbe->dmaRead(pciToDma(txd_op::getBuf(desc)),
   tsoHeaderLen, , tsoHeader, 0);
 }
 }
@@ -1594,9 +1594,9 @@
 assert(unusedCache.size());
 TxDesc *desc = unusedCache.front();
 DPRINTF(EthernetDesc, "TSO: len: %d tsoHeaderLen: %d\n",
-TxdOp::getLen(desc), tsoHeaderLen);
+txd_op::getLen(desc), tsoHeaderLen);

-if (TxdOp::getLen(desc) == tsoHeaderLen) {
+if (txd_op::getLen(desc) == tsoHeaderLen) {
 tsoDescBytesUsed = 0;
 tsoLoadedHeader = true;
 unusedCache.pop_front();
@@ -1630,24 +1630,24 @@

 if (tsoPktHasHeader)
 tsoCopyBytes =  std::min((tsoMss + tsoHeaderLen) - p->length,
- TxdOp::getLen(desc) -  
tsoDescBytesUsed);
+ txd_op::getLen(desc) -  
tsoDescBytesUsed);

 else
 tsoCopyBytes =  std::min(tsoMss,
- TxdOp::getLen(desc) -  
tsoDescBytesUsed);
+ 

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename sinic::Regs namespace as sinic::registers

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45388 )


Change subject: dev: Rename sinic::Regs namespace as sinic::registers
..

dev: Rename sinic::Regs namespace as sinic::registers

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

sinic::Regs became sinic::registers.

"registers" was chosen over "regs" to reduce conflict
resolution (there is already a variable called regs).

Change-Id: I329d40884906bb55d1b1d749610b9f0dee243418
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45388
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/net/sinicreg.hh
3 files changed, 84 insertions(+), 76 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index e0fed58..53f8b88 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -146,7 +146,7 @@
 void
 Device::prepareRead(ContextID cpu, int index)
 {
-using namespace Regs;
+using namespace registers;
 prepareIO(cpu, index);

 VirtualReg  = virtualRegs[index];
@@ -203,14 +203,14 @@
 daddr -= BARs[0]->addr();

 ContextID cpu = pkt->req->contextId();
-Addr index = daddr >> Regs::VirtualShift;
-Addr raddr = daddr & Regs::VirtualMask;
+Addr index = daddr >> registers::VirtualShift;
+Addr raddr = daddr & registers::VirtualMask;

 if (!regValid(raddr))
 panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d",
   cpu, index, daddr, pkt->getAddr(), pkt->getSize());

-const Regs::Info  = regInfo(raddr);
+const registers::Info  = regInfo(raddr);
 if (!info.read)
 panic("read %s (write only): "
   "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
@@ -241,7 +241,7 @@

 // reading the interrupt status register has the side effect of
 // clearing it
-if (raddr == Regs::IntrStatus)
+if (raddr == registers::IntrStatus)
 devIntrClear();

 return pioDelay;
@@ -256,7 +256,7 @@
 if (!regValid(daddr))
 panic("invalid address: da=%#x", daddr);

-const Regs::Info  = regInfo(daddr);
+const registers::Info  = regInfo(daddr);
 if (!info.read)
 panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu,  
daddr);


@@ -290,14 +290,14 @@
 daddr -= BARs[0]->addr();

 ContextID cpu = pkt->req->contextId();
-Addr index = daddr >> Regs::VirtualShift;
-Addr raddr = daddr & Regs::VirtualMask;
+Addr index = daddr >> registers::VirtualShift;
+Addr raddr = daddr & registers::VirtualMask;

 if (!regValid(raddr))
 panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
 cpu, daddr, pkt->getAddr(), pkt->getSize());

-const Regs::Info  = regInfo(raddr);
+const registers::Info  = regInfo(raddr);
 if (!info.write)
 panic("write %s (read only): "
   "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
@@ -319,34 +319,34 @@
 prepareWrite(cpu, index);

 switch (raddr) {
-  case Regs::Config:
+  case registers::Config:
 changeConfig(pkt->getLE());
 break;

-  case Regs::Command:
+  case registers::Command:
 command(pkt->getLE());
 break;

-  case Regs::IntrStatus:
+  case registers::IntrStatus:
 devIntrClear(regs.IntrStatus &
 pkt->getLE());
 break;

-  case Regs::IntrMask:
+  case registers::IntrMask:
 devIntrChangeMask(pkt->getLE());
 break;

-  case Regs::RxData:
-if (Regs::get_RxDone_Busy(vnic.RxDone))
+  case registers::RxData:
+if (registers::get_RxDone_Busy(vnic.RxDone))
 panic("receive machine busy with another request! rxState=%s",
   RxStateStrings[rxState]);

 vnic.rxUnique = rxUnique++;
-vnic.RxDone = Regs::RxDone_Busy;
+vnic.RxDone = registers::RxDone_Busy;
 vnic.RxData = pkt->getLE();
 rxBusyCount++;

-if (Regs::get_RxData_Vaddr(pkt->getLE())) {
+if (registers::get_RxData_Vaddr(pkt->getLE())) {
 panic("vtophys not implemented in newmem");
 } else {
 DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d)\n",
@@ -367,15 +367,15 @@
 }
 break;

-  case Regs::TxData:
-if (Regs::get_TxDone_Busy(vnic.TxDone))
+  case registers::TxData:
+if (registers::get_TxDone_Busy(vnic.TxDone))
 panic("transmit machine busy with another request! txState=%s",
   TxStateStrings[txState]);

 vnic.txUnique = txUnique++;
-vnic.TxDone = Regs::TxDone_Busy;
+vnic.TxDone = registers::TxDone_Busy;

- 

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Rename SCMI namespace as scmi

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45392 )


Change subject: dev-arm: Rename SCMI namespace as scmi
..

dev-arm: Rename SCMI namespace as scmi

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::SCMI became ::scmi.

Change-Id: I68f729124079ecce02120577d2b89b25f10bde4a
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45392
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/dev/arm/css/Scmi.py
M src/dev/arm/css/scmi_platform.cc
M src/dev/arm/css/scmi_platform.hh
M src/dev/arm/css/scmi_protocols.cc
M src/dev/arm/css/scmi_protocols.hh
5 files changed, 15 insertions(+), 11 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/css/Scmi.py b/src/dev/arm/css/Scmi.py
index 790806f..b5759cf 100644
--- a/src/dev/arm/css/Scmi.py
+++ b/src/dev/arm/css/Scmi.py
@@ -46,7 +46,7 @@
 """
 type = 'ScmiChannel'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::VirtualChannel"
+cxx_class = "scmi::VirtualChannel"
 shmem_range = Param.AddrRange(
 "Virtual channel's shared memory address range")
 phys_id = Param.Unsigned(4,
@@ -78,7 +78,7 @@
 """
 type = 'ScmiAgentChannel'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::AgentChannel"
+cxx_class = "scmi::AgentChannel"


 class ScmiPlatformChannel(ScmiChannel):
@@ -87,7 +87,7 @@
 """
 type = 'ScmiPlatformChannel'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::PlatformChannel"
+cxx_class = "scmi::PlatformChannel"

 class ScmiCommunication(SimObject):
 """
@@ -98,7 +98,7 @@
 """
 type = 'ScmiCommunication'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::Communication"
+cxx_class = "scmi::Communication"

 agent_channel = Param.ScmiAgentChannel(
 "Agent to Platform channel")
@@ -108,7 +108,7 @@
 class ScmiPlatform(Scp):
 type = 'ScmiPlatform'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::Platform"
+cxx_class = "scmi::Platform"

 comms = VectorParam.ScmiCommunication([],
 "SCMI Communications")
diff --git a/src/dev/arm/css/scmi_platform.cc  
b/src/dev/arm/css/scmi_platform.cc

index 823d225..d9a42da 100644
--- a/src/dev/arm/css/scmi_platform.cc
+++ b/src/dev/arm/css/scmi_platform.cc
@@ -43,7 +43,7 @@
 #include "dev/arm/doorbell.hh"
 #include "mem/packet_access.hh"

-using namespace SCMI;
+using namespace scmi;

 AgentChannel::AgentChannel(const ScmiChannelParams )
   : VirtualChannel(p),
diff --git a/src/dev/arm/css/scmi_platform.hh  
b/src/dev/arm/css/scmi_platform.hh

index 8b23a09..5cd52bc 100644
--- a/src/dev/arm/css/scmi_platform.hh
+++ b/src/dev/arm/css/scmi_platform.hh
@@ -46,7 +46,8 @@

 class Doorbell;

-namespace SCMI
+GEM5_DEPRECATED_NAMESPACE(SCMI, scmi);
+namespace scmi
 {

 class Platform;
@@ -326,6 +327,6 @@
 DmaPort dmaPort;
 };

-} // namespace SCMI
+} // namespace scmi

 #endif // __DEV_ARM_CSS_SCMI_PLATFORM_H__
diff --git a/src/dev/arm/css/scmi_protocols.cc  
b/src/dev/arm/css/scmi_protocols.cc

index dcec68e..61b3174 100644
--- a/src/dev/arm/css/scmi_protocols.cc
+++ b/src/dev/arm/css/scmi_protocols.cc
@@ -40,7 +40,7 @@
 #include "debug/SCMI.hh"
 #include "dev/arm/css/scmi_platform.hh"

-using namespace SCMI;
+using namespace scmi;

 const std::string
 Protocol::name() const
diff --git a/src/dev/arm/css/scmi_protocols.hh  
b/src/dev/arm/css/scmi_protocols.hh

index 041dba2..28d8d6c 100644
--- a/src/dev/arm/css/scmi_protocols.hh
+++ b/src/dev/arm/css/scmi_protocols.hh
@@ -41,7 +41,10 @@
 #include 
 #include 

-namespace SCMI
+#include "base/compiler.hh"
+
+GEM5_DEPRECATED_NAMESPACE(SCMI, scmi);
+namespace scmi
 {

 class Platform;
@@ -148,6 +151,6 @@

 };

-}; // namespace SCMI
+}; // namespace scmi

 #endif



3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45392
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I68f729124079ecce02120577d2b89b25f10bde4a
Gerrit-Change-Number: 45392
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
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[gem5-dev] Change in gem5/gem5[develop]: dev: Rename iGbReg namespace as igbreg

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45391 )


Change subject: dev: Rename iGbReg namespace as igbreg
..

dev: Rename iGbReg namespace as igbreg

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::iGbReg became ::igbreg.

Change-Id: I4b19503c8cda37248667464be0ac4fd9a7bb42d8
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45391
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/i8254xGBe_defs.hh
3 files changed, 18 insertions(+), 17 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 73bea7a..c5affcf 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -52,7 +52,7 @@
 #include "sim/stats.hh"
 #include "sim/system.hh"

-using namespace iGbReg;
+using namespace igbreg;
 using namespace Net;

 IGbE::IGbE(const Params )
@@ -1898,7 +1898,7 @@
 {
 DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n",
 completionEnabled);
-igbe->postInterrupt(iGbReg::IT_TXDW);
+igbe->postInterrupt(igbreg::IT_TXDW);
 if (completionEnabled) {
 descEnd = igbe->regs.tdh();
 DPRINTF(EthernetDesc,
@@ -2365,7 +2365,7 @@
 SERIALIZE_SCALAR(eeOpcode);
 SERIALIZE_SCALAR(eeAddr);
 SERIALIZE_SCALAR(lastInterrupt);
-SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
+SERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);

 rxFifo.serialize("rxfifo", cp);
 txFifo.serialize("txfifo", cp);
@@ -2416,7 +2416,7 @@
 UNSERIALIZE_SCALAR(eeOpcode);
 UNSERIALIZE_SCALAR(eeAddr);
 UNSERIALIZE_SCALAR(lastInterrupt);
-UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
+UNSERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);

 rxFifo.unserialize("rxfifo", cp);
 txFifo.unserialize("txfifo", cp);
diff --git a/src/dev/net/i8254xGBe.hh b/src/dev/net/i8254xGBe.hh
index 6ae0cb3..2677528 100644
--- a/src/dev/net/i8254xGBe.hh
+++ b/src/dev/net/i8254xGBe.hh
@@ -60,12 +60,12 @@
 IGbEInt *etherInt;

 // device registers
-iGbReg::Regs regs;
+igbreg::Regs regs;

 // eeprom data, status and control bits
 int eeOpBits, eeAddrBits, eeDataBits;
 uint8_t eeOpcode, eeAddr;
-uint16_t flash[iGbReg::EEPROM_SIZE];
+uint16_t flash[igbreg::EEPROM_SIZE];

 // packet fifos
 PacketFifo rxFifo;
@@ -95,7 +95,7 @@
 rxDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting RXT interrupt because RDTR timer expired\n");
-postInterrupt(iGbReg::IT_RXT);
+postInterrupt(igbreg::IT_RXT);
 }

 EventFunctionWrapper rdtrEvent;
@@ -105,7 +105,7 @@
 rxDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting RXT interrupt because RADV timer expired\n");
-postInterrupt(iGbReg::IT_RXT);
+postInterrupt(igbreg::IT_RXT);
 }

 EventFunctionWrapper radvEvent;
@@ -115,7 +115,7 @@
 txDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting TXDW interrupt because TADV timer expired\n");
-postInterrupt(iGbReg::IT_TXDW);
+postInterrupt(igbreg::IT_TXDW);
 }

 EventFunctionWrapper tadvEvent;
@@ -125,7 +125,7 @@
 txDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting TXDW interrupt because TIDV timer expired\n");
-postInterrupt(iGbReg::IT_TXDW);
+postInterrupt(igbreg::IT_TXDW);
 }
 EventFunctionWrapper tidvEvent;

@@ -145,7 +145,7 @@
  * @param t the type of interrupt we are posting
  * @param now should we ignore the interrupt limiting timer
  */
-void postInterrupt(iGbReg::IntTypes t, bool now = false);
+void postInterrupt(igbreg::IntTypes t, bool now = false);

 /** Check and see if changes to the mask register have caused an  
interrupt

  * to need to be sent or perhaps removed an interrupt cause.
@@ -299,7 +299,7 @@
 };


-class RxDescCache : public DescCache
+class RxDescCache : public DescCache
 {
   protected:
 Addr descBase() const override { return igbe->regs.rdba(); }
@@ -360,7 +360,7 @@

 RxDescCache rxDescCache;

-class TxDescCache  : public DescCache
+class TxDescCache  : public DescCache
 {
   protected:
 Addr descBase() const override { return igbe->regs.tdba(); }
@@ -418,7 +418,7 @@
 unsigned
 descInBlock(unsigned num_desc)
 {
-return num_desc / igbe->cacheBlockSize() /  
sizeof(iGbReg::TxDesc);
+return num_desc / igbe->cacheBlockSize() /  
sizeof(igbreg::TxDesc);

 }

 /** Ask if the packet has been 

[gem5-dev] Change in gem5/gem5[develop]: base: Add macros to deprecate namespaces and classes

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45246 )


Change subject: base: Add macros to deprecate namespaces and classes
..

base: Add macros to deprecate namespaces and classes

The GEM5_DEPRECATED_NAMESPACE macro temporarily declares
a namespace with the deprecated name that prints a
warning message when used. It also make sure that when
the old namespace name is used the new name is referenced.

The GEM5_DEPRECATED_CLASS macro deprecates classes that
were renamed, or moved to different namespaces.

Attributes in namespaces are an issue, though.
- Clang only allows from version 6 on, and only when
  using C++17.
- GCC has a bug before version 10 where the deprecated
  attribute was not properly recognized in namespaces:
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79817

Possible solutions for GCC < 10:
1)
\#define GEM5_DEPRECATED_NAMESPACE() \
namespace gem5 { namespace deprecated { \
auto namespace_##old_namespace = [](){ \
GEM5_DEPRECATED("Please use the new namespace: '" \
  \#new_namespace "'") \
int old_namespace; \
return old_namespace; \
}; \
}} \
namespace new_namespace {} \
namespace old_namespace { \
using namespace new_namespace; \
}

Add the above macro to all headers that previously
declared the deprecated namespace to trigger a
warning. This is extremely inconvenient because
every file that includes that header will trigger
the deprecation warning, so the compilation output
gets VERY clogged.
2)  Similar to 1), but do not use the temporary variable
on declaration. This would require using the variable
somewhere else, like a respective .c file. This is
not always possible, so we could resort to adding a
special file (e.g., base/deprecated_elements.cc)
containing all uses of the deprecated temporary
variables.
3)
\#define GEM5_DEPRECATED_NAMESPACE(old_ns, new_ns) \
namespace old_ns = new_ns;
Similar to 3), but simply declare an alias in the
header files (see above macro) to maintain backwards
compatibility. Then use the special file to declare
all deprecation messages.
4)
Rely on release notes / e-mail to the mailing list
to inform that those are deprecated.

We have selected option 4 for these problematic instances.

Checking if namespace deprecation is possible is done
through scons.

Jira issues:
https://gem5.atlassian.net/browse/GEM5-975
https://gem5.atlassian.net/browse/GEM5-991

Change-Id: Ide234f6a8707d88a869fa843bf8c61ca7714e4f3
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45246
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/SConsopts
M src/base/compiler.hh
2 files changed, 39 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/SConsopts b/src/base/SConsopts
index 9b301c3..ea11bd4 100644
--- a/src/base/SConsopts
+++ b/src/base/SConsopts
@@ -56,10 +56,20 @@
 # alternative stacks.
 conf.env['HAVE_VALGRIND'] = conf.CheckCHeader('valgrind/valgrind.h')

+conf.env['HAVE_DEPRECATED_NAMESPACE'] = conf.TryCompile('''
+int main() {return 0;}
+namespace [[gnu::deprecated("Test namespace deprecation")]]
+test_deprecated_namespace {}
+''', '.cc')
+if not conf.env['HAVE_DEPRECATED_NAMESPACE']:
+warning("Deprecated namespaces are not supported by this  
compiler.\n"
+"Please make sure to check the mailing list for  
deprecation "

+"announcements.")

 sticky_vars.Add(BoolVariable('USE_POSIX_CLOCK', 'Use POSIX Clocks',
  have_posix_clock))


 export_vars.extend([
-'HAVE_FENV', 'HAVE_PNG', 'USE_POSIX_CLOCK', 'HAVE_VALGRIND'])
+'HAVE_FENV', 'HAVE_PNG', 'USE_POSIX_CLOCK', 'HAVE_VALGRIND',
+'HAVE_DEPRECATED_NAMESPACE'])
diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 17124be..8fd3808 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -43,6 +43,8 @@

 #include 

+#include "config/have_deprecated_namespace.hh"
+
 // http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html


@@ -138,6 +140,32 @@
 #  define GEM5_DEPRECATED_MACRO_STMT(name, definition, message) \
  do {{definition;} GEM5_DEPRECATED_MACRO(name, {}, message);} while (0)

+// To mark a class as deprecated in favor of a new name, add a respective
+// instance of this macro to the file that used to declare the old name.
+// This macro should be used *after* the new class has been defined.
+#  define GEM5_DEPRECATED_CLASS(old_class, new_class) \
+using old_class \
+GEM5_DEPRECATED("Please use the new class name: '" #new_class "'")  
= \

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename CopyEngineReg namespace as copy_engine_reg

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45387 )


Change subject: dev: Rename CopyEngineReg namespace as copy_engine_reg
..

dev: Rename CopyEngineReg namespace as copy_engine_reg

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::CopyEngineReg became ::copy_engine_reg.

Change-Id: I8ac5ff272ab6a663a25f245c48827c7ff1b6abc5
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45387
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/pci/copy_engine_defs.hh
3 files changed, 9 insertions(+), 7 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc
index 82a2909..74a4dab 100644
--- a/src/dev/pci/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -56,7 +56,7 @@
 #include "sim/stats.hh"
 #include "sim/system.hh"

-using namespace CopyEngineReg;
+using namespace copy_engine_reg;

 CopyEngine::CopyEngine(const Params )
 : PciDevice(p),
diff --git a/src/dev/pci/copy_engine.hh b/src/dev/pci/copy_engine.hh
index 4a5aca6..59f6e39 100644
--- a/src/dev/pci/copy_engine.hh
+++ b/src/dev/pci/copy_engine.hh
@@ -62,9 +62,9 @@
   private:
 DmaPort cePort;
 CopyEngine *ce;
-CopyEngineReg::ChanRegs  cr;
+copy_engine_reg::ChanRegs  cr;
 int channelId;
-CopyEngineReg::DmaDesc *curDmaDesc;
+copy_engine_reg::DmaDesc *curDmaDesc;
 uint8_t *copyBuffer;

 bool busy;
@@ -149,7 +149,7 @@
 } copyEngineStats;

 // device registers
-CopyEngineReg::Regs regs;
+copy_engine_reg::Regs regs;

 // Array of channels each one with regs/dma port/etc
 std::vector chan;
diff --git a/src/dev/pci/copy_engine_defs.hh  
b/src/dev/pci/copy_engine_defs.hh

index 6ac8b48..6fdcd6d 100644
--- a/src/dev/pci/copy_engine_defs.hh
+++ b/src/dev/pci/copy_engine_defs.hh
@@ -30,10 +30,12 @@
  * Register and structure descriptions for Intel's I/O AT DMA Engine
  */
 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "sim/serialize.hh"

-namespace CopyEngineReg {
-
+GEM5_DEPRECATED_NAMESPACE(CopyEngineReg, copy_engine_reg);
+namespace copy_engine_reg
+{

 // General Channel independant registers, 128 bytes starting at 0x00
 const uint32_t GEN_CHANCOUNT= 0x00;
@@ -232,6 +234,6 @@

 };

-} // namespace CopyEngineReg
+} // namespace copy_engine_reg





3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8ac5ff272ab6a663a25f245c48827c7ff1b6abc5
Gerrit-Change-Number: 45387
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Rename ps2 variables as ps2Device

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45389 )


Change subject: dev: Rename ps2 variables as ps2Device
..

dev: Rename ps2 variables as ps2Device

Pave the way for a ps2 namespace.

Change-Id: I61fa33c57aee3e7c6df02a364420e4f83901f60b
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45389
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Gabe Black 
Maintainer: Bobby R. Bruce 
---
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
2 files changed, 7 insertions(+), 7 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 18fb1f1..4f0541e 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -51,9 +51,9 @@
 Pl050::Pl050(const Pl050Params )
 : AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
   rawInterrupts(0),
-  ps2(p.ps2)
+  ps2Device(p.ps2)
 {
-ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
+ps2Device->hostRegDataAvailable([this]() { this->updateRxInt(); });
 }

 Tick
@@ -72,13 +72,13 @@
 break;

   case kmiStat:
-status.rxfull = ps2->hostDataAvailable() ? 1 : 0;
+status.rxfull = ps2Device->hostDataAvailable() ? 1 : 0;
 DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status);
 data = status;
 break;

   case kmiData:
-data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
+data = ps2Device->hostDataAvailable() ? ps2Device->hostRead() : 0;
 updateRxInt();
 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
 break;
@@ -134,7 +134,7 @@
 DPRINTF(Pl050, "Write Data: %#x\n", data);
 // Clear the TX interrupt before writing new data.
 setTxInt(false);
-ps2->hostWrite((uint8_t)data);
+ps2Device->hostWrite((uint8_t)data);
 // Data is written in 0 time, so raise the TX interrupt again.
 setTxInt(true);
 break;
@@ -167,7 +167,7 @@
 {
 InterruptReg ints = rawInterrupts;

-ints.rx = ps2->hostDataAvailable() ? 1 : 0;
+ints.rx = ps2Device->hostDataAvailable() ? 1 : 0;

 setInterrupts(ints);
 }
diff --git a/src/dev/arm/kmi.hh b/src/dev/arm/kmi.hh
index 2d83c13..03e9dbd 100644
--- a/src/dev/arm/kmi.hh
+++ b/src/dev/arm/kmi.hh
@@ -123,7 +123,7 @@
 InterruptReg getInterrupt() const;

 /** PS2 device connected to this KMI interface */
-PS2Device *ps2;
+PS2Device *ps2Device;

   public:
 Pl050(const Pl050Params );



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I61fa33c57aee3e7c6df02a364420e4f83901f60b
Gerrit-Change-Number: 45389
Gerrit-PatchSet: 5
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Stop using the DmaPort in the TableWalker

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45599 )


Change subject: arch-arm: Stop using the DmaPort in the TableWalker
..

arch-arm: Stop using the DmaPort in the TableWalker

Using a custom TableWalker port instead

Signed-off-by: Giacomo Travaglini 
Change-Id: I9e77324569ef0f74f6c8a3941f90bc988abf3c57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45599
Reviewed-by: Andreas Sandberg 
Reviewed-by: Daniel Carvalho 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
5 files changed, 173 insertions(+), 35 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index a741537..0071bd8 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -48,8 +48,8 @@

 Stage2MMU::Stage2MMU(const Params )
 : SimObject(p), _stage1Tlb(p.tlb), _stage2Tlb(p.stage2_tlb),
-  port(_stage1Tlb->getTableWalker(), p.sys),
-  requestorId(p.sys->getRequestorId(_stage1Tlb->getTableWalker()))
+  requestorId(p.sys->getRequestorId(_stage1Tlb->getTableWalker())),
+  port(_stage1Tlb->getTableWalker(), requestorId)
 {
 // we use the stage-one table walker as the parent of the port,
 // and to get our requestor id, this is done to keep things
@@ -131,9 +131,10 @@
 }

 if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
-parent.getDMAPort().dmaAction(
-MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
-tc->getCpuPtr()->clockPeriod(), req->getFlags());
+TableWalker::Port  = parent.getTableWalkerPort();
+port.sendTimingReq(
+req->getPaddr(), numBytes, data, req->getFlags(),
+tc->getCpuPtr()->clockPeriod(), event);
 } else {
 // We can't do the DMA access as there's been a problem, so tell  
the

 // event we're done
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index c416b15..ebf6820 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -39,8 +39,8 @@
 #define __ARCH_ARM_STAGE2_MMU_HH__

 #include "arch/arm/faults.hh"
+#include "arch/arm/table_walker.hh"
 #include "arch/arm/tlb.hh"
-#include "dev/dma_device.hh"
 #include "mem/request.hh"
 #include "params/ArmStage2MMU.hh"
 #include "sim/eventq.hh"
@@ -55,13 +55,12 @@
 TLB *_stage2Tlb;

   protected:
-
-/** Port to issue translation requests from */
-DmaPort port;
-
 /** Request id for requests generated by this MMU */
 RequestorID requestorId;

+/** Port to issue translation requests from */
+TableWalker::Port port;
+
   public:
 /** This translation class is used to trigger the data fetch once a  
timing

 translation returns the translated physical address */
@@ -109,7 +108,7 @@
  * is used by the two table walkers, and is exposed externally and
  * connected through the stage-one table walker.
  */
-DmaPort& getDMAPort() { return port; }
+TableWalker::Port& getTableWalkerPort() { return port; }

 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
 uint8_t *data, int numBytes, Request::Flags flags, bool  
isFunctional);

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 2452ebc..e135cb8 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2019 ARM Limited
+ * Copyright (c) 2010, 2012-2019, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -36,6 +36,7 @@
  */
 #include "arch/arm/table_walker.hh"

+#include 
 #include 

 #include "arch/arm/faults.hh"
@@ -50,7 +51,6 @@
 #include "debug/PageTableWalker.hh"
 #include "debug/TLB.hh"
 #include "debug/TLBVerbose.hh"
-#include "dev/dma_device.hh"
 #include "sim/system.hh"

 using namespace ArmISA;
@@ -102,7 +102,7 @@
 TableWalker::setMMU(Stage2MMU *m, RequestorID requestor_id)
 {
 stage2Mmu = m;
-port = >getDMAPort();
+port = >getTableWalkerPort();
 requestorId = requestor_id;
 }

@@ -143,6 +143,107 @@
 {
 }

[gem5-dev] Change in gem5/gem5[develop]: arch: Make MMU::flushAll virtual

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45779 )


Change subject: arch: Make MMU::flushAll virtual
..

arch: Make MMU::flushAll virtual

This is enabling ISA specific MMUs to reimplement the flushing
according to their TLB structure

Change-Id: Ic407ab95137b299206cb94926fb69d8898ed33f8
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45779
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/generic/mmu.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh
index 79e53dc..d7c048c 100644
--- a/src/arch/generic/mmu.hh
+++ b/src/arch/generic/mmu.hh
@@ -61,7 +61,7 @@
 }

   public:
-void
+virtual void
 flushAll()
 {
 dtb->flushAll();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic407ab95137b299206cb94926fb69d8898ed33f8
Gerrit-Change-Number: 45779
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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