date:20210618

[gem5-dev] Change in gem5/gem5[develop]: base,tests: Fix trace.test.cc for .fast

2021-06-18 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46959 )


Change subject: base,tests: Fix trace.test.cc for .fast
..

base,tests: Fix trace.test.cc for .fast

Due to DPRINTFs compiling in all cases:
https://gem5-review.googlesource.com/c/public/gem5/+/44988,
trace.test.cc failed to compile for the .fast build (`scons
build/NULL/unittests.fast`). This patch fixes this by moving the
DPRINTFs into the `TRACING_ON` compile guards.

Change-Id: Ib37b2d90f19b9dbc1503941d69d5a2dc0c1c9d9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46959
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/trace.test.cc
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/trace.test.cc b/src/base/trace.test.cc
index beefbe4..45e6f6c 100644
--- a/src/base/trace.test.cc
+++ b/src/base/trace.test.cc
@@ -491,19 +491,19 @@
 Trace::enable();
 EXPECT_TRUE(Debug::changeFlag("TraceTestDebugFlag", true));
 EXPECT_TRUE(Debug::changeFlag("FmtFlag", true));
-DPRINTFS(TraceTestDebugFlag, named_ptr, "Test message");
 #if TRACING_ON
+DPRINTFS(TraceTestDebugFlag, named_ptr, "Test message");
 ASSERT_EQ(getString(Trace::output()),
 "  0: TraceTestDebugFlag: Foo: Test message");
-#else
-ASSERT_EQ(getString(Trace::output()), "");
 #endif

 // Flag disabled
 Trace::disable();
 EXPECT_TRUE(Debug::changeFlag("TraceTestDebugFlag", false));
+#if TRACING_ON
 DPRINTFS(TraceTestDebugFlag, named_ptr, "Test message");
 ASSERT_EQ(getString(Trace::output()), "");
+#endif
 }

 /** Test DPRINTFR with tracing on. */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib37b2d90f19b9dbc1503941d69d5a2dc0c1c9d9b
Gerrit-Change-Number: 46959
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: add MSHR debuging stats

2021-06-18 Thread Tom Rollet (Gerrit) via gem5-dev

Tom Rollet has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46979 )



Change subject: mem: add MSHR debuging stats
..

mem: add MSHR debuging stats

MSHR does not have debug stat.

This commit adds 2 debug flags: MSHREntries and MSHRTargets.

MSHREntries only print the number of used MSHR on
allocation/deallocation of a MSHR.

MSHRTargets is way more verbose and for each allocated/ deallocated
target, it will print all informations about the added/removed target
but also on the MSHR.

In further patches, more information could be added for MSHRTargets,
especially for debugging the interaction between regular targets
and deferred ones.

Change-Id: If9943b9ea57e351060824521f9e25192ab25403a
---
M src/mem/cache/SConscript
M src/mem/cache/base.cc
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
6 files changed, 74 insertions(+), 10 deletions(-)



diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index f07a918..2d3d245 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -47,9 +47,14 @@
 DebugFlag('CacheVerbose')
 DebugFlag('HWPrefetch')

+DebugFlag('MSHREntries')
+DebugFlag('MSHRTargets')
+
+
 # CacheTags is so outrageously verbose, printing the cache's entire tag
 # array on each timing access, that you should probably have to ask for
 # it explicitly even above and beyond CacheAll.
 CompoundFlag('CacheAll', ['Cache', 'CacheComp', 'CachePort', 'CacheRepl',
-  'CacheVerbose', 'HWPrefetch'])
+  'CacheVerbose', 'HWPrefetch',
+  'MSHREntries', 'MSHRTargets'])

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 928c30b..4aa4f30 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -76,7 +76,7 @@
 : ClockedObject(p),
   cpuSidePort (p.name + ".cpu_side_port", this, "CpuSidePort"),
   memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),
-  mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve), // see below
+  mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve, p.name),
   writeBuffer("write buffer", p.write_buffers, p.mshrs), // see below
   tags(p.tags),
   compressor(p.compressor),
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 9dae03d..481a66f 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -53,6 +53,8 @@
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "debug/Cache.hh"
+#include "debug/MSHREntries.hh"
+#include "debug/MSHRTargets.hh"
 #include "mem/cache/base.hh"
 #include "mem/request.hh"
 #include "sim/core.hh"
@@ -317,6 +319,8 @@

 // All targets must refer to the same block
 assert(target->matchBlockAddr(targets.front().pkt, blkSize));
+
+DPRINTF(MSHRTargets, "New target allocated %s", print());
 }


@@ -406,6 +410,8 @@
 targets.add(pkt, whenReady, _order, Target::FromCPU, !inService,
 alloc_on_fill);
 }
+
+DPRINTF(MSHRTargets, "New target allocated %s", print());
 }

 bool
@@ -714,12 +720,12 @@
  hasFromCache() ? "HasFromCache" : "");

 if (!targets.empty()) {
-ccprintf(os, "%s  Targets:\n", prefix);
-targets.print(os, verbosity, prefix + "");
+ccprintf(os, "%s  Targets:\n", prefix);
+targets.print(os, verbosity, prefix + "");
 }
 if (!deferredTargets.empty()) {
-ccprintf(os, "%s  Deferred Targets:\n", prefix);
-deferredTargets.print(os, verbosity, prefix + "  ");
+ccprintf(os, "%s  Deferred Targets:\n", prefix);
+deferredTargets.print(os, verbosity, prefix + "  ");
 }
 }

@@ -731,6 +737,12 @@
 return str.str();
 }

+std::string
+MSHR::name() const
+{
+return cacheName;
+}
+
 bool
 MSHR::matchBlockAddr(const Addr addr, const bool is_secure) const
 {
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 306b5ac..3931caa 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -53,7 +53,9 @@
 #include 

 #include "base/printable.hh"
+#include "base/trace.hh"
 #include "base/types.hh"
+#include "debug/MSHRTargets.hh"
 #include "mem/cache/queue_entry.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
@@ -460,6 +462,8 @@
  */
 void popTarget()
 {
+DPRINTF(MSHRTargets, "Force deallocate MSHR target: %s\n",
+targets.front().pkt->print());
 targets.pop_front();
 }

@@ -502,6 +506,10 @@
 void print(std::ostream ,
int verbosity = 0,
const std::string  = "") const override;
+
+std::string cacheName;
+std::string name() const;
+
 /**
  * A no-args wrapper of print(std::ostream...)  meant to be
  * invoked from DPRINTFs avoiding string overheads in fast mode
diff --git a/src/mem/cache/mshr_queue.cc

[gem5-dev] Build failed in Jenkins: weekly #31

2021-06-18 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[Giacomo Travaglini] cpu: Implement basic HTM capabilities in the CheckerCPU

[matthew.poremba] mem-ruby,sim: Add support for VGA ROM memory region

[matthew.poremba] dev-amdgpu: Implement MMIO trace reader

[matthew.poremba] dev-amdgpu,configs: checkpoint before MMIOs

[matthew.poremba] util: Add scripts to recreate amdgpu ROM and MMIOs

[matthew.poremba] dev-amdgpu: Handle framebuffer counter accesses

[odanrc] util: Fix typo in cpt upgrader

[byrakocalan99] mem-cache: queued prefetcher bug fix

[matthew.poremba] sim,mem-ruby: Handle interleaved device memory

[odanrc] sim,util: Remove event dependencies from serialize.hh

[odanrc] sim: Remove (UN)SERIALIZE_OBJ_PTR

[odanrc] sim: Remove SimObject dependency from serialize.hh

[odanrc] sim: Make IniFile non-pointer in CheckpointIn

[odanrc] base: Add unit test for base/trace.hh

[odanrc] sim: Add unit test for sim/port

[odanrc] sim: Add missing compiler include

[odanrc] base: Make Named::name() virtual

[odanrc] base: Make Named::name() non-reference

[odanrc] sim: Make SimObject inherit from Named

[odanrc] sim: Remove SimObject dependency from Drainable

[odanrc] base-stats: Remove SimObject dependency from stats group

[odanrc] base-stats: Remove Stats::Group dependency from Stats::Info

[odanrc] base-stats: Fix self addition bug in addStatGroup

[odanrc] base-stats: Fix null addStatGroup

[odanrc] base: Document the SymbolTable

[odanrc] base-stats,mem: Fix empty Stats::Info names


--
[...truncated 577.54 KB...]
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron.cc -> .o
 [SOPARMHH] MultiperspectivePerceptron8KB -> 
GCN3_X86/params/MultiperspectivePerceptron8KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_8KB.cc -> .o
 [SOPARMHH] MultiperspectivePerceptron64KB -> 
GCN3_X86/params/MultiperspectivePerceptron64KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_64KB.cc -> .o
 [SOPARMHH] MPP_LoopPredictor -> GCN3_X86/params/MPP_LoopPredictor.hh
 [SOPARMHH] MPP_StatisticalCorrector -> 
GCN3_X86/params/MPP_StatisticalCorrector.hh
 [SOPARMHH] MPP_TAGE -> GCN3_X86/params/MPP_TAGE.hh
 [SOPARMHH] MultiperspectivePerceptronTAGE -> 
GCN3_X86/params/MultiperspectivePerceptronTAGE.hh
 [SOPARMHH] StatisticalCorrector -> GCN3_X86/params/StatisticalCorrector.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_tage.cc -> .o
 [SOPARMHH] MPP_LoopPredictor_8KB -> GCN3_X86/params/MPP_LoopPredictor_8KB.hh
 [SOPARMHH] MPP_StatisticalCorrector_8KB -> 
GCN3_X86/params/MPP_StatisticalCorrector_8KB.hh
 [SOPARMHH] MPP_TAGE_8KB -> GCN3_X86/params/MPP_TAGE_8KB.hh
 [SOPARMHH] MultiperspectivePerceptronTAGE8KB -> 
GCN3_X86/params/MultiperspectivePerceptronTAGE8KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_tage_8KB.cc -> .o
 [SOPARMHH] MPP_StatisticalCorrector_64KB -> 
GCN3_X86/params/MPP_StatisticalCorrector_64KB.hh
 [SOPARMHH] MultiperspectivePerceptronTAGE64KB -> 
GCN3_X86/params/MultiperspectivePerceptronTAGE64KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_tage_64KB.cc -> .o
 [ CXX] GCN3_X86/cpu/pred/statistical_corrector.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/TageSCL.hh
 [SOPARMHH] TAGE_SC_L -> GCN3_X86/params/TAGE_SC_L.hh
 [SOPARMHH] TAGE_SC_L_LoopPredictor -> 
GCN3_X86/params/TAGE_SC_L_LoopPredictor.hh
 [SOPARMHH] TAGE_SC_L_TAGE -> GCN3_X86/params/TAGE_SC_L_TAGE.hh
 [ CXX] GCN3_X86/cpu/pred/tage_sc_l.cc -> .o
 [SOPARMHH] TAGE_SC_L_8KB -> GCN3_X86/params/TAGE_SC_L_8KB.hh
 [SOPARMHH] TAGE_SC_L_8KB_StatisticalCorrector -> 
GCN3_X86/params/TAGE_SC_L_8KB_StatisticalCorrector.hh
 [SOPARMHH] TAGE_SC_L_TAGE_8KB -> GCN3_X86/params/TAGE_SC_L_TAGE_8KB.hh
 [ CXX] GCN3_X86/cpu/pred/tage_sc_l_8KB.cc -> .o
 [SOPARMHH] TAGE_SC_L_64KB -> GCN3_X86/params/TAGE_SC_L_64KB.hh
 [SOPARMHH] TAGE_SC_L_64KB_StatisticalCorrector -> 
GCN3_X86/params/TAGE_SC_L_64KB_StatisticalCorrector.hh
 [SOPARMHH] TAGE_SC_L_TAGE_64KB -> GCN3_X86/params/TAGE_SC_L_TAGE_64KB.hh
 [ CXX] GCN3_X86/cpu/pred/tage_sc_l_64KB.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/address_manager.cc -> .o
 [SOPARMHH] ProtocolTester -> GCN3_X86/params/ProtocolTester.hh
 [SOPARMHH] CpuThread -> GCN3_X86/params/CpuThread.hh
 [SOPARMHH] DmaThread -> GCN3_X86/params/DmaThread.hh
 [SOPARMHH] GpuWavefront -> GCN3_X86/params/GpuWavefront.hh
 [SOPARMHH] TesterThread -> GCN3_X86/params/TesterThread.hh
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/episode.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/ProtocolTest.hh
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/protocol_tester.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/cpu_thread.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/dma_thread.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/gpu_wavefront.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/tester_thread.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/GarnetSyntheticTraffic.hh
 [SOPARMHH]

[gem5-dev] Change in gem5/gem5[develop]: base,tests: Fix trace.test.cc for .fast

[gem5-dev] Change in gem5/gem5[develop]: mem: add MSHR debuging stats

[gem5-dev] Build failed in Jenkins: weekly #31

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