[gem5-dev] Re: gem5 namespace
Dear all,
We have already renamed most of the existing namespaces to snake case. Before
moving on to the last ones, which may generate more conflicts, I have
encapsulated most of gem5 in a gem5 namespace. This will ensure that these last
- and possibly most likely to generate conflicts - renames generate less
issues. The respective chain can be found in
https://gem5-review.googlesource.com/c/public/gem5/+/46323/4 .
The approach taken to implement the gem5 namespace was not ideal, since it is a
huge dump on the whole project instead of a per-dir approach; however, it was a
trade-off between number of rebasing conflicts that I would have to deal with,
and the time I had available for this project. To make it at least a bit
reviewable, I have split it into sub-patches with common approaches. These
patches will be squashed as soon as they are approved.
Finally, every time I do a git push, many conflicts pop up. This requires a lot
of effort to support, and processing power to recompile everything and make
sure everything still works (I don't currently have the latter). Also, the next
version is on the corner, and it would be great to deliver the gem5 namespace
with it. Therefore, I would like to get these changes in ASAP. When problems
show up - and they will - they can be more easily fixed, since this change is
trivial - one will most likely just need to add a "namespace gem5 {" to a
specific file that is compiled in a specific simulation configuration.
tl;dr: Could you review the namespace patches so that we can try to get them in
for the next version?
Regards,Daniel
Em sexta-feira, 7 de maio de 2021 02:30:13 BRT, Gabe Black via gem5-dev
escreveu:
Be warned though, that there are some pitfalls with this namespace deprecation
approach. The namespaces here are not actually equivalent, and so the old
deprecated namespace can have things added to it that won't show up in the new
one. This is probably not that big a deal in practice, and should be pretty
useful letting people know what's going on, but it's still important to be
aware of limitations.
Gabe
On Thu, May 6, 2021 at 7:36 AM Jason Lowe-Power via gem5-dev
wrote:
Thanks for putting this all together, Daniel!
IMO, we should do our best with providing deprecation notices, but not bend
over backwards. For things that are easy to add deprecations to (e.g., function
names / class names) we should do it, and for things that have a big impact on
our users we should provide the warnings. However, if it's very difficult to
provide the notice *and* if it's for something that is unlikely to affect
users, then the deprecation warnings are less important.
Example: if we change `panic` to `gem5_panic` (or `GEM5_PANIC`?) we definitely
need a deprecation warning. This will significantly impact users. If, on the
other hand, we change a macro that is used in exactly one place, it's probably
less important
Thanks for coming up with a way to do namespaces! This will be useful.
Cheers,Jason
On Thu, May 6, 2021 at 7:06 AM Daniel Carvalho via gem5-dev
wrote:
Glad to see that we are reaching a consensus! Then we will create the "gem5"
namespace, rename (most) macros to use a "GEM5_" prefix, and will rename all
namespaces to snake case.
I agree that we should do the renaming on a case-by-case basis. I've created a
new Jira Epic to cover converting all namespaces to snake case:
https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-974 .
Regarding deprecating namespaces, aliases cannot be assigned attributes (thus
they cannot be marked as deprecated), but I believe this will do the trick:
#define GEM5_DEPRECATE_NAMESPACE(old_namespace, new_namespace) \
namespace [[gnu::deprecated("Please use the new namespace: '" \
#new_namespace "'")]] old_namespace { \
using namespace new_namespace; \
}
Example:
// Suppose we want to rename a namespace from Test to test
namespace test { int var;
} // This can be added to the base file (i.e., the one we know everybody
will include)
GEM5_DEPRECATE_NAMESPACE(Test, test)
...
// In code, somewhere: test::var = 2; // Does not show deprecation
warning
Test::var = 2; // Shows deprecation warning
Cheers,
Daniel
Em quarta-feira, 5 de maio de 2021 23:28:31 BRT, Gabe Black via gem5-dev
escreveu:
Yeah, we don't have a ton of namespaces already, but having two copies of all
of them for a while might be messy. I also don't think you can really mark a
namespace as deprecated without even more macro trickery.
Using snake case for the namespaces would be a change to acclimate to and I'm
not *excited* to make a big change like that, especially to something I'm so
used to, but importantly it would maintain consistency which is arguably more
important. It would bring us in line with namespaces like "std" too, which,
given how common it is, wouldn't be the worst thing.
We would have
[gem5-dev] Change in gem5/gem5[develop]: mem: Adopt the memory namespace in qos files
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47308 )
Change subject: mem: Adopt the memory namespace in qos files
..
mem: Adopt the memory namespace in qos files
Encapsulate everything qos-related in the gem5::memory
namespace.
Change-Id: Ib906ddd6d76b9d4a56f2eb705efe6cd498829155
Issued-on: https://gem5.atlassian.net/browse/GEM5-983
Signed-off-by: Daniel R. Carvalho
---
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/qos/QoSMemCtrl.py
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qos/QoSMemSinkInterface.py
M src/mem/qos/QoSPolicy.py
M src/mem/qos/QoSTurnaround.py
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qos/policy.cc
M src/mem/qos/policy.hh
M src/mem/qos/policy_fixed_prio.cc
M src/mem/qos/policy_fixed_prio.hh
M src/mem/qos/policy_pf.cc
M src/mem/qos/policy_pf.hh
M src/mem/qos/q_policy.cc
M src/mem/qos/q_policy.hh
M src/mem/qos/turnaround_policy.hh
M src/mem/qos/turnaround_policy_ideal.cc
M src/mem/qos/turnaround_policy_ideal.hh
22 files changed, 71 insertions(+), 11 deletions(-)
diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index 132cd3f..0e1c0a6 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -53,7 +53,7 @@
{
MemCtrl::MemCtrl(const MemCtrlParams ) :
-qos::MemCtrl(p),
+memory::qos::MemCtrl(p),
port(name() + ".port", *this), isTimingMode(false),
retryRdReq(false), retryWrReq(false),
nextReqEvent([this]{ processNextReqEvent(); }, name()),
@@ -1395,7 +1395,7 @@
MemCtrl::getPort(const std::string _name, PortID idx)
{
if (if_name != "port") {
-return qos::MemCtrl::getPort(if_name, idx);
+return memory::qos::MemCtrl::getPort(if_name, idx);
} else {
return port;
}
diff --git a/src/mem/mem_ctrl.hh b/src/mem/mem_ctrl.hh
index b78796f..a30fcb3 100644
--- a/src/mem/mem_ctrl.hh
+++ b/src/mem/mem_ctrl.hh
@@ -236,7 +236,7 @@
* please cite the paper.
*
*/
-class MemCtrl : public qos::MemCtrl
+class MemCtrl : public memory::qos::MemCtrl
{
private:
diff --git a/src/mem/qos/QoSMemCtrl.py b/src/mem/qos/QoSMemCtrl.py
index b3391fb..842b62b 100644
--- a/src/mem/qos/QoSMemCtrl.py
+++ b/src/mem/qos/QoSMemCtrl.py
@@ -44,7 +44,7 @@
class QoSMemCtrl(ClockedObject):
type = 'QoSMemCtrl'
cxx_header = "mem/qos/mem_ctrl.hh"
-cxx_class = 'gem5::qos::MemCtrl'
+cxx_class = 'gem5::memory::qos::MemCtrl'
abstract = True
system = Param.System(Parent.any, "System that the controller belongs
to.")
diff --git a/src/mem/qos/QoSMemSinkCtrl.py b/src/mem/qos/QoSMemSinkCtrl.py
index 234d8bc..486e74b 100644
--- a/src/mem/qos/QoSMemSinkCtrl.py
+++ b/src/mem/qos/QoSMemSinkCtrl.py
@@ -42,7 +42,7 @@
class QoSMemSinkCtrl(QoSMemCtrl):
type = 'QoSMemSinkCtrl'
cxx_header = "mem/qos/mem_sink.hh"
-cxx_class = 'gem5::qos::MemSinkCtrl'
+cxx_class = 'gem5::memory::qos::MemSinkCtrl'
port = ResponsePort("Response ports")
diff --git a/src/mem/qos/QoSMemSinkInterface.py
b/src/mem/qos/QoSMemSinkInterface.py
index d493dce..2544df8 100644
--- a/src/mem/qos/QoSMemSinkInterface.py
+++ b/src/mem/qos/QoSMemSinkInterface.py
@@ -38,7 +38,7 @@
class QoSMemSinkInterface(AbstractMemory):
type = 'QoSMemSinkInterface'
cxx_header = "mem/qos/mem_sink.hh"
-cxx_class = 'gem5::qos::MemSinkInterface'
+cxx_class = 'gem5::memory::qos::MemSinkInterface'
def controller(self):
"""
diff --git a/src/mem/qos/QoSPolicy.py b/src/mem/qos/QoSPolicy.py
index fba2e86..99a3f2f 100644
--- a/src/mem/qos/QoSPolicy.py
+++ b/src/mem/qos/QoSPolicy.py
@@ -41,12 +41,12 @@
type = 'QoSPolicy'
abstract = True
cxx_header = "mem/qos/policy.hh"
-cxx_class = 'gem5::qos::Policy'
+cxx_class = 'gem5::memory::qos::Policy'
class QoSFixedPriorityPolicy(QoSPolicy):
type = 'QoSFixedPriorityPolicy'
cxx_header = "mem/qos/policy_fixed_prio.hh"
-cxx_class = 'gem5::qos::FixedPriorityPolicy'
+cxx_class = 'gem5::memory::qos::FixedPriorityPolicy'
cxx_exports = [
PyBindMethod('initRequestorName'),
@@ -90,7 +90,7 @@
class QoSPropFairPolicy(QoSPolicy):
type = 'QoSPropFairPolicy'
cxx_header = "mem/qos/policy_pf.hh"
-cxx_class = 'gem5::qos::PropFairPolicy'
+cxx_class = 'gem5::memory::qos::PropFairPolicy'
cxx_exports = [
PyBindMethod('initRequestorName'),
diff --git a/src/mem/qos/QoSTurnaround.py b/src/mem/qos/QoSTurnaround.py
index c74f5e8..7a8d1e3 100644
--- a/src/mem/qos/QoSTurnaround.py
+++ b/src/mem/qos/QoSTurnaround.py
@@ -39,10 +39,10 @@
class QoSTurnaroundPolicy(SimObject):
type = 'QoSTurnaroundPolicy'
cxx_header = "mem/qos/turnaround_policy.hh"
-cxx_class = 'gem5::qos::TurnaroundPolicy'
+cxx_class = 'gem5::memory::qos::TurnaroundPolicy'
abstract = True
class QoSTurnaroundPolicyIdeal(QoSTurnaroundPolicy):
[gem5-dev] Change in gem5/gem5[develop]: mem: Adopt a memory namespace for memories
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47309 )
Change subject: mem: Adopt a memory namespace for memories
..
mem: Adopt a memory namespace for memories
Encapsulate every class inheriting from Abstract or Physical
memories, and the memory controller in a memory namespace.
Change-Id: I228f7e55efc395089e3616ae0a0a6325867bd782
Issued-on: https://gem5.atlassian.net/browse/GEM5-983
Signed-off-by: Daniel R. Carvalho
---
M src/arch/arm/semihosting.cc
M src/cpu/kvm/vm.cc
M src/cpu/o3/inst_queue.hh
M src/mem/AbstractMemory.py
M src/mem/CfiMemory.py
M src/mem/DRAMInterface.py
M src/mem/DRAMSim2.py
M src/mem/DRAMsim3.py
M src/mem/MemCtrl.py
M src/mem/MemInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/cfi_mem.cc
M src/mem/cfi_mem.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/dramsim2_wrapper.cc
M src/mem/dramsim2_wrapper.hh
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/dramsim3_wrapper.cc
M src/mem/dramsim3_wrapper.hh
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/mem_interface.cc
M src/mem/mem_interface.hh
M src/mem/physical.cc
M src/mem/physical.hh
M src/mem/ruby/system/RubySystem.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/sim/system.cc
M src/sim/system.hh
35 files changed, 115 insertions(+), 24 deletions(-)
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 1f06b51..59ea4aa 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -551,7 +551,7 @@
Addr _base, Addr _limit,
Addr _base, Addr _limit)
{
-const PhysicalMemory = tc->getSystemPtr()->getPhysMem();
+const memory::PhysicalMemory = tc->getSystemPtr()->getPhysMem();
const AddrRangeList memories = phys.getConfAddrRanges();
fatal_if(memories.size() < 1, "No memories reported from System");
warn_if(memories.size() > 1, "Multiple physical memory ranges
available. "
diff --git a/src/cpu/kvm/vm.cc b/src/cpu/kvm/vm.cc
index f1fdeec..cd975ac 100644
--- a/src/cpu/kvm/vm.cc
+++ b/src/cpu/kvm/vm.cc
@@ -50,6 +50,7 @@
#include "cpu/kvm/base.hh"
#include "debug/Kvm.hh"
+#include "mem/physical.hh"
#include "params/KvmVM.hh"
#include "sim/system.hh"
@@ -355,7 +356,7 @@
KvmVM::delayedStartup()
{
assert(system); // set by the system during its construction
-const std::vector (
+const std::vector (
system->getPhysMem().getBackingStore());
DPRINTF(Kvm, "Mapping %i memory region(s)\n", memories.size());
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index b69344a..b2d9303 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -65,7 +65,11 @@
{
struct O3CPUParams;
+
+namespace memory
+{
class MemInterface;
+} // namespace memory
namespace o3
{
@@ -284,7 +288,7 @@
CPU *cpu;
/** Cache interface. */
-MemInterface *dcacheInterface;
+memory::MemInterface *dcacheInterface;
/** Pointer to IEW stage. */
IEW *iewStage;
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 3fe94f3..ed2a02c 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -43,7 +43,7 @@
type = 'AbstractMemory'
abstract = True
cxx_header = "mem/abstract_mem.hh"
-cxx_class = 'gem5::AbstractMemory'
+cxx_class = 'gem5::memory::AbstractMemory'
# A default memory size of 128 MiB (starting at 0) is used to
# simplify the regressions
diff --git a/src/mem/CfiMemory.py b/src/mem/CfiMemory.py
index 6ac539e..aa6b18a 100644
--- a/src/mem/CfiMemory.py
+++ b/src/mem/CfiMemory.py
@@ -43,7 +43,7 @@
class CfiMemory(AbstractMemory):
type = 'CfiMemory'
cxx_header = "mem/cfi_mem.hh"
-cxx_class = 'gem5::CfiMemory'
+cxx_class = 'gem5::memory::CfiMemory'
port = ResponsePort("Response port")
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 91e1540..3f938dd 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -49,7 +49,7 @@
class DRAMInterface(MemInterface):
type = 'DRAMInterface'
cxx_header = "mem/mem_interface.hh"
-cxx_class = 'gem5::DRAMInterface'
+cxx_class = 'gem5::memory::DRAMInterface'
# scheduler page policy
page_policy = Param.PageManage('open_adaptive', "Page management
policy")
diff --git a/src/mem/DRAMSim2.py b/src/mem/DRAMSim2.py
index d6f92ef..11f9b4e 100644
--- a/src/mem/DRAMSim2.py
+++ b/src/mem/DRAMSim2.py
@@ -40,7 +40,7 @@
class DRAMSim2(AbstractMemory):
type = 'DRAMSim2'
cxx_header = "mem/dramsim2.hh"
-cxx_class = 'gem5::DRAMSim2'
+cxx_class = 'gem5::memory::DRAMSim2'
# A single port for now
port = ResponsePort("This port sends responses and receives requests")
diff --git a/src/mem/DRAMsim3.py b/src/mem/DRAMsim3.py
index
[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Add a garnet namespace
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47306 )
Change subject: mem-garnet: Add a garnet namespace
..
mem-garnet: Add a garnet namespace
Add a namespace encapsulating all garnet files.
GarnetSyntheticTraffic, from
cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
has not been added to this namespace.
Change-Id: I5304ad3130100ba325e35e20883ee9286f51a75a
Issued-on: https://gem5.atlassian.net/browse/GEM5-987
Signed-off-by: Daniel R. Carvalho
---
M src/mem/ruby/network/garnet/CommonTypes.hh
M src/mem/ruby/network/garnet/Credit.cc
M src/mem/ruby/network/garnet/Credit.hh
M src/mem/ruby/network/garnet/CreditLink.hh
M src/mem/ruby/network/garnet/CrossbarSwitch.cc
M src/mem/ruby/network/garnet/CrossbarSwitch.hh
M src/mem/ruby/network/garnet/GarnetLink.cc
M src/mem/ruby/network/garnet/GarnetLink.hh
M src/mem/ruby/network/garnet/GarnetLink.py
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/GarnetNetwork.hh
M src/mem/ruby/network/garnet/GarnetNetwork.py
M src/mem/ruby/network/garnet/InputUnit.cc
M src/mem/ruby/network/garnet/InputUnit.hh
M src/mem/ruby/network/garnet/NetworkBridge.cc
M src/mem/ruby/network/garnet/NetworkBridge.hh
M src/mem/ruby/network/garnet/NetworkInterface.cc
M src/mem/ruby/network/garnet/NetworkInterface.hh
M src/mem/ruby/network/garnet/NetworkLink.cc
M src/mem/ruby/network/garnet/NetworkLink.hh
M src/mem/ruby/network/garnet/OutVcState.cc
M src/mem/ruby/network/garnet/OutVcState.hh
M src/mem/ruby/network/garnet/OutputUnit.cc
M src/mem/ruby/network/garnet/OutputUnit.hh
M src/mem/ruby/network/garnet/Router.cc
M src/mem/ruby/network/garnet/Router.hh
M src/mem/ruby/network/garnet/RoutingUnit.cc
M src/mem/ruby/network/garnet/RoutingUnit.hh
M src/mem/ruby/network/garnet/SwitchAllocator.cc
M src/mem/ruby/network/garnet/SwitchAllocator.hh
M src/mem/ruby/network/garnet/VirtualChannel.cc
M src/mem/ruby/network/garnet/VirtualChannel.hh
M src/mem/ruby/network/garnet/flit.cc
M src/mem/ruby/network/garnet/flit.hh
M src/mem/ruby/network/garnet/flitBuffer.cc
M src/mem/ruby/network/garnet/flitBuffer.hh
36 files changed, 149 insertions(+), 10 deletions(-)
diff --git a/src/mem/ruby/network/garnet/CommonTypes.hh
b/src/mem/ruby/network/garnet/CommonTypes.hh
index c0d8af2..c2b8b65 100644
--- a/src/mem/ruby/network/garnet/CommonTypes.hh
+++ b/src/mem/ruby/network/garnet/CommonTypes.hh
@@ -36,6 +36,9 @@
namespace gem5
{
+namespace garnet
+{
+
// All common enums and typedefs go here
enum flit_type {HEAD_, BODY_, TAIL_, HEAD_TAIL_,
@@ -68,6 +71,7 @@
#define INFINITE_ 1
+} // namespace garnet
} // namespace gem5
#endif //__MEM_RUBY_NETWORK_GARNET_0_COMMONTYPES_HH__
diff --git a/src/mem/ruby/network/garnet/Credit.cc
b/src/mem/ruby/network/garnet/Credit.cc
index 5624005..e88faa0 100644
--- a/src/mem/ruby/network/garnet/Credit.cc
+++ b/src/mem/ruby/network/garnet/Credit.cc
@@ -35,6 +35,9 @@
namespace gem5
{
+namespace garnet
+{
+
// Credit Signal for buffers inside VC
// Carries m_vc (inherits from flit.hh)
// and m_is_free_signal (whether VC is free or not)
@@ -83,4 +86,5 @@
out << "]";
}
+} // namespace garnet
} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/Credit.hh
b/src/mem/ruby/network/garnet/Credit.hh
index 2db47d0..98469e1 100644
--- a/src/mem/ruby/network/garnet/Credit.hh
+++ b/src/mem/ruby/network/garnet/Credit.hh
@@ -41,6 +41,9 @@
namespace gem5
{
+namespace garnet
+{
+
// Credit Signal for buffers inside VC
// Carries m_vc (inherits from flit.hh)
// and m_is_free_signal (whether VC is free or not)
@@ -64,6 +67,7 @@
bool m_is_free_signal;
};
+} // namespace garnet
} // namespace gem5
#endif // __MEM_RUBY_NETWORK_GARNET_0_CREDIT_HH__
diff --git a/src/mem/ruby/network/garnet/CreditLink.hh
b/src/mem/ruby/network/garnet/CreditLink.hh
index 96842dc..c85dc4e 100644
--- a/src/mem/ruby/network/garnet/CreditLink.hh
+++ b/src/mem/ruby/network/garnet/CreditLink.hh
@@ -37,6 +37,9 @@
namespace gem5
{
+namespace garnet
+{
+
class CreditLink : public NetworkLink
{
public:
@@ -44,6 +47,7 @@
CreditLink(const Params ) : NetworkLink(p) {}
};
+} // namespace garnet
} // namespace gem5
#endif // __MEM_RUBY_NETWORK_GARNET_0_CREDITLINK_HH__
diff --git a/src/mem/ruby/network/garnet/CrossbarSwitch.cc
b/src/mem/ruby/network/garnet/CrossbarSwitch.cc
index 2e6c29d..d94f728 100644
--- a/src/mem/ruby/network/garnet/CrossbarSwitch.cc
+++ b/src/mem/ruby/network/garnet/CrossbarSwitch.cc
@@ -38,6 +38,9 @@
namespace gem5
{
+namespace garnet
+{
+
CrossbarSwitch::CrossbarSwitch(Router *router)
: Consumer(router), m_router(router), m_num_vcs(m_router->get_num_vcs()),
m_crossbar_activity(0), switchBuffers(0)
@@ -103,4 +106,5 @@
m_crossbar_activity = 0;
}
+} // namespace garnet
} // namespace gem5
diff --git a/src/mem/ruby/network/garnet/CrossbarSwitch.hh
[gem5-dev] Change in gem5/gem5[develop]: cpu: Add a branch_prediction namespace
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47303 )
Change subject: cpu: Add a branch_prediction namespace
..
cpu: Add a branch_prediction namespace
Encapsulate all branch-prediction-related files
in a branch_prediction namespace. This will allow
these files to be renamed to drop the BP suffix.
Issued-on: https://gem5.atlassian.net/browse/GEM5-982
Change-Id: I640c0caa846a3aade6fae95e9a93e4318ae9fca0
Signed-off-by: Daniel R. Carvalho
---
M src/cpu/minor/fetch2.hh
M src/cpu/o3/fetch.hh
M src/cpu/pred/2bit_local.cc
M src/cpu/pred/2bit_local.hh
M src/cpu/pred/BranchPredictor.py
M src/cpu/pred/bi_mode.cc
M src/cpu/pred/bi_mode.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
M src/cpu/pred/btb.cc
M src/cpu/pred/btb.hh
M src/cpu/pred/indirect.hh
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/ltage.cc
M src/cpu/pred/ltage.hh
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
M src/cpu/pred/multiperspective_perceptron_64KB.cc
M src/cpu/pred/multiperspective_perceptron_64KB.hh
M src/cpu/pred/multiperspective_perceptron_8KB.cc
M src/cpu/pred/multiperspective_perceptron_8KB.hh
M src/cpu/pred/multiperspective_perceptron_tage.cc
M src/cpu/pred/multiperspective_perceptron_tage.hh
M src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
M src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
M src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
M src/cpu/pred/ras.cc
M src/cpu/pred/ras.hh
M src/cpu/pred/simple_indirect.cc
M src/cpu/pred/simple_indirect.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage.cc
M src/cpu/pred/tage.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.cc
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/pred/tage_sc_l_8KB.cc
M src/cpu/pred/tage_sc_l_8KB.hh
M src/cpu/pred/tournament.cc
M src/cpu/pred/tournament.hh
M src/cpu/simple/base.hh
47 files changed, 216 insertions(+), 37 deletions(-)
diff --git a/src/cpu/minor/fetch2.hh b/src/cpu/minor/fetch2.hh
index 09b7867..41a7a7f 100644
--- a/src/cpu/minor/fetch2.hh
+++ b/src/cpu/minor/fetch2.hh
@@ -93,7 +93,7 @@
bool processMoreThanOneInput;
/** Branch predictor passed from Python configuration */
-BPredUnit
+branch_prediction::BPredUnit
public:
/* Public so that Pipeline can pass it to Fetch1 */
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index b543709..c0ba0d0 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -410,7 +410,7 @@
TimeBuffer::wire toDecode;
/** BPredUnit. */
-BPredUnit *branchPred;
+branch_prediction::BPredUnit *branchPred;
TheISA::PCState pc[MaxThreads];
diff --git a/src/cpu/pred/2bit_local.cc b/src/cpu/pred/2bit_local.cc
index 61ce776..c9aa714 100644
--- a/src/cpu/pred/2bit_local.cc
+++ b/src/cpu/pred/2bit_local.cc
@@ -36,6 +36,9 @@
namespace gem5
{
+namespace branch_prediction
+{
+
LocalBP::LocalBP(const LocalBPParams )
: BPredUnit(params),
localPredictorSize(params.localPredictorSize),
@@ -137,4 +140,5 @@
{
}
+} // namespace branch_prediction
} // namespace gem5
diff --git a/src/cpu/pred/2bit_local.hh b/src/cpu/pred/2bit_local.hh
index 8d2a09b..55f45ca 100644
--- a/src/cpu/pred/2bit_local.hh
+++ b/src/cpu/pred/2bit_local.hh
@@ -51,6 +51,9 @@
namespace gem5
{
+namespace branch_prediction
+{
+
/**
* Implements a local predictor that uses the PC to index into a table of
* counters. Note that any time a pointer to the bp_history is given, it
@@ -125,6 +128,7 @@
const unsigned indexMask;
};
+} // namespace branch_prediction
} // namespace gem5
#endif // __CPU_PRED_2BIT_LOCAL_PRED_HH__
diff --git a/src/cpu/pred/BranchPredictor.py
b/src/cpu/pred/BranchPredictor.py
index aa8e5cf..c6abebb 100644
--- a/src/cpu/pred/BranchPredictor.py
+++ b/src/cpu/pred/BranchPredictor.py
@@ -31,7 +31,7 @@
class IndirectPredictor(SimObject):
type = 'IndirectPredictor'
-cxx_class = 'gem5::IndirectPredictor'
+cxx_class = 'gem5::branch_prediction::IndirectPredictor'
cxx_header = "cpu/pred/indirect.hh"
abstract = True
@@ -39,7 +39,7 @@
class SimpleIndirectPredictor(IndirectPredictor):
type = 'SimpleIndirectPredictor'
-cxx_class = 'gem5::SimpleIndirectPredictor'
+cxx_class = 'gem5::branch_prediction::SimpleIndirectPredictor'
cxx_header = "cpu/pred/simple_indirect.hh"
indirectHashGHR = Param.Bool(True, "Hash branch predictor GHR")
@@ -54,7 +54,7 @@
class BranchPredictor(SimObject):
type = 'BranchPredictor'
-cxx_class = 'gem5::BPredUnit'
+cxx_class = 'gem5::branch_prediction::BPredUnit'
cxx_header = "cpu/pred/bpred_unit.hh"
abstract = True
@@ -69,7 +69,7 @@
[gem5-dev] Change in gem5/gem5[develop]: mem: Conclude deprecation of MemObject
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47299 )
Change subject: mem: Conclude deprecation of MemObject
..
mem: Conclude deprecation of MemObject
This has been marked as deprecated a few versions ago,
so it is safe to conclude its deprecation process.
Change-Id: I20d37700c97264080a7b19cf0cf9ccf8a5b65c32
Signed-off-by: Daniel R. Carvalho
---
M src/dev/arm/css/scmi_platform.hh
D src/mem/MemObject.py
M src/mem/SConscript
D src/mem/mem_object.hh
4 files changed, 0 insertions(+), 98 deletions(-)
diff --git a/src/dev/arm/css/scmi_platform.hh
b/src/dev/arm/css/scmi_platform.hh
index 5cd52bc..e56f024 100644
--- a/src/dev/arm/css/scmi_platform.hh
+++ b/src/dev/arm/css/scmi_platform.hh
@@ -41,7 +41,6 @@
#include "dev/arm/css/scmi_protocols.hh"
#include "dev/arm/css/scp.hh"
#include "dev/dma_device.hh"
-#include "mem/mem_object.hh"
#include "params/ScmiPlatform.hh"
class Doorbell;
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
deleted file mode 100644
index 76b519a..000
--- a/src/mem/MemObject.py
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from m5.objects.ClockedObject import ClockedObject
-
-class MemObject(ClockedObject):
-type = 'MemObject'
-abstract = True
-cxx_header = "mem/mem_object.hh"
diff --git a/src/mem/SConscript b/src/mem/SConscript
index edf2985..5d3c5e6 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -53,7 +53,6 @@
SimObject('ExternalMaster.py')
SimObject('ExternalSlave.py')
SimObject('CfiMemory.py')
-SimObject('MemObject.py')
SimObject('SimpleMemory.py')
SimObject('XBar.py')
SimObject('HMCController.py')
diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh
deleted file mode 100644
index 916eb26..000
--- a/src/mem/mem_object.hh
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND
[gem5-dev] Change in gem5/gem5[develop]: python,scons,mem-ruby: Tag origin of generated files
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47301 )
Change subject: python,scons,mem-ruby: Tag origin of generated files
..
python,scons,mem-ruby: Tag origin of generated files
This will make it easier to backtrack and modify
such files when needed.
Change-Id: If09b6f848e607fb21a0acf2114ce0b9b0aa4751f
Signed-off-by: Daniel R. Carvalho
---
M src/SConscript
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/SymbolTable.py
M src/mem/slicc/symbols/Type.py
M src/python/m5/util/code_formatter.py
5 files changed, 32 insertions(+), 42 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index 08cfeee..804160b 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1149,10 +1149,6 @@
# file header
code('''
-/*
- * DO NOT EDIT THIS FILE! Automatically generated by SCons.
- */
-
#include "base/debug.hh"
namespace Debug {
@@ -1206,10 +1202,6 @@
# file header boilerplate
code('''\
-/*
- * DO NOT EDIT THIS FILE! Automatically generated by SCons.
- */
-
#ifndef __DEBUG_${name}_HH__
#define __DEBUG_${name}_HH__
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 0c4651d..42b5553 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -272,11 +272,7 @@
c_ident = "%s_Controller" % self.ident
code('''
-/** \\file $c_ident.hh
- *
- * Auto generated C++ code started by $__file__:$__line__
- * Created by slicc definition of Module "${{self.short}}"
- */
+// Created by slicc definition of Module "${{self.short}}"
#ifndef __${ident}_CONTROLLER_HH__
#define __${ident}_CONTROLLER_HH__
@@ -492,11 +488,7 @@
'''
code('''
-/** \\file $c_ident.cc
- *
- * Auto generated C++ code started by $__file__:$__line__
- * Created by slicc definition of Module "${{self.short}}"
- */
+// Created by slicc definition of Module "${{self.short}}"
#include
#include
@@ -1220,7 +1212,6 @@
outputRequest_types = False
code('''
-// Auto generated C++ code started by $__file__:$__line__
// ${ident}: ${{self.short}}
#include
@@ -1343,7 +1334,6 @@
ident = self.ident
code('''
-// Auto generated C++ code started by $__file__:$__line__
// ${ident}: ${{self.short}}
#include
diff --git a/src/mem/slicc/symbols/SymbolTable.py
b/src/mem/slicc/symbols/SymbolTable.py
index e4fc0a3..fb01b01 100644
--- a/src/mem/slicc/symbols/SymbolTable.py
+++ b/src/mem/slicc/symbols/SymbolTable.py
@@ -126,7 +126,6 @@
makeDir(path)
code = self.codeFormatter()
-code('/** Auto generated C++ code started by $__file__:$__line__
*/')
for include_path in includes:
code('#include "${{include_path}}"')
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index a1ca200..c6013f8 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -204,12 +204,6 @@
def printTypeHH(self, path):
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.hh
- *
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#ifndef __${{self.c_ident}}_HH__
#define __${{self.c_ident}}_HH__
@@ -404,11 +398,6 @@
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.cc
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#include
#include
@@ -449,11 +438,6 @@
def printEnumHH(self, path):
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.hh
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#ifndef __${{self.c_ident}}_HH__
#define __${{self.c_ident}}_HH__
@@ -555,11 +539,6 @@
def printEnumCC(self, path):
code = self.symtab.codeFormatter()
code('''
-/** \\file ${{self.c_ident}}.hh
- *
- * Auto generated C++ code started by $__file__:$__line__
- */
-
#include
#include
#include
diff --git a/src/python/m5/util/code_formatter.py
b/src/python/m5/util/code_formatter.py
index 0ca8c98..8d726d2 100644
--- a/src/python/m5/util/code_formatter.py
+++ b/src/python/m5/util/code_formatter.py
@@ -154,6 +154,36 @@
def write(self, *args):
f = open(os.path.join(*args), "w")
+name, extension = os.path.splitext(f.name)
+
+# Add a comment to inform which file generated the generated file
+# to make it easier to backtrack and modify generated code
+frame = inspect.currentframe().f_back
+if re.match('\.(cc|hh|c|h)', extension) is not None:
+f.write('''/**
+ * DO NOT EDIT THIS FILE!
+ * File automatically generated by
+ * %s:%s
+ */
+
+''' % (frame.f_code.co_filename, frame.f_lineno))
+elif re.match('\.py', extension) is not None:
+f.write('''#
+# DO NOT EDIT THIS FILE!
+# File automatically
[gem5-dev] Change in gem5/gem5[develop]: mem: Move QoS' MemSinkInterface into gem5::qos
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47300 )
Change subject: mem: Move QoS' MemSinkInterface into gem5::qos
..
mem: Move QoS' MemSinkInterface into gem5::qos
This class has been mistakenly added outside the
qos namespace.
Change-Id: I12c5dc7558a689c771761754e59d78a8010e422f
Signed-off-by: Daniel R. Carvalho
---
M src/mem/qos/QoSMemSinkInterface.py
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/src/mem/qos/QoSMemSinkInterface.py
b/src/mem/qos/QoSMemSinkInterface.py
index 37ddf78..9b3b89e 100644
--- a/src/mem/qos/QoSMemSinkInterface.py
+++ b/src/mem/qos/QoSMemSinkInterface.py
@@ -38,6 +38,7 @@
class QoSMemSinkInterface(AbstractMemory):
type = 'QoSMemSinkInterface'
cxx_header = "mem/qos/mem_sink.hh"
+cxx_class = 'qos::MemSinkInterface'
def controller(self):
"""
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc
index 98a5e3f..f9be06c 100644
--- a/src/mem/qos/mem_sink.cc
+++ b/src/mem/qos/mem_sink.cc
@@ -386,9 +386,9 @@
return mem.recvTimingReq(pkt);
}
-} // namespace qos
-
-QoSMemSinkInterface::QoSMemSinkInterface(const QoSMemSinkInterfaceParams
&_p)
+MemSinkInterface::MemSinkInterface(const QoSMemSinkInterfaceParams &_p)
: AbstractMemory(_p)
{
}
+
+} // namespace qos
diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh
index 3c229ec..247db22 100644
--- a/src/mem/qos/mem_sink.hh
+++ b/src/mem/qos/mem_sink.hh
@@ -52,12 +52,13 @@
#include "sim/eventq.hh"
struct QoSMemSinkInterfaceParams;
-class QoSMemSinkInterface;
GEM5_DEPRECATED_NAMESPACE(QoS, qos);
namespace qos
{
+class MemSinkInterface;
+
/**
* QoS Memory Sink
*
@@ -177,7 +178,7 @@
/**
* Create pointer to interface of actual media
*/
-QoSMemSinkInterface* const interface;
+MemSinkInterface* const interface;
/** Read request pending */
bool retryRdReq;
@@ -262,19 +263,18 @@
MemSinkCtrlStats stats;
};
-} // namespace qos
-
-class QoSMemSinkInterface : public AbstractMemory
+class MemSinkInterface : public AbstractMemory
{
public:
/** Setting a pointer to the interface */
-void setMemCtrl(qos::MemSinkCtrl* _ctrl) { ctrl = _ctrl; };
+void setMemCtrl(MemSinkCtrl* _ctrl) { ctrl = _ctrl; };
/** Pointer to the controller */
-qos::MemSinkCtrl* ctrl;
+MemSinkCtrl* ctrl;
-QoSMemSinkInterface(const QoSMemSinkInterfaceParams &_p);
+MemSinkInterface(const QoSMemSinkInterfaceParams &_p);
};
+} // namespace qos
#endif /* __MEM_QOS_MEM_SINK_HH__ */
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47300
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I12c5dc7558a689c771761754e59d78a8010e422f
Gerrit-Change-Number: 47300
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: ext: Adopt the gem5 namespace in ext/
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47302 )
Change subject: ext: Adopt the gem5 namespace in ext/
..
ext: Adopt the gem5 namespace in ext/
Change-Id: I3da8adffdcfe9e47e88cd85b7b66f6f8e1a1757a
Signed-off-by: Daniel R. Carvalho
---
M ext/sst/ExtMaster.cc
M ext/sst/ExtMaster.hh
M ext/sst/ExtSlave.cc
M ext/sst/ExtSlave.hh
M ext/sst/gem5.cc
M ext/sst/gem5.hh
6 files changed, 92 insertions(+), 71 deletions(-)
diff --git a/ext/sst/ExtMaster.cc b/ext/sst/ExtMaster.cc
index 3afd6b4..e727537 100644
--- a/ext/sst/ExtMaster.cc
+++ b/ext/sst/ExtMaster.cc
@@ -56,10 +56,10 @@
using namespace SST::gem5;
using namespace SST::MemHierarchy;
-ExtMaster::ExtMaster(gem5Component *g, Output , ::ExternalMaster& p,
+ExtMaster::ExtMaster(gem5Component *g, Output , ::gem5::ExternalMaster&
p,
std::string ) :
-Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
-gem5(g), name(n)
+::gem5::ExternalMaster::Port(n, p), out(o), port(p),
+simPhase(CONSTRUCTION), gem5(g), name(n)
{
Params _p; // will be ignored
nic =
dynamic_cast(gem5->loadModuleWithComponent("memHierarchy.memNIC",
g, _p));
@@ -130,12 +130,12 @@
}
Command cmdI = ev->getCmd(); // command in - SST
-MemCmd::Command cmdO;// command out - gem5
+::gem5::MemCmd::Command cmdO;// command out - gem5
bool data = false;
switch (cmdI) {
-case GetS: cmdO = MemCmd::ReadReq;break;
-case GetX: cmdO = MemCmd::WriteReq; data = true; break;
+case GetS: cmdO = ::gem5::MemCmd::ReadReq;
break;
+case GetX: cmdO = ::gem5::MemCmd::WriteReq; data = true;
break;
case GetSEx:
case PutS:
case PutM:
@@ -158,23 +158,24 @@
CommandString[cmdI]);
}
-Request::FlagsType flags = 0;
+::gem5::Request::FlagsType flags = 0;
if (ev->queryFlag(MemEvent::F_LOCKED))
-flags |= Request::LOCKED_RMW;
+flags |= ::gem5::Request::LOCKED_RMW;
if (ev->queryFlag(MemEvent::F_NONCACHEABLE))
-flags |= Request::UNCACHEABLE;
+flags |= ::gem5::Request::UNCACHEABLE;
if (ev->isLoadLink()) {
assert(cmdI == GetS);
-cmdO = MemCmd::LoadLockedReq;
+cmdO = ::gem5::MemCmd::LoadLockedReq;
} else if (ev->isStoreConditional()) {
assert(cmdI == GetX);
-cmdO = MemCmd::StoreCondReq;
+cmdO = ::gem5::MemCmd::StoreCondReq;
}
-auto req = std::make_shared(ev->getAddr(), ev->getSize(),
flags, 0);
+auto req = std::make_shared<::gem5::Request>(
+ev->getAddr(), ev->getSize(), flags, 0);
req->setContext(ev->getGroupId());
-auto pkt = new Packet(req, cmdO);
+auto pkt = new ::gem5::Packet(req, cmdO);
pkt->allocate();
if (data) {
pkt->setData(ev->getPayload().data());
@@ -186,7 +187,7 @@
}
bool
-ExtMaster::recvTimingResp(PacketPtr pkt) {
+ExtMaster::recvTimingResp(::gem5::PacketPtr pkt) {
if (simPhase == INIT) {
out.fatal(CALL_INFO, 1, "not prepared to handle INIT-phase
traffic\n");
}
diff --git a/ext/sst/ExtMaster.hh b/ext/sst/ExtMaster.hh
index 04e98e5..8b4020b 100644
--- a/ext/sst/ExtMaster.hh
+++ b/ext/sst/ExtMaster.hh
@@ -51,10 +51,11 @@
#include
#include
-#include
+#include
+#include
#include
#include
-#include
+#include
namespace SST {
@@ -70,34 +71,35 @@
class gem5Component;
-class ExtMaster : public ExternalMaster::Port {
+class ExtMaster : public ::gem5::ExternalMaster::Port
+{
enum Phase { CONSTRUCTION, INIT, RUN };
Output& out;
-const ExternalMaster& port;
+const ::gem5::ExternalMaster& port;
Phase simPhase;
gem5Component *const gem5;
const std::string name;
-std::list sendQ;
+std::list<::gem5::PacketPtr> sendQ;
bool blocked() { return !sendQ.empty(); }
MemHierarchy::MemNIC * nic;
-struct SenderState : public Packet::SenderState
+struct SenderState : public ::gem5::Packet::SenderState
{
MemEvent *event;
SenderState(MemEvent* e) : event(e) {}
};
-std::set ranges;
+std::set<::gem5::AddrRange> ranges;
public:
-bool recvTimingResp(PacketPtr);
+bool recvTimingResp(::gem5::PacketPtr);
void recvReqRetry();
-ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
+ExtMaster(gem5Component*, Output&, ::gem5::ExternalMaster&,
std::string&);
void init(unsigned phase);
void setup();
void finish();
diff --git a/ext/sst/ExtSlave.cc b/ext/sst/ExtSlave.cc
index 0e2f8b4..b9a5e78 100644
--- a/ext/sst/ExtSlave.cc
+++ b/ext/sst/ExtSlave.cc
@@ -48,13 +48,15 @@
#undef fatal
#endif
+#include
+
using namespace SST;
using namespace SST::gem5;
using namespace SST::MemHierarchy;
ExtSlave::ExtSlave(gem5Component *g5c, Output ,
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Rename debug variables
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47304 )
Change subject: arch-arm: Rename debug variables
..
arch-arm: Rename debug variables
Pave the way for a "debug" namespace.
Change-Id: I1796711cbde527269637b30b0b09cd06c9e25fa1
Signed-off-by: Daniel R. Carvalho
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/self_debug.cc
3 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index adb1207..d81651b 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1103,16 +1103,16 @@
} else if (stage2) {
tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
tc->setMiscReg(T::HFarIndex, OVAddr);
-} else if (debug > ArmFault::NODEBUG) {
+} else if (debugType > ArmFault::NODEBUG) {
DBGDS32 Rext = tc->readMiscReg(MISCREG_DBGDSCRext);
tc->setMiscReg(T::FarIndex, faultAddr);
-if (debug == ArmFault::BRKPOINT){
+if (debugType == ArmFault::BRKPOINT){
Rext.moe = 0x1;
-} else if (debug == ArmFault::VECTORCATCH){
+} else if (debugType == ArmFault::VECTORCATCH){
Rext.moe = 0x5;
-} else if (debug > ArmFault::VECTORCATCH) {
+} else if (debugType > ArmFault::VECTORCATCH) {
Rext.moe = 0xa;
-fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
+fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
}
tc->setMiscReg(T::FsrIndex, fsr);
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index da05eb9..6d5411f 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -456,7 +456,7 @@
bool stage2;
bool s1ptw;
ArmFault::TranMethod tranMethod;
-ArmFault::DebugType debug;
+ArmFault::DebugType debugType;
public:
AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
@@ -465,7 +465,8 @@
ArmFault::DebugType _debug = ArmFault::NODEBUG) :
faultAddr(_faultAddr), OVAddr(0), write(_write),
domain(_domain), source(_source), srcEncoded(0),
-stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
debug(_debug)
+stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
+debugType(_debug)
{}
bool getFaultVAddr(Addr ) const override;
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 21d4000..13ee2f7 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -96,8 +96,7 @@
if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
const DBGBCR ctr = p.getControlReg(tc);
if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
-bool debug = p.test(tc, pc, el, ctr, false);
-if (debug){
+if (p.test(tc, pc, el, ctr, false)) {
if (to32)
p.onUse = true;
return triggerException(tc, pc);
@@ -138,8 +137,7 @@
for (auto : arWatchPoints){
idxtmp ++;
if (p.enable) {
-bool debug = p.test(tc, vaddr, el, write, atomic, size);
-if (debug){
+if (p.test(tc, vaddr, el, write, atomic, size)) {
return triggerWatchpointException(tc, vaddr, write, cm);
}
}
@@ -212,12 +210,8 @@
bool
BrkPoint::testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
{
-bool debug = false;
const DBGBCR ctr = getControlReg(tc);
-if ((ctr.bt & 0x1) && enable) {
-debug = test(tc, vaddr, el, ctr, true);
-}
-return debug;
+return ((ctr.bt & 0x1) && enable) && test(tc, vaddr, el, ctr, true);
}
bool
@@ -730,12 +724,12 @@
return NoFault;
ExceptionLevel el = (ExceptionLevel) currEL(tc);
-bool debug;
+bool do_debug;
if (fault == nullptr)
-debug = vcExcpt->addressMatching(tc, addr, el);
+do_debug = vcExcpt->addressMatching(tc, addr, el);
else
-debug = vcExcpt->exceptionTrapping(tc, el, fault);
-if (debug) {
+do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
+if (do_debug) {
if (enableTdeTge) {
return std::make_shared(0, 0x22,
EC_PREFETCH_ABORT_TO_HYP);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47304
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1796711cbde527269637b30b0b09cd06c9e25fa1
Gerrit-Change-Number: 47304
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho
Gerrit-MessageType: newchange
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