[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor process initialization
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40941 )
Change subject: arch-power: Refactor process initialization
..
arch-power: Refactor process initialization
This generalizes parts of the process initialization
routines in preparation for multi-mode support and
adds flexibility in terms of data types and byte order
used for setting up the environment corresponding to
the mode in use.
Change-Id: Ia9efb93d044682af8b0f0809bca64a17570bf197
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40941
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/process.cc
M src/arch/power/process.hh
2 files changed, 24 insertions(+), 20 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index a9a28b3..bc63146 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -81,13 +81,16 @@
{
Process::initState();
-argsInit(sizeof(uint32_t), PageBytes);
+argsInit(PageBytes);
}
+template
void
-PowerProcess::argsInit(int intSize, int pageSize)
+PowerProcess::argsInit(int pageSize)
{
-std::vector> auxv;
+int intSize = sizeof(IntType);
+ByteOrder byteOrder = objFile->getByteOrder();
+std::vector> auxv;
std::string filename;
if (argv.size() < 1)
@@ -106,7 +109,7 @@
//Auxilliary vectors are loaded only for elf formatted executables.
auto *elfObject = dynamic_cast(objFile);
if (elfObject) {
-uint32_t features = 0;
+IntType features = 0;
//Bits which describe the system hardware capabilities
//XXX Figure out what these should be
@@ -209,15 +212,15 @@
roundUp(memState->getStackSize(),
pageSize), "stack");
// map out initial stack contents
-uint32_t sentry_base = memState->getStackBase() - sentry_size;
-uint32_t aux_data_base = sentry_base - aux_data_size;
-uint32_t env_data_base = aux_data_base - env_data_size;
-uint32_t arg_data_base = env_data_base - arg_data_size;
-uint32_t platform_base = arg_data_base - platform_size;
-uint32_t auxv_array_base = platform_base - aux_array_size -
aux_padding;
-uint32_t envp_array_base = auxv_array_base - envp_array_size;
-uint32_t argv_array_base = envp_array_base - argv_array_size;
-uint32_t argc_base = argv_array_base - argc_size;
+IntType sentry_base = memState->getStackBase() - sentry_size;
+IntType aux_data_base = sentry_base - aux_data_size;
+IntType env_data_base = aux_data_base - env_data_size;
+IntType arg_data_base = env_data_base - arg_data_size;
+IntType platform_base = arg_data_base - platform_size;
+IntType auxv_array_base = platform_base - aux_array_size - aux_padding;
+IntType envp_array_base = auxv_array_base - envp_array_size;
+IntType argv_array_base = envp_array_base - argv_array_size;
+IntType argc_base = argv_array_base - argc_size;
DPRINTF(Stack, "The addresses of items on the initial stack:\n");
DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
@@ -233,11 +236,11 @@
// write contents to stack
// figure out argc
-uint32_t argc = argv.size();
-uint32_t guestArgc = htobe(argc);
+IntType argc = argv.size();
+IntType guestArgc = htog(argc, byteOrder);
//Write out the sentry void *
-uint32_t sentry_NULL = 0;
+IntType sentry_NULL = 0;
initVirtMem->writeBlob(sentry_base, _NULL, sentry_size);
//Fix up the aux vectors which point to other data
@@ -256,7 +259,7 @@
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto : auxv) {
-initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
+initVirtMem->write(auxv_array_end, aux, byteOrder);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxilliary vector
@@ -265,9 +268,9 @@
auxv_array_end += sizeof(zero);
copyStringArray(envp, envp_array_base, env_data_base,
-ByteOrder::big, *initVirtMem);
+byteOrder, *initVirtMem);
copyStringArray(argv, argv_array_base, arg_data_base,
-ByteOrder::big, *initVirtMem);
+byteOrder, *initVirtMem);
initVirtMem->writeBlob(argc_base, , intSize);
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh
index 210bce2..9f2ce4b 100644
--- a/src/arch/power/process.hh
+++ b/src/arch/power/process.hh
@@ -49,7 +49,8 @@
public:
PowerProcess(const ProcessParams , loader::ObjectFile *objFile);
-void argsInit(int intSize, int pageSize);
+template
+void argsInit(int pageSize);
};
} // namespace gem5
--
To view, visit
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Update copyrights
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40948 ) Change subject: arch-power: Update copyrights .. arch-power: Update copyrights Change-Id: Ifabd1e7178b5250767a2b560b57570512b732278 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40948 Reviewed-by: Boris Shingarov Maintainer: Boris Shingarov Tested-by: kokoro --- M src/arch/power/SConscript M src/arch/power/decoder.hh M src/arch/power/insts/branch.cc M src/arch/power/insts/branch.hh M src/arch/power/insts/integer.cc M src/arch/power/insts/integer.hh M src/arch/power/insts/mem.cc M src/arch/power/insts/mem.hh M src/arch/power/isa.hh M src/arch/power/isa/bitfields.isa M src/arch/power/isa/decoder.isa M src/arch/power/isa/formats/branch.isa M src/arch/power/isa/formats/integer.isa M src/arch/power/isa/formats/mem.isa M src/arch/power/isa/formats/unimp.isa M src/arch/power/isa/formats/unknown.isa M src/arch/power/isa/formats/util.isa M src/arch/power/isa/operands.isa M src/arch/power/linux/se_workload.cc M src/arch/power/page_size.hh M src/arch/power/process.cc M src/arch/power/process.hh M src/arch/power/regs/int.hh M src/arch/power/regs/misc.hh M src/arch/power/remote_gdb.cc M src/arch/power/remote_gdb.hh M src/arch/power/types.hh M src/arch/power/vecregs.hh 28 files changed, 28 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript index 52a607d..74b2c81 100644 --- a/src/arch/power/SConscript +++ b/src/arch/power/SConscript @@ -2,6 +2,7 @@ # Copyright (c) 2009 The University of Edinburgh # Copyright (c) 2020 LabWare +# Copyright (c) 2021 IBM Corporation # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh index 20726a0..c30af91 100644 --- a/src/arch/power/decoder.hh +++ b/src/arch/power/decoder.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2012 Google + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc index a1b6d8c..8992143 100644 --- a/src/arch/power/insts/branch.cc +++ b/src/arch/power/insts/branch.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh index cad91c2..1359086 100644 --- a/src/arch/power/insts/branch.hh +++ b/src/arch/power/insts/branch.hh @@ -1,5 +1,6 @@ /* Copyright (c) 2007-2008 The Florida State University * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc index 7798d40..cf065a1 100644 --- a/src/arch/power/insts/integer.cc +++ b/src/arch/power/insts/integer.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh index 2e34876..1c298a0 100644 --- a/src/arch/power/insts/integer.hh +++ b/src/arch/power/insts/integer.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc index 7e44fd8..1f6700e 100644 --- a/src/arch/power/insts/mem.cc +++ b/src/arch/power/insts/mem.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh index 6fcfb12..732ea11 100644 --- a/src/arch/power/insts/mem.hh +++ b/src/arch/power/insts/mem.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index 784f368..d563ebe 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -1,6 +1,7 @@ /* * Copyright (c) 2009 The Regents of The University of Michigan * Copyright (c) 2009 The University of Edinburgh + *
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix load-store timing sequence
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40947 )
Change subject: arch-power: Fix load-store timing sequence
..
arch-power: Fix load-store timing sequence
To properly implement load-store instructions for use with
the TimingSimpleCPU model, the initiateAcc() part of the
instruction should only be responsible for performing the
effective address computation and then initiating memory
access.
The completeAcc() part of the instruction should then be
responsible for setting the condition register flags or
updating the base register based on the outcome of the
memory access. This fixes the following instructions:
* Load Byte and Zero with Update (lbzu)
* Load Halfword and Zero with Update (lhzu)
* Load Halfword Algebraic with Update (lhau)
* Load Word and Zero with Update (lwzu)
* Load Doubleword with Update (ldu)
* Load Floating Single with Update (lfsu)
* Load Floating Double with Update (lfdu)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Halfword and Zero with Update Indexed (lhzux)
* Load Halfword Algebraic with Update Indexed (lhaux)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic with Update Indexed (lwaux)
* Load Doubleword with Update Indexed (ldux)
* Load Floating Single with Update Indexed (lfsux)
* Load Floating Double with Update Indexed (lfdux)
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Word And Reserve Indexed (lwarx)
* Load Doubleword And Reserve Indexed (ldarx)
* Store Byte with Update (stbu)
* Store Halfword with Update (sthu)
* Store Word with Update (stwu)
* Store Doubleword with Update (stdu)
* Store Byte with Update Indexed (stbux)
* Store Halfword with Update Indexed (sthux)
* Store Word with Update Indexed (stwux)
* Store Doubleword with Update Indexed (stdux)
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Word Conditional Indexed (stwcx.)
* Store Doubleword Conditional Indexed (stdcx.)
* Store Floating Single with Update (stfsu)
* Store Floating Double with Update (stdsu)
* Store Floating Single with Update Indexed (stfsux)
* Store Floating Double with Update Indexed (stfdux)
Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40947
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 73 insertions(+), 55 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 461e2cb..a40fbca 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -333,10 +333,8 @@
4: IntTrapOp::tw({{ Ra_sw }}, {{ Rb_sw }});
format LoadIndexOp {
-20: lwarx({{
-Rt = Mem_uw;
-Rsv = 1; RsvLen = 4; RsvAddr = EA;
-}});
+20: lwarx({{ Rt = Mem_uw; }},
+ {{ Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
21: ldx({{ Rt = Mem; }});
23: lwzx({{ Rt = Mem_uw; }});
@@ -373,10 +371,8 @@
cr = makeCRFieldUnsigned((uint32_t)Ra, (uint32_t)Rb,
xer.so);
}});
-52: LoadIndexOp::lbarx({{
-Rt = Mem_ub;
-Rsv = 1; RsvLen = 1; RsvAddr = EA;
-}});
+52: LoadIndexOp::lbarx({{ Rt = Mem_ub; }},
+ {{ Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
@@ -389,17 +385,13 @@
68: IntTrapOp::td({{ Ra }}, {{ Rb }});
format LoadIndexOp {
-84: ldarx({{
-Rt = Mem_ud;
-Rsv = 1; RsvLen = 8; RsvAddr = EA;
-}});
+84: ldarx({{ Rt = Mem_ud; }},
+ {{ Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
87: lbzx({{ Rt = Mem_ub; }});
-116: lharx({{
-Rt = Mem_uh;
-Rsv = 1; RsvLen = 2; RsvAddr = EA;
-}});
+116: lharx({{ Rt = Mem_uh;}},
+ {{ Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
}
119: LoadIndexUpdateOp::lbzux({{ Rt = Mem_ub; }});
@@ -424,8 +416,9 @@
format StoreIndexOp {
149: stdx({{ Mem = Rs }});
150: stwcx({{
-bool store_performed = false;
Mem_uw = Rs_uw;
+}}, {{
+bool store_performed = false;
if (Rsv) {
if (RsvLen == 4) {
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add support for trapping user faults
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47359 )
Change subject: arch-power: Add support for trapping user faults
..
arch-power: Add support for trapping user faults
This adds support for trapping into GDB when user-mode
faults such as those pertaining to alignment (SIGBUS),
traps (SIGTRAP) and unimplemented opcodes (SIGILL) are
encountered.
Change-Id: Ieb557abd4173b5acb4be6f0c30964aea1eba71a5
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47359
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/SConscript
A src/arch/power/faults.cc
M src/arch/power/faults.hh
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/unknown.isa
M src/arch/power/tlb.cc
6 files changed, 89 insertions(+), 10 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 720455c..52a607d 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -34,6 +34,7 @@
# Scons bug id: 2006 M5 Bug id: 308
Dir('isa/formats')
Source('decoder.cc')
+Source('faults.cc')
Source('insts/branch.cc')
Source('insts/mem.cc')
Source('insts/integer.cc')
diff --git a/src/arch/power/faults.cc b/src/arch/power/faults.cc
new file mode 100644
index 000..3b8851e
--- /dev/null
+++ b/src/arch/power/faults.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2021 IBM Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/power/faults.hh"
+
+#include
+
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+
+namespace gem5
+{
+
+namespace PowerISA
+{
+
+void
+UnimplementedOpcodeFault::invoke(ThreadContext *tc, const StaticInstPtr
)
+{
+panic_if(tc->getSystemPtr()->trapToGdb(SIGILL, tc->contextId()),
+ "Unimplemented opcode encountered at virtual address %#x\n",
+ tc->pcState().pc());
+}
+
+void
+AlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr )
+{
+panic_if(!tc->getSystemPtr()->trapToGdb(SIGBUS, tc->contextId()),
+ "Alignment fault when accessing virtual address %#x\n",
vaddr);
+}
+
+void
+TrapFault::invoke(ThreadContext *tc, const StaticInstPtr )
+{
+panic_if(tc->getSystemPtr()->trapToGdb(SIGTRAP, tc->contextId()),
+ "Trap encountered at virtual address %#x\n",
+ tc->pcState().pc());
+}
+
+} // namespace PowerISA
+
+} // namespace gem5
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index edfcc8f..037 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -63,6 +63,9 @@
: PowerFault("Unimplemented Opcode")
{
}
+
+void invoke(ThreadContext *tc, const StaticInstPtr =
+nullStaticInstPtr) override;
};
@@ -78,11 +81,16 @@
class AlignmentFault : public PowerFault
{
+ private:
+Addr vaddr;
public:
-AlignmentFault()
-: PowerFault("Alignment")
+AlignmentFault(Addr va)
+: PowerFault("Alignment"), vaddr(va)
{
}
+
+void invoke(ThreadContext *tc, const StaticInstPtr =
+nullStaticInstPtr) override;
};
@@ -93,6 +101,9 @@
: PowerFault("Trap")
{
}
+
+void invoke(ThreadContext *tc, const StaticInstPtr =
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add multi-mode debugging support
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40946 )
Change subject: arch-power: Add multi-mode debugging support
..
arch-power: Add multi-mode debugging support
This adds multi-mode support for remote debugging via GDB
with the addition of the XML target description files for
both 32-bit and 64-bit variants of the Power architecture.
Proper byte order conversions have also been added.
MSR has now been modeled to some extent but it is still
not exposed by getRegs() since its a privileged register
that cannot be modified from userspace. Similarly, the
target descriptions require FPSCR to also be part of the
payload and hence, it has been added too.
Change-Id: I156fdccb791f161959dbb2c3dd8ab1e510d9cd4b
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40946
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
A ext/gdb-xml/power-core.xml
A ext/gdb-xml/power-fpu.xml
D ext/gdb-xml/power.xml
A ext/gdb-xml/power64-core.xml
A ext/gdb-xml/powerpc-32.xml
A ext/gdb-xml/powerpc-64.xml
M src/arch/power/SConscript
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
9 files changed, 319 insertions(+), 115 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/gdb-xml/power-core.xml b/ext/gdb-xml/power-core.xml
new file mode 100644
index 000..6cf57b1
--- /dev/null
+++ b/ext/gdb-xml/power-core.xml
@@ -0,0 +1,49 @@
+
+
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diff --git a/ext/gdb-xml/power-fpu.xml b/ext/gdb-xml/power-fpu.xml
new file mode 100644
index 000..145eede
--- /dev/null
+++ b/ext/gdb-xml/power-fpu.xml
@@ -0,0 +1,44 @@
+
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diff --git a/ext/gdb-xml/power.xml b/ext/gdb-xml/power.xml
deleted file mode 100644
index da5a07c..000
--- a/ext/gdb-xml/power.xml
+++ /dev/null
@@ -1,92 +0,0 @@
-
-
-
-
-
- powerpc
-
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diff --git a/ext/gdb-xml/power64-core.xml b/ext/gdb-xml/power64-core.xml
new file mode 100644
index 000..cd5bc6d
--- /dev/null
+++ b/ext/gdb-xml/power64-core.xml
@@ -0,0 +1,49 @@
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ext/gdb-xml/powerpc-32.xml b/ext/gdb-xml/powerpc-32.xml
new file mode 100644
index 000..a537f92
--- /dev/null
+++ b/ext/gdb-xml/powerpc-32.xml
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+ powerpc:common
+
+
+
diff --git a/ext/gdb-xml/powerpc-64.xml b/ext/gdb-xml/powerpc-64.xml
new file mode 100644
index 000..a762f8c
--- /dev/null
+++ b/ext/gdb-xml/powerpc-64.xml
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+ powerpc:common64
+
+
+
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 24bf5db..720455c 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -59,4 +59,8 @@
ISADesc('isa/main.isa')
-GdbXml('power.xml', 'gdb_xml_power')
+GdbXml('power-core.xml', 'gdb_xml_power_core')
+GdbXml('power64-core.xml', 'gdb_xml_power64_core')
+GdbXml('power-fpu.xml', 'gdb_xml_power_fpu')
+GdbXml('powerpc-32.xml', 'gdb_xml_powerpc_32')
+GdbXml('powerpc-64.xml', 'gdb_xml_powerpc_64')
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index 886a840..5536879 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -136,7 +136,12 @@
#include
-#include "blobs/gdb_xml_power.hh"
+#include "arch/power/regs/misc.hh"
+#include "blobs/gdb_xml_power64_core.hh"
+#include "blobs/gdb_xml_power_core.hh"
+#include "blobs/gdb_xml_power_fpu.hh"
+#include "blobs/gdb_xml_powerpc_32.hh"
+#include "blobs/gdb_xml_powerpc_64.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
@@ -149,7 +154,7 @@
using namespace PowerISA;
RemoteGDB::RemoteGDB(System *_system, int _port)
-: BaseRemoteGDB(_system, _port), regCache(this)
+: BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
{
}
@@ -173,22 +178,26 @@
{
DPRINTF(GDBAcc, "getRegs in remotegdb \n");
+Msr msr = context->readIntReg(INTREG_MSR);
+ByteOrder order = (msr.le ?
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix process initialization
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40945 ) Change subject: arch-power: Fix process initialization .. arch-power: Fix process initialization During process initialization, special purpose registers should either be explicitly set or cleared. These contain flag bits which might have unforseen side effects on the execution of a program. Change-Id: If7c5af9a93283a53717cc8cbba4bf373a7e40560 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40945 Reviewed-by: Boris Shingarov Maintainer: Boris Shingarov Tested-by: kokoro --- M src/arch/power/process.cc 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index 8ac5946..27f7607 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -338,6 +338,10 @@ //Set the stack pointer register tc->setIntReg(StackPointerReg, stack_min); +//Reset the special-purpose registers +for (int i = 0; i < NumIntSpecialRegs; i++) +tc->setIntReg(NumIntArchRegs + i, 0); + //Set the machine status for a typical userspace Msr msr = 0; msr.sf = is64bit; 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40945 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If7c5af9a93283a53717cc8cbba4bf373a7e40560 Gerrit-Change-Number: 40945 Gerrit-PatchSet: 12 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add multi-mode support
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40944 )
Change subject: arch-power: Add multi-mode support
..
arch-power: Add multi-mode support
This adds multi-mode support and allows the simulator to
read, interpret and execute 32bit and 64-bit, big and
little endian binaries in syscall emulation mode.
During process initialization, a minimal set of hardware
capabilities are also advertised by the simulator to show
support for 64-bit mode and little endian byte order.
This also adds some fixups specific to 64-bit ELF ABI v1
that readjust the entry point and symbol table due to the
use of function descriptors.
Change-Id: I124339eff7b70dbd14e50ff970340c88c13bd0ad
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40944
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/PowerSeWorkload.py
M src/arch/power/linux/se_workload.cc
M src/arch/power/process.cc
M src/arch/power/regs/int.hh
M src/base/loader/elf_object.cc
M src/base/loader/object_file.cc
M src/base/loader/object_file.hh
7 files changed, 100 insertions(+), 18 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/PowerSeWorkload.py
b/src/arch/power/PowerSeWorkload.py
index ef7bbb5..2b081f2 100644
--- a/src/arch/power/PowerSeWorkload.py
+++ b/src/arch/power/PowerSeWorkload.py
@@ -40,5 +40,5 @@
@classmethod
def _is_compatible_with(cls, obj):
-return obj.get_arch() == 'power' and \
+return obj.get_arch() in ('power', 'power64') and \
obj.get_op_sys() in ('linux', 'unknown')
diff --git a/src/arch/power/linux/se_workload.cc
b/src/arch/power/linux/se_workload.cc
index 75eb210..815a145 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -50,7 +50,9 @@
Process *
load(const ProcessParams , loader::ObjectFile *obj) override
{
-if (obj->getArch() != loader::Power)
+auto arch = obj->getArch();
+
+if (arch != loader::Power && arch != loader::Power64)
return nullptr;
auto opsys = obj->getOpSys();
@@ -60,7 +62,10 @@
opsys = loader::Linux;
}
-if (opsys != loader::Linux)
+if ((arch == loader::Power && opsys != loader::Linux) ||
+(arch == loader::Power64 &&
+ opsys != loader::LinuxPower64ABIv1 &&
+ opsys != loader::LinuxPower64ABIv2))
return nullptr;
return new PowerProcess(params, obj);
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 688cc1e..8ac5946 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -82,7 +82,55 @@
{
Process::initState();
-argsInit(PageBytes);
+if (objFile->getArch() == loader::Power)
+argsInit(PageBytes);
+else
+argsInit(PageBytes);
+
+// Fix up entry point and symbol table for 64-bit ELF ABI v1
+if (objFile->getOpSys() != loader::LinuxPower64ABIv1)
+return;
+
+// Fix entry point address and the base TOC pointer by looking the
+// the function descriptor in the .opd section
+Addr entryPoint, tocBase;
+ByteOrder byteOrder = objFile->getByteOrder();
+ThreadContext *tc = system->threads[contextIds[0]];
+
+// The first doubleword of the descriptor contains the address of the
+// entry point of the function
+initVirtMem->readBlob(getStartPC(), , sizeof(Addr));
+
+// Update the PC state
+auto pc = tc->pcState();
+pc.byteOrder(byteOrder);
+pc.set(gtoh(entryPoint, byteOrder));
+tc->pcState(pc);
+
+// The second doubleword of the descriptor contains the TOC base
+// address for the function
+initVirtMem->readBlob(getStartPC() + 8, , sizeof(Addr));
+tc->setIntReg(TOCPointerReg, gtoh(tocBase, byteOrder));
+
+// Fix symbol table entries as they would otherwise point to the
+// function descriptor rather than the actual entry point address
+auto *symbolTable = new loader::SymbolTable;
+
+for (auto sym : loader::debugSymbolTable) {
+Addr entry;
+loader::Symbol symbol = sym;
+
+// Try to read entry point from function descriptor
+if (initVirtMem->tryReadBlob(sym.address, , sizeof(Addr)))
+symbol.address = gtoh(entry, byteOrder);
+
+symbolTable->insert(symbol);
+}
+
+// Replace the current debug symbol table
+loader::debugSymbolTable.clear();
+loader::debugSymbolTable.insert(*symbolTable);
+delete symbolTable;
}
template
@@ -91,6 +139,8 @@
{
int intSize = sizeof(IntType);
ByteOrder byteOrder = objFile->getByteOrder();
+bool is64bit = (objFile->getArch() == loader::Power64);
+bool isLittleEndian = (byteOrder ==
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add hardware features
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40942 )
Change subject: arch-power: Add hardware features
..
arch-power: Add hardware features
This adds definitions for the hardware feature bits that
are currently available from the AT_HWCAP and AT_HWCAP2
auxv entries for the Power architecture. These are being
defined for future use.
Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40942
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/process.hh
1 file changed, 41 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh
index 9f2ce4b..ea5e957 100644
--- a/src/arch/power/process.hh
+++ b/src/arch/power/process.hh
@@ -55,4 +55,45 @@
} // namespace gem5
+enum PowerHWCAPFeature
+{
+HWCAP_FEATURE_32 = 1ULL << 31,// Always set for powerpc64
+HWCAP_FEATURE_64 = 1ULL << 30,// Always set for powerpc64
+HWCAP_FEATURE_HAS_ALTIVEC = 1ULL << 28,
+HWCAP_FEATURE_HAS_FPU = 1ULL << 27,
+HWCAP_FEATURE_HAS_MMU = 1ULL << 26,
+HWCAP_FEATURE_UNIFIED_CACHE = 1ULL << 24,
+HWCAP_FEATURE_NO_TB = 1ULL << 20, // 601/403gx have no timebase
+HWCAP_FEATURE_POWER4 = 1ULL << 19,// POWER4 ISA 2.00
+HWCAP_FEATURE_POWER5 = 1ULL << 18,// POWER5 ISA 2.02
+HWCAP_FEATURE_POWER5_PLUS = 1ULL << 17, // POWER5+ ISA 2.03
+HWCAP_FEATURE_CELL_BE = 1ULL << 16, // CELL Broadband Engine
+HWCAP_FEATURE_BOOKE = 1ULL << 15, // ISA Category Embedded
+HWCAP_FEATURE_SMT = 1ULL << 14, // Simultaneous
Multi-Threading
+HWCAP_FEATURE_ICACHE_SNOOP = 1ULL << 13,
+HWCAP_FEATURE_ARCH_2_05 = 1ULL << 12, // ISA 2.05
+HWCAP_FEATURE_PA6T = 1ULL << 11, // PA Semi 6T Core
+HWCAP_FEATURE_HAS_DFP = 1ULL << 10, // Decimal FP Unit
+HWCAP_FEATURE_POWER6_EXT = 1ULL << 9, // P6 + mffgpr/mftgpr
+HWCAP_FEATURE_ARCH_2_06 = 1ULL << 8, // ISA 2.06
+HWCAP_FEATURE_HAS_VSX = 1ULL << 7,// P7 Vector Extension
+HWCAP_FEATURE_PSERIES_PERFMON_COMPAT = 1ULL << 6,
+HWCAP_FEATURE_TRUE_LE = 1ULL << 1,
+HWCAP_FEATURE_PPC_LE = 1ULL << 0
+};
+
+enum PowerHWCAP2Feature
+{
+HWCAP2_FEATURE_ARCH_2_07 = 1ULL << 31,// ISA 2.07
+HWCAP2_FEATURE_HAS_HTM = 1ULL << 30, // Hardware Transactional
Memory
+HWCAP2_FEATURE_HAS_DSCR = 1ULL << 29, // Data Stream Control
Register
+HWCAP2_FEATURE_HAS_EBB = 1ULL << 28, // Event Base Branching
+HWCAP2_FEATURE_HAS_ISEL = 1ULL << 27, // Integer Select
+HWCAP2_FEATURE_HAS_TAR = 1ULL << 26, // Target Address Register
+HWCAP2_FEATURE_HAS_VCRYPTO = 1ULL << 25, // Vector AES category
+HWCAP2_FEATURE_HTM_NOSC = 1ULL << 24,
+HWCAP2_FEATURE_ARCH_3_00 = 1ULL << 23,// ISA 3.0
+HWCAP2_FEATURE_HAS_IEEE128 = 1ULL << 22, // VSX IEEE Binary Float
128-bit
+};
+
#endif // __POWER_PROCESS_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40942
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51
Gerrit-Change-Number: 40942
Gerrit-PatchSet: 12
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add MSR and associated dependencies
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40943 )
Change subject: arch-power: Add MSR and associated dependencies
..
arch-power: Add MSR and associated dependencies
This adds the definition of the Machine State Register
(MSR) in preparation for multi-mode support. The MSR
has bits that define the state of the processor. This
defines all the bitfields and sets the ones that are
typically used for userspace environments.
In preparation for multi-mode support, the SF and LE
bits are used by instructions to check if the simulation
is running in 64-bit mode and if memory accesses are to
be performed in little endian byte order respectively.
This introduces changes in areas such as target address
computation for branch instructions, carry and overflow
computation for arithmetic instructions, etc.
Change-Id: If9ac69415ca85b0c873bd8579e7d1bd2219eac62
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40943
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/operands.isa
M src/arch/power/process.cc
M src/arch/power/regs/int.hh
M src/arch/power/regs/misc.hh
9 files changed, 127 insertions(+), 41 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index ca52d83..a1b6d8c 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -27,6 +27,8 @@
*/
#include "arch/power/insts/branch.hh"
+#include "arch/power/regs/int.hh"
+#include "arch/power/regs/misc.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
@@ -54,12 +56,17 @@
PowerISA::PCState
-BranchOp::branchTarget(const PowerISA::PCState ) const
+BranchOp::branchTarget(ThreadContext *tc) const
{
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr;
+
if (aa)
-return li;
+addr = li;
else
-return pc.pc() + li;
+addr = tc->pcState().pc() + li;
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -97,13 +104,17 @@
PowerISA::PCState
-BranchDispCondOp::branchTarget(const PowerISA::PCState ) const
+BranchDispCondOp::branchTarget(ThreadContext *tc) const
{
-if (aa) {
-return bd;
-} else {
-return pc.pc() + bd;
-}
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr;
+
+if (aa)
+addr = bd;
+else
+addr = tc->pcState().pc() + bd;
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -146,8 +157,9 @@
PowerISA::PCState
BranchRegCondOp::branchTarget(ThreadContext *tc) const
{
-Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
-return addr & -4ULL;
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
+return msr.sf ? addr : addr & UINT32_MAX;
}
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 5c5982c..cad91c2 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -87,7 +87,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
@@ -158,7 +158,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
diff --git a/src/arch/power/isa/formats/branch.isa
b/src/arch/power/isa/formats/branch.isa
index b970bc0..efb5f06 100644
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -87,11 +87,11 @@
# Check the condition register (CR) allows the branch to be taken.
def GetCondCode(br_code):
-cond_code = 'if (condOk(CR)) {\n'
+cond_code = 'Msr msr = MSR;\n'
+cond_code += 'if (condOk(CR)) {\n'
cond_code += '' + br_code + '\n'
-cond_code += '} else {\n'
-cond_code += 'NIA = NIA;\n'
cond_code += '}\n'
+cond_code += 'NIA = msr.sf ? NIA : NIA & UINT32_MAX;\n'
return cond_code
# Check the condition register (CR) and count register (CTR) allow the
@@ -99,11 +99,11 @@
# register too. This takes place in ctrOk within BranchCondOp classes.
def GetCtrCondCode(br_code):
cond_code = 'uint64_t ctr = CTR;\n'
+cond_code += 'Msr msr = MSR;\n'
cond_code += 'if (ctrOk(ctr) && condOk(CR)) {\n'
cond_code
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add byte order attribute for PC state
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40940 )
Change subject: arch-power: Add byte order attribute for PC state
..
arch-power: Add byte order attribute for PC state
This adds byte order as an attribute for PC state by
introducing a new PCState class. The decoder can now
fetch instructions bytes in the specified byte order
in preparation for multi-mode support.
Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40940
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/decoder.hh
M src/arch/power/pcstate.hh
2 files changed, 37 insertions(+), 2 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index 4e0c92b..20726a0 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -68,7 +68,7 @@
void
moreBytes(const PCState , Addr fetchPC)
{
-emi = betoh(emi);
+emi = gtoh(emi, pc.byteOrder());
instDone = true;
}
diff --git a/src/arch/power/pcstate.hh b/src/arch/power/pcstate.hh
index 9553c73..d0757839 100644
--- a/src/arch/power/pcstate.hh
+++ b/src/arch/power/pcstate.hh
@@ -30,6 +30,8 @@
#define __ARCH_POWER_PCSTATE_HH__
#include "arch/generic/types.hh"
+#include "arch/power/types.hh"
+#include "enums/ByteOrder.hh"
namespace gem5
{
@@ -37,7 +39,40 @@
namespace PowerISA
{
-typedef GenericISA::SimplePCState<4> PCState;
+class PCState : public GenericISA::SimplePCState<4>
+{
+ private:
+typedef GenericISA::SimplePCState<4> Base;
+ByteOrder guestByteOrder = ByteOrder::big;
+
+ public:
+PCState()
+{}
+
+void
+set(Addr val)
+{
+Base::set(val);
+npc(val + 4);
+}
+
+PCState(Addr val)
+{
+set(val);
+}
+
+ByteOrder
+byteOrder() const
+{
+return guestByteOrder;
+}
+
+void
+byteOrder(ByteOrder order)
+{
+guestByteOrder = order;
+}
+};
} // namespace PowerISA
} // namespace gem5
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40940
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Gerrit-Change-Number: 40940
Gerrit-PatchSet: 11
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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