[gem5-dev] Change in gem5/gem5[develop]: python: Fix L1 data cache size in cache components
Austin Harris has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/51452 ) Change subject: python: Fix L1 data cache size in cache components .. python: Fix L1 data cache size in cache components Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51452 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py 2 files changed, 15 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py index 03150da..ce04f46 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py @@ -102,7 +102,7 @@ ] self.l1dcaches = [ -L1DCache(size=self._l1i_size) +L1DCache(size=self._l1d_size) for i in range(board.get_processor().get_num_cores()) ] # ITLB Page walk caches diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py index eb4dae1..cd55c6e 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py @@ -127,7 +127,7 @@ for i in range(board.get_processor().get_num_cores()) ] self.l1dcaches = [ -L1DCache(size=self._l1i_size) +L1DCache(size=self._l1d_size) for i in range(board.get_processor().get_num_cores()) ] self.l2buses = [ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51452 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9 Gerrit-Change-Number: 51452 Gerrit-PatchSet: 2 Gerrit-Owner: Austin Harris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Fix argparse description in simple_binary_run.py
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/51451 ) Change subject: tests: Fix argparse description in simple_binary_run.py .. tests: Fix argparse description in simple_binary_run.py Change-Id: I3a86cf9e3326a06f442315d2510c5aec326af358 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51451 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M tests/gem5/configs/simple_binary_run.py 1 file changed, 14 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/gem5/configs/simple_binary_run.py b/tests/gem5/configs/simple_binary_run.py index 2c27ef7..229cebd 100644 --- a/tests/gem5/configs/simple_binary_run.py +++ b/tests/gem5/configs/simple_binary_run.py @@ -43,8 +43,7 @@ import argparse parser = argparse.ArgumentParser( -description="A script to run the gem5 boot test. This test boots the " -"linux kernel." +description="A gem5 script for running simple binaries in SE mode." ) parser.add_argument( -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51451 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3a86cf9e3326a06f442315d2510c5aec326af358 Gerrit-Change-Number: 51451 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: Rearrange functions to be next to the code that uses them.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49402 )
(
19 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: scons: Rearrange functions to be next to the code that
uses them.
..
scons: Rearrange functions to be next to the code that uses them.
The code which generated SimObject related param wrappers, cxx wrappers,
enum headers, etc was organized strangely. All the functions which
were used as SCons Actions were listed next to each other, and then all
the code which would set up each of those types of files and actually
use the Actions were next to each other.
This change rearranges that code so that the Action function is
immediately before the code which applies it. Or in other words, this
section of the SConscript is now grouped by the files being created,
rather than the type of the piece of machinery being defined to do that.
Change-Id: Ideee7bd44dac89c51840ec5970d95f6ccbbd1c8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49402
Tested-by: kokoro
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
---
M src/SConscript
1 file changed, 73 insertions(+), 48 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/SConscript b/src/SConscript
index fd5b9f9..18f7d12 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -645,6 +645,8 @@
# Create all of the SimObject param headers and enum headers
#
+# Generate all of the SimObject param C++ struct header files
+
def createSimObjectParamStruct(target, source, env):
assert len(target) == 1 and len(source) == 1
@@ -655,54 +657,6 @@
obj.cxx_param_decl(code)
code.write(target[0].abspath)
-def createSimObjectCxxConfig(is_header):
-def body(target, source, env):
-assert len(target) == 1 and len(source) == 1
-
-name = source[0].get_contents().decode('utf-8')
-obj = sim_objects[name]
-
-code = code_formatter()
-obj.cxx_config_param_file(code, is_header)
-code.write(target[0].abspath)
-return body
-
-def createEnumStrings(target, source, env):
-assert len(target) == 1 and len(source) == 2
-
-name = source[0].get_text_contents()
-use_python = source[1].read()
-obj = all_enums[name]
-
-code = code_formatter()
-obj.cxx_def(code)
-if use_python:
-obj.pybind_def(code)
-code.write(target[0].abspath)
-
-def createEnumDecls(target, source, env):
-assert len(target) == 1 and len(source) == 1
-
-name = source[0].get_text_contents()
-obj = all_enums[name]
-
-code = code_formatter()
-obj.cxx_decl(code)
-code.write(target[0].abspath)
-
-def createSimObjectWrappers(target, source, env):
-name = source[0].get_text_contents()
-obj = sim_objects[name]
-
-code = code_formatter()
-# We want to generate a single .cc file which contains most of the
-# SimObject autogenerated code to reduce the number of files to
compile and
-# link. We need to pass in whether python is enabled so that the pybind
-# wrappers are only generated when python is enabled
-obj.params_create_decl(code, env['USE_PYTHON'])
-code.write(target[0].abspath)
-
-# Generate all of the SimObject param C++ struct header files
params_hh_files = []
for name,simobj in sorted(sim_objects.items()):
# If this simobject's source changes, we need to regenerate the header.
@@ -724,6 +678,18 @@
# C++ parameter description files
if GetOption('with_cxx_config'):
+def createSimObjectCxxConfig(is_header):
+def body(target, source, env):
+assert len(target) == 1 and len(source) == 1
+
+name = source[0].get_contents().decode('utf-8')
+obj = sim_objects[name]
+
+code = code_formatter()
+obj.cxx_config_param_file(code, is_header)
+code.write(target[0].abspath)
+return body
+
for name,simobj in sorted(sim_objects.items()):
py_source = PySource.modules[simobj.__module__]
extra_deps = [ py_source.tnode ]
@@ -783,6 +749,29 @@
Source(cxx_config_init_cc_file)
# Generate all enum header files
+def createEnumStrings(target, source, env):
+assert len(target) == 1 and len(source) == 2
+
+name = source[0].get_text_contents()
+use_python = source[1].read()
+obj = all_enums[name]
+
+code = code_formatter()
+obj.cxx_def(code)
+if use_python:
+obj.pybind_def(code)
+code.write(target[0].abspath)
+
+def createEnumDecls(target, source, env):
+assert len(target) == 1 and len(source) == 1
+
+name = source[0].get_text_contents()
+obj = all_enums[name]
+
+code = code_formatter()
+obj.cxx_decl(code)
+code.write(target[0].abspath)
+
for name,enum in
[gem5-dev] Change in gem5/gem5[develop]: scons: Pull the code which generates debug/flags.cc into a helper scr...
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49401 )
Change subject: scons: Pull the code which generates debug/flags.cc into a
helper script.
..
scons: Pull the code which generates debug/flags.cc into a helper script.
Change-Id: Ib4ce51ae0311428e3bcd2dae431cfb0abe185c5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49401
Reviewed-by: Yu-hsin Wang
Maintainer: Gabe Black
Tested-by: kokoro
---
A build_tools/debugflagcc.py
M src/SConscript
2 files changed, 148 insertions(+), 52 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/build_tools/debugflagcc.py b/build_tools/debugflagcc.py
new file mode 100644
index 000..3dfcbad
--- /dev/null
+++ b/build_tools/debugflagcc.py
@@ -0,0 +1,123 @@
+# Copyright (c) 2018, 2020 ARM Limited
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import collections
+import sys
+
+from code_formatter import code_formatter
+
+def usage():
+print(f"Usage: {sys.argv[0]} CC [NAME DESC FMT COMPONENTS]...",
+file=sys.stderr)
+sys.exit(1)
+
+if len(sys.argv) < 2:
+usage()
+
+cc = sys.argv[1]
+
+
+FlagInfo = collections.namedtuple('FlagInfo',
+['name', 'desc', 'fmt', 'components'])
+
+flags = []
+
+pos = 2
+# Extract groups of arguments for each flag.
+while pos < len(sys.argv):
+if len(sys.argv) < pos + 4:
+usage()
+
+name, desc, fmt, components = sys.argv[pos:pos+4]
+pos += 4
+fmt = fmt.lower()
+if fmt == 'true':
+fmt = True
+elif fmt == 'false':
+fmt = False
+else:
+print(f'Unrecognized "FMT" value {fmt}', file=sys.stderr)
+sys.exit(1)
+components = components.split(':') if components else []
+flags.append(FlagInfo(name, desc, fmt, components))
+
+
+code = code_formatter()
+
+# File header.
+code('''
+#include "base/compiler.hh" // For namespace deprecation
+#include "base/debug.hh"
+
+namespace gem5
+{
+
+GEM5_DEPRECATED_NAMESPACE(Debug, debug);
+namespace debug
+{
+''')
+
+# Group the flags into either simple flags or compound flags.
+simple_flags = sorted(filter(lambda f: not f.components, flags))
+compound_flags = sorted(filter(lambda f: f.components, flags))
+
+# We intentionally make flag a reference to a heap allocated object so
+# (1) It has a similar interface to a global object like before
+# (2) It does not get destructed at the end of simulation
+# The second property is desirable as global objects from different
+# translation units do not have a defined destruction order, so it'll
+# be unsafe to access debug flags in their destructor in such cases.
+for flag in simple_flags:
+name, desc, components, fmt = \
+flag.name, flag.desc, flag.components,
[gem5-dev] Change in gem5/gem5[develop]: misc: Using OS::size_t in syscall signature
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51489 )
Change subject: misc: Using OS::size_t in syscall signature
..
misc: Using OS::size_t in syscall signature
Using the host size_t is confusing the guest ABI engine every time
the host and the guest adopt a different data model (ILP32 vs LP64)
For example when a LP64 machine is running an ILP32 application in SE
mode, "size_t" will wrongly inform the guest ABI engine to retrieve the
argument by loading a 64 bit (instead of 32) value from the stack
JIRA: https://gem5.atlassian.net/browse/GEM5-1074
Change-Id: Id7d7740ac429f534a4089331bedf21dc3951bbad
Signed-off-by: Giacomo Travaglini
---
M src/arch/mips/linux/se_workload.cc
M src/arch/sparc/linux/syscalls.cc
M src/arch/power/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.cc
M src/arch/x86/linux/syscall_tbl32.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/arch/arm/freebsd/se_workload.cc
M src/arch/arm/linux/se_workload.cc
M src/arch/x86/linux/syscall_tbl64.cc
10 files changed, 239 insertions(+), 236 deletions(-)
diff --git a/src/arch/arm/freebsd/se_workload.cc
b/src/arch/arm/freebsd/se_workload.cc
index 542510b..66e587e 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -136,7 +136,7 @@
{4, "write", writeFunc },
{ 17, "obreak", brkFunc },
{ 54, "ioctl", ioctlFunc },
-{ 58, "readlink", readlinkFunc },
+{ 58, "readlink", readlinkFunc },
{ 117, "getrusage", getrusageFunc },
{ 189, "fstat", fstatFunc },
#if !defined ( __GNU_LIBRARY__ )
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index 450d540..c715e1d 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -216,13 +216,13 @@
{ base + 81, "setgroups" },
{ base + 82, "reserved#82" },
{ base + 83, "symlink" },
-{ base + 85, "readlink", readlinkFunc },
+{ base + 85, "readlink", readlinkFunc },
{ base + 86, "uselib" },
{ base + 87, "swapon" },
{ base + 88, "reboot" },
{ base + 89, "readdir" },
{ base + 90, "mmap", mmapFunc },
-{ base + 91, "munmap", munmapFunc },
+{ base + 91, "munmap", munmapFunc },
{ base + 92, "truncate", truncateFunc },
{ base + 93, "ftruncate", ftruncateFunc },
{ base + 94, "fchmod" },
@@ -413,9 +413,9 @@
{ base + 287, "getpeername" },
{ base + 288, "socketpair" },
{ base + 289, "send" },
-{ base + 290, "sendto", sendtoFunc },
+{ base + 290, "sendto", sendtoFunc },
{ base + 291, "recv" },
-{ base + 292, "recvfrom", recvfromFunc },
+{ base + 292, "recvfrom", recvfromFunc },
{ base + 293, "shutdown" },
{ base + 294, "setsockopt" },
{ base + 295, "getsockopt" },
@@ -708,8 +708,8 @@
{ base + 203, "connect" },
{ base + 204, "getsockname" },
{ base + 205, "getpeername" },
-{ base + 206, "sendto", sendtoFunc },
-{ base + 207, "recvfrom", recvfromFunc },
+{ base + 206, "sendto", sendtoFunc },
+{ base + 207, "recvfrom", recvfromFunc },
{ base + 208, "setsockopt" },
{ base + 209, "getsockopt" },
{ base + 210, "shutdown" },
@@ -717,7 +717,7 @@
{ base + 212, "recvmsg" },
{ base + 213, "readahead" },
{ base + 214, "brk", brkFunc },
-{ base + 215, "munmap", munmapFunc },
+{ base + 215, "munmap", munmapFunc },
{ base + 216, "mremap", mremapFunc },
{ base + 217, "add_key" },
{ base + 218, "request_key" },
@@ -769,7 +769,7 @@
{ base + 1032, "lchown" },
{ base + 1033, "access", accessFunc },
{ base + 1034, "rename", renameFunc },
-{ base + 1035, "readlink", readlinkFunc },
+{ base + 1035, "readlink", readlinkFunc },
{ base + 1036, "symlink" },
{ base + 1037, "utimes" },
{ base + 1038, "stat64", stat64Func },
diff --git a/src/arch/mips/linux/se_workload.cc
b/src/arch/mips/linux/se_workload.cc
index 647c0ca..09752d1 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -243,13 +243,13 @@
{ 4082, "reserved#82" },
{ 4083, "symlink" },
{ 4084, "unused#84" },
-{ 4085, "readlink", readlinkFunc },
+{ 4085, "readlink", readlinkFunc },
{ 4086, "uselib" },
{ 4087, "swapon", gethostnameFunc },
{ 4088, "reboot" },
{ 4089, "readdir" },
{ 4090, "mmap", mmapFunc },
-{ 4091, "munmap",munmapFunc },
+{ 4091, "munmap",munmapFunc },
{ 4092, "truncate", truncateFunc },
{ 4093, "ftruncate", ftruncateFunc },
{ 4094, "fchmod", fchmodFunc },
diff --git
[gem5-dev] Change in gem5/gem5[develop]: misc: Using OS::off_t in syscall signature
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51490 )
Change subject: misc: Using OS::off_t in syscall signature
..
misc: Using OS::off_t in syscall signature
Change-Id: Iefa1e207a3e825959b0fe8df30e6be182d73a0f8
Signed-off-by: Giacomo Travaglini
---
M src/arch/mips/linux/se_workload.cc
M src/arch/power/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.cc
M src/arch/x86/linux/syscall_tbl32.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/arch/arm/linux/se_workload.cc
M src/arch/x86/linux/syscall_tbl64.cc
8 files changed, 92 insertions(+), 89 deletions(-)
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index c715e1d..3755dec 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -223,8 +223,8 @@
{ base + 89, "readdir" },
{ base + 90, "mmap", mmapFunc },
{ base + 91, "munmap", munmapFunc },
-{ base + 92, "truncate", truncateFunc },
-{ base + 93, "ftruncate", ftruncateFunc },
+{ base + 92, "truncate", truncateFunc },
+{ base + 93, "ftruncate", ftruncateFunc },
{ base + 94, "fchmod" },
{ base + 95, "fchown", fchownFunc },
{ base + 96, "getpriority" },
@@ -545,7 +545,7 @@
{ base + 44, "fstatfs64" },
{ base + 45, "truncate64" },
{ base + 46, "ftruncate64", ftruncate64Func },
-{ base + 47, "fallocate", fallocateFunc },
+{ base + 47, "fallocate", fallocateFunc },
{ base + 48, "faccessat", faccessatFunc },
{ base + 49, "chdir" },
{ base + 50, "fchdir" },
@@ -781,8 +781,8 @@
{ base + 1044, "eventfd" },
{ base + 1045, "signalfd" },
{ base + 1046, "sendfile" },
-{ base + 1047, "ftruncate", ftruncateFunc },
-{ base + 1048, "truncate", truncateFunc },
+{ base + 1047, "ftruncate", ftruncateFunc },
+{ base + 1048, "truncate", truncateFunc },
{ base + 1049, "stat", statFunc },
{ base + 1050, "lstat" },
{ base + 1051, "fstat", fstatFunc },
diff --git a/src/arch/mips/linux/se_workload.cc
b/src/arch/mips/linux/se_workload.cc
index 09752d1..6767bf7 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -250,8 +250,8 @@
{ 4089, "readdir" },
{ 4090, "mmap", mmapFunc },
{ 4091, "munmap",munmapFunc },
-{ 4092, "truncate", truncateFunc },
-{ 4093, "ftruncate", ftruncateFunc },
+{ 4092, "truncate", truncateFunc },
+{ 4093, "ftruncate", ftruncateFunc },
{ 4094, "fchmod", fchmodFunc },
{ 4095, "fchown", fchownFunc },
{ 4096, "getpriority" },
diff --git a/src/arch/power/linux/se_workload.cc
b/src/arch/power/linux/se_workload.cc
index 975d5dd..9b54fd8 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -199,8 +199,8 @@
{ 89, "readdir" },
{ 90, "mmap", mmapFunc },
{ 91, "munmap",munmapFunc },
-{ 92, "truncate", truncateFunc },
-{ 93, "ftruncate", ftruncateFunc },
+{ 92, "truncate", truncateFunc },
+{ 93, "ftruncate", ftruncateFunc },
{ 94, "fchmod" },
{ 95, "fchown" },
{ 96, "getpriority" },
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index 3b0079d..2e2a7d2 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -169,9 +169,9 @@
{ 42, "nfsservctl" },
{ 43, "statfs", statfsFunc },
{ 44, "fstatfs", fstatfsFunc },
-{ 45, "truncate", truncateFunc },
+{ 45, "truncate", truncateFunc },
{ 46, "ftruncate", ftruncate64Func },
-{ 47, "fallocate", fallocateFunc },
+{ 47, "fallocate", fallocateFunc },
{ 48, "faccessat", faccessatFunc },
{ 49, "chdir" },
{ 50, "fchdir" },
@@ -500,9 +500,9 @@
{ 42, "nfsservctl" },
{ 43, "statfs", statfsFunc },
{ 44, "fstatfs", fstatfsFunc },
-{ 45, "truncate", truncateFunc },
-{ 46, "ftruncate", ftruncateFunc },
-{ 47, "fallocate", fallocateFunc },
+{ 45, "truncate", truncateFunc },
+{ 46, "ftruncate", ftruncateFunc },
+{ 47, "fallocate", fallocateFunc },
{ 48, "faccessat", faccessatFunc },
{ 49, "chdir" },
{ 50, "fchdir" },
@@ -749,8 +749,8 @@
{ 1044, "eventfd" },
{ 1045, "signalfd" },
{ 1046, "sendfile" },
-{ 1047, "ftruncate", ftruncateFunc },
-{ 1048, "truncate", truncateFunc },
+{ 1047, "ftruncate", ftruncateFunc },
+{ 1048, "truncate", truncateFunc },
{ 1049, "stat", statFunc },
{ 1050, "lstat", lstatFunc },
{ 1051, "fstat", fstatFunc },
diff --git a/src/arch/x86/linux/syscall_tbl32.cc
b/src/arch/x86/linux/syscall_tbl32.cc
index 43b2a71..7f8e905 100644
---
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add sendto and recvfrom implementations to the Syscall Table
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51487 )
Change subject: arch-arm: Add sendto and recvfrom implementations to the
Syscall Table
..
arch-arm: Add sendto and recvfrom implementations to the Syscall Table
Change-Id: Id3fd65778ad3b5af8ec54381a0b8824115c309f6
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/linux/se_workload.cc
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index fdbdbef..d3bf0ea 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -413,9 +413,9 @@
{ base + 287, "getpeername" },
{ base + 288, "socketpair" },
{ base + 289, "send" },
-{ base + 290, "sendto" },
+{ base + 290, "sendto", sendtoFunc },
{ base + 291, "recv" },
-{ base + 292, "recvfrom" },
+{ base + 292, "recvfrom", recvfromFunc },
{ base + 293, "shutdown" },
{ base + 294, "setsockopt" },
{ base + 295, "getsockopt" },
@@ -708,8 +708,8 @@
{ base + 203, "connect" },
{ base + 204, "getsockname" },
{ base + 205, "getpeername" },
-{ base + 206, "sendto" },
-{ base + 207, "recvfrom" },
+{ base + 206, "sendto", sendtoFunc },
+{ base + 207, "recvfrom", recvfromFunc },
{ base + 208, "setsockopt" },
{ base + 209, "getsockopt" },
{ base + 210, "shutdown" },
--
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Gerrit-Change-Id: Id3fd65778ad3b5af8ec54381a0b8824115c309f6
Gerrit-Change-Number: 51487
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add ftruncate implementation to the Syscall Table
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51488 )
Change subject: arch-arm: Add ftruncate implementation to the Syscall Table
..
arch-arm: Add ftruncate implementation to the Syscall Table
Change-Id: I27c526c5c8107f888aee7c99b952f086d4fa0e35
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/linux/se_workload.cc
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index d3bf0ea..450d540 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -545,7 +545,7 @@
{ base + 44, "fstatfs64" },
{ base + 45, "truncate64" },
{ base + 46, "ftruncate64", ftruncate64Func },
-{ base + 47, "fallocate" },
+{ base + 47, "fallocate", fallocateFunc },
{ base + 48, "faccessat", faccessatFunc },
{ base + 49, "chdir" },
{ base + 50, "fchdir" },
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I27c526c5c8107f888aee7c99b952f086d4fa0e35
Gerrit-Change-Number: 51488
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: tests: add additional space in weekly DNNMark tests
Matt Sinclair has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51453 )
Change subject: tests: add additional space in weekly DNNMark tests
..
tests: add additional space in weekly DNNMark tests
Add space between -c and binary name for all DNNMark tests to conform to
the other tests style and reduce confusion.
Change-Id: I6d0777ba2186f0eedfe7e99db51161106837a624
---
M tests/weekly.sh
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tests/weekly.sh b/tests/weekly.sh
index 5a8accc..5997ae9 100755
--- a/tests/weekly.sh
+++ b/tests/weekly.sh
@@ -128,7 +128,7 @@
-w "${gem5_root}/gem5-resources/src/gpu/DNNMark"
gcr.io/gem5-test/gcn-gpu \
"${gem5_root}/build/GCN3_X86/gem5.opt" "${gem5_root}/configs/example/apu_se.py"
-n3
\
--benchmark-root="${gem5_root}/gem5-resources/src/gpu/DNNMark/build/benchmarks/test_fwd_softmax"
\
- -cdnnmark_test_fwd_softmax \
+ -c dnnmark_test_fwd_softmax \
--options="-config
${gem5_root}/gem5-resources/src/gpu/DNNMark/config_example/softmax_config.dnnmark
\
-mmap ${gem5_root}/gem5-resources/src/gpu/DNNMark/mmap.bin"
@@ -137,7 +137,7 @@
-w "${gem5_root}/gem5-resources/src/gpu/DNNMark"
gcr.io/gem5-test/gcn-gpu \
"${gem5_root}/build/GCN3_X86/gem5.opt" "${gem5_root}/configs/example/apu_se.py"
-n3
\
--benchmark-root="${gem5_root}/gem5-resources/src/gpu/DNNMark/build/benchmarks/test_fwd_pool"
\
- -cdnnmark_test_fwd_pool \
+ -c dnnmark_test_fwd_pool \
--options="-config
${gem5_root}/gem5-resources/src/gpu/DNNMark/config_example/pool_config.dnnmark
\
-mmap ${gem5_root}/gem5-resources/src/gpu/DNNMark/mmap.bin"
@@ -146,7 +146,7 @@
-w "${gem5_root}/gem5-resources/src/gpu/DNNMark"
gcr.io/gem5-test/gcn-gpu \
"${gem5_root}/build/GCN3_X86/gem5.opt" "${gem5_root}/configs/example/apu_se.py"
-n3
\
--benchmark-root="${gem5_root}/gem5-resources/src/gpu/DNNMark/build/benchmarks/test_bwd_bn"
\
- -cdnnmark_test_bwd_bn \
+ -c dnnmark_test_bwd_bn \
--options="-config
${gem5_root}/gem5-resources/src/gpu/DNNMark/config_example/bn_config.dnnmark
\
-mmap ${gem5_root}/gem5-resources/src/gpu/DNNMark/mmap.bin"
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I6d0777ba2186f0eedfe7e99db51161106837a624
Gerrit-Change-Number: 51453
Gerrit-PatchSet: 1
Gerrit-Owner: Matt Sinclair
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix L1 data cache size in cache components
Austin Harris has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/51452 ) Change subject: python: Fix L1 data cache size in cache components .. python: Fix L1 data cache size in cache components Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9 --- M src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py index 03150da..ce04f46 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py @@ -102,7 +102,7 @@ ] self.l1dcaches = [ -L1DCache(size=self._l1i_size) +L1DCache(size=self._l1d_size) for i in range(board.get_processor().get_num_cores()) ] # ITLB Page walk caches diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py index eb4dae1..cd55c6e 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py @@ -127,7 +127,7 @@ for i in range(board.get_processor().get_num_cores()) ] self.l1dcaches = [ -L1DCache(size=self._l1i_size) +L1DCache(size=self._l1d_size) for i in range(board.get_processor().get_num_cores()) ] self.l2buses = [ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51452 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9 Gerrit-Change-Number: 51452 Gerrit-PatchSet: 1 Gerrit-Owner: Austin Harris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Fix argparse description in simple_binary_run.py
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/51451 ) Change subject: tests: Fix argparse description in simple_binary_run.py .. tests: Fix argparse description in simple_binary_run.py Change-Id: I3a86cf9e3326a06f442315d2510c5aec326af358 --- M tests/gem5/configs/simple_binary_run.py 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/tests/gem5/configs/simple_binary_run.py b/tests/gem5/configs/simple_binary_run.py index 2c27ef7..229cebd 100644 --- a/tests/gem5/configs/simple_binary_run.py +++ b/tests/gem5/configs/simple_binary_run.py @@ -43,8 +43,7 @@ import argparse parser = argparse.ArgumentParser( -description="A script to run the gem5 boot test. This test boots the " -"linux kernel." +description="A gem5 script for running simple binaries in SE mode." ) parser.add_argument( -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51451 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3a86cf9e3326a06f442315d2510c5aec326af358 Gerrit-Change-Number: 51451 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: HTMSequencer stats initialized twice
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51407 )
Change subject: mem-ruby: HTMSequencer stats initialized twice
..
mem-ruby: HTMSequencer stats initialized twice
HTMSequencer stats are already initialized in the constructor
This is a bug from:
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/36478
Change-Id: Id7d9b11f45035a46af32584ed86470c65d2a80b6
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51407
Reviewed-by: Hoa Nguyen
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/system/HTMSequencer.cc
M src/mem/ruby/system/HTMSequencer.hh
2 files changed, 21 insertions(+), 35 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Hoa Nguyen: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/HTMSequencer.cc
b/src/mem/ruby/system/HTMSequencer.cc
index 5157842..98f6d35 100644
--- a/src/mem/ruby/system/HTMSequencer.cc
+++ b/src/mem/ruby/system/HTMSequencer.cc
@@ -210,40 +210,6 @@
}
void
-HTMSequencer::regStats()
-{
-// hardware transactional memory
-m_htm_transaction_cycles
-.init(10)
-.name(name() + ".htm_transaction_cycles")
-.desc("number of cycles spent in an outer transaction")
-.flags(statistics::pdf | statistics::dist | statistics::nozero |
-statistics::nonan)
-;
-m_htm_transaction_instructions
-.init(10)
-.name(name() + ".htm_transaction_instructions")
-.desc("number of instructions spent in an outer transaction")
-.flags(statistics::pdf | statistics::dist | statistics::nozero |
-statistics::nonan)
-;
-auto num_causes = static_cast(HtmFailureFaultCause::NUM_CAUSES);
-m_htm_transaction_abort_cause
-.init(num_causes)
-.name(name() + ".htm_transaction_abort_cause")
-.desc("cause of htm transaction abort")
-.flags(statistics::total | statistics::pdf | statistics::dist |
-statistics::nozero)
-;
-
-for (unsigned cause_idx = 0; cause_idx < num_causes; ++cause_idx) {
-m_htm_transaction_abort_cause.subname(
-cause_idx,
-htmFailureToStr(HtmFailureFaultCause(cause_idx)));
-}
-}
-
-void
HTMSequencer::rubyHtmCallback(PacketPtr pkt,
const HtmFailedInCacheReason htm_return_code)
{
diff --git a/src/mem/ruby/system/HTMSequencer.hh
b/src/mem/ruby/system/HTMSequencer.hh
index 2f19f39..3b39331 100644
--- a/src/mem/ruby/system/HTMSequencer.hh
+++ b/src/mem/ruby/system/HTMSequencer.hh
@@ -68,7 +68,6 @@
bool empty() const override;
void print(std::ostream& out) const override;
-void regStats() override;
void wakeup() override;
private:
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id7d9b11f45035a46af32584ed86470c65d2a80b6
Gerrit-Change-Number: 51407
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: fix square and HeteroSync nightly regression command
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51247 )
Change subject: tests: fix square and HeteroSync nightly regression command
..
tests: fix square and HeteroSync nightly regression command
Square and HeteroSync's pre-built binaries were downloaded into the
tests folder in the nightly regression script, but the docker
command running them assumed we were in GEM5_ROOT. This commit
fixes this problem by specificying the benchmark root for the
applications.
Change-Id: I905c8bde7231bc708db01bff196fd85d99c7ceac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51247
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Bobby R. Bruce
---
M tests/nightly.sh
1 file changed, 24 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/nightly.sh b/tests/nightly.sh
index 6631bb0..89c7005 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -101,7 +101,7 @@
# basic GPU functionality is working.
docker run --rm -u $UID:$GUID --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}" gcr.io/gem5-test/gcn-gpu:latest build/GCN3_X86/gem5.opt
\
-configs/example/apu_se.py -n3 -c square
+configs/example/apu_se.py -n3 --benchmark-root="${gem5_root}/tests" -c
square
# get HeteroSync
wget -qN
http://dist.gem5.org/dist/develop/test-progs/heterosync/gcn3/allSyncPrims-1kernel
@@ -112,8 +112,8 @@
# atomics are tested.
docker run --rm -u $UID:$GUID --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}" gcr.io/gem5-test/gcn-gpu:latest build/GCN3_X86/gem5.opt
\
-configs/example/apu_se.py -n3 -callSyncPrims-1kernel \
---options="sleepMutex 10 16 4"
+configs/example/apu_se.py -n3 --benchmark-root="${gem5_root}/tests" \
+-c allSyncPrims-1kernel --options="sleepMutex 10 16 4"
# run HeteroSync LFBarr -- similar setup to sleepMutex above -- 16 WGs
# accessing unique data and then joining a lock-free barrier, 10 Ld/St per
@@ -122,5 +122,5 @@
# atomics are tested.
docker run --rm -u $UID:$GUID --volume "${gem5_root}":"${gem5_root}" -w \
"${gem5_root}" gcr.io/gem5-test/gcn-gpu:latest build/GCN3_X86/gem5.opt
\
-configs/example/apu_se.py -n3 -callSyncPrims-1kernel \
---options="lfTreeBarrUniq 10 16 4"
+configs/example/apu_se.py -n3 --benchmark-root="${gem5_root}/tests" \
+-c allSyncPrims-1kernel --options="lfTreeBarrUniq 10 16 4"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I905c8bde7231bc708db01bff196fd85d99c7ceac
Gerrit-Change-Number: 51247
Gerrit-PatchSet: 5
Gerrit-Owner: Matt Sinclair
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: kokoro
Gerrit-CC: Alex Dutu
Gerrit-CC: Kyle Roarty
Gerrit-CC: Matthew Poremba
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-hsa,gpu-compute: fix bug with gfx8 VAs for HSA Queues
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51371 )
Change subject: dev-hsa,gpu-compute: fix bug with gfx8 VAs for HSA Queues
..
dev-hsa,gpu-compute: fix bug with gfx8 VAs for HSA Queues
GFX7 (not supported in gem5) and GFX8 have a bug with how virtual
addresses are calculated for their HSA queues. The ROCr component of
ROCm solves this problem by doubling the HSA queue size that is
requested, then mapping all virtual addresses in the second half of the
queue to the same virtual addresses as the first half of the queue.
This commit fixes gem5's support to mimic this behavior.
Note that this change does not affect Vega's HSA queue support, because
according to the ROCm documentation, Vega does not have the same problem
as GCN3.
Change-Id: I133cf1acc3a00a0baded0c4c3c2a25f39effdb51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51371
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matthew Poremba
---
M src/dev/hsa/hsa_packet_processor.cc
M src/dev/hsa/hsa_packet_processor.hh
M src/gpu-compute/gpu_compute_driver.cc
M src/dev/hsa/hw_scheduler.cc
M src/dev/hsa/hw_scheduler.hh
5 files changed, 75 insertions(+), 17 deletions(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Matt Sinclair: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/hsa/hsa_packet_processor.cc
b/src/dev/hsa/hsa_packet_processor.cc
index 0427def..22124b1 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -44,6 +44,7 @@
#include "dev/dma_device.hh"
#include "dev/hsa/hsa_packet.hh"
#include "dev/hsa/hw_scheduler.hh"
+#include "enums/GfxVersion.hh"
#include "gpu-compute/gpu_command_processor.hh"
#include "mem/packet_access.hh"
#include "mem/page_table.hh"
@@ -100,13 +101,15 @@
HSAPacketProcessor::setDeviceQueueDesc(uint64_t hostReadIndexPointer,
uint64_t basePointer,
uint64_t queue_id,
- uint32_t size, int doorbellSize)
+ uint32_t size, int doorbellSize,
+ GfxVersion gfxVersion)
{
DPRINTF(HSAPacketProcessor,
"%s:base = %p, qID = %d, ze = %d\n", __FUNCTION__,
(void *)basePointer, queue_id, size);
hwSchdlr->registerNewQueue(hostReadIndexPointer,
- basePointer, queue_id, size, doorbellSize);
+ basePointer, queue_id, size, doorbellSize,
+ gfxVersion);
}
AddrRangeList
diff --git a/src/dev/hsa/hsa_packet_processor.hh
b/src/dev/hsa/hsa_packet_processor.hh
index 9545006..aabe24e 100644
--- a/src/dev/hsa/hsa_packet_processor.hh
+++ b/src/dev/hsa/hsa_packet_processor.hh
@@ -39,9 +39,11 @@
#include
#include "base/types.hh"
+#include "debug/HSAPacketProcessor.hh"
#include "dev/dma_virt_device.hh"
#include "dev/hsa/hsa.h"
#include "dev/hsa/hsa_queue.hh"
+#include "enums/GfxVersion.hh"
#include "params/HSAPacketProcessor.hh"
#include "sim/eventq.hh"
@@ -84,14 +86,16 @@
uint64_t hostReadIndexPtr;
bool stalledOnDmaBufAvailability;
bool dmaInProgress;
+GfxVersion gfxVersion;
HSAQueueDescriptor(uint64_t base_ptr, uint64_t db_ptr,
- uint64_t hri_ptr, uint32_t size)
+ uint64_t hri_ptr, uint32_t size,
+ GfxVersion gfxVersion)
: basePointer(base_ptr), doorbellPointer(db_ptr),
writeIndex(0), readIndex(0),
numElts(size / AQL_PACKET_SIZE), hostReadIndexPtr(hri_ptr),
stalledOnDmaBufAvailability(false),
-dmaInProgress(false)
+dmaInProgress(false), gfxVersion(gfxVersion)
{ }
uint64_t spaceRemaining() { return numElts - (writeIndex -
readIndex); }
uint64_t spaceUsed() { return writeIndex - readIndex; }
@@ -102,15 +106,38 @@
uint64_t ptr(uint64_t ix)
{
-/**
- * Sometimes queues report that their size is 512k, which would
- * indicate numElts of 0x2000. However, they only have 256k
- * mapped which means any index over 0x1000 will fail an
- * address translation.
+/*
+ * Based on ROCm Documentation:
+ * -
https://github.com/RadeonOpenCompute/ROCm_Documentation/blob/
+
10ca0a99bbd0252f5bf6f08d1503e59f1129df4a/ROCm_Libraries/
+ rocr/src/core/runtime/amd_aql_queue.cpp#L99
+ * -
https://github.com/RadeonOpenCompute/ROCm_Documentation/blob/
+
10ca0a99bbd0252f5bf6f08d1503e59f1129df4a/ROCm_Libraries/
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add fchownat implementation to the Syscall Table
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51052 )
Change subject: arch-arm: Add fchownat implementation to the Syscall Table
..
arch-arm: Add fchownat implementation to the Syscall Table
Change-Id: If2e05b84064886bd924348930a151c7c00877c38
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51052
Reviewed-by: Bobby R. Bruce
Reviewed-by: Richard Cooper
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/arch/arm/linux/se_workload.cc
1 file changed, 17 insertions(+), 2 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index c70dda0..fdbdbef 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -447,7 +447,7 @@
{ base + 322, "openat", openatFunc },
{ base + 323, "mkdirat" },
{ base + 324, "mknodat" },
-{ base + 325, "fchownat" },
+{ base + 325, "fchownat", fchownatFunc },
{ base + 326, "futimesat" },
{ base + 327, "fstatat64" },
{ base + 328, "unlinkat", unlinkatFunc },
@@ -552,7 +552,7 @@
{ base + 51, "chroot" },
{ base + 52, "fchmod" },
{ base + 53, "fchmodat" },
-{ base + 54, "fchownat" },
+{ base + 54, "fchownat", fchownatFunc },
{ base + 55, "fchown", fchownFunc },
{ base + 56, "openat", openatFunc },
{ base + 57, "close", closeFunc },
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If2e05b84064886bd924348930a151c7c00877c38
Gerrit-Change-Number: 51052
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Rewrite some syscalls to use a syscallImpl function
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51047 )
Change subject: sim-se: Rewrite some syscalls to use a syscallImpl function
..
sim-se: Rewrite some syscalls to use a syscallImpl function
The following at suffixed syscalls are implemented on top of their
CWD version
* readlinkat -> readlink
* unlinkat -> unlink
* renameat -> rename
* faccessat -> access
With this patch we are decoupling interface from implementation, moving
the latter into a separate syscallImpl function which will by called by
both syscall flavours
This is a required step towards properly implementing AT based syscalls
JIRA: https://gem5.atlassian.net/browse/GEM5-1098
Change-Id: I022e9876a2a0b9ddf2d70d10cd4e6851ba7ff094
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51047
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Gabe Black
Reviewed-by: Richard Cooper
---
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
2 files changed, 100 insertions(+), 11 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index a8b1221..2f73800 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -403,11 +403,18 @@
VPtr<> pathname, VPtr<> buf_ptr, size_t bufsiz)
{
std::string path;
-auto p = tc->getProcessPtr();
-
if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
return -EFAULT;
+return readlinkImpl(desc, tc, path, buf_ptr, bufsiz);
+}
+
+SyscallReturn
+readlinkImpl(SyscallDesc *desc, ThreadContext *tc,
+ std::string path, VPtr<> buf_ptr, size_t bufsiz)
+{
+auto p = tc->getProcessPtr();
+
// Adjust path for cwd and redirection
path = p->checkPathRedirect(path);
@@ -460,11 +467,16 @@
unlinkFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
{
std::string path;
-auto p = tc->getProcessPtr();
-
if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
return -EFAULT;
+return unlinkImpl(desc, tc, path);
+}
+
+SyscallReturn
+unlinkImpl(SyscallDesc *desc, ThreadContext *tc, std::string path)
+{
+auto p = tc->getProcessPtr();
path = p->checkPathRedirect(path);
int result = unlink(path.c_str());
@@ -531,8 +543,6 @@
renameFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> oldpath,
VPtr<> newpath)
{
-auto p = tc->getProcessPtr();
-
SETranslatingPortProxy proxy(tc);
std::string old_name;
if (!proxy.tryReadString(old_name, oldpath))
@@ -542,6 +552,15 @@
if (!proxy.tryReadString(new_name, newpath))
return -EFAULT;
+return renameImpl(desc, tc, old_name, new_name);
+}
+
+SyscallReturn
+renameImpl(SyscallDesc *desc, ThreadContext *tc,
+ std::string old_name, std::string new_name)
+{
+auto p = tc->getProcessPtr();
+
// Adjust path for cwd and redirection
old_name = p->checkPathRedirect(old_name);
new_name = p->checkPathRedirect(new_name);
@@ -550,6 +569,7 @@
return (result == -1) ? -errno : result;
}
+
SyscallReturn
truncateFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname,
off_t length)
@@ -1011,10 +1031,17 @@
VPtr<> pathname, mode_t mode)
{
std::string path;
-auto p = tc->getProcessPtr();
if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
return -EFAULT;
+return accessImpl(desc, tc, path, mode);
+}
+
+SyscallReturn
+accessImpl(SyscallDesc *desc, ThreadContext *tc,
+ std::string path, mode_t mode)
+{
+auto p = tc->getProcessPtr();
// Adjust path for cwd and redirection
path = p->checkPathRedirect(path);
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 8929f90..d98076d 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -191,10 +191,14 @@
/// Target readlink() handler.
SyscallReturn readlinkFunc(SyscallDesc *desc, ThreadContext *tc,
VPtr<> pathname, VPtr<> buf, size_t bufsiz);
+SyscallReturn readlinkImpl(SyscallDesc *desc, ThreadContext *tc,
+ std::string path, VPtr<> buf, size_t bufsiz);
/// Target unlink() handler.
SyscallReturn unlinkFunc(SyscallDesc *desc, ThreadContext *tc,
VPtr<> pathname);
+SyscallReturn unlinkImpl(SyscallDesc *desc, ThreadContext *tc,
+ std::string path);
/// Target link() handler
SyscallReturn linkFunc(SyscallDesc *desc, ThreadContext *tc,
@@ -221,6 +225,8 @@
/// Target rename() handler.
SyscallReturn renameFunc(SyscallDesc *desc, ThreadContext *tc,
VPtr<> oldpath, VPtr<> newpath);
+SyscallReturn renameImpl(SyscallDesc
[gem5-dev] Change in gem5/gem5[develop]: sim-se: Implement at suffixed syscalls
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51048 )
Change subject: sim-se: Implement at suffixed syscalls
..
sim-se: Implement at suffixed syscalls
All syscalls with the "at" suffix rely on a directory file descriptor
(dirfd) and a pathname, provided as arguments to the syscall
If the pathname is relative, then it is interpreted relative to the
directory referred to by the file descriptor dirfd (rather than relative
to the current working directory of the calling process)
Prior to this patch, only the openat syscall was properly implemented.
Other syscalls were discarding the dirfd argument and producing
a warning instead
JIRA: https://gem5.atlassian.net/browse/GEM5-1098
Change-Id: I0cc20c6ef79fca8c8d1c2c9a52eb54ede3d51312
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51048
Reviewed-by: Richard Cooper
Reviewed-by: Gabe Black
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/sim/syscall_emul.hh
1 file changed, 84 insertions(+), 49 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index d98076d..a7a7baf 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015, 2019-2020 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2019-2021 Arm Limited
* Copyright (c) 2015 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -380,6 +380,25 @@
SyscallReturn getsocknameFunc(SyscallDesc *desc, ThreadContext *tc,
int tgt_fd, VPtr<> addrPtr, VPtr<> lenPtr);
+template
+SyscallReturn
+atSyscallPath(ThreadContext *tc, int dirfd, std::string )
+{
+// If pathname is absolute, then dirfd is ignored.
+if (dirfd != OS::TGT_AT_FDCWD && !startswith(path, "/")) {
+auto process = tc->getProcessPtr();
+
+std::shared_ptr fdep = ((*process->fds)[dirfd]);
+auto ffdp = std::dynamic_pointer_cast(fdep);
+if (!ffdp)
+return -EBADF;
+
+path = ffdp->getFileName() + "/" + path;
+}
+
+return 0;
+}
+
/// Futex system call
/// Implemented by Daniel Sanchez
/// Used by printf's in multi-threaded apps
@@ -928,8 +947,10 @@
if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
return -EFAULT;
-if (dirfd != OS::TGT_AT_FDCWD)
-warn("unlinkat: first argument not AT_FDCWD; unlikely to work");
+// Modifying path from the directory descriptor
+if (auto res = atSyscallPath(tc, dirfd, path); !res.successful()) {
+return res;
+}
return unlinkImpl(desc, tc, path);
}
@@ -944,8 +965,10 @@
if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
return -EFAULT;
-if (dirfd != OS::TGT_AT_FDCWD)
-warn("faccessat: first argument not AT_FDCWD; unlikely to work");
+// Modifying path from the directory descriptor
+if (auto res = atSyscallPath(tc, dirfd, path); !res.successful()) {
+return res;
+}
return accessImpl(desc, tc, path, mode);
}
@@ -960,8 +983,10 @@
if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
return -EFAULT;
-if (dirfd != OS::TGT_AT_FDCWD)
-warn("openat: first argument not AT_FDCWD; unlikely to work");
+// Modifying path from the directory descriptor
+if (auto res = atSyscallPath(tc, dirfd, path); !res.successful()) {
+return res;
+}
return readlinkImpl(desc, tc, path, buf, bufsiz);
}
@@ -981,11 +1006,15 @@
if (!proxy.tryReadString(new_name, newpath))
return -EFAULT;
-if (olddirfd != OS::TGT_AT_FDCWD)
-warn("renameat: first argument not AT_FDCWD; unlikely to work");
+// Modifying old_name from the directory descriptor
+if (auto res = atSyscallPath(tc, olddirfd,
old_name); !res.successful()) {
+return res;
+}
-if (newdirfd != OS::TGT_AT_FDCWD)
-warn("renameat: third argument not AT_FDCWD; unlikely to work");
+// Modifying new_name from the directory descriptor
+if (auto res = atSyscallPath(tc, newdirfd,
new_name); !res.successful()) {
+return res;
+}
return renameImpl(desc, tc, old_name, new_name);
}
@@ -1233,39 +1262,6 @@
return 0;
}
-
-/// Target stat64() handler.
-template
-SyscallReturn
-stat64Func(SyscallDesc *desc, ThreadContext *tc,
- VPtr<> pathname, VPtr tgt_stat)
-{
-std::string path;
-auto process = tc->getProcessPtr();
-
-if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
-return -EFAULT;
-
-// Adjust path for cwd and redirection
-path = process->checkPathRedirect(path);
-
-#if NO_STAT64
-struct stat hostBuf;
-int
[gem5-dev] Change in gem5/gem5[develop]: sim-se: Implemnt fchownat syscall
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51050 )
Change subject: sim-se: Implemnt fchownat syscall
..
sim-se: Implemnt fchownat syscall
JIRA: https://gem5.atlassian.net/browse/GEM5-1098
Change-Id: I46f9a5ba30a27c29a8a50323a0fb95074016ddb2
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51050
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
2 files changed, 46 insertions(+), 2 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 2f73800..3a732c0 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -657,11 +657,18 @@
VPtr<> pathname, uint32_t owner, uint32_t group)
{
std::string path;
-auto p = tc->getProcessPtr();
-
if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
return -EFAULT;
+return chownImpl(desc, tc, path, owner, group);
+}
+
+SyscallReturn
+chownImpl(SyscallDesc *desc, ThreadContext *tc,
+ std::string path, uint32_t owner, uint32_t group)
+{
+auto p = tc->getProcessPtr();
+
/* XXX endianess */
uid_t hostOwner = owner;
gid_t hostGroup = group;
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index a7a7baf..e46f059 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -256,6 +256,8 @@
/// Target chown() handler.
SyscallReturn chownFunc(SyscallDesc *desc, ThreadContext *tc,
VPtr<> pathname, uint32_t owner, uint32_t group);
+SyscallReturn chownImpl(SyscallDesc *desc, ThreadContext *tc,
+std::string path, uint32_t owner, uint32_t group);
/// Target getpgrpFunc() handler.
SyscallReturn getpgrpFunc(SyscallDesc *desc, ThreadContext *tc);
@@ -1019,6 +1021,25 @@
return renameImpl(desc, tc, old_name, new_name);
}
+/// Target fchownat() handler
+template
+SyscallReturn
+fchownatFunc(SyscallDesc *desc, ThreadContext *tc,
+ int dirfd, VPtr<> pathname, uint32_t owner, uint32_t group,
+ int flags)
+{
+std::string path;
+if (!SETranslatingPortProxy(tc).tryReadString(path, pathname))
+return -EFAULT;
+
+// Modifying path from the directory descriptor
+if (auto res = atSyscallPath(tc, dirfd, path); !res.successful()) {
+return res;
+}
+
+return chownImpl(desc, tc, path, owner, group);
+}
+
/// Target sysinfo() handler.
template
SyscallReturn
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I46f9a5ba30a27c29a8a50323a0fb95074016ddb2
Gerrit-Change-Number: 51050
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add existing at impl to ArmLinux32 Syscall Table
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51049 )
Change subject: arch-arm: Add existing at impl to ArmLinux32 Syscall Table
..
arch-arm: Add existing at impl to ArmLinux32 Syscall Table
Change-Id: Ia1e7cb02ce9513e6ef5d7037dafc84fbd52b8504
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51049
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Richard Cooper
---
M src/arch/arm/linux/se_workload.cc
1 file changed, 18 insertions(+), 4 deletions(-)
Approvals:
Richard Cooper: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index 8ca3684..0d9165e 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -450,13 +450,13 @@
{ base + 325, "fchownat" },
{ base + 326, "futimesat" },
{ base + 327, "fstatat64" },
-{ base + 328, "unlinkat" },
-{ base + 329, "renameat" },
+{ base + 328, "unlinkat", unlinkatFunc },
+{ base + 329, "renameat", renameatFunc },
{ base + 330, "linkat" },
{ base + 331, "symlinkat" },
-{ base + 332, "readlinkat" },
+{ base + 332, "readlinkat", readlinkatFunc },
{ base + 333, "fchmodat" },
-{ base + 334, "faccessat" },
+{ base + 334, "faccessat", faccessatFunc },
{ base + 335, "pselect6" },
{ base + 336, "ppoll" },
{ base + 337, "unshare" },
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51049
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia1e7cb02ce9513e6ef5d7037dafc84fbd52b8504
Gerrit-Change-Number: 51049
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add fchown implementation to the Syscall Table
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51051 )
Change subject: arch-arm: Add fchown implementation to the Syscall Table
..
arch-arm: Add fchown implementation to the Syscall Table
Change-Id: I4696e305383492e3bf3cf079ffb68eac24f6a19d
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51051
Reviewed-by: Bobby R. Bruce
Reviewed-by: Richard Cooper
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/arch/arm/linux/se_workload.cc
1 file changed, 18 insertions(+), 3 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index 0d9165e..c70dda0 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -226,7 +226,7 @@
{ base + 92, "truncate", truncateFunc },
{ base + 93, "ftruncate", ftruncateFunc },
{ base + 94, "fchmod" },
-{ base + 95, "fchown" },
+{ base + 95, "fchown", fchownFunc },
{ base + 96, "getpriority" },
{ base + 97, "setpriority" },
{ base + 99, "statfs" },
@@ -330,7 +330,7 @@
{ base + 204, "setregid" },
{ base + 205, "getgroups" },
{ base + 206, "setgroups" },
-{ base + 207, "fchown" },
+{ base + 207, "fchown", fchownFunc },
{ base + 208, "setresuid" },
{ base + 209, "getresuid" },
{ base + 210, "setresgid" },
@@ -553,7 +553,7 @@
{ base + 52, "fchmod" },
{ base + 53, "fchmodat" },
{ base + 54, "fchownat" },
-{ base + 55, "fchown" },
+{ base + 55, "fchown", fchownFunc },
{ base + 56, "openat", openatFunc },
{ base + 57, "close", closeFunc },
{ base + 58, "vhangup" },
--
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Gerrit-Change-Id: I4696e305383492e3bf3cf079ffb68eac24f6a19d
Gerrit-Change-Number: 51051
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Generalize ruby components in library
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/51448 ) Change subject: python: Generalize ruby components in library .. python: Generalize ruby components in library The Ruby protocols in the components library had some special cases for x86 that ended up breaking other ISAs (RISC-V in my testing). This change generalizes those scripts slightly so they will work with both x86 and RISC-V Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6 Signed-off-by: Jason Lowe-Power --- M src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py 2 files changed, 29 insertions(+), 28 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py index e5d0353..9d42365 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py @@ -110,21 +110,14 @@ board.get_clock_domain(), ) +cache.sequencer = RubySequencer( +version=i, +dcache=cache.L1Dcache, +clk_domain=cache.clk_domain, +) + if board.has_io_bus(): -cache.sequencer = RubySequencer( -version=i, -dcache=cache.L1Dcache, -clk_domain=cache.clk_domain, -pio_request_port=board.get_io_bus().cpu_side_ports, -mem_request_port=board.get_io_bus().cpu_side_ports, -pio_response_port=board.get_io_bus().mem_side_ports, -) -else: -cache.sequencer = RubySequencer( -version=i, -dcache=cache.L1Dcache, -clk_domain=cache.clk_domain, -) +cache.sequencer.connectIOPorts(board.get_io_bus()) cache.ruby_system = self.ruby_system diff --git a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py index 338d1c4..523ba49 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py @@ -97,21 +97,14 @@ clk_domain=board.get_clock_domain(), ) +cache.sequencer = RubySequencer( +version=i, +dcache=cache.cacheMemory, +clk_domain=cache.clk_domain, +) + if board.has_io_bus(): -cache.sequencer = RubySequencer( -version=i, -dcache=cache.cacheMemory, -clk_domain=cache.clk_domain, -pio_request_port=board.get_io_bus().cpu_side_ports, -mem_request_port=board.get_io_bus().cpu_side_ports, -pio_response_port=board.get_io_bus().mem_side_ports, -) -else: -cache.sequencer = RubySequencer( -version=i, -dcache=cache.L1Dcache, -clk_domain=cache.clk_domain, -) +cache.sequencer.connectIOPorts(board.get_io_bus()) cache.ruby_system = self.ruby_system -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51448 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6 Gerrit-Change-Number: 51448 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python,configs: Add Ruby support to RISC-V board
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51449 )
Change subject: python,configs: Add Ruby support to RISC-V board
..
python,configs: Add Ruby support to RISC-V board
Take out guards stopping the RISC-V board from being configured with
Ruby and update the I/O config with a check for Ruby. Also, add a
comment in the example file that Ruby is now supported.
Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Signed-off-by: Jason Lowe-Power
---
M src/python/gem5/components/boards/riscv_board.py
M configs/example/components-library/riscv_fs.py
2 files changed, 36 insertions(+), 17 deletions(-)
diff --git a/configs/example/components-library/riscv_fs.py
b/configs/example/components-library/riscv_fs.py
index eadac8b..9b9d5f0 100644
--- a/configs/example/components-library/riscv_fs.py
+++ b/configs/example/components-library/riscv_fs.py
@@ -57,7 +57,9 @@
PrivateL1PrivateL2CacheHierarchy,
)
-# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been
tested.
+# Setup the cache hierarchy.
+# For classic, PrivateL1PrivateL2 and NoCache have been tested.
+# For Ruby, MESI_Two_Level and MI_example have been tested.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
)
diff --git a/src/python/gem5/components/boards/riscv_board.py
b/src/python/gem5/components/boards/riscv_board.py
index 2cc151d..7ad1b73 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -89,9 +89,6 @@
requires(isa_required=ISA.RISCV)
-if cache_hierarchy.is_ruby():
-raise EnvironmentError("RiscvBoard is not compatible with
Ruby")
-
self.workload = RiscvLinux()
# Contains a CLINT, PLIC, UART, and some functions for the dtb,
etc.
@@ -124,20 +121,26 @@
def _setup_io_devices(self) -> None:
"""Connect the I/O devices to the I/O bus"""
-for device in self._off_chip_devices:
-device.pio = self.iobus.mem_side_ports
-for device in self._on_chip_devices:
-device.pio = self.get_cache_hierarchy().get_mem_side_port()
-self.bridge = Bridge(delay="10ns")
-self.bridge.mem_side_port = self.iobus.cpu_side_ports
-self.bridge.cpu_side_port = (
-self.get_cache_hierarchy().get_mem_side_port()
-)
-self.bridge.ranges = [
-AddrRange(dev.pio_addr, size=dev.pio_size)
-for dev in self._off_chip_devices
-]
+if self.get_cache_hierarchy().is_ruby():
+for device in self._off_chip_devices + self._on_chip_devices:
+device.pio = self.iobus.mem_side_ports
+
+else:
+for device in self._off_chip_devices:
+device.pio = self.iobus.mem_side_ports
+for device in self._on_chip_devices:
+device.pio = self.get_cache_hierarchy().get_mem_side_port()
+
+self.bridge = Bridge(delay="10ns")
+self.bridge.mem_side_port = self.iobus.cpu_side_ports
+self.bridge.cpu_side_port = (
+self.get_cache_hierarchy().get_mem_side_port()
+)
+self.bridge.ranges = [
+AddrRange(dev.pio_addr, size=dev.pio_size)
+for dev in self._off_chip_devices
+]
def _setup_pma(self) -> None:
"""Set the PMA devices on each core"""
--
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add RISC-V Ruby boot tests
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51450 )
Change subject: tests: Add RISC-V Ruby boot tests
..
tests: Add RISC-V Ruby boot tests
Change-Id: I6a173dcef974fef726991bf3db8b7355838e2d04
Signed-off-by: Jason Lowe-Power
---
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M tests/gem5/configs/riscv_boot_exit_run.py
2 files changed, 62 insertions(+), 9 deletions(-)
diff --git a/tests/gem5/configs/riscv_boot_exit_run.py
b/tests/gem5/configs/riscv_boot_exit_run.py
index b97c8ad..1798e4d 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -36,6 +36,7 @@
import m5
from m5.objects import Root
+from gem5.components.boards.riscv_board import RiscvBoard
from gem5.components.memory.single_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
@@ -67,6 +68,15 @@
)
parser.add_argument(
+"-m",
+"--mem-system",
+type=str,
+choices=("classic", "mi_example",),
+required=True,
+help="The memory system.",
+)
+
+parser.add_argument(
"-t",
"--tick-exit",
type=int,
@@ -94,15 +104,24 @@
# Run a check to ensure the right version of gem5 is being used.
requires(isa_required=ISA.RISCV)
-from gem5.components.cachehierarchies.classic.\
-private_l1_private_l2_cache_hierarchy import \
-PrivateL1PrivateL2CacheHierarchy
-from gem5.components.boards.riscv_board import RiscvBoard
+if args.mem_system == "classic":
+from gem5.components.cachehierarchies.classic.\
+private_l1_private_l2_cache_hierarchy import \
+PrivateL1PrivateL2CacheHierarchy
-# Setup the cache hierarchy.
-cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
-l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
-)
+# Setup the cache hierarchy.
+cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
+)
+elif args.mem_system == "mi_example":
+from gem5.components.cachehierarchies.ruby.\
+mi_example_cache_hierarchy import \
+MIExampleCacheHierarchy
+
+# Setup the cache hierarchy.
+cache_hierarchy = MIExampleCacheHierarchy(
+size="32KiB", assoc=8
+)
# Setup the system memory.
memory = SingleChannelDDR3_1600()
diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py
b/tests/gem5/riscv-boot-tests/test_linux_boot.py
index bdaa1e6..940702a 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -37,10 +37,12 @@
def test_boot(
cpu: str,
num_cpus: int,
+cache_type: str,
to_tick: int,
length: str,
):
-name = "{}-cpu_{}-cores_riscv-boot-test_to-tick".format(cpu,
str(num_cpus))
+name = "{}-cpu_{}-{}-cores_riscv-boot-test_to-tick".format(
+cpu, str(num_cpus), cache_type)
verifiers = []
exit_regex = re.compile(
@@ -66,6 +68,8 @@
cpu,
"--num-cpus",
str(num_cpus),
+"--mem-system",
+cache_type,
"--tick-exit",
str(to_tick),
"--override-download",
@@ -83,6 +87,7 @@
test_boot(
cpu="atomic",
num_cpus=1,
+cache_type="classic",
to_tick=100, # Simulates 1/100th of a second.
length=constants.quick_tag,
)
@@ -90,6 +95,15 @@
test_boot(
cpu="timing",
num_cpus=1,
+cache_type="classic",
+to_tick=100,
+length=constants.quick_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=1,
+cache_type="mi_example",
to_tick=100,
length=constants.quick_tag,
)
@@ -97,6 +111,7 @@
test_boot(
cpu="o3",
num_cpus=1,
+cache_type="classic",
to_tick=100,
length=constants.quick_tag,
)
@@ -104,6 +119,15 @@
test_boot(
cpu="timing",
num_cpus=4,
+cache_type="classic",
+to_tick=100,
+length=constants.quick_tag,
+)
+
+test_boot(
+cpu="timing",
+num_cpus=4,
+cache_type="mi_example",
to_tick=100,
length=constants.quick_tag,
)
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add RISC-V atomic support to Ruby
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51447 )
Change subject: mem-ruby: Add RISC-V atomic support to Ruby
..
mem-ruby: Add RISC-V atomic support to Ruby
RISC-V atomics carry a atomic functor that needs to be executed in the
cache hierarchy. To implement this in Ruby, we execute the functor in
the hitCallback function. Note that these functions are slightly
different than the atomic functions used in the GPU model and the GPU
coalescer even though they have similar semantics.
This change was tested with RISC-V Linux boot which has a few atomics
and linux boot finishes successfully. Previously, the boot got stuck
after the incorrect atomic operation.
Change-Id: I47a69c05ad9f4267d0220023289116e62b5231be
Signed-off-by: Jason Lowe-Power
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 29 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 77ab170..ac52c5f 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -613,6 +613,15 @@
data.setData(_val[0],
getOffset(request_address), pkt->getSize());
DPRINTF(RubySequencer, "swap data %s\n", data);
+} else if (pkt->isAtomicOp()) {
+// Set the data in the packet to the old value in the cache
+pkt->setData(
+data.getData(getOffset(request_address), pkt->getSize()));
+DPRINTF(RubySequencer, "AMO original data %s\n", data);
+// execute AMO operation
+(*(pkt->getAtomicOp()))(
+data.getDataMod(getOffset(request_address)));
+DPRINTF(RubySequencer, "AMO new data %s\n", data);
} else if (type != RubyRequestType_Store_Conditional ||
llscSuccess) {
// Types of stores set the actual data here, apart from
// failed Store Conditional requests
--
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[gem5-dev] Re: reduce the number of checkpoints in the ARM checkpoint test?
> -Original Message- > From: Gabe Black > Sent: 12 October 2021 10:28 > To: Giacomo Travaglini > Cc: gem5 Developer List > Subject: Re: [gem5-dev] reduce the number of checkpoints in the ARM > checkpoint test? > > Hi Giacomo. it's definitely minutes, probably between 5 and 10 per > checkpoint. I see > > Another thing I noticed is that often, the test infrastructure will schedule > the > typically two final and longer running tests (I think both ARM boot tests) at > the same time, but sometimes I'll wait and wait for the checkpoint one to run, > and then it will start the other ARM test serially after it, even though I > passed > in -t 6 (run 6 tests in parallel). It's just a guess, but is the framework > setting up > 6 static schedules of tests and then feeding them to 6 threads to run? Or is > it > dynamically scheduling them based on when different threads finish their > current task? If it's the first, I think the second would be a great > improvement as well, since that will save the occasional unnecessary > serialization of long running tests. As far as I can see we are using the multiprocessing.Pool object [1] which means a worker process Will be used as soon as it becomes available. There shouldn't be dependencies between linux boot tests, except For the regex matching tests which complete in almost zero time > > Gabe > Kind Regards Giacomo [1]: https://github.com/gem5/gem5/blob/stable/ext/testlib/runner.py#L177 IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Added trusted DRAM to vexpress Realview
Quentin Forcioli has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/49989 ) Change subject: dev-arm: Added trusted DRAM to vexpress Realview .. dev-arm: Added trusted DRAM to vexpress Realview Added the 32MB of trusted DRAM to the VExpress_GEM5_Base Realview. This trusted DRAM is however not protected against unsecure access. This commit is part of series of commit to enable booting OPTEE on gem5. Change-Id: Icbbaec8488dd72e1cbe70015a7f7904de35b38bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49989 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- M src/dev/arm/RealView.py 1 file changed, 26 insertions(+), 2 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 0ba929b..837fe7e 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -977,7 +977,9 @@ Memory map: 0x-0x03ff: Boot memory (CS0) - 0x0400-0x07ff: Reserved + 0x0400-0x07ff: Trusted Memory/Reserved +0x0400-0x0403: 256kB Trusted SRAM +0x0600-0x07ff: 32MB Trusted DRAM 0x0800-0x0bff: NOR FLASH0 (CS0 alias) 0x0c00-0x0fff: NOR FLASH1 (Off-chip, CS4) 0x1000-0x13ff: gem5-specific peripherals (Off-chip, CS5) @@ -1094,7 +1096,10 @@ # Trusted SRAM trusted_sram = SimpleMemory(range=AddrRange(0x0400, size='256KiB'), conf_table_reported=False) - +# Trusted DRAM +# TODO: preventing access from unsecure world to the trusted RAM +trusted_dram=SimpleMemory(range=AddrRange(0x0600, size='32MB'), +conf_table_reported=False) # Non-Trusted SRAM non_trusted_sram = MmioSRAM(range=AddrRange(0x2e00, size=0x8000), conf_table_reported=False) @@ -1145,6 +1150,7 @@ memories = [ self.bootmem, self.trusted_sram, +self.trusted_dram, self.non_trusted_sram, self.flash0, ] -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49989 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icbbaec8488dd72e1cbe70015a7f7904de35b38bf Gerrit-Change-Number: 49989 Gerrit-PatchSet: 6 Gerrit-Owner: Quentin Forcioli Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Quentin Forcioli Gerrit-Reviewer: kokoro Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: reduce the number of checkpoints in the ARM checkpoint test?
Hi Giacomo. it's definitely minutes, probably between 5 and 10 per checkpoint. Another thing I noticed is that often, the test infrastructure will schedule the typically two final and longer running tests (I think both ARM boot tests) at the same time, but sometimes I'll wait and wait for the checkpoint one to run, and then it will start the other ARM test serially after it, even though I passed in -t 6 (run 6 tests in parallel). It's just a guess, but is the framework setting up 6 static schedules of tests and then feeding them to 6 threads to run? Or is it dynamically scheduling them based on when different threads finish their current task? If it's the first, I think the second would be a great improvement as well, since that will save the occasional unnecessary serialization of long running tests. Gabe On Tue, Oct 12, 2021 at 2:10 AM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Hi Gabe, are we talking about seconds or minutes (per run)? > In the latter case I agree we could reduce the max_number to 3. > > If it is just saving us few seconds then it is probably not worth it IMHO > > Kind Regards > > Giacomo > > > -Original Message- > > From: Gabe Black via gem5-dev > > Sent: 12 October 2021 09:18 > > To: gem5 Developer List > > Cc: Gabe Black > > Subject: [gem5-dev] reduce the number of checkpoints in the ARM > > checkpoint test? > > > > I notice that the long pole in running the quick regressions seems to be > the > > tests/gem5/configs/realview64-simple-atomic-checkpoint.py test which > > does some sort of ARM linux boot (I assume) and checkpoints 5 times as it > > comes up. Would it make sense to reduce that down to 3 or even 2? I think > > that would get largely the same test coverage but hopefully take > > substantially less time to run. > > > > Alternatively we could increase the interval and decrease the max number > of > > checkpoints to get more separate (and more different?) state for > > checkpoints. > > > > Longer term, we should look at why taking (and restoring?) checkpoints > is so > > slow and try to fix that, but nearer term, when I have to run lots of > these in a > > row, it would be really nice to trim them down by a good number of > minutes > > a time. > > > > Gabe > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: reduce the number of checkpoints in the ARM checkpoint test?
Hi Gabe, are we talking about seconds or minutes (per run)? In the latter case I agree we could reduce the max_number to 3. If it is just saving us few seconds then it is probably not worth it IMHO Kind Regards Giacomo > -Original Message- > From: Gabe Black via gem5-dev > Sent: 12 October 2021 09:18 > To: gem5 Developer List > Cc: Gabe Black > Subject: [gem5-dev] reduce the number of checkpoints in the ARM > checkpoint test? > > I notice that the long pole in running the quick regressions seems to be the > tests/gem5/configs/realview64-simple-atomic-checkpoint.py test which > does some sort of ARM linux boot (I assume) and checkpoints 5 times as it > comes up. Would it make sense to reduce that down to 3 or even 2? I think > that would get largely the same test coverage but hopefully take > substantially less time to run. > > Alternatively we could increase the interval and decrease the max number of > checkpoints to get more separate (and more different?) state for > checkpoints. > > Longer term, we should look at why taking (and restoring?) checkpoints is so > slow and try to fix that, but nearer term, when I have to run lots of these > in a > row, it would be really nice to trim them down by a good number of minutes > a time. > > Gabe IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Don't update stats in (read|set)Arch*Reg methods.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51428 )
Change subject: cpu-o3: Don't update stats in (read|set)Arch*Reg methods.
..
cpu-o3: Don't update stats in (read|set)Arch*Reg methods.
These are called from the ThreadContext, and should not be counted in
the statistics. The (read|set)*Reg methods, aka readIntReg and not
readArchIntReg, are called from the (read|set)*RegOperand methods in the
DynInst, which is the ExecContext implementation when running on O3.
Change-Id: I9abf90fc7bbe80a742325b6dfd3c0e14392af54c
---
M src/cpu/o3/cpu.cc
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 8f0c531..a574a4b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1244,7 +1244,6 @@
RegVal
CPU::readArchIntReg(int reg_idx, ThreadID tid)
{
-cpuStats.intRegfileReads++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(IntRegClass, reg_idx));
@@ -1254,7 +1253,6 @@
RegVal
CPU::readArchFloatReg(int reg_idx, ThreadID tid)
{
-cpuStats.fpRegfileReads++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(FloatRegClass, reg_idx));
@@ -1266,7 +1264,7 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
-return readVecReg(phys_reg);
+return regFile.readVecReg(phys_reg);
}
TheISA::VecRegContainer&
@@ -1274,7 +1272,7 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
-return getWritableVecReg(phys_reg);
+return regFile.getWritableVecReg(phys_reg);
}
RegVal
@@ -1283,7 +1281,7 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecElemClass, reg_idx, ldx));
-return readVecElem(phys_reg);
+return regFile.readVecElem(phys_reg);
}
const TheISA::VecPredRegContainer&
@@ -1291,7 +1289,7 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecPredRegClass, reg_idx));
-return readVecPredReg(phys_reg);
+return regFile.readVecPredReg(phys_reg);
}
TheISA::VecPredRegContainer&
@@ -1299,13 +1297,12 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecPredRegClass, reg_idx));
-return getWritableVecPredReg(phys_reg);
+return regFile.getWritableVecPredReg(phys_reg);
}
RegVal
CPU::readArchCCReg(int reg_idx, ThreadID tid)
{
-cpuStats.ccRegfileReads++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(CCRegClass, reg_idx));
@@ -1315,7 +1312,6 @@
void
CPU::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
{
-cpuStats.intRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(IntRegClass, reg_idx));
@@ -1325,7 +1321,6 @@
void
CPU::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
{
-cpuStats.fpRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(FloatRegClass, reg_idx));
@@ -1338,7 +1333,7 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
-setVecReg(phys_reg, val);
+regFile.setVecReg(phys_reg, val);
}
void
@@ -1347,7 +1342,7 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecElemClass, reg_idx, ldx));
-setVecElem(phys_reg, val);
+regFile.setVecElem(phys_reg, val);
}
void
@@ -1356,13 +1351,12 @@
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecPredRegClass, reg_idx));
-setVecPredReg(phys_reg, val);
+regFile.setVecPredReg(phys_reg, val);
}
void
CPU::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
{
-cpuStats.ccRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(CCRegClass, reg_idx));
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9abf90fc7bbe80a742325b6dfd3c0e14392af54c
Gerrit-Change-Number: 51428
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] reduce the number of checkpoints in the ARM checkpoint test?
I notice that the long pole in running the quick regressions seems to be the tests/gem5/configs/realview64-simple-atomic-checkpoint.py test which does some sort of ARM linux boot (I assume) and checkpoints 5 times as it comes up. Would it make sense to reduce that down to 3 or even 2? I think that would get largely the same test coverage but hopefully take substantially less time to run. Alternatively we could increase the interval and decrease the max number of checkpoints to get more separate (and more different?) state for checkpoints. Longer term, we should look at why taking (and restoring?) checkpoints is so slow and try to fix that, but nearer term, when I have to run lots of these in a row, it would be really nice to trim them down by a good number of minutes a time. Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: misc: Fix hdf5 stats + test
Davide Basilio Bartolini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51061 )
Change subject: misc: Fix hdf5 stats + test
..
misc: Fix hdf5 stats + test
HDF5 stats file creation was not completing correctly due to name
clashes.
Change-Id: Ifc2d52f4bbc62b0c6798ce92f4d027b0ec69a373
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51061
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M tests/gem5/verifier.py
M tests/gem5/stats/test_hdf5.py
M src/mem/mem_interface.cc
M src/base/stats/hdf5.cc
M src/cpu/o3/iew.cc
5 files changed, 47 insertions(+), 12 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/stats/hdf5.cc b/src/base/stats/hdf5.cc
index 90bd8cd..d5b7f1e 100644
--- a/src/base/stats/hdf5.cc
+++ b/src/base/stats/hdf5.cc
@@ -39,6 +39,8 @@
#include "base/logging.hh"
#include "base/stats/info.hh"
+#include "base/trace.hh"
+#include "debug/Stats.hh"
namespace gem5
{
@@ -254,6 +256,8 @@
fspace = H5::DataSpace(rank, dims, max_dims.data());
try {
+DPRINTF(Stats, "Creating dataset %s in group %s\n",
+info.name, group.getObjName());
data_set = group.createDataSet(info.name,
H5::PredType::NATIVE_DOUBLE, fspace, props);
} catch (const H5::Exception ) {
diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
index 7cdc8d8..d899e8b 100644
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -143,7 +143,7 @@
}
IEW::IEWStats::IEWStats(CPU *cpu)
-: statistics::Group(cpu),
+: statistics::Group(cpu, "iew"),
ADD_STAT(idleCycles, statistics::units::Cycle::get(),
"Number of cycles IEW is idle"),
ADD_STAT(squashCycles, statistics::units::Cycle::get(),
diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc
index 8036aca..a3e5963 100644
--- a/src/mem/mem_interface.cc
+++ b/src/mem/mem_interface.cc
@@ -1893,10 +1893,6 @@
ADD_STAT(bytesPerActivate, statistics::units::Byte::get(),
"Bytes accessed per row activation"),
-ADD_STAT(bytesRead, statistics::units::Byte::get(),
- "Total number of bytes read from DRAM"),
-ADD_STAT(bytesWritten, statistics::units::Byte::get(),
-"Total number of bytes written to DRAM"),
ADD_STAT(avgRdBW, statistics::units::Rate<
statistics::units::Byte, statistics::units::Second>::get(),
"Average DRAM read bandwidth in MiBytes/s"),
@@ -2548,10 +2544,6 @@
statistics::units::Tick, statistics::units::Count>::get(),
"Average memory access latency per NVM burst"),
-ADD_STAT(bytesRead, statistics::units::Byte::get(),
- "Total number of bytes read from NVM"),
-ADD_STAT(bytesWritten, statistics::units::Byte::get(),
- "Total number of bytes written to NVM"),
ADD_STAT(avgRdBW, statistics::units::Rate<
statistics::units::Byte, statistics::units::Second>::get(),
"Average DRAM read bandwidth in MiBytes/s"),
diff --git a/tests/gem5/stats/test_hdf5.py b/tests/gem5/stats/test_hdf5.py
index ad730f3..545ef58 100644
--- a/tests/gem5/stats/test_hdf5.py
+++ b/tests/gem5/stats/test_hdf5.py
@@ -44,7 +44,6 @@
import os
from testlib import *
-
if config.bin_path:
resource_path = config.bin_path
else:
@@ -68,12 +67,20 @@
ok_exit_regex = re.compile(
r"Exiting @ tick \d+ because exiting with last active thread
context"
)
+ok_verifier = verifier.MatchRegex(ok_exit_regex)
-stdout_verifier = verifier.MatchRegex(ok_exit_regex)
+# FIXME: flaky, should check return code instead...
+# See: https://gem5.atlassian.net/browse/GEM5-1099
+err_regex = re.compile(
+r'RuntimeError: Failed creating H5::DataSet \w+; .*'
+)
+err_verifier = verifier.NoMatchRegex(err_regex, True, False)
+
h5_verifier = verifier.CheckH5StatsExist()
+
gem5_verify_config(
name="hdf5_test",
-verifiers=[stdout_verifier, h5_verifier],
+verifiers=[ok_verifier, err_verifier, h5_verifier],
fixtures=(),
config=joinpath(
config.base_dir,
@@ -92,3 +99,4 @@
gem5_args=["--stats-file=h5://stats.h5"],
valid_isas=(constants.arm_tag,),
)
+
diff --git a/tests/gem5/verifier.py b/tests/gem5/verifier.py
index f6687f5..c947a62 100644
--- a/tests/gem5/verifier.py
+++ b/tests/gem5/verifier.py
@@ -229,6 +229,21 @@
filenames.append(constants.gem5_simulation_stderr)
super(MatchRegex, self).__init__(regex, filenames)
+class NoMatchRegex(MatchRegex):
+"""
+Checks that the given pattern does *not* match
+"""
+def __init__(self, regex, match_stderr=True, match_stdout=True):
+super(NoMatchRegex, self).__init__(regex, match_stderr,
