[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Add KCONFIG.md file which talks about Kconfig files.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58634 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: misc: Add KCONFIG.md file which talks about Kconfig files. .. misc: Add KCONFIG.md file which talks about Kconfig files. There are some minor aspects about how Kconfig files are used in gem5 which are a little different from how they are documented online or are used in other projects. Document that in this file. Change-Id: Ib981d1e265cf466d453071b33820d6baa24e17d4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58634 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- A KCONFIG.md 1 file changed, 131 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/KCONFIG.md b/KCONFIG.md new file mode 100644 index 000..9292539 --- /dev/null +++ b/KCONFIG.md @@ -0,0 +1,114 @@ +This file explains how to work with gem5's implementation of the kconfig +configuration system, very similar to what's used by the linux kernel. It talks +about how to work with the Kconfig files themselves which define what user +adjustable configuration parameters there are, and how they work and +interoperate. + +This file does *not*: + + * Describe how kconfig works generally. This is well documented elsewhere, for +instance [here]( +https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html): + * The settings in gem5's kconfig files. These should be documented with help + text within the kconfig files, and in the code where these options are + consumed. + * The various tools which can manipulate a given configuration. These are + documented in gem5's SCons help text. + +# kconfiglib + +gem5 uses the kconfiglib python library for consuming and manipulating kconfig +configurations. It is very similar to the kconfig implementation used by the +linux kernel, but is slightly different and has some small extensions added to +it. Almost all kconfig documentation written for the kernel's implementation +should apply here as well, but it may occasionally be necessary to refer to the +kconfiglib documentation. + +Also, because gem5's build system is more modular than kconfig's design +supports out of the box, particularly for "choice" blocks, we have extended +kconfiglib and added a "cont_choice" keyword. This keyword is very similar to +"choice", except "cont_choice" blocks can be re-opened and extended with more +options further into the config. + +This can be used to set up a central point where the user can choose between +mutually exclusive options, and still allow new Kconfig files to add new +options without modifying the original source. + +Having to choose between mutually exclusive options should be avoided in +general, but is unavoidable in a few key places in gem5 at the moment. Once +those areas have been addressed, this keyword may be removed in the future. + +# The 'CONF' dict in the SCons environment + +In "env" SCons environment in SConscript files, or the "main" environment in +SConsopts files, can hold many variables which help SCons operate generally, +like setting what include paths to use, what the compiler command line is, etc. +These environments each have a 'CONF' sub-dict which holds all the variables +which are actually used to configure gem5, and not to configure SCons and the +build process itself. + +All variables in this dict are automatically available to include in c++. To +access the value of env['CONF']['FOO'], you would #include "config/foo.hh". +Because these variables are in a shared namespace, their names should be unique +and distinctive. + +These values are available in config scripts through the m5.defines.buildEnv +dict. + +# Automatic/measured configuration values. + +Some configuration values are not set by the user, and are measured from the +host environment. These could reflect the availability of a header file, +library or tool, whether the compiler supports a particular option or language +feature, etc. + +These values should be measured in SConsopts files, and stored in the 'CONF' +dict described above. Like any other variable in 'CONF', they are then +available to C++ through generated header files, to config scripts through +buildEnv, etc. They are also available in the kconfig files themselves through +a mechanism discussed below. + +# Accessing 'CONF' values in Kconfig files. + +When the gem5 Kconfig files are processed to either manipulate a configuration +through a tool, or to apply a configuration to the gem5 build, all the values +in 'CONF' are temporarily put into environment variables. In the Kconfig files +themselves, these
[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Export more CortexR52 reset pin
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58811 )
Change subject: fastmodel: Export more CortexR52 reset pin
..
fastmodel: Export more CortexR52 reset pin
Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
8 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index 710584d..615935e 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -114,6 +114,8 @@
ext_slave = AmbaTargetSocket(64, 'AMBA target socket')
top_reset = IntSinkPin('This signal resets timer and interrupt
controller.')
+dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross
Trigger ' \
+'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
"CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 85a4c2a..2b92b2a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -158,7 +158,8 @@
{
if (if_name == "spi") {
return evs->gem5_getPort(if_name, idx);
-} else if (if_name == "ext_slave" || if_name == "top_reset") {
+} else if (if_name == "ext_slave" || if_name == "top_reset" ||
+ if_name == "dbg_reset") {
assert(idx == InvalidPortID);
return evs->gem5_getPort(if_name, idx);
} else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 720f1cc..f9f1583 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -96,9 +96,10 @@
ScxEvsCortexR52::ScxEvsCortexR52(
const sc_core::sc_module_name _name, const Params ) :
Base(mod_name),
-params(p),
ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
-top_reset(p.name + ".top_reset", 0)
+top_reset(p.name + ".top_reset", 0),
+dbg_reset(p.name + ".dbg_reset", 0),
+params(p)
{
for (int i = 0; i < CoreCount; i++)
corePins.emplace_back(new CorePins(this, i));
@@ -109,6 +110,7 @@
}
top_reset.signal_out.bind(Base::top_reset);
+dbg_reset.signal_out.bind(Base::dbg_reset);
clockRateControl.bind(this->clock_rate_s);
signalInterrupt.bind(this->signal_interrupt);
@@ -144,6 +146,8 @@
return this->ext_slave;
} else if (if_name == "top_reset") {
return this->top_reset;
+} else if (if_name == "dbg_reset") {
+return this->dbg_reset;
} else if (if_name == "spi") {
return *this->spis.at(idx);
} else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index fa9d7fe..eee44c7 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -119,14 +119,16 @@
std::vector> spis;
-CortexR52Cluster *gem5CpuCluster;
-
-const Params
-
AmbaTarget ext_slave;
SignalSender top_reset;
+SignalSender dbg_reset;
+
+CortexR52Cluster *gem5CpuCluster;
+
+const Params
+
public:
ScxEvsCortexR52(const Params ) : ScxEvsCortexR52(p.name.c_str(), p)
{}
ScxEvsCortexR52(const sc_core::sc_module_name _name, const Params
);
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
index 36f3279..2a7299d 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -45,9 +45,12 @@
core.flash_m => self.flash;
core.pvbus_core_m => self.amba;
self.ext_slave => core.ext_slave_s;
+
+// Reset signals.
self.core_reset => core.reset;
self.poweron_reset => core.cpuporeset;
self.top_reset => core.topreset;
+self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
// Clocks.
@@ -77,6 +80,7 @@
slave port poweron_reset[1];
slave port halt[1];
slave port top_reset;
+slave port dbg_reset;
slave port cfgvectable[1];
slave port clock_rate_s
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
index 492d289..9100a5b 100644
---
[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexA76 artifact reset port
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58814 )
Change subject: fastmodel: Add CortexA76 artifact reset port
..
fastmodel: Add CortexA76 artifact reset port
The artifact reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.
Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
4 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index 9a56f29..420b499 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -31,6 +31,7 @@
from m5.objects.ArmISA import ArmISA
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.FastModelResetPort import FastModelResetResponsePort
from m5.objects.IntPin import IntSinkPin
from m5.objects.Gic import ArmPPI
from m5.objects.Iris import IrisBaseCPU
@@ -172,6 +173,8 @@
'all resettable registers in DynamIQ.')
dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross
Trigger ' \
'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+artifact_reset = FastModelResetResponsePort(
+'An artifact reset port to reset the whole cluster.')
# These parameters are described in "Fast Models Reference Manual"
section
# 3.4.19, "ARMCortexA7x1CT".
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index e67a0f6..24f873b 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,7 +104,8 @@
Port &
CortexA76::getPort(const std::string _name, PortID idx)
{
-if (if_name == "redistributor" || if_name == "core_reset")
+if (if_name == "redistributor" || if_name == "core_reset" ||
+if_name == "poweron_reset")
return cluster->getEvs()->gem5_getPort(if_name, num);
else
return Base::getPort(if_name, idx);
@@ -200,7 +201,7 @@
CortexA76Cluster::getPort(const std::string _name, PortID idx)
{
if (if_name == "amba" || if_name == "top_reset" ||
-if_name == "dbg_reset") {
+if_name == "dbg_reset" || if_name == "artifact_reset") {
return evs->gem5_getPort(if_name, idx);
} else {
return SimObject::getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index d54ad78..76b2840 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -71,12 +71,27 @@
}
template
+void
+ScxEvsCortexA76::requestReset()
+{
+// Reset all cores.
+for (auto _reset : this->poweron_reset) {
+poweron_reset->signal_out.set_state(0, true);
+}
+// Reset DSU.
+this->top_reset.signal_out.set_state(0, true);
+// Reset debug APB.
+this->dbg_reset.signal_out.set_state(0, true);
+}
+
+template
ScxEvsCortexA76::ScxEvsCortexA76(
const sc_core::sc_module_name _name, const Params ) :
Base(mod_name),
amba(Base::amba, p.name + ".amba", -1),
top_reset(p.name + ".top_reset", 0),
dbg_reset(p.name + ".dbg_reset", 0),
+artifact_reset(p.name + ".artifact_reset", -1, this),
params(p)
{
for (int i = 0; i < CoreCount; i++) {
@@ -178,6 +193,8 @@
return top_reset;
else if (if_name == "dbg_reset")
return dbg_reset;
+else if (if_name == "artifact_reset")
+return artifact_reset;
else
return Base::gem5_getPort(if_name, idx);
}
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index e1b6aed..28a473d 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -31,6 +31,7 @@
#include
#include "arch/arm/fastmodel/amba_ports.hh"
+#include "arch/arm/fastmodel/common/reset_port.hh"
#include "arch/arm/fastmodel/common/signal_receiver.hh"
#include "arch/arm/fastmodel/common/signal_sender.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
@@ -98,6 +99,8 @@
SignalSender dbg_reset;
+ResetResponsePort artifact_reset;
+
CortexA76Cluster *gem5CpuCluster;
const Params
@@ -126,6 +129,8 @@
void setCluster(SimObject *cluster) override;
void setResetAddr(int core, Addr addr, bool secure) override;
+
+void requestReset();
};
struct ScxEvsCortexA76x1Types
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58814
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Add a special reset interface to consolidate reset logic
Yu-hsin Wang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58810 ) Change subject: fastmodel: Add a special reset interface to consolidate reset logic .. fastmodel: Add a special reset interface to consolidate reset logic How to reset a model correctly is very different between models. Take cpu models for instance, they have different reset pins for different parts(typically one for each core, one for shared component, one for debug interface). To make users more easily to reset the model, here we want to introduce a special reset port. By implementing the port, users can simply request a whole reset to the model. If users want to do partial resets, users still can access the raw pins to achieve what they want. Change-Id: I746121d16441e021dc3392aeae1a6d9fa33d637a --- A src/arch/arm/fastmodel/common/FastModelResetPort.py A src/arch/arm/fastmodel/common/SConscript A src/arch/arm/fastmodel/common/reset_port.cc A src/arch/arm/fastmodel/common/reset_port.hh 4 files changed, 229 insertions(+), 0 deletions(-) diff --git a/src/arch/arm/fastmodel/common/FastModelResetPort.py b/src/arch/arm/fastmodel/common/FastModelResetPort.py new file mode 100644 index 000..b33a7fa --- /dev/null +++ b/src/arch/arm/fastmodel/common/FastModelResetPort.py @@ -0,0 +1,50 @@ +# Copyright 2022 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.params import * + +RESET_REQUEST_ROLE = 'FastModel Reset Request' +RESET_RESPONSE_ROLE = 'FastModel Reset Response' +Port.compat(RESET_REQUEST_ROLE, RESET_RESPONSE_ROLE) + +# FastModelResetRequestPort is an artifact request port for reset purpose. +class FastModelResetRequestPort(Port): +def __init__(self, desc): +super(FastModelResetRequestPort, self).__init__( +RESET_REQUEST_ROLE, desc, is_source=True) + +# FastModelResetResponsePort is an artifact response port for reset purpose. +# The owner should perform whole reset when receiving a request. +class FastModelResetResponsePort(Port): +def __init__(self, desc): +super(FastModelResetResponsePort, self).__init__( +RESET_RESPONSE_ROLE, desc) + +# VectorFastModelResetRequestPort presents a bank of artifact reset request +# ports. +class VectorFastModelResetRequestPort(VectorPort): +def __init__(self, desc): +super(VectorFastModelResetRequestPort, self).__init__( +RESET_REQUEST_ROLE, desc, is_source=True) diff --git a/src/arch/arm/fastmodel/common/SConscript b/src/arch/arm/fastmodel/common/SConscript new file mode 100644 index 000..46826f5 --- /dev/null +++ b/src/arch/arm/fastmodel/common/SConscript @@ -0,0 +1,30 @@ +# Copyright 2022 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export more CortexA76 reset pin
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58812 )
Change subject: fastmodel: Export more CortexA76 reset pin
..
fastmodel: Export more CortexA76 reset pin
Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
8 files changed, 89 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index c7d46ff..9a56f29 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -31,6 +31,7 @@
from m5.objects.ArmISA import ArmISA
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.IntPin import IntSinkPin
from m5.objects.Gic import ArmPPI
from m5.objects.Iris import IrisBaseCPU
from m5.objects.SystemC import SystemC_ScModule
@@ -46,6 +47,10 @@
evs = Parent.evs
redistributor = Gicv3CommsTargetSocket('GIC communication target')
+core_reset = IntSinkPin('Raising this signal will put the core into ' \
+'reset mode.')
+poweron_reset = IntSinkPin('Power on reset. Initializes all the ' \
+ 'processor logic, including debug logic.')
CFGEND = Param.Bool(False, "Endianness configuration at reset. "\
"0, little endian. 1, big endian.")
@@ -163,6 +168,10 @@
"Non-secure physical timer event")
amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
+top_reset = IntSinkPin('A single cluster-wide power on reset signal
for ' \
+'all resettable registers in DynamIQ.')
+dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross
Trigger ' \
+'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
# These parameters are described in "Fast Models Reference Manual"
section
# 3.4.19, "ARMCortexA7x1CT".
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index e77e734..e67a0f6 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,7 +104,7 @@
Port &
CortexA76::getPort(const std::string _name, PortID idx)
{
-if (if_name == "redistributor")
+if (if_name == "redistributor" || if_name == "core_reset")
return cluster->getEvs()->gem5_getPort(if_name, num);
else
return Base::getPort(if_name, idx);
@@ -199,7 +199,8 @@
Port &
CortexA76Cluster::getPort(const std::string _name, PortID idx)
{
-if (if_name == "amba") {
+if (if_name == "amba" || if_name == "top_reset" ||
+if_name == "dbg_reset") {
return evs->gem5_getPort(if_name, idx);
} else {
return SimObject::getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 935d139..d54ad78 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -73,7 +73,10 @@
template
ScxEvsCortexA76::ScxEvsCortexA76(
const sc_core::sc_module_name _name, const Params ) :
-Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
+Base(mod_name),
+amba(Base::amba, p.name + ".amba", -1),
+top_reset(p.name + ".top_reset", 0),
+dbg_reset(p.name + ".dbg_reset", 0),
params(p)
{
for (int i = 0; i < CoreCount; i++) {
@@ -93,6 +96,10 @@
new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
rvbaraddr.emplace_back(new SignalInitiator(
csprintf("rvbaraddr[%d]", i).c_str()));
+core_reset.emplace_back(
+new SignalSender(csprintf("core_reset[%d]", i), 0));
+poweron_reset.emplace_back(
+new SignalSender(csprintf("poweron_reset[%d]", i), 0));
Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
@@ -104,8 +111,13 @@
Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);
rvbaraddr[i]->bind(Base::rvbaraddr[i]);
+core_reset[i]->signal_out.bind(Base::core_reset[i]);
+poweron_reset[i]->signal_out.bind(Base::poweron_reset[i]);
}
+top_reset.signal_out.bind(Base::top_reset);
+dbg_reset.signal_out.bind(Base::dbg_reset);
+
clockRateControl.bind(this->clock_rate_s);
[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexR52 artifact reset port
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58813 )
Change subject: fastmodel: Add CortexR52 artifact reset port
..
fastmodel: Add CortexR52 artifact reset port
The artifact reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.
Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
4 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index 615935e..151ed11 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -30,6 +30,7 @@
from m5.objects.ArmInterrupts import ArmInterrupts
from m5.objects.ArmISA import ArmISA
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
+from m5.objects.FastModelResetPort import FastModelResetResponsePort
from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
from m5.objects.Iris import IrisBaseCPU
from m5.objects.SystemC import SystemC_ScModule
@@ -116,6 +117,8 @@
top_reset = IntSinkPin('This signal resets timer and interrupt
controller.')
dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross
Trigger ' \
'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+artifact_reset = FastModelResetResponsePort(
+'An artifact reset port to reset the whole cluster.')
CLUSTER_ID = Param.UInt16(0, "CLUSTER_ID[15:8] equivalent to " \
"CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1")
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index 2b92b2a..d4d7c87 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -159,7 +159,7 @@
if (if_name == "spi") {
return evs->gem5_getPort(if_name, idx);
} else if (if_name == "ext_slave" || if_name == "top_reset" ||
- if_name == "dbg_reset") {
+ if_name == "dbg_reset" || if_name == "artifact_reset") {
assert(idx == InvalidPortID);
return evs->gem5_getPort(if_name, idx);
} else {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index f9f1583..3dfc0af 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -99,6 +99,7 @@
ext_slave(Base::ext_slave, p.name + ".ext_slave", -1),
top_reset(p.name + ".top_reset", 0),
dbg_reset(p.name + ".dbg_reset", 0),
+artifact_reset(p.name + ".artifact_reset", -1, this),
params(p)
{
for (int i = 0; i < CoreCount; i++)
@@ -148,6 +149,8 @@
return this->top_reset;
} else if (if_name == "dbg_reset") {
return this->dbg_reset;
+} else if (if_name == "artifact_reset") {
+return this->artifact_reset;
} else if (if_name == "spi") {
return *this->spis.at(idx);
} else if (if_name.substr(0, 3) == "ppi") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index eee44c7..50c0d18 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -31,6 +31,7 @@
#include
#include "arch/arm/fastmodel/amba_ports.hh"
+#include "arch/arm/fastmodel/common/reset_port.hh"
#include "arch/arm/fastmodel/common/signal_receiver.hh"
#include "arch/arm/fastmodel/common/signal_sender.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
@@ -125,6 +126,8 @@
SignalSender dbg_reset;
+ResetResponsePort artifact_reset;
+
CortexR52Cluster *gem5CpuCluster;
const Params
@@ -145,6 +148,19 @@
this->signalInterrupt->spi(num, false);
}
+void
+requestReset()
+{
+// Reset all cores.
+for (auto _pin : corePins) {
+core_pin->poweron_reset.signal_out.set_state(0, true);
+}
+// Reset L2 system.
+this->top_reset.signal_out.set_state(0, true);
+// Reset debug APB.
+this->dbg_reset.signal_out.set_state(0, true);
+}
+
Port _getPort(const std::string _name, int idx) override;
void
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Gerrit-Change-Number: 58813
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang
Gerrit-MessageType: newchange
___
[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix script failed when default files not found
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58809 )
Change subject: scons: Fix script failed when default files not found
..
scons: Fix script failed when default files not found
Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
---
M SConstruct
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/SConstruct b/SConstruct
index cf130c1..95ebff1 100755
--- a/SConstruct
+++ b/SConstruct
@@ -633,7 +633,7 @@
(' or '.join(current_vars_files), default_vars_file))
else:
error("Cannot find variables file(s) %s or default
file(s) %s" %
-(' or '.join(current_vars_file),
+(' or '.join(current_vars_files),
' or '.join(default_vars_files)))
Exit(1)
--
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Gerrit-Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
Gerrit-Change-Number: 58809
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, configs: Migrate riscv-ubuntu-run example to Simulator
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58790 )
Change subject: stdlib, configs: Migrate riscv-ubuntu-run example to
Simulator
..
stdlib, configs: Migrate riscv-ubuntu-run example to Simulator
Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Signed-off-by: Hoa Nguyen
---
M configs/example/gem5_library/riscv-ubuntu-run.py
1 file changed, 13 insertions(+), 29 deletions(-)
diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py
b/configs/example/gem5_library/riscv-ubuntu-run.py
index d54fa90..1c95d3f 100644
--- a/configs/example/gem5_library/riscv-ubuntu-run.py
+++ b/configs/example/gem5_library/riscv-ubuntu-run.py
@@ -53,6 +53,7 @@
from gem5.isas import ISA
from gem5.coherence_protocol import CoherenceProtocol
from gem5.resources.resource import Resource
+from gem5.simulate.simulator import Simulator
# This runs a check to ensure the gem5 binary is compiled for RISCV.
@@ -116,32 +117,5 @@
root = Root(full_system=True, system=board)
-m5.instantiate()
-
-# We simulate the system till we encounter `m5_exit instruction
encountered`.
-
-exit_event = m5.simulate()
-
-# We check whether the simulation ended with `m5_exit instruction
encountered`
-
-if exit_event.getCause() == "m5_exit instruction encountered":
-# We acknowledge the user that the boot was successful.
-
-print("Successfully completed booting!")
-else:
-# `m5_exit instruction encountered` was never encountered. We exit the
-# program unsuccessfully.
-
-print("The startup was not completed successfully!",)
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
-exit(-1)
-
-# We are done with the simulation. We exit the program now.
-
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
+simulator = Simulator(board=board)
+simulator.run()
--
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Gerrit-Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Gerrit-Change-Number: 58790
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Gerrit-Owner: Hoa Nguyen
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Add checkpoint to Simulator
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58789 ) Change subject: stdlib: Add checkpoint to Simulator .. stdlib: Add checkpoint to Simulator Change-Id: I58b686b6b4f69260ab45709c6ef0bddf4539f0c4 Signed-off-by: Hoa Nguyen --- M src/python/gem5/simulate/simulator.py 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/python/gem5/simulate/simulator.py b/src/python/gem5/simulate/simulator.py index 1645dfc..7e5db87 100644 --- a/src/python/gem5/simulate/simulator.py +++ b/src/python/gem5/simulate/simulator.py @@ -32,6 +32,7 @@ from m5.util import warn import os +from pathlib import Path from typing import Optional, List, Tuple, Dict, Generator, Union from .exit_event_generators import ( @@ -76,6 +77,7 @@ Dict[Union[str, ExitEvent], Generator[Optional[bool], None, None]] ] = None, expected_execution_order: Optional[List[ExitEvent]] = None, +checkpoint_path: Optional[Path] = None, ) -> None: """ :param board: The board to be simulated. @@ -177,6 +179,8 @@ self._last_exit_event = None self._exit_event_count = 0 +self._checkpoint_path = checkpoint_path + def get_stats(self) -> Dict: """ Obtain the current simulation statistics as a Dictionary, conforming @@ -277,7 +281,10 @@ m5.ticks.fixGlobalFrequency() root.sim_quantum = m5.ticks.fromSeconds(0.001) -m5.instantiate() +if self._checkpoint_path: +m5.instantiate(self._checkpoint_path) +else: +m5.instantiate() self._instantiated = True def run(self, max_ticks: int = m5.MaxTick) -> None: @@ -347,3 +354,7 @@ # run loop. if exit_on_completion: return + +def save_checkpoint(self, checkpoint_folder: Path) -> None: +m5.checkpoint(str(checkpoint_folder)) + -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58789 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I58b686b6b4f69260ab45709c6ef0bddf4539f0c4 Gerrit-Change-Number: 58789 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Disable failing MI_Example/Timing CPU X86 Boot Tests
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58769 )
Change subject: tests: Disable failing MI_Example/Timing CPU X86 Boot Tests
..
tests: Disable failing MI_Example/Timing CPU X86 Boot Tests
As noted in this jira issue:
https://gem5.atlassian.net/browse/GEM5-1216, these tests are failing.
We are going to disable them until we can figure out the root cause of
this problem.
Change-Id: I8511beaac0bae3c6d2a42af59035cc4620cd5bb2
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index 482cf16..ee9c257 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -261,10 +261,10 @@
8: False, # Not Supported
},
"timing": {
-1: True,
-2: True,
-4: True,
-8: True,
+1: False, # MI_Example does not successfully boot with the
Timing
+2: False, # Jira: https://gem5.atlassian.net/browse/GEM5-1216
+4: False,
+8: False,
},
"o3": {
1: False, # Timeout
--
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Gerrit-Change-Id: I8511beaac0bae3c6d2a42af59035cc4620cd5bb2
Gerrit-Change-Number: 58769
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Remove 8-core boot tests for Timing and Atomic
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58770 )
Change subject: tests: Remove 8-core boot tests for Timing and Atomic
..
tests: Remove 8-core boot tests for Timing and Atomic
As noted here: https://gem5.atlassian.net/browse/GEM5-1217, the Atomic
and Timing Core systems are not working with 8 cores when run with a
classic or MI_example cache heirarchy. Until the root cause of this
issue can be determined. These tests are being disabled.
Change-Id: Ia19579029bd20c57cca8d225068d17c4b29f1773
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index ee9c257..7e3ad4e 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -238,13 +238,13 @@
1: True,
2: True,
4: False, # We already run this in the long (Nightly) tests.
-8: True,
+8: False, # Jira: https://gem5.atlassian.net/browse/GEM5-1217
},
"timing": {
1: True,
2: True,
4: True,
-8: True,
+8: False, # Jira: https://gem5.atlassian.net/browse/GEM5-1217
},
"o3": {
1: False, # Timeout
--
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Gerrit-Change-Number: 58770
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Gerrit-Owner: Bobby Bruce
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement SOP2 S_MUL_HI instructions
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58473 )
Change subject: arch-vega: Implement SOP2 S_MUL_HI instructions
..
arch-vega: Implement SOP2 S_MUL_HI instructions
Two new 32-bit signed and unsigned variants of S_MUL were added in
gfx900 which operate similar to S_MUL expect they shift the product by
32 bits after multiplication. Tested with Histogram HIP-Sample and
b+tree in rodinia 3.0 HIP port.
Change-Id: I1bed32b17ccda7aa47f3b59528eb3304912d3610
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58473
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
Tested-by: kokoro
---
M src/arch/amdgpu/vega/decoder.cc
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
3 files changed, 150 insertions(+), 3 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/decoder.cc
b/src/arch/amdgpu/vega/decoder.cc
index 3344365..f716636 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -4438,14 +4438,13 @@
GPUStaticInst*
Decoder::decode_OP_SOP2__S_MUL_HI_U32(MachInst iFmt)
{
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_SOP2__S_MUL_HI_U32(>iFmt_SOP2);
}
GPUStaticInst*
Decoder::decode_OP_SOP2__S_MUL_HI_I32(MachInst iFmt)
{
-return new Inst_SOP2__S_MUL_I32(>iFmt_SOP2);
+return new Inst_SOP2__S_MUL_HI_I32(>iFmt_SOP2);
}
GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 32d048e..edf908d 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -1473,6 +1473,68 @@
{
panicUnimplemented();
} // execute
+// --- Inst_SOP2__S_MUL_HI_U32 class methods ---
+
+Inst_SOP2__S_MUL_HI_U32::Inst_SOP2__S_MUL_HI_U32(InFmt_SOP2 *iFmt)
+: Inst_SOP2(iFmt, "s_mul_hi_u32")
+{
+setFlag(ALU);
+} // Inst_SOP2__S_MUL_HI_U32
+
+Inst_SOP2__S_MUL_HI_U32::~Inst_SOP2__S_MUL_HI_U32()
+{
+} // ~Inst_SOP2__S_MUL_HI_U32
+
+// --- description from .arch file ---
+// D.u = (S0.u * S1.u) >> 32;
+void
+Inst_SOP2__S_MUL_HI_U32::execute(GPUDynInstPtr gpuDynInst)
+{
+ConstScalarOperandU32 src0(gpuDynInst, instData.SSRC0);
+ConstScalarOperandU32 src1(gpuDynInst, instData.SSRC1);
+ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
+
+src0.read();
+src1.read();
+
+VecElemU64 tmp_dst =
+((VecElemU64)src0.rawData() * (VecElemU64)src1.rawData());
+sdst = (tmp_dst >> 32);
+
+sdst.write();
+} // execute
+// --- Inst_SOP2__S_MUL_HI_I32 class methods ---
+
+Inst_SOP2__S_MUL_HI_I32::Inst_SOP2__S_MUL_HI_I32(InFmt_SOP2 *iFmt)
+: Inst_SOP2(iFmt, "s_mul_hi_i32")
+{
+setFlag(ALU);
+} // Inst_SOP2__S_MUL_HI_I32
+
+Inst_SOP2__S_MUL_HI_I32::~Inst_SOP2__S_MUL_HI_I32()
+{
+} // ~Inst_SOP2__S_MUL_HI_I32
+
+// --- description from .arch file ---
+// D.u = (S0.u * S1.u) >> 32;
+void
+Inst_SOP2__S_MUL_HI_I32::execute(GPUDynInstPtr gpuDynInst)
+{
+ConstScalarOperandI32 src0(gpuDynInst, instData.SSRC0);
+ConstScalarOperandI32 src1(gpuDynInst, instData.SSRC1);
+ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
+
+src0.read();
+src1.read();
+
+VecElemI64 tmp_src0 =
+sext::digits>(src0.rawData());
+VecElemI64 tmp_src1 =
+sext::digits>(src1.rawData());
+sdst = (VecElemI32)((tmp_src0 * tmp_src1) >> 32);
+
+sdst.write();
+} // execute
// --- Inst_SOPK__S_MOVK_I32 class methods ---
Inst_SOPK__S_MOVK_I32::Inst_SOPK__S_MOVK_I32(InFmt_SOPK *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index e14f52f..e9361c3 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -1538,6 +1538,74 @@
void execute(GPUDynInstPtr) override;
}; // Inst_SOP2__S_RFE_RESTORE_B64
+class Inst_SOP2__S_MUL_HI_U32 : public Inst_SOP2
+{
+ public:
+Inst_SOP2__S_MUL_HI_U32(InFmt_SOP2*);
+~Inst_SOP2__S_MUL_HI_U32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 2; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+ case 0: //ssrc_0
+return 4;
+ case 1: //ssrc_1
+
[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: Added upstream_nodes to AbstractController
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57296 )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: Added upstream_nodes to AbstractController
..
mem-ruby: Added upstream_nodes to AbstractController
Added support for an upstream_nodes NetAddr list in AbstractController,
which will be used in future CHI work.
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I30a6d621d7f201d89f0b13dab8ed4dd1f1f6caa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57296
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
3 files changed, 33 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 396b128..e11d780 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -108,7 +108,13 @@
}
downstreamDestinations.add(mid);
}
-
+// Initialize the addr->upstream machine list.
+// We do not need to map address -> upstream machine,
+// so we don't examine the address ranges
+upstreamDestinations.resize();
+for (auto abs_cntrl : params().upstream_destinations) {
+upstreamDestinations.add(abs_cntrl->getMachineID());
+}
}
void
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 56c164f..46bd3f8 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -214,8 +214,12 @@
MachineID mapAddressToDownstreamMachine(Addr addr,
MachineType mtype = MachineType_NUM)
const;
+/** List of downstream destinations (towards memory) */
const NetDest& allDownstreamDest() const { return
downstreamDestinations; }
+/** List of upstream destinations (towards the CPU) */
+const NetDest& allUpstreamDest() const { return upstreamDestinations; }
+
protected:
//! Profiles original cache requests including PUTs
void profileRequest(const std::string );
@@ -375,6 +379,7 @@
AddrRangeMap downstreamAddrMap;
NetDest downstreamDestinations;
+NetDest upstreamDestinations;
public:
struct ControllerStats : public statistics::Group
diff --git a/src/mem/ruby/slicc_interface/Controller.py
b/src/mem/ruby/slicc_interface/Controller.py
index 15366de2..c73836d 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017,2019,2020 ARM Limited
+# Copyright (c) 2017,2019-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -75,5 +75,7 @@
# These can be used by a protocol to enable reuse of the same machine
# types to model different levels of the cache hierarchy
+upstream_destinations = VectorParam.RubyController([],
+"Possible destinations for requests sent towards the
CPU")
downstream_destinations = VectorParam.RubyController([],
"Possible destinations for requests sent towards
memory")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/57296
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30a6d621d7f201d89f0b13dab8ed4dd1f1f6caa3
Gerrit-Change-Number: 57296
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: AbstractController unaddressed profiling
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57297 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: AbstractController unaddressed profiling
..
mem-ruby: AbstractController unaddressed profiling
Adds support for profiling "unaddressed" transactions,
which are associated with a unique ID rather than a memory address,
to AbstractController.
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ib75f3f38dc4910acc2ad4f1c7bf88c9193568203
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57297
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/AbstractController.hh
1 file changed, 59 insertions(+), 9 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 46bd3f8..19cfe51 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -228,23 +228,33 @@
// Tracks outstanding transactions for latency profiling
struct TransMapPair { unsigned transaction; unsigned state; Tick time;
};
-std::unordered_map m_inTrans;
-std::unordered_map m_outTrans;
+std::unordered_map m_inTransAddressed;
+std::unordered_map m_outTransAddressed;
+
+std::unordered_map m_inTransUnaddressed;
+std::unordered_map m_outTransUnaddressed;
/**
* Profiles an event that initiates a protocol transactions for a
specific
* line (e.g. events triggered by incoming request messages).
* A histogram with the latency of the transactions is generated for
* all combinations of trigger event, initial state, and final state.
+ * This function also supports "unaddressed" transactions,
+ * those not associated with an address in memory but
+ * instead associated with a unique ID.
*
- * @param addr address of the line
+ * @param addr address of the line, or unique transaction ID
* @param type event that started the transaction
* @param initialState state of the line before the transaction
+ * @param isAddressed is addr a line address or a unique ID
*/
template
void incomingTransactionStart(Addr addr,
-EventType type, StateType initialState, bool retried)
+EventType type, StateType initialState, bool retried,
+bool isAddressed=true)
{
+auto& m_inTrans =
+ isAddressed ? m_inTransAddressed : m_inTransUnaddressed;
assert(m_inTrans.find(addr) == m_inTrans.end());
m_inTrans[addr] = {type, initialState, curTick()};
if (retried)
@@ -253,13 +263,20 @@
/**
* Profiles an event that ends a transaction.
+ * This function also supports "unaddressed" transactions,
+ * those not associated with an address in memory but
+ * instead associated with a unique ID.
*
- * @param addr address of the line with a outstanding transaction
+ * @param addr address or unique ID with an outstanding transaction
* @param finalState state of the line after the transaction
+ * @param isAddressed is addr a line address or a unique ID
*/
template
-void incomingTransactionEnd(Addr addr, StateType finalState)
+void incomingTransactionEnd(Addr addr, StateType finalState,
+bool isAddressed=true)
{
+auto& m_inTrans =
+ isAddressed ? m_inTransAddressed : m_inTransUnaddressed;
auto iter = m_inTrans.find(addr);
assert(iter != m_inTrans.end());
stats.inTransLatHist[iter->second.transaction]
@@ -273,13 +290,20 @@
/**
* Profiles an event that initiates a transaction in a peer controller
* (e.g. an event that sends a request message)
+ * This function also supports "unaddressed" transactions,
+ * those not associated with an address in memory but
+ * instead associated with a unique ID.
*
- * @param addr address of the line
+ * @param addr address of the line or a unique transaction ID
* @param type event that started the transaction
+ * @param isAddressed is addr a line address or a unique ID
*/
template
-void outgoingTransactionStart(Addr addr, EventType type)
+void outgoingTransactionStart(Addr addr, EventType type,
+bool isAddressed=true)
{
+auto& m_outTrans =
+ isAddressed ? m_outTransAddressed : m_outTransUnaddressed;
assert(m_outTrans.find(addr) == m_outTrans.end());
m_outTrans[addr] = {type, 0, curTick()};
}
@@ -287,11 +311,18 @@
/**
* Profiles the end of an outgoing
[gem5-dev] [M] Change in gem5/gem5[develop]: cpu: Handle external TLBI Sync requests in O3CPU
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57292 )
Change subject: cpu: Handle external TLBI Sync requests in O3CPU
..
cpu: Handle external TLBI Sync requests in O3CPU
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I02e55a42e0f717211b481e65d59900fc3d05f061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57292
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/o3/lsq.cc
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
4 files changed, 166 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index 752298a..654fd67 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -73,6 +73,8 @@
_cacheBlocked(false),
cacheStorePorts(params.cacheStorePorts), usedStorePorts(0),
cacheLoadPorts(params.cacheLoadPorts), usedLoadPorts(0),
+ waitingForStaleTranslation(false),
+ staleTranslationWaitTxnId(0),
lsqPolicy(params.smtLSQPolicy),
LQEntries(params.LQEntries),
SQEntries(params.SQEntries),
@@ -431,6 +433,10 @@
// Update the LSQRequest state (this may delete the request)
request->packetReplied();
+if (waitingForStaleTranslation) {
+checkStaleTranslations();
+}
+
return true;
}
@@ -447,6 +453,19 @@
for (ThreadID tid = 0; tid < numThreads; tid++) {
thread[tid].checkSnoop(pkt);
}
+} else if (pkt->req && pkt->req->isTlbiExtSync()) {
+DPRINTF(LSQ, "received TLBI Ext Sync\n");
+assert(!waitingForStaleTranslation);
+
+waitingForStaleTranslation = true;
+staleTranslationWaitTxnId = pkt->req->getExtraData();
+
+for (auto& unit : thread) {
+unit.startStaleTranslationFlush();
+}
+
+// In case no units have pending ops, just go ahead
+checkStaleTranslations();
}
}
@@ -1048,7 +1067,8 @@
LSQ::LSQRequest::LSQRequest(
LSQUnit *port, const DynInstPtr& inst, bool isLoad,
const Addr& addr, const uint32_t& size, const Request::Flags&
flags_,
- PacketDataPtr data, uint64_t* res, AtomicOpFunctorPtr amo_op)
+PacketDataPtr data, uint64_t* res, AtomicOpFunctorPtr amo_op,
+bool stale_translation)
: _state(State::NotIssued),
numTranslatedFragments(0),
numInTranslationFragments(0),
@@ -1056,7 +1076,8 @@
_res(res), _addr(addr), _size(size),
_flags(flags_),
_numOutstandingPackets(0),
-_amo_op(std::move(amo_op))
+_amo_op(std::move(amo_op)),
+_hasStaleTranslation(stale_translation)
{
flags.set(Flag::IsLoad, isLoad);
flags.set(Flag::WriteBackToRegister,
@@ -1134,6 +1155,36 @@
this, isLoad() ? BaseMMU::Read : BaseMMU::Write);
}
+void
+LSQ::SingleDataRequest::markAsStaleTranslation()
+{
+// If this element has been translated and is currently being
requested,
+// then it may be stale
+if ((!flags.isSet(Flag::Complete)) &&
+(!flags.isSet(Flag::Discarded)) &&
+(flags.isSet(Flag::TranslationStarted))) {
+_hasStaleTranslation = true;
+}
+
+DPRINTF(LSQ, "SingleDataRequest %d 0x%08x isBlocking:%d\n",
+(int)_state, (uint32_t)flags, _hasStaleTranslation);
+}
+
+void
+LSQ::SplitDataRequest::markAsStaleTranslation()
+{
+// If this element has been translated and is currently being
requested,
+// then it may be stale
+if ((!flags.isSet(Flag::Complete)) &&
+(!flags.isSet(Flag::Discarded)) &&
+(flags.isSet(Flag::TranslationStarted))) {
+_hasStaleTranslation = true;
+}
+
+DPRINTF(LSQ, "SplitDataRequest %d 0x%08x isBlocking:%d\n",
+(int)_state, (uint32_t)flags, _hasStaleTranslation);
+}
+
bool
LSQ::SingleDataRequest::recvTimingResp(PacketPtr pkt)
{
@@ -1141,6 +1192,7 @@
flags.set(Flag::Complete);
assert(pkt == _packets.front());
_port.completeDataAccess(pkt);
+_hasStaleTranslation = false;
return true;
}
@@ -1166,6 +1218,7 @@
_port.completeDataAccess(resp);
delete resp;
}
+_hasStaleTranslation = false;
return true;
}
@@ -1424,6 +1477,14 @@
}
void
+LSQ::UnsquashableDirectRequest::markAsStaleTranslation()
+{
+// HTM/TLBI operations do not translate,
+// so cannot have stale translations
+_hasStaleTranslation = false;
+}
+
+void
LSQ::UnsquashableDirectRequest::finish(const Fault ,
const RequestPtr , gem5::ThreadContext* tc,
BaseMMU::Mode mode)
@@ -1431,6 +1492,36 @@
panic("unexpected behaviour - finish()");
}
+void
+LSQ::checkStaleTranslations()
+{
+assert(waitingForStaleTranslation);
+
+DPRINTF(LSQ, "Checking pending TLBI sync\n");
+// Check if all thread queues are
[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: Support for unaddressed mem requests in the RubyRequest
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57293 )
Change subject: mem-ruby: Support for unaddressed mem requests in the
RubyRequest
..
mem-ruby: Support for unaddressed mem requests in the RubyRequest
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I5aa44186888b95f81bec524ff57e8dbf4c9166f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57293
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/RubyRequest.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
4 files changed, 91 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index cea6c04..ef83e01 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -183,16 +183,23 @@
HTM_Commit,desc="hardware memory transaction: commit";
HTM_Cancel,desc="hardware memory transaction: cancel";
HTM_Abort, desc="hardware memory transaction: abort";
+ TLBI, desc="TLB Invalidation - Initiation";
+ TLBI_SYNC, desc="TLB Invalidation Sync operation - Potential
initiation";
+ TLBI_EXT_SYNC, desc="TLB Invalidation Sync operation - External
Sync has been requested";
+ TLBI_EXT_SYNC_COMP, desc="TLB Invalidation Sync operation - External
Sync has been completed";
}
bool isWriteRequest(RubyRequestType type);
bool isDataReadRequest(RubyRequestType type);
bool isReadRequest(RubyRequestType type);
bool isHtmCmdRequest(RubyRequestType type);
+bool isTlbiRequest(RubyRequestType type);
// hardware transactional memory
RubyRequestType htmCmdToRubyRequestType(Packet *pkt);
+RubyRequestType tlbiCmdToRubyRequestType(Packet *pkt);
+
enumeration(HtmCallbackMode, desc="...", default="HtmCallbackMode_NULL") {
HTM_CMD, desc="htm command";
LD_FAIL, desc="htm transaction failed - inform via read";
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index e5ecb00..8d76f78 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -139,6 +139,11 @@
Cycles, Cycles, Cycles);
void writeUniqueCallback(Addr, DataBlock);
+ void unaddressedCallback(Addr, RubyRequestType);
+ void unaddressedCallback(Addr, RubyRequestType, MachineType);
+ void unaddressedCallback(Addr, RubyRequestType, MachineType,
+Cycles, Cycles, Cycles);
+
// ll/sc support
void writeCallbackScFail(Addr, DataBlock);
bool llscCheckMonitor(Addr);
@@ -170,6 +175,8 @@
PacketPtr pkt, desc="Packet associated with this request";
bool htmFromTransaction, desc="Memory request originates within a HTM
transaction";
int htmTransactionUid, desc="Used to identify the unique HTM
transaction that produced this request";
+ bool isTlbi, desc="Memory request is a TLB shootdown
(invalidation) operation";
+ Addr tlbiTransactionUid, desc="Unique identifier of the TLB shootdown
operation that produced this request";
RequestPtr getRequestPtr();
}
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh
b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 8324f6e..2345c22 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -76,6 +76,9 @@
uint64_t m_instSeqNum;
bool m_htmFromTransaction;
uint64_t m_htmTransactionUid;
+bool m_isTlbi;
+// Should be uint64, but SLICC complains about casts
+Addr m_tlbiTransactionUid;
RubyRequest(Tick curTime, uint64_t _paddr, int _len,
uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
@@ -91,11 +94,34 @@
m_pkt(_pkt),
m_contextId(_core_id),
m_htmFromTransaction(false),
- m_htmTransactionUid(0)
+ m_htmTransactionUid(0),
+ m_isTlbi(false),
+ m_tlbiTransactionUid(0)
{
m_LineAddress = makeLineAddress(m_PhysicalAddress);
}
+/** RubyRequest for memory management commands */
+RubyRequest(Tick curTime,
+uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
+PacketPtr _pkt, ContextID _proc_id, ContextID _core_id)
+: Message(curTime),
+ m_PhysicalAddress(0),
+ m_Type(_type),
+ m_ProgramCounter(_pc),
+ m_AccessMode(_access_mode),
+ m_Size(0),
+ m_Prefetch(PrefetchBit_No),
+ m_pkt(_pkt),
+ m_contextId(_core_id),
+ m_htmFromTransaction(false),
+
[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: Add TLBI callbacks to the RubyPort
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57295 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: Add TLBI callbacks to the RubyPort
..
mem-ruby: Add TLBI callbacks to the RubyPort
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I984fd497b7209772106150abb853c91c3d818dfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57295
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
2 files changed, 67 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index c52ee58..48f655d 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013,2020 ARM Limited
+ * Copyright (c) 2012-2013,2020-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -474,6 +474,54 @@
}
void
+RubyPort::ruby_unaddressed_callback(PacketPtr pkt)
+{
+DPRINTF(RubyPort, "Unaddressed callback for %s\n", pkt->cmdString());
+
+assert(pkt->isRequest());
+
+// First we must retrieve the request port from the sender State
+RubyPort::SenderState *senderState =
+safe_cast(pkt->popSenderState());
+MemResponsePort *port = senderState->port;
+assert(port != NULL);
+delete senderState;
+
+port->hitCallback(pkt);
+
+trySendRetries();
+}
+
+void
+RubyPort::ruby_stale_translation_callback(Addr txnId)
+{
+DPRINTF(RubyPort, "Stale Translation Callback\n");
+
+// Allocate the invalidate request and packet on the stack, as it is
+// assumed they will not be modified or deleted by receivers.
+// TODO: should this really be using funcRequestorId?
+auto request = std::make_shared(
+0, RubySystem::getBlockSizeBytes(), Request::TLBI_EXT_SYNC,
+Request::funcRequestorId);
+// Store the txnId in extraData instead of the address
+request->setExtraData(txnId);
+
+// Use a single packet to signal all snooping ports of the external
sync.
+// This assumes that snooping ports do NOT modify the packet/request
+// TODO rename TlbiExtSync to StaleTranslation
+Packet pkt(request, MemCmd::TlbiExtSync);
+// TODO - see where response_ports is filled, might be we only want to
send
+// to specific places
+for (auto : response_ports) {
+// check if the connected request port is snooping
+if (port->isSnooping()) {
+// send as a snoop request
+port->sendTimingSnoopReq();
+}
+}
+}
+
+void
RubyPort::trySendRetries()
{
//
diff --git a/src/mem/ruby/system/RubyPort.hh
b/src/mem/ruby/system/RubyPort.hh
index 12a88d4..e9d073e 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013,2019 ARM Limited
+ * Copyright (c) 2012-2013,2019,2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -179,6 +179,8 @@
protected:
void trySendRetries();
void ruby_hit_callback(PacketPtr pkt);
+void ruby_unaddressed_callback(PacketPtr pkt);
+void ruby_stale_translation_callback(Addr txnId);
void testDrainComplete();
void ruby_eviction_callback(Addr address);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/57295
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I984fd497b7209772106150abb853c91c3d818dfd
Gerrit-Change-Number: 57295
Gerrit-PatchSet: 10
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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