date:20230209

[gem5-dev] Jenkins build is back to normal : nightly #515

2023-02-09 Thread jenkins-no-reply--- via gem5-dev

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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix failing SST and SystemC nightly tests

2023-02-09 Thread Melissa Jost (Gerrit) via gem5-dev

Melissa Jost has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67817?usp=email )



Change subject: tests: Fix failing SST and SystemC nightly tests
..

tests: Fix failing SST and SystemC nightly tests

There was a bug with the SST and SystemC tests where they wouldn't
compile due to a missing path for the gdbremote/signals.hh
header, and this change includes that so they run properly.

Change-Id: I9ff0404e327358fe2d1b77388bbcc1f807136ebe
---
M ext/sst/Makefile
M util/systemc/gem5_within_systemc/Makefile
2 files changed, 15 insertions(+), 2 deletions(-)



diff --git a/ext/sst/Makefile b/ext/sst/Makefile
index 682af3d..a7467bf 100644
--- a/ext/sst/Makefile
+++ b/ext/sst/Makefile
@@ -4,7 +4,7 @@
 OFLAG=3

 LDFLAGS=-shared -fno-common ${shell pkg-config ${SST_VERSION} --libs}  
-L../../build/${ARCH}/ -Wl,-rpath ../../build/${ARCH}
-CXXFLAGS=-std=c++17 -g -O${OFLAG} -fPIC ${shell pkg-config ${SST_VERSION}  
--cflags} ${shell python3-config --includes} -I../../build/${ARCH}/  
-I../../ext/pybind11/include/ -I../../build/softfloat/
+CXXFLAGS=-std=c++17 -g -O${OFLAG} -fPIC ${shell pkg-config ${SST_VERSION}  
--cflags} ${shell python3-config --includes} -I../../build/${ARCH}/  
-I../../ext/pybind11/include/ -I../../build/softfloat/ -I../..//

 CPPFLAGS+=-MMD -MP
 SRC=$(wildcard *.cc)

diff --git a/util/systemc/gem5_within_systemc/Makefile  
b/util/systemc/gem5_within_systemc/Makefile

index cc6a389..f2baf88 100644
--- a/util/systemc/gem5_within_systemc/Makefile
+++ b/util/systemc/gem5_within_systemc/Makefile
@@ -39,7 +39,7 @@
 SYSTEMC_INC = /opt/systemc/include
 SYSTEMC_LIB = /opt/systemc/lib-linux64

-CXXFLAGS = -I../../../build/$(ARCH) -L../../../build/$(ARCH)
+CXXFLAGS = -I../../../build/$(ARCH) -L../../../build/$(ARCH)  
-I../../../ext/

 CXXFLAGS += -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB)
 CXXFLAGS += -std=c++17
 CXXFLAGS += -g -DTRACING_ON

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9ff0404e327358fe2d1b77388bbcc1f807136ebe
Gerrit-Change-Number: 67817
Gerrit-PatchSet: 1
Gerrit-Owner: Melissa Jost 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext: Fix typo in DRAMSIM2 Sconscript

2023-02-09 Thread Zhengrong Wang (Gerrit) via gem5-dev

Zhengrong Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67759?usp=email )


Change subject: ext: Fix typo in DRAMSIM2 Sconscript
..

ext: Fix typo in DRAMSIM2 Sconscript

ClockDoenv should be ClockDomain.

Change-Id: Ibcf3d0dc969624a4e20d86924ef834781b5bbf21
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67759
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M ext/dramsim2/SConscript
1 file changed, 16 insertions(+), 1 deletion(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/ext/dramsim2/SConscript b/ext/dramsim2/SConscript
index 95b999d..7eb178d 100644
--- a/ext/dramsim2/SConscript
+++ b/ext/dramsim2/SConscript
@@ -59,7 +59,7 @@
 DRAMFile('Bank.cpp')
 DRAMFile('BankState.cpp')
 DRAMFile('BusPacket.cpp')
-DRAMFile('ClockDoenv.cpp')
+DRAMFile('ClockDomain.cpp')
 DRAMFile('CommandQueue.cpp')
 DRAMFile('IniReader.cpp')
 DRAMFile('MemoryController.cpp')

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibcf3d0dc969624a4e20d86924ef834781b5bbf21
Gerrit-Change-Number: 67759
Gerrit-PatchSet: 2
Gerrit-Owner: Zhengrong Wang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Zhengrong Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Jenkins build is back to normal : compiler-checks #513

2023-02-09 Thread jenkins-no-reply--- via gem5-dev

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-vega: Make VGPR-offset for global SGPR-base signed

2023-02-09 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67412?usp=email )


Change subject: arch-vega: Make VGPR-offset for global SGPR-base signed
..

arch-vega: Make VGPR-offset for global SGPR-base signed

The VGPR-offset used when SGPR-base addressing is used can be signed in
Vega. These are global instructions of the format:
`global_load_dword v0, v1, s[0:1]`. This is not explicitly stated in the
ISA manual however based on compiler output the offset can be negative.

This changeset assigns the offset to a signed 32-bit integer and the
compiler takes care of the signedness in the expression which calculates
the final address. This fixes a bad address calculation in a rocPRIM
unit test.

Change-Id: I271edfbb4c6344cb1a6a69a0fd3df58a6198d599
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67412
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/op_encodings.hh
1 file changed, 25 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/insts/op_encodings.hh  
b/src/arch/amdgpu/vega/insts/op_encodings.hh

index 34f6040..1071ead 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.hh
+++ b/src/arch/amdgpu/vega/insts/op_encodings.hh
@@ -1007,8 +1007,9 @@
 // mask any upper bits from the vaddr.
 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
 if (gpuDynInst->exec_mask[lane]) {
+ScalarRegI32 voffset = vaddr[lane];
 gpuDynInst->addr.at(lane) =
-saddr.rawData() + (vaddr[lane] & 0x) +  
offset;

+saddr.rawData() + voffset + offset;
 }
 }
 }

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I271edfbb4c6344cb1a6a69a0fd3df58a6198d599
Gerrit-Change-Number: 67412
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_write_b8_d16_hi

2023-02-09 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67411?usp=email )


Change subject: arch-vega: Implement ds_write_b8_d16_hi
..

arch-vega: Implement ds_write_b8_d16_hi

Writes a byte to the upper 16-bit input word to an address.

Change-Id: I0bfd573526b9c46585d0008cde07c769b1d29ebd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67411
Maintainer: Matt Sinclair 
Reviewed-by: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/decoder.cc
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
3 files changed, 112 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/decoder.cc  
b/src/arch/amdgpu/vega/decoder.cc

index 18c72a4..291dd69 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -7706,8 +7706,7 @@
 GPUStaticInst*
 Decoder::decode_OP_DS__DS_WRITE_B8_D16_HI(MachInst iFmt)
 {
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_DS__DS_WRITE_B8_D16_HI(&iFmt->iFmt_DS);
 }

 GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index 6cf01fb..f019dfd 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34877,6 +34877,68 @@
 Inst_DS__DS_WRITE_B8::completeAcc(GPUDynInstPtr gpuDynInst)
 {
 } // completeAcc
+// --- Inst_DS__DS_WRITE_B8_D16_HI class methods ---
+
+Inst_DS__DS_WRITE_B8_D16_HI::Inst_DS__DS_WRITE_B8_D16_HI(InFmt_DS  
*iFmt)

+: Inst_DS(iFmt, "ds_write_b8_d16_hi")
+{
+setFlag(MemoryRef);
+setFlag(Store);
+} // Inst_DS__DS_WRITE_B8_D16_HI
+
+Inst_DS__DS_WRITE_B8_D16_HI::~Inst_DS__DS_WRITE_B8_D16_HI()
+{
+} // ~Inst_DS__DS_WRITE_B8_D16_HI
+
+// --- description from .arch file ---
+// MEM[ADDR] = DATA[23:16].
+// Byte write in to high word.
+void
+Inst_DS__DS_WRITE_B8_D16_HI::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU8 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->d_data))[lane]
+= bits(data[lane], 23, 16);
+}
+}
+
+ 
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);

+} // execute
+
+void
+Inst_DS__DS_WRITE_B8_D16_HI::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initMemWrite(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_WRITE_B8_D16_HI::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
 // --- Inst_DS__DS_WRITE_B16 class methods ---

 Inst_DS__DS_WRITE_B16::Inst_DS__DS_WRITE_B16(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh  
b/src/arch/amdgpu/vega/insts/instructions.hh

index 2896732..dc2ee08 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31934,6 +31934,40 @@
 void completeAcc(GPUDynInstPtr) override;
 }; // Inst_DS__DS_WRITE_B8

+class Inst_DS__DS_WRITE_B8_D16_HI : public Inst_DS
+{
+  public:
+Inst_DS__DS_WRITE_B8_D16_HI(InFmt_DS*);
+~Inst_DS__DS_WRITE_B8_D16_HI();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 0; }
+int numSrcRegOperands() override { return 2; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+  case 0: //vgpr_a
+return 4;
+  case 1: //vgpr_d0
+return 1;
+  default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+void initiateAcc(GPUDynInstPtr) override;
+

[gem5-dev] [S] Change in gem5/gem5[develop]: python: Ensure that m5.internal.params is available

2023-02-09 Thread Nikos Nikoleris (Gerrit) via gem5-dev

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67797?usp=email )



Change subject: python: Ensure that m5.internal.params is available
..

python: Ensure that m5.internal.params is available

Add an import to m5.internal.params which became necessary after:

95f9017c2e configs,python: Clean some cruft out of m5.objects.

This import is necessary but also causes problems when scons calls
build_tools/sim_object_param_struct_hh.py to generate
params/SimObject.hh. m5.internal.params itself imports _m5 and _m5 is
unavalailable resulting in an ImportError. This is bening and we can
safely ignore it.

Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Signed-off-by: Nikos Nikoleris 
---
M src/python/m5/SimObject.py
M src/python/m5/internal/params.py
2 files changed, 35 insertions(+), 4 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b5dfca9..e3ff0ab 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -445,6 +445,8 @@
 return cls.__name__

 def getCCClass(cls):
+# Ensure that m5.internal.params is available.
+import m5.internal.params
 return getattr(m5.internal.params, cls.pybind_class)

 # See ParamValue.cxx_predecls for description.
diff --git a/src/python/m5/internal/params.py  
b/src/python/m5/internal/params.py

index 8762a69..8225d0b 100644
--- a/src/python/m5/internal/params.py
+++ b/src/python/m5/internal/params.py
@@ -37,8 +37,17 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 import inspect
-import _m5

-for name, module in inspect.getmembers(_m5):
-if name.startswith("param_") or name.startswith("enum_"):
-exec("from _m5.%s import *" % name)
+try:
+# Avoid ImportErrors at build time when _m5 is not available
+import _m5
+
+in_gem5 = True
+except ImportError:
+# The import failed, we're being called from the build system
+in_gem5 = False
+
+if in_gem5:
+for name, module in inspect.getmembers(_m5):
+if name.startswith("param_") or name.startswith("enum_"):
+exec("from _m5.%s import *" % name)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3809e81284e730fb9c9e0e7e91bd61b801d73f90
Gerrit-Change-Number: 67797
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Fix the CSR instruction behavior.

2023-02-09 Thread chengyong zhong (Gerrit) via gem5-dev

chengyong zhong has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67717?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: Fix the CSR instruction behavior.
..

arch-riscv: Fix the CSR instruction behavior.

The RISC-V spec clarifies the CSR instruction operation, some of them
shall not read or write CSR by the hints of RD/RS1/uimm, but the
original version use the 'data != oldData' condition to determine
whether write or not, and always read CSR first.
See CSR instruction in spec:
Section 9.1 Page 56 of  
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf


Change-Id: I5e7a43cf639474ae76c19a1f430d314b4634ce62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67717
Reviewed-by: Hoa Nguyen 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 45 insertions(+), 7 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git a/src/arch/riscv/insts/standard.hh  
b/src/arch/riscv/insts/standard.hh

index 5b0e8c2..afcfd7a 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -91,18 +91,33 @@
   protected:
 uint64_t csr;
 uint64_t uimm;
+bool read;
+bool write;

 /// Constructor
 CSROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 : RiscvStaticInst(mnem, _machInst, __opClass),
-csr(FUNCT12), uimm(CSRIMM)
+csr(FUNCT12), uimm(CSRIMM), read(true), write(true)
 {
 if (csr == CSR_SATP) {
 flags[IsSquashAfter] = true;
 }
+if (strcmp(mnemonic, "csrrw") == 0 ||
+strcmp(mnemonic, "csrrwi") == 0) {
+  if (RD == 0){
+read = false;
+  }
+} else if (strcmp(mnemonic, "csrrs") == 0 ||
+   strcmp(mnemonic, "csrrc") == 0 ||
+   strcmp(mnemonic, "csrrsi") == 0 ||
+   strcmp(mnemonic, "csrrci") == 0 ){
+  if (RS1 == 0) {
+write = false;
+  }
+}
 }

-std::string generateDisassembly(
+  std::string generateDisassembly(
 Addr pc, const loader::SymbolTable *symtab) const override;
 };

diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index bb500f5..1bd431a 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -358,7 +358,7 @@
 %(op_decl)s;
 %(op_rd)s;

-RegVal data, olddata;
+RegVal data = 0, olddata = 0;
 auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
 if (pm < lowestAllowedMode) {
@@ -380,11 +380,13 @@
 break;
 }

-if (csr == CSR_FCSR) {
+if (read) {
+  if (csr == CSR_FCSR) {
 olddata = xc->readMiscReg(MISCREG_FFLAGS) |
-  (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
+  (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+  } else {
 olddata = xc->readMiscReg(midx);
+  }
 }
 olddata = rvZext(olddata);
 auto olddata_all = olddata;
@@ -396,7 +398,7 @@
 %(code)s;

 data &= maskVal;
-if (data != olddata) {
+if (write) {
 if (bits(csr, 11, 10) == 0x3) {
 return std::make_shared(
 csprintf("CSR %s is read-only\n", csrName),  
machInst);


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e7a43cf639474ae76c19a1f430d314b4634ce62
Gerrit-Change-Number: 67717
Gerrit-PatchSet: 3
Gerrit-Owner: chengyong zhong 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: chengyong zhong 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext: Fix typo in DRAMSIM2 Sconscript

2023-02-09 Thread ZHENGRONG WANG (Gerrit) via gem5-dev

ZHENGRONG WANG has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67759?usp=email )



Change subject: ext: Fix typo in DRAMSIM2 Sconscript
..

ext: Fix typo in DRAMSIM2 Sconscript

ClockDoenv should be ClockDomain.

Change-Id: Ibcf3d0dc969624a4e20d86924ef834781b5bbf21
---
M ext/dramsim2/SConscript
1 file changed, 12 insertions(+), 1 deletion(-)



diff --git a/ext/dramsim2/SConscript b/ext/dramsim2/SConscript
index 95b999d..7eb178d 100644
--- a/ext/dramsim2/SConscript
+++ b/ext/dramsim2/SConscript
@@ -59,7 +59,7 @@
 DRAMFile('Bank.cpp')
 DRAMFile('BankState.cpp')
 DRAMFile('BusPacket.cpp')
-DRAMFile('ClockDoenv.cpp')
+DRAMFile('ClockDomain.cpp')
 DRAMFile('CommandQueue.cpp')
 DRAMFile('IniReader.cpp')
 DRAMFile('MemoryController.cpp')

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibcf3d0dc969624a4e20d86924ef834781b5bbf21
Gerrit-Change-Number: 67759
Gerrit-PatchSet: 1
Gerrit-Owner: ZHENGRONG WANG 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: cpu: Add a generic model_reset port on the BaseCPU.

2023-02-09 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67574?usp=email )


Change subject: cpu: Add a generic model_reset port on the BaseCPU.
..

cpu: Add a generic model_reset port on the BaseCPU.

This port will stop execution on the CPU when raised. When lowered, it
will allow execution to reset the state of the CPU and allow execution
to resume. The state could theoretically be reset when the reset state
starts, but then it wouldn't reflect the most up to date condition of
the CPU when resuming. For instance, if a reset vector was set
somehow, that wouldn't be updated if it was changed while reset was
asserted. The tradeoff is that the state won't look like it will when
execution resumes while reset is held (to GDB for instance), but that
seems like a more obvious and less common sort of problem.

This signal is managed by the BaseCPU itself, but is backed by a
virtual method which can be overridden by other CPU types which may
not work the same way or have the same components. For instance, a
fast model CPU could toggle reset lines on the underlying model and
let it handle resetting all the state.

The fast models in particular already have a generic reset line with
the same name, but they have it at the level of the fast model which
may have multiple cores within it, each represented by a gem5 CPU.

It isn't implemented here, but there could be some sort of cooperation
between these signals where the reset at the core level is considered
an "or" of the cluster level reset and the individual core level
resets. At least in the A76 model, there are resets for each individual
core within the cluster as well, which the generic reset toggles.

Another option would be to get rid of the whole cluster reset pin, and
make the user gang the resets for each of the cores together to
whatever reset signal they're using. That's effectively what the
cluster level reset is doing, but within the C++ of the model wrapper
instead of in the python config.

Change-Id: Ie6b4769298ea224ec5dc88360cbb52ee8fbbf69c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67574
Tested-by: kokoro 
Reviewed-by: Roger Chang 
Maintainer: Gabe Black 
Reviewed-by: Yu-hsin Wang 
---
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
3 files changed, 106 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Roger Chang: Looks good to me, but someone else must approve




diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 438d4f4..d77036a 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -53,6 +53,7 @@
 from m5.objects.SubSystem import SubSystem
 from m5.objects.ClockDomain import *
 from m5.objects.Platform import Platform
+from m5.objects.ResetPort import ResetResponsePort

 default_tracer = ExeTracer()

@@ -153,6 +154,8 @@
 "between CPU models)",
 )

+model_reset = ResetResponsePort("Generic reset for the CPU")
+
 tracer = Param.InstTracer(default_tracer, "Instruction tracer")

 icache_port = RequestPort("Instruction Port")
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 98c53d4..60d443a 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -47,6 +47,8 @@
 #include 
 #include 

+#include "arch/generic/decoder.hh"
+#include "arch/generic/isa.hh"
 #include "arch/generic/tlb.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
@@ -130,6 +132,7 @@
   _dataRequestorId(p.system->getRequestorId(this, "data")),
   _taskId(context_switch_task_id::Unknown), _pid(invldPid),
   _switchedOut(p.switched_out),  
_cacheLineSize(p.system->cacheLineSize()),

+  modelResetPort(p.name + ".model_reset"),
   interrupts(p.interrupts), numThreads(p.numThreads), system(p.system),
   previousCycle(0), previousState(CPU_STATE_SLEEP),
   functionTraceStream(nullptr), currentFunctionStart(0),
@@ -178,6 +181,10 @@
 fatal("Number of ISAs (%i) assigned to the CPU does not equal  
number "

   "of threads (%i).\n", params().isa.size(), numThreads);
 }
+
+modelResetPort.onChange([this](const bool &new_val) {
+setReset(new_val);
+});
 }

 void
@@ -413,6 +420,8 @@
 return getDataPort();
 else if (if_name == "icache_port")
 return getInstPort();
+else if (if_name == "model_reset")
+return modelResetPort;
 else
 return ClockedObject::getPort(if_name, idx);
 }
@@ -479,6 +488,12 @@
 void
 BaseCPU::activateContext(ThreadID thread_num)
 {
+if (modelResetPort.state()) {
+DPRINTF(Thread, "CPU in reset, not activating context %d\n",
+threadContexts[thread_num]->contextId());
+return;
+}
+
 DPRINTF(Thread, "activate contextId %d\n",
 threadContexts[thread_num]->contextId());
 // Squash enter power gating event while cpu gets activa

[gem5-dev] [S] Change in gem5/gem5[develop]: dev: Add a definition for VectorResetResponsePort.

2023-02-09 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67576?usp=email )


Change subject: dev: Add a definition for VectorResetResponsePort.
..

dev: Add a definition for VectorResetResponsePort.

This is just a simple extension of the regular ResetResponsePort, and
is useful if there is a collection of reset pins on a device.

Change-Id: I6ccb21e949d3a51bf8b788ffd23e4b2b02706da9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67576
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
Maintainer: Gabe Black 
---
M src/dev/ResetPort.py
1 file changed, 24 insertions(+), 1 deletion(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Gabe Black: Looks good to me, approved




diff --git a/src/dev/ResetPort.py b/src/dev/ResetPort.py
index f35bc11..15caa47 100644
--- a/src/dev/ResetPort.py
+++ b/src/dev/ResetPort.py
@@ -42,8 +42,15 @@
 super().__init__(RESET_RESPONSE_ROLE, desc)


-# VectorResetRequestPort presents a bank of artifact reset request
+# VectorResetRequestPort represents a bank of artifact reset request
 # ports.
 class VectorResetRequestPort(VectorPort):
 def __init__(self, desc):
 super().__init__(RESET_REQUEST_ROLE, desc, is_source=True)
+
+
+# VectorResetResponsePort represents a bank of artifact reset request
+# ports.
+class VectorResetResponsePort(VectorPort):
+def __init__(self, desc):
+super().__init__(RESET_RESPONSE_ROLE, desc)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ccb21e949d3a51bf8b788ffd23e4b2b02706da9
Gerrit-Change-Number: 67576
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Jenkins build is back to normal : nightly #515

[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix failing SST and SystemC nightly tests

[gem5-dev] [S] Change in gem5/gem5[develop]: ext: Fix typo in DRAMSIM2 Sconscript

[gem5-dev] Jenkins build is back to normal : compiler-checks #513

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-vega: Make VGPR-offset for global SGPR-base signed

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_write_b8_d16_hi

[gem5-dev] [S] Change in gem5/gem5[develop]: python: Ensure that m5.internal.params is available

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Fix the CSR instruction behavior.

[gem5-dev] [S] Change in gem5/gem5[develop]: ext: Fix typo in DRAMSIM2 Sconscript

[gem5-dev] [M] Change in gem5/gem5[develop]: cpu: Add a generic model_reset port on the BaseCPU.

[gem5-dev] [S] Change in gem5/gem5[develop]: dev: Add a definition for VectorResetResponsePort.

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