[gem5-dev] Jenkins build is back to normal : nightly #608

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[gem5-dev] [XS] Change in gem5/gem5[develop]: tests: Add '--duplicate-sources' to libgem5 SST build

[Alex Richardson (Gerrit) via gem5-dev]

Alex Richardson has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70497?usp=email )


Change subject: tests: Add '--duplicate-sources' to libgem5 SST build
..

tests: Add '--duplicate-sources' to libgem5 SST build

Unfortunately the building of SST (in "ext/sst") depends on generated
header files. Therefore it adds the build directory to the include path.
For this to work the libgem5.so must be build with
"--duplicate-sources".

Change-Id: I5ed26a89c81402d421f5dfa110de7cf758f28694
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70497
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M ext/sst/INSTALL.md
M tests/nightly.sh
2 files changed, 5 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/ext/sst/INSTALL.md b/ext/sst/INSTALL.md
index 1034d7d..91f92eb 100644
--- a/ext/sst/INSTALL.md
+++ b/ext/sst/INSTALL.md
@@ -61,9 +61,12 @@
 At the root of gem5 folder,

 ```sh
-scons build/RISCV/libgem5_opt.so -j $(nproc) --without-tcmalloc
+scons build/RISCV/libgem5_opt.so -j $(nproc) --without-tcmalloc  
--duplicate-sources

 ```

+**Note:** `--without-tcmalloc` is required to avoid a conflict with SST's  
malloc.
+`--duplicate-sources` is required as the compilation of SST depends on  
sources to be present in the "build" directory.

+
 ### Compiling the SST integration

 At the root of gem5 folder,
diff --git a/tests/nightly.sh b/tests/nightly.sh
index f5f9295..9286c54 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -159,7 +159,7 @@
 "${gem5_root}" --rm  --memory="${docker_mem_limit}" \
 gcr.io/gem5-test/sst-env:${tag} bash -c "\
 scons build/${isa}/libgem5_${variant}.so -j${compile_threads} \
---without-tcmalloc --ignore-style && \
+--without-tcmalloc --duplicate-sources --ignore-style && \
 cd ext/sst && \
 make clean; make -j ${compile_threads} && \
 sst --add-lib-path=./ sst/example.py && \

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ed26a89c81402d421f5dfa110de7cf758f28694
Gerrit-Change-Number: 70497
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Alex Richardson 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: default to not duplicating sources in the build directory

[Alex Richardson (Gerrit) via gem5-dev]

Alex Richardson has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68758?usp=email )


Change subject: scons: default to not duplicating sources in the build  
directory

..

scons: default to not duplicating sources in the build directory

We now default to --no-duplicate-sources, but keep --duplicate-sources to
opt-out of this new build behaviour in case it introduces regressions.

Change-Id: I2f01ceaef7b6b9bff80f4402081f007110f7e6f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68758
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 7 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/SConstruct b/SConstruct
index e09f0d5..9b25b33 100755
--- a/SConstruct
+++ b/SConstruct
@@ -145,7 +145,13 @@
   help='Enable support for the gprof profiler')
 AddOption('--pprof', action='store_true',
   help='Enable support for the pprof profiler')
-AddOption('--no-duplicate-sources', action='store_false', default=True,
+# Default to --no-duplicate-sources, but keep --duplicate-sources to  
opt-out
+# of this new build behaviour in case it introduces regressions. We could  
use

+# action=argparse.BooleanOptionalAction here once Python 3.9 is required.
+AddOption('--duplicate-sources', action='store_true', default=False,
+  dest='duplicate_sources',
+  help='Create symlinks to sources in the build directory')
+AddOption('--no-duplicate-sources', action='store_false',
   dest='duplicate_sources',
   help='Do not create symlinks to sources in the build directory')


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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2f01ceaef7b6b9bff80f4402081f007110f7e6f3
Gerrit-Change-Number: 68758
Gerrit-PatchSet: 6
Gerrit-Owner: Alex Richardson 
Gerrit-Reviewer: Alex Richardson 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Fix WFI for O3 CPU

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70657?usp=email )


Change subject: arch-riscv: Fix WFI for O3 CPU
..

arch-riscv: Fix WFI for O3 CPU

This commit:
https://gem5-review.googlesource.com/c/public/gem5/+/61511
introduced a bug where the O3 CPU hangs. This is because WFI must be
tagged as `IsNonSpeculative`, `IsQuiesce`, and `IsSerializeAfter` to
function correctly with O3 CPUs.

Change-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445
Issue-on: https://gem5.atlassian.net/browse/GEM5-1323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70657
Maintainer: Jason Lowe-Power 
Reviewed-by: Roger Chang 
Reviewed-by: Jui-min Lee 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Jui-min Lee: Looks good to me, approved
  Roger Chang: Looks good to me, but someone else must approve
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index f22efb0..3acd80e 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2278,7 +2278,8 @@
 && xc->readMiscReg(MISCREG_NMIP) == 0) {
 tc->quiesce();
 }
-}}, No_OpClass);
+}}, IsNonSpeculative, IsQuiesce,
+IsSerializeAfter, No_OpClass);
 }
 0x9: sfence_vma({{
 STATUS status = xc->readMiscReg(MISCREG_STATUS);

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445
Gerrit-Change-Number: 70657
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Helper methods for SDWA/DPP for VOP2

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70738?usp=email )



Change subject: arch-vega: Helper methods for SDWA/DPP for VOP2
..

arch-vega: Helper methods for SDWA/DPP for VOP2

Many of the outstanding issues with the GPU model are related to
instructions not having SDWA/DPP implementations and executing by
ignoring the special registers leading to incorrect executiong.
Adding SDWA/DPP is current very cumbersome as there is a lot of
boilerplate code.

This changeset adds helper methods for VOP2 with one instruction
changed as an example. This review is intended to get feedback
before applying this change to all VOP2 instructions that support
SDWA/DPP.

Change-Id: I1edbc3f3bb166d34f151545aa9f47a94150e1406
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/op_encodings.hh
2 files changed, 97 insertions(+), 52 deletions(-)



diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index 6c014bc..0d3f2dc 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -6384,65 +6384,17 @@
 void
 Inst_VOP2__V_MUL_U32_U24::execute(GPUDynInstPtr gpuDynInst)
 {
-Wavefront *wf = gpuDynInst->wavefront();
-ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
-VecOperandU32 src1(gpuDynInst, instData.VSRC1);
-VecOperandU32 vdst(gpuDynInst, instData.VDST);
-
-src0.readSrc();
-src1.read();
-
-if (isSDWAInst()) {
-VecOperandU32 src0_sdwa(gpuDynInst,  
extData.iFmt_VOP_SDWA.SRC0);

-// use copies of original src0, src1, and dest during selecting
-VecOperandU32 origSrc0_sdwa(gpuDynInst,
-extData.iFmt_VOP_SDWA.SRC0);
-VecOperandU32 origSrc1(gpuDynInst, instData.VSRC1);
-VecOperandU32 origVdst(gpuDynInst, instData.VDST);
-
-src0_sdwa.read();
-origSrc0_sdwa.read();
-origSrc1.read();
-
-DPRINTF(VEGA, "Handling V_MUL_U32_U24 SRC SDWA. SRC0:  
register "

-"v[%d], DST_SEL: %d, DST_U: %d, CLMP: %d, SRC0_SEL: "
-"%d, SRC0_SEXT: %d, SRC0_NEG: %d, SRC0_ABS: %d,  
SRC1_SEL: "

-"%d, SRC1_SEXT: %d, SRC1_NEG: %d, SRC1_ABS: %d\n",
-extData.iFmt_VOP_SDWA.SRC0,  
extData.iFmt_VOP_SDWA.DST_SEL,

-extData.iFmt_VOP_SDWA.DST_U,
-extData.iFmt_VOP_SDWA.CLMP,
-extData.iFmt_VOP_SDWA.SRC0_SEL,
-extData.iFmt_VOP_SDWA.SRC0_SEXT,
-extData.iFmt_VOP_SDWA.SRC0_NEG,
-extData.iFmt_VOP_SDWA.SRC0_ABS,
-extData.iFmt_VOP_SDWA.SRC1_SEL,
-extData.iFmt_VOP_SDWA.SRC1_SEXT,
-extData.iFmt_VOP_SDWA.SRC1_NEG,
-extData.iFmt_VOP_SDWA.SRC1_ABS);
-
-processSDWA_src(extData.iFmt_VOP_SDWA, src0_sdwa,  
origSrc0_sdwa,

-src1, origSrc1);
-
-for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
-if (wf->execMask(lane)) {
-vdst[lane] = bits(src0_sdwa[lane], 23, 0) *
- bits(src1[lane], 23, 0);
-origVdst[lane] = vdst[lane]; // keep copy consistent
-}
-}
-
-processSDWA_dst(extData.iFmt_VOP_SDWA, vdst, origVdst);
-} else {
+auto opImpl = [](VecOperandU32& src0, VecOperandU32& src1,
+ VecOperandU32& vdst, Wavefront* wf) {
 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
 if (wf->execMask(lane)) {
 vdst[lane] = bits(src0[lane], 23, 0) *
  bits(src1[lane], 23, 0);
 }
 }
-}
+};

-
-vdst.write();
+vop2Helper(gpuDynInst, opImpl);
 } // execute
 // --- Inst_VOP2__V_MUL_HI_U32_U24 class methods ---

diff --git a/src/arch/amdgpu/vega/insts/op_encodings.hh  
b/src/arch/amdgpu/vega/insts/op_encodings.hh

index 1071ead..f195472 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.hh
+++ b/src/arch/amdgpu/vega/insts/op_encodings.hh
@@ -272,6 +272,99 @@
 InstFormat extData;
 uint32_t varSize;

+template
+T sdwaSrcHelper(GPUDynInstPtr gpuDynInst, T & src1)
+{
+T src0_sdwa(gpuDynInst, extData.iFmt_VOP_SDWA.SRC0);
+// use copies of original src0, src1, and dest during selecting
+T origSrc0_sdwa(gpuDynInst, extData.iFmt_VOP_SDWA.SRC0);
+T origSrc1(gpuDynInst, instData.VSRC1);
+
+src0_sdwa.read();
+origSrc0_sdwa.read();
+origSrc1.read();
+
+DPRINTF(VEGA, 

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email

to review the following change.


Change subject: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT  
insts.

..

arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.

Re-factored the Arm instruction decoder to add placeholders for the
SVE Integer mixed-sign DOT product instructions. This has involved
moving some existing decode helper functions.

Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/formats/sve_top_level.isa
2 files changed, 128 insertions(+), 16 deletions(-)



diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa  
b/src/arch/arm/isa/formats/sve_2nd_level.isa

index e0ab5f9..4148b96 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2241,7 +2241,7 @@
 }

 StaticInstPtr
-decodeSveMultiplyAddUnpred(ExtMachInst machInst)
+decodeSveIntegerDotProductUnpred(ExtMachInst machInst)
 {
 RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
 RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
@@ -2273,10 +2273,10 @@
 }

 return new Unknown64(machInst);
-} // decodeSveMultiplyAddUnpred
+} // decodeSveIntegerDotProductUnpred

 StaticInstPtr
-decodeSveMultiplyIndexed(ExtMachInst machInst)
+decodeSveIntegerDotProductIndexed(ExtMachInst machInst)
 {
 RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
 RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
@@ -2310,7 +2310,59 @@
 }
 }
 return new Unknown64(machInst);
-} // decodeSveMultiplyIndexed
+} // decodeSveIntegerDotProductIndexed
+
+StaticInstPtr
+decodeSveMixedSignDotProduct(ExtMachInst machInst)
+{
+uint8_t size = (uint8_t) bits(machInst, 23, 22);
+if (size != 0b10) {
+return new Unknown64(machInst);
+}
+
+RegIndex zda M5_VAR_USED = (RegIndex)
+  (uint8_t) bits(machInst, 4, 0);
+RegIndex zn M5_VAR_USED = (RegIndex)
+  (uint8_t) bits(machInst, 9, 5);
+RegIndex zm M5_VAR_USED = (RegIndex)
+  (uint8_t) bits(machInst, 20, 16);
+
+// Placeholder for SveUsdotv
+//return SveUsdotv(machInst, zda, zn,  
zm);

+return new Unknown64(machInst);
+} // decodeSveMixedSignDotProduct
+
+StaticInstPtr
+decodeSveMixedSignDotProductIndexed(ExtMachInst machInst)
+{
+uint8_t size = (uint8_t) bits(machInst, 23, 22);
+if (size != 0b10) {
+return new Unknown64(machInst);
+}
+
+RegIndex zda M5_VAR_USED = (RegIndex)
+  (uint8_t) bits(machInst, 4, 0);
+RegIndex zn M5_VAR_USED = (RegIndex)
+  (uint8_t) bits(machInst, 9, 5);
+RegIndex zm M5_VAR_USED = (RegIndex)
+  (uint8_t) bits(machInst, 18, 16);
+uint8_t i2 M5_VAR_USED = (uint8_t) bits(machInst, 20, 19);
+
+uint8_t usig = (uint8_t) bits(machInst, 10);
+
+if (usig) {
+// Placeholder for SveSudoti
+//return SveSudoti
+// (machInst, zda, zn, zm, i2);
+return new Unknown64(machInst);
+} else {
+// Placeholder for SveUsdoti
+//return SveUsdoti
+// (machInst, zda, zn, zm, i2);
+return new Unknown64(machInst);
+}
+
+} // decodeSveMixedSignDotProductIndexed

 StaticInstPtr
 decodeSveFpFastReduc(ExtMachInst machInst)
@@ -3805,6 +3857,43 @@
 return new Unknown64(machInst);
 }  // decodeSveMisc

+StaticInstPtr
+decodeSveIntegerMulAddUnpred(ExtMachInst machInst)
+{
+uint8_t op1 = (uint8_t) bits(machInst, 13, 11);
+if (bits(machInst, 14) == 0b0) {
+if (op1 == 0b000) {
+return decodeSveIntegerDotProductUnpred(machInst);
+} else {
+return new Unknown64(machInst);
+}
+} else {
+if (op1 == 0b111 &&
+bits(machInst, 10) == 0b0) {
+return decodeSveMixedSignDotProduct(machInst);
+} else {
+return new Unknown64(machInst);
+}
+}
+}
+
+StaticInstPtr
+decodeSveMultiplyIndexed(ExtMachInst machInst)
+{
+if (bits(machInst, 15, 13) == 0b000) {
+switch (bits(machInst, 12, 11)) {
+  case 0b00:
+return 

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-F64MM.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70729?usp=email

to review the following change.


Change subject: arch-arm: Declare support for Armv8.2-F64MM.
..

arch-arm: Declare support for Armv8.2-F64MM.

Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares
support for ARMv8.2-F64MM.

This indicates that all pre-requisites for Armv8.2 SVE FP64
double-precision floating-point matrix multiplication instructions
have been met.

FMMLA, and LD1RO* instructions have been implemented, as well as the
128-bit element variants of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
3 files changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 31ecbcb..fbd93b6 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -54,6 +54,7 @@
 "FEAT_RDM",
 # Armv8.2
 "FEAT_F32MM",
+"FEAT_F64MM",
 "FEAT_SVE",
 # Armv8.3
 "FEAT_FCMA",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 06d1dcc..5517632 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -79,6 +79,7 @@
 "FEAT_LVA",  # Optional in Armv8.2
 "FEAT_LPA",  # Optional in Armv8.2
 "FEAT_F32MM", # Optional in Armv8.2
+"FEAT_F64MM", # Optional in Armv8.2
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -165,6 +166,7 @@
 "FEAT_LPA",
 "FEAT_SVE",
 "FEAT_F32MM",
+"FEAT_F64MM",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -199,6 +201,7 @@
 "FEAT_LPA",
 "FEAT_SVE",
 "FEAT_F32MM",
+"FEAT_F64MM",
 ]


diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6cabfca..362f996 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5405,6 +5405,7 @@
 .reset([this](){
 AA64ZFR0 zfr0_el1 = 0;
 zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 :  
0;
+zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 :  
0;

 return zfr0_el1;
 }())
 .faultRead(EL0, faultIdst)

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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440
Gerrit-Change-Number: 70729
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-I8MM NEON extension.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70737?usp=email

to review the following change.


Change subject: arch-arm: Add support for Armv8.2-I8MM NEON extension.
..

arch-arm: Add support for Armv8.2-I8MM NEON extension.

Add support for the Armv8.2-I8MM NEON extension. This provides the
SUDOT and USDOT mixed-sign SIMD Dot Product instructions, as well as
the SMMLA, UMMLA, and USMMLA SIMD Matrix Multiply-Accumulate
instructions.

For more information please refer to the Arm Architecture Reference
Manual (https://developer.arm.com/documentation/ddi0487/latest/).

Additional Contributors: Giacomo Travaglini

Change-Id: I6fb9318f67cc9d2737079283e1a095630c4d2ad9
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/neon64.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc_types.hh
4 files changed, 138 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index e083f6f..8d9b74d 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -510,6 +510,7 @@
 decodeNeon3RegExtension(ExtMachInst machInst)
 {
 uint8_t q  = bits(machInst, 30);
+uint8_t u  = bits(machInst, 29);
 uint8_t qu = bits(machInst, 30, 29);
 uint8_t size   = bits(machInst, 23, 22);
 uint8_t opcode = bits(machInst, 15, 11);
@@ -546,6 +547,20 @@
 default:
   return new Unknown64(machInst);
   }
+  case 0x13:
+  if (q) {
+  return new UsdotQX(machInst, vd, vn, vm);
+  } else {
+  return new UsdotDX(machInst, vd, vn, vm);
+  }
+  case 0x14:
+  if (u) {
+  return new UmmlaQX(machInst, vd, vn, vm);
+  } else {
+  return new SmmlaQX(machInst, vd, vn, vm);
+  }
+  case 0x15:
+  return new UsmmlaQX(machInst, vd, vn, vm);
   case 0x18:
   case 0x19:
   case 0x1a:
@@ -1590,9 +1605,6 @@
 return decodeNeonSThreeImmHAndWReg(
 q, size, machInst, vd, vn, vm, index);
-  case 0xf:
-return decodeNeonSThreeImmHAndWRegSqrdmlshElemQX>(

-q, size, machInst, vd, vn, vm, index);
   case 0xe:
   switch (qu) {
 case 0b00:
@@ -1610,6 +1622,39 @@
 default:
   return new Unknown64(machInst);
   }
+  case 0xf:
+  if (u) {
+   // Armv8.2-RDMA SQRDMLSH(elem)
+   return decodeNeonSThreeImmHAndWReg(
+   q, size, machInst, vd, vn, vm, index);
+  } else {
+  switch (size) {
+  case 0x0:
+  if (q) {
+  return new SudotElemQX(
+  machInst, vd, vn, vm_dp, index_dp);
+  } else {
+  return new SudotElemDX(
+  machInst, vd, vn, vm_dp, index_dp);
+  }
+  case 0x1:
+   // Armv8.2-BF16 BFDOT(elem)
+   return new Unknown64(machInst);
+  case 0x2:
+  if (q) {
+  return new UsdotElemQX(
+  machInst, vd, vn, vm_dp, index_dp);
+  } else {
+  return new UsdotElemDX(
+  machInst, vd, vn, vm_dp, index_dp);
+  }
+  case 0x3:
+  default:
+   // Armv8.2-BF16 BFMLALB(elem), BFMLALT(elem)
+   return new Unknown64(machInst);
+  }
+  }
   default:
 return new Unknown64(machInst);
 }
diff --git a/src/arch/arm/isa/insts/neon64.isa  
b/src/arch/arm/isa/insts/neon64.isa

index 53c0f11..6608f61 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1146,6 +1146,94 @@
 # UDOT (element)
 intDotInst('udot', 'UdotElemDX', 'SimdAluOp', False, False, False, 2,  
True)
 intDotInst('udot', 'UdotElemQX', 'SimdAluOp', False, False, False, 4,  
True)

+# SUDOT (element)
+intDotInst('sudot', 'SudotElemDX', 'SimdAluOp', True, True, False, 2,  
True)
+intDotInst('sudot', 'SudotElemQX', 'SimdAluOp', True, True, False, 4,  
True)

+# USDOT (vector)
+intDotInst('usdot', 'UsdotDX', 'SimdAluOp', True, False, True, 2,  
False)
+intDotInst('usdot', 'UsdotQX', 'SimdAluOp', True, False, True, 4,  
False)

+

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-I8MM.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70733?usp=email

to review the following change.


Change subject: arch-arm: Declare support for Armv8.2-I8MM.
..

arch-arm: Declare support for Armv8.2-I8MM.

Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares
support for ARMv8.2-I8MM.

This indicates that all pre-requisites for Armv8.2 SVE Int8 matrix
multiplication instructions have been met.

SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
3 files changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index fbd93b6..ffe63eb 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -56,6 +56,7 @@
 "FEAT_F32MM",
 "FEAT_F64MM",
 "FEAT_SVE",
+"FEAT_I8MM",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5517632..9e66ee7 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -80,6 +80,7 @@
 "FEAT_LPA",  # Optional in Armv8.2
 "FEAT_F32MM", # Optional in Armv8.2
 "FEAT_F64MM", # Optional in Armv8.2
+"FEAT_I8MM", # Optional in Armv8.2
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -167,6 +168,7 @@
 "FEAT_SVE",
 "FEAT_F32MM",
 "FEAT_F64MM",
+"FEAT_I8MM",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -202,6 +204,7 @@
 "FEAT_SVE",
 "FEAT_F32MM",
 "FEAT_F64MM",
+"FEAT_I8MM",
 ]


diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 362f996..6b299aa 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5406,6 +5406,7 @@
 AA64ZFR0 zfr0_el1 = 0;
 zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 :  
0;
 zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 :  
0;

+zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0;
 return zfr0_el1;
 }())
 .faultRead(EL0, faultIdst)

--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4
Gerrit-Change-Number: 70733
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix too long lines in existing Arm NEON instructons.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70735?usp=email

to review the following change.


Change subject: arch-arm: Fix too long lines in existing Arm NEON  
instructons.

..

arch-arm: Fix too long lines in existing Arm NEON instructons.

These lines break the current gem5 coding guidelines.

Change-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/neon64.isa
M src/arch/arm/isa/insts/neon64.isa
2 files changed, 39 insertions(+), 26 deletions(-)



diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index c200da7..5cce0d7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2012-2013 ARM Limited
+// Copyright (c) 2012-2013, 2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -1213,13 +1213,17 @@

 switch (imm5_pos) {
   case 0:
-return new InsElemX(machInst, vd, vn, index1,  
index2);

+return new InsElemX(
+machInst, vd, vn, index1, index2);
   case 1:
-return new InsElemX(machInst, vd, vn, index1,  
index2);

+return new InsElemX(
+machInst, vd, vn, index1, index2);
   case 2:
-return new InsElemX(machInst, vd, vn, index1,  
index2);

+return new InsElemX(
+machInst, vd, vn, index1, index2);
   case 3:
-return new InsElemX(machInst, vd, vn, index1,  
index2);

+return new InsElemX(
+machInst, vd, vn, index1, index2);
   default:
 return new Unknown64(machInst);
 }
@@ -1547,14 +1551,16 @@
 if (u || (size == 0x0 || size == 0x3))
 return new Unknown64(machInst);
 else
-return decodeNeonSThreeImmHAndWRegSqdmullElem2X>(

-q, size, machInst, vd, vn, vm, index);
+return decodeNeonSThreeImmHAndWReg
+(
+q, size, machInst, vd, vn, vm, index);
   case 0xc:
 if (u || (size == 0x0 || size == 0x3))
 return new Unknown64(machInst);
 else
-return decodeNeonSThreeImmHAndWRegSqdmulhElemQX>(

-q, size, machInst, vd, vn, vm, index);
+return decodeNeonSThreeImmHAndWReg
+(
+q, size, machInst, vd, vn, vm, index);
   case 0xd:
 if (u)
 return decodeNeonSThreeImmHAndWReg-return decodeNeonSThreeHAndWReg(size, machInst,  
vd, vn, vm);

+return decodeNeonSThreeHAndWReg(
+size, machInst, vd, vn, vm);
   case 0xb:
-return decodeNeonSThreeHAndWReg(size, machInst,  
vd, vn, vm);

+return decodeNeonSThreeHAndWReg(
+size, machInst, vd, vn, vm);
   case 0xd:
-return decodeNeonSThreeHAndWReg(size, machInst,  
vd, vn, vm);

+return decodeNeonSThreeHAndWReg(
+size, machInst, vd, vn, vm);
   default:
 return new Unknown64(machInst);
 }
diff --git a/src/arch/arm/isa/insts/neon64.isa  
b/src/arch/arm/isa/insts/neon64.isa

index e0083c9..0da7f06 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1,6 +1,6 @@
 // -*- mode: c++ -*-

-// Copyright (c) 2012-2013, 2015-2018 ARM Limited
+// Copyright (c) 2012-2013, 2015-2018, 2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -1993,9 +1993,9 @@
 Element carryBit =
 (((unsigned)srcElem1 & 0x1) +
  ((unsigned)srcElem2 & 0x1)) >> 1;
-// Use division instead of a shift to ensure the sign  
extension works
-// right. The compiler will figure out if it can be a shift.  
Mask the

-// inputs so they get truncated correctly.
+// Use division instead of a shift to ensure the sign extension
+// works right. The compiler will figure out if it can be a  
shift.

+// Mask the inputs so they get truncated correctly.
 destElem = (((srcElem1 & ~(Element)1) / 2) +
 ((srcElem2 & ~(Element)1) / 2)) + carryBit;
 '''
@@ -2035,9 +2035,9 @@
 hsubCode = '''
 Element borrowBit =
 (((srcElem1 & 0x1) - (srcElem2 & 0x1)) >> 1) & 0x1;
-// Use division instead of a shift to ensure the 

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70734?usp=email

to review the following change.


Change subject: arch-arm, cpu, configs: Add new Op Classes for Matrix  
Multiply insts

..

arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE
Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and
I8MM extensions.

Initial latencies have been set to be the same as SimdMultAcc and
SimdFloatMultAcc respectively.

Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Reviewed-by: Richard Cooper 
---
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M src/arch/arm/isa/insts/sve.isa
M src/cpu/FuncUnit.py
M src/cpu/minor/BaseMinorCPU.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/op_class.hh
9 files changed, 23 insertions(+), 7 deletions(-)



diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

index c7a8127..d3d4605 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -1420,6 +1420,7 @@
 "SimdMisc",
 "SimdMult",
 "SimdMultAcc",
+"SimdMatMultAcc",
 "SimdShift",
 "SimdShiftAcc",
 "SimdSqrt",
@@ -1431,6 +1432,7 @@
 "SimdFloatMisc",
 "SimdFloatMult",
 "SimdFloatMultAcc",
+"SimdFloatMatMultAcc",
 "SimdFloatSqrt",
 ]
 )
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py  
b/configs/common/cores/arm/O3_ARM_v7a.py

index 77dc4e4..be9abd6 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -53,6 +53,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=5),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass='SimdMatMultAcc',opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -64,6 +65,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=3),
 OpDesc(opClass="SimdFloatMult", opLat=3),
 OpDesc(opClass="SimdFloatMultAcc", opLat=5),
+OpDesc(opClass='SimdFloatMatMultAcc',opLat=5),
 OpDesc(opClass="SimdFloatSqrt", opLat=9),
 OpDesc(opClass="FloatAdd", opLat=5),
 OpDesc(opClass="FloatCmp", opLat=5),
diff --git a/configs/common/cores/arm/ex5_LITTLE.py  
b/configs/common/cores/arm/ex5_LITTLE.py

index 6974837..b6fed94 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -56,6 +56,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=4),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass='SimdMatMultAcc',opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -67,6 +68,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=6),
 OpDesc(opClass="SimdFloatMult", opLat=15),
 OpDesc(opClass="SimdFloatMultAcc", opLat=6),
+OpDesc(opClass='SimdFloatMatMultAcc',opLat=6),
 OpDesc(opClass="SimdFloatSqrt", opLat=17),
 OpDesc(opClass="FloatAdd", opLat=8),
 OpDesc(opClass="FloatCmp", opLat=6),
diff --git a/configs/common/cores/arm/ex5_big.py  
b/configs/common/cores/arm/ex5_big.py

index 70af6b8..4383f96 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -58,6 +58,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=6),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass='SimdMatMultAcc',opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -69,6 +70,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=3),
 OpDesc(opClass="SimdFloatMult", opLat=6),
 OpDesc(opClass="SimdFloatMultAcc", opLat=1),
+OpDesc(opClass='SimdFloatMatMultAcc',opLat=1),
 OpDesc(opClass="SimdFloatSqrt", opLat=9),
 OpDesc(opClass="FloatAdd", opLat=6),
 OpDesc(opClass="FloatCmp", opLat=5),
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b6b560d..0993c47 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3929,7 +3929,7 @@
 fplibMul(srcElemA, srcElemB, fpscr), fpscr);
 '''
 # FMMLA (vectors)
-sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMultAccOp', floatTypes,
+sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMatMultAccOp', 

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE Integer Matrix instructions.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70730?usp=email

to review the following change.


Change subject: arch-arm: Add support for Arm SVE Integer Matrix  
instructions.

..

arch-arm: Add support for Arm SVE Integer Matrix instructions.

Add support for the Arm SVE Integer Matrix Multiply-Accumulate
(SMMLA, USMMLA, UMMLA) instructions. Because the associated SUDOT and
USDOT instructions have not yet been implemented, the SVE Feature ID
register 0 (ID_AA64ZFR0_EL1) has not yet been updated to indicate
support for SVE Int8 matrix multiplication instructions at this time.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Additional Contributors: Giacomo Travaglini

Change-Id: Ia50e28fae03634cbe04b42a9900bab65a604817f
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/insts/sve.isa
3 files changed, 72 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa  
b/src/arch/arm/isa/formats/sve_2nd_level.isa

index 6add341..e0ab5f9 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -246,6 +246,33 @@
 }  // decodeSveIntMulAdd

 StaticInstPtr
+decodeSveIntMatMulAdd(ExtMachInst machInst)
+{
+RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+
+uint8_t uns = bits(machInst, 23, 22);
+
+switch (uns) {
+  case 0x0:
+return new SveSmmla(
+ machInst, zda, zn, zm);
+  case 0x2:
+return new SveUsmmla(
+ machInst, zda, zn, zm);
+  case 0x3:
+return new SveUmmla(
+ machInst, zda, zn, zm);
+  case 0x1:
+  default:
+return new Unknown64(machInst);
+}
+
+return new Unknown64(machInst);
+}  // decodeSveIntMatMulAdd
+
+StaticInstPtr
 decodeSveShiftByImmPred0(ExtMachInst machInst)
 {
 RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
@@ -3763,5 +3790,21 @@
 return new Unknown64(machInst);
 }  // decodeSveMemStore

+StaticInstPtr
+decodeSveMisc(ExtMachInst machInst) {
+switch(bits(machInst, 13, 10)) {
+  case 0b0110: {
+  return decodeSveIntMatMulAdd(machInst);
+  break;
+  }
+  default: {
+  return new Unknown64(machInst);
+  break;
+  }
+}
+return new Unknown64(machInst);
+}  // decodeSveMisc
+
+
 }  // namespace Aarch64
 }};
diff --git a/src/arch/arm/isa/formats/sve_top_level.isa  
b/src/arch/arm/isa/formats/sve_top_level.isa

index 1f3b463..0699637 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -44,6 +44,7 @@
 StaticInstPtr decodeSveShiftByImmPred(ExtMachInst machInst);
 StaticInstPtr decodeSveIntArithUnaryPred(ExtMachInst machInst);
 StaticInstPtr decodeSveIntMulAdd(ExtMachInst machInst);
+StaticInstPtr decodeSveIntMatMulAdd(ExtMachInst machInst);
 StaticInstPtr decodeSveIntArithUnpred(ExtMachInst machInst);
 StaticInstPtr decodeSveIntLogUnpred(ExtMachInst machInst);
 StaticInstPtr decodeSveIndexGen(ExtMachInst machInst);
@@ -93,6 +94,8 @@
 StaticInstPtr decodeSveMemContigLoad(ExtMachInst machInst);
 StaticInstPtr decodeSveMemGather64(ExtMachInst machInst);
 StaticInstPtr decodeSveMemStore(ExtMachInst machInst);
+
+StaticInstPtr decodeSveMisc(ExtMachInst machInst);
 }
 }};

@@ -103,6 +106,14 @@
 StaticInstPtr
 decodeSveInt(ExtMachInst machInst)
 {
+if (bits(machInst, 31, 29) == 0b010) {
+if (bits(machInst, 24) == 0b1 &&
+bits(machInst, 21) == 0b0 &&
+bits(machInst, 15, 14)==0b10) {
+return decodeSveMisc(machInst);
+}
+}
+
 uint8_t b_29_24_21 = (bits(machInst, 29) << 2) |
  (bits(machInst, 24) << 1) |
  bits(machInst, 21);
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 30dbeba..f7bf8a3 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -4192,6 +4192,24 @@
 # MLS
 mlsCode = 'destElem -= srcElem1 * srcElem2;'
 sveTerInst('mls', 'Mls', 'SimdMultAccOp', signedTypes, mlsCode)
+
+   

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Added Armv8.2-I8MM SVE mixed-sign dot product instrs.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70732?usp=email

to review the following change.


Change subject: arch-arm: Added Armv8.2-I8MM SVE mixed-sign dot product  
instrs.

..

arch-arm: Added Armv8.2-I8MM SVE mixed-sign dot product instrs.

Add support for the SVE mixed sign dot product instructions (USDOT,
SUDOT) required by the Armv8.2 SVE Int8 matrix multiplication
extension (ARMv8.2-I8MM).

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Change-Id: I83841654cee74b940f967b3a37b99d87c01bd92c
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/templates/sve.isa
3 files changed, 91 insertions(+), 47 deletions(-)



diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa  
b/src/arch/arm/isa/formats/sve_2nd_level.isa

index 4148b96..051323f 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2256,19 +2256,19 @@
 uint8_t usig = (uint8_t) bits(machInst, 10);
 if (size & 0x1) {
 if (usig) {
-return new SveUdotv(machInst,
-zda, zn, zm);
+return new SveUdotv
+(machInst, zda, zn, zm);
 } else {
-return new SveSdotv(machInst,
-zda, zn, zm);
+return new SveSdotv
+(machInst, zda, zn, zm);
 }
 } else {
 if (usig) {
-return new SveUdotv(machInst,
-zda, zn, zm);
+return new SveUdotv
+(machInst, zda, zn, zm);
 } else {
-return new SveSdotv(machInst,
-zda, zn, zm);
+return new SveSdotv
+(machInst, zda, zn, zm);
 }
 }

@@ -2292,21 +2292,21 @@
 RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 19, 16);
 uint8_t i1 = (uint8_t) bits(machInst, 20);
 if (usig) {
-return new SveUdoti(machInst,
-zda, zn, zm, i1);
+return new SveUdoti
+   (machInst, zda, zn, zm, i1);
 } else {
-return new SveSdoti(machInst,
-zda, zn, zm, i1);
+return new SveSdoti
+   (machInst, zda, zn, zm, i1);
 }
 } else {
 RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 18, 16);
 uint8_t i2 = (uint8_t) bits(machInst, 20, 19);
 if (usig) {
-return new SveUdoti(machInst,
-zda, zn, zm, i2);
+return new SveUdoti
+(machInst, zda, zn, zm, i2);
 } else {
-return new SveSdoti(machInst,
-zda, zn, zm, i2);
+return new SveSdoti
+(machInst, zda, zn, zm, i2);
 }
 }
 return new Unknown64(machInst);
@@ -2327,9 +2327,8 @@
 RegIndex zm M5_VAR_USED = (RegIndex)
   (uint8_t) bits(machInst, 20, 16);

-// Placeholder for SveUsdotv
-//return SveUsdotv(machInst, zda, zn,  
zm);

-return new Unknown64(machInst);
+return new SveUsdotv
+ (machInst, zda, zn, zm);
 } // decodeSveMixedSignDotProduct

 StaticInstPtr
@@ -2351,15 +2350,11 @@
 uint8_t usig = (uint8_t) bits(machInst, 10);

 if (usig) {
-// Placeholder for SveSudoti
-//return SveSudoti
-// (machInst, zda, zn, zm, i2);
-return new Unknown64(machInst);
+return new SveSudoti
+ (machInst, zda, zn, zm, i2);
 } else {
-// Placeholder for SveUsdoti
-//return SveUsdoti
-// (machInst, zda, zn, zm, i2);
-return new Unknown64(machInst);
+return new SveUsdoti
+ 

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Support Arm SVE Load-Broadcast Octaword instructions.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70727?usp=email

to review the following change.


Change subject: arch-arm: Support Arm SVE Load-Broadcast Octaword  
instructions.

..

arch-arm: Support Arm SVE Load-Broadcast Octaword instructions.

Add support for the Arm SVE Load-Broadcast Octaword (LD1RO{B,H,W,D})
instructions. These are similar to the Load-Broadcast
Quadword (LD1RQ{B,H,W,D}) instructions, but work on a 32-byte memory
segment rather than a 16-byte memory segment. Consequently, the LD1ROx
implementations build on the code for the LD1RQx implementations.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Change-Id: I98ee4f56c8099bf40c9034baa488d318ae57d3aa
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve_mem.isa
2 files changed, 115 insertions(+), 54 deletions(-)



diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa  
b/src/arch/arm/isa/formats/sve_2nd_level.isa

index bb3c8e2..be57223 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2839,9 +2839,9 @@
 StaticInstPtr
 decodeSveFpFusedMatMulAdd(ExtMachInst machInst)
 {
-IntRegIndex zda = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
-IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
-IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);

 uint8_t size = bits(machInst, 23, 22);
 switch (size) {
@@ -3173,66 +3173,96 @@
 }  // decodeSveMemGather32

 StaticInstPtr
-decodeSveLoadBcastQuadSS(ExtMachInst machInst)
+decodeSveLoadBcastMultiSS(ExtMachInst machInst)
 {
-uint8_t num = bits(machInst, 22, 21);
-if (num != 0x00) {
-return new Unknown64(machInst);
-}
-
 RegIndex zt = (RegIndex)(uint8_t) bits(machInst, 4, 0);
 RegIndex rn = makeSP((RegIndex)(uint8_t) bits(machInst, 9, 5));
 RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
 RegIndex rm = (RegIndex)(uint8_t) bits(machInst, 20, 16);
-uint8_t msz = bits(machInst, 24, 23);
-switch (msz) {
-case 0:
+
+uint8_t msz_esz = bits(machInst, 24, 21);
+
+switch (msz_esz) {
+// Load-Broadcast Quad-word Variants
+case 0b: // 0x0:
 return new SveLd1RqSS("ld1rqb",
 machInst, zt, pg, rn, rm);
-case 1:
-return new SveLd1RqSS("ld1rqh",
+case 0b0100: // 0x4:
+ return new SveLd1RqSS("ld1rqh",
 machInst, zt, pg, rn, rm);
-case 2:
+case 0b1000: // 0x8:
 return new SveLd1RqSS("ld1rqw",
 machInst, zt, pg, rn, rm);
-case 3:
+case 0b1100: // 0xc:
 return new SveLd1RqSS("ld1rqd",
 machInst, zt, pg, rn, rm);
+
+// Load-Broadcast Octa-word Variants
+case 0b0001: // 0x1:
+return new SveLd1RoSS("ld1rqb",
+machInst, zt, pg, rn, rm);
+case 0b0101: // 0x5:
+return new SveLd1RoSS("ld1rqh",
+machInst, zt, pg, rn, rm);
+case 0b1001: // 0x9:
+return new SveLd1RoSS("ld1rqw",
+machInst, zt, pg, rn, rm);
+case 0b1101: // 0xd:
+return new SveLd1RoSS("ld1rqd",
+machInst, zt, pg, rn, rm);
+
+default:
+  return new Unknown64(machInst);
 }

 return new Unknown64(machInst);
-}  // decodeSveLoadBcastQuadSS
+}  // decodeSveLoadBcastMultiSS

 StaticInstPtr
-decodeSveLoadBcastQuadSI(ExtMachInst machInst)
+decodeSveLoadBcastMultiSI(ExtMachInst machInst)
 {
-uint8_t num = bits(machInst, 22, 21);
-if (num != 0x00) {
-return new Unknown64(machInst);
-}
-
 RegIndex zt = (RegIndex)(uint8_t) bits(machInst, 4, 0);
 RegIndex rn = makeSP((RegIndex)(uint8_t) bits(machInst, 9, 5));
 RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
 uint64_t imm = sext<4>(bits(machInst, 19, 16));
-uint8_t msz = bits(machInst, 24, 23);
-switch (msz) {
-case 0:
+
+

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-DotProd NEON extension.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70736?usp=email

to review the following change.


Change subject: arch-arm: Add support for Armv8.2-DotProd NEON extension.
..

arch-arm: Add support for Armv8.2-DotProd NEON extension.

Add support for the Armv8.2-DotProd NEON extension. This provides the
SDOT and UDOT SIMD Dot Product instructions.

For more information please refer to the Arm Architecture Reference
Manual (https://developer.arm.com/documentation/ddi0487/latest/).

Change-Id: I4caa3b97a74c65f32421487c55c3e36427194e61
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa/formats/neon64.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/regs/misc.cc
5 files changed, 107 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index ffe63eb..8c1ee5a 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -57,6 +57,7 @@
 "FEAT_F64MM",
 "FEAT_SVE",
 "FEAT_I8MM",
+"FEAT_DOTPROD",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 9e66ee7..c113483 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -81,6 +81,7 @@
 "FEAT_F32MM", # Optional in Armv8.2
 "FEAT_F64MM", # Optional in Armv8.2
 "FEAT_I8MM", # Optional in Armv8.2
+"FEAT_DOTPROD", # Optional in Armv8.2
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -169,6 +170,7 @@
 "FEAT_F32MM",
 "FEAT_F64MM",
 "FEAT_I8MM",
+"FEAT_DOTPROD",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -205,6 +207,7 @@
 "FEAT_F32MM",
 "FEAT_F64MM",
 "FEAT_I8MM",
+"FEAT_DOTPROD",
 ]


diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index 5cce0d7..e083f6f 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -510,6 +510,7 @@
 decodeNeon3RegExtension(ExtMachInst machInst)
 {
 uint8_t q  = bits(machInst, 30);
+uint8_t qu = bits(machInst, 30, 29);
 uint8_t size   = bits(machInst, 23, 22);
 uint8_t opcode = bits(machInst, 15, 11);

@@ -532,6 +533,19 @@
 else
 return decodeNeonSThreeHAndWReg(
 size, machInst, vd, vn, vm);
+  case 0x12:
+  switch (qu) {
+case 0b00:
+  return new SdotDX(machInst, vd, vn, vm);
+case 0b01:
+  return new UdotDX(machInst, vd, vn, vm);
+case 0b10:
+  return new SdotQX(machInst, vd, vn, vm);
+case 0b11:
+  return new UdotQX(machInst, vd, vn, vm);
+default:
+  return new Unknown64(machInst);
+  }
   case 0x18:
   case 0x19:
   case 0x1a:
@@ -1351,6 +1365,7 @@
 {
 uint8_t q = bits(machInst, 30);
 uint8_t u = bits(machInst, 29);
+uint8_t qu = bits(machInst, 30, 29);
 uint8_t size = bits(machInst, 23, 22);
 uint8_t L = bits(machInst, 21);
 uint8_t M = bits(machInst, 20);
@@ -1387,6 +1402,11 @@
 }
 RegIndex vm_fp = (RegIndex) (uint8_t) (vmh << 4 | vm_bf);

+// Index and 2nd register operand for FEAT_DOTPROD and
+// FEAT_I8MM instructions
+uint8_t index_dp = (H << 1) | L;
+RegIndex vm_dp = (RegIndex) (uint8_t) (M << 4 | vm_bf);
+
 switch (opcode) {
   case 0x0:
 if (!u || (size == 0x0 || size == 0x3))
@@ -1573,6 +1593,23 @@
   case 0xf:
 return decodeNeonSThreeImmHAndWRegSqrdmlshElemQX>(

 q, size, machInst, vd, vn, vm, index);
+  case 0xe:
+  switch (qu) {
+case 0b00:
+  return new SdotElemDX(machInst,
+ vd, vn, vm_dp, index_dp);
+case 0b01:
+  return new UdotElemDX(machInst,
+  vd, vn, vm_dp, index_dp);
+case 0b10:
+  return new SdotElemQX(machInst,
+ vd, vn, vm_dp, index_dp);
+case 0b11:
+  return new UdotElemQX(machInst,
+  vd, vn, vm_dp, index_dp);
+default:
+  return new Unknown64(machInst);
+  }
   default:
 return new Unknown64(machInst);
 }
diff --git a/src/arch/arm/isa/insts/neon64.isa  

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE fmmla instruction.

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70726?usp=email

to review the following change.


Change subject: arch-arm: Add support for Arm SVE fmmla instruction.
..

arch-arm: Add support for Arm SVE fmmla instruction.

Add support for the Arm SVE Floating Point Matrix Multiply-Accumulate
(FMMLA) instruction. Both 32-bit element (single precision) and 64-bit
element (double precision) encodings are implemented, but because the
associated required instructions (LD1RO*, etc) have not yet been
implemented, the SVE Feature ID register 0 (ID_AA64ZFR0_EL1) has only
been updated to indicate 32-bit element support at this time.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Additional Contributors: Giacomo Travaglini

Change-Id: If3547378ffa48527fe540767399bcc37a5dab524
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/insts/sve.cc
M src/arch/arm/insts/sve.hh
A src/arch/arm/insts/vector_element_traits.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve.isa
M src/arch/arm/regs/misc.cc
12 files changed, 319 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 37970dc..31ecbcb 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -53,6 +53,7 @@
 "FEAT_LSE",
 "FEAT_RDM",
 # Armv8.2
+"FEAT_F32MM",
 "FEAT_SVE",
 # Armv8.3
 "FEAT_FCMA",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index b826f0d..06d1dcc 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -78,6 +78,7 @@
 "FEAT_UAO",
 "FEAT_LVA",  # Optional in Armv8.2
 "FEAT_LPA",  # Optional in Armv8.2
+"FEAT_F32MM", # Optional in Armv8.2
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -163,6 +164,7 @@
 "FEAT_LVA",
 "FEAT_LPA",
 "FEAT_SVE",
+"FEAT_F32MM",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -196,6 +198,7 @@
 "FEAT_LVA",
 "FEAT_LPA",
 "FEAT_SVE",
+"FEAT_F32MM",
 ]


diff --git a/src/arch/arm/insts/sve.cc b/src/arch/arm/insts/sve.cc
index 546074c..b2f166e 100644
--- a/src/arch/arm/insts/sve.cc
+++ b/src/arch/arm/insts/sve.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019 ARM Limited
+ * Copyright (c) 2017-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -436,6 +436,20 @@
 }

 std::string
+SveTerUnpredOp::generateDisassembly(
+Addr pc, const loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printVecReg(ss, dest, true);
+ccprintf(ss, ", ");
+printVecReg(ss, op1, true);
+ccprintf(ss, ", ");
+printVecReg(ss, op2, true);
+return ss.str();
+}
+
+std::string
 SveTerImmUnpredOp::generateDisassembly(
 Addr pc, const loader::SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh
index 66d82f0..73f4766 100644
--- a/src/arch/arm/insts/sve.hh
+++ b/src/arch/arm/insts/sve.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019 ARM Limited
+ * Copyright (c) 2017-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -498,6 +498,22 @@
 Addr pc, const loader::SymbolTable *symtab) const override;
 };

+/// Ternary, destructive, unpredicated SVE instruction.
+class SveTerUnpredOp : public ArmStaticInst
+{
+  protected:
+RegIndex dest, op1, op2;
+
+SveTerUnpredOp(const char* mnem, ExtMachInst _machInst, OpClass  
__opClass,

+   RegIndex _dest, RegIndex _op1, RegIndex _op2) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), op2(_op2)
+{}
+
+std::string generateDisassembly(
+Addr pc, const loader::SymbolTable *symtab) const override;
+};
+
 /// Ternary with immediate, destructive, unpredicated SVE instruction.
 class SveTerImmUnpredOp : public ArmStaticInst
 {
diff --git a/src/arch/arm/insts/vector_element_traits.hh  
b/src/arch/arm/insts/vector_element_traits.hh

new file mode 100644
index 000..3495bef
--- /dev/null
+++ b/src/arch/arm/insts/vector_element_traits.hh
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to 

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email

to review the following change.


Change subject: arch-arm: Rename AdvSIMD instruction pool
..

arch-arm: Rename AdvSIMD instruction pool

The decoding function was wrongly named decodeNeon3SameExtra,
referring to the "AdvSIMD three same Extra" instruction pool

This might be an old name as I can only find the
"AdvSIMD *scalar* three same Extra" in the Arm arm. The
encoding space reserved to the pool bears the
"Advanced SIMD three-register extension" name; we
therefore rename the function to decodeNeon3RegExtension

Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/neon64.isa
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 9ad2de2..47d509e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2461,7 +2461,7 @@
 return new Unknown64(machInst);
 }
 } else if (bits(machInst, 15) == 1) {
-return decodeNeon3SameExtra(machInst);
+return decodeNeon3RegExtension(machInst);
 } else if (bits(machInst, 10) == 1) {
 if (bits(machInst, 23, 22))
 return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index 72b7e28..c200da7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -39,9 +39,9 @@
 // AdvSIMD three same
 template 
 StaticInstPtr decodeNeon3Same(ExtMachInst machInst);
-// AdvSIMD three same Extra
+// AdvSIMD three register extension
 template 
-StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst);
+StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst);
 // AdvSIMD three different
 inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst);
 // AdvSIMD two-reg misc
@@ -507,7 +507,7 @@

 template 
 StaticInstPtr
-decodeNeon3SameExtra(ExtMachInst machInst)
+decodeNeon3RegExtension(ExtMachInst machInst)
 {
 uint8_t q  = bits(machInst, 30);
 uint8_t size   = bits(machInst, 23, 22);

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Gerrit-Branch: develop
Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Gerrit-Change-Number: 70724
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70719?usp=email

to review the following change.


Change subject: arch-arm: Implement FEAT_FLAGM(2)
..

arch-arm: Implement FEAT_FLAGM(2)

Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/isa/templates/misc64.isa
M src/arch/arm/regs/misc.cc
8 files changed, 239 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index e73046d..37970dc 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -58,6 +58,10 @@
 "FEAT_FCMA",
 "FEAT_JSCVT",
 "FEAT_PAuth",
+# Armv8.4
+"FEAT_FLAGM",
+# Armv8.5
+"FEAT_FLAGM2",
 # Armv9.2
 "FEAT_SME",
 # Other
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 9e2da8e..e08108f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -85,6 +85,9 @@
 # Armv8.4
 "FEAT_SEL2",
 "FEAT_TLBIOS",
+"FEAT_FLAGM",
+# Armv8.5
+"FEAT_FLAGM2",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -164,6 +167,9 @@
 # Armv8.4
 "FEAT_SEL2",
 "FEAT_TLBIOS",
+"FEAT_FLAGM",
+# Armv8.5
+"FEAT_FLAGM2",
 # Armv9.2
 "FEAT_SME",
 ]
@@ -194,11 +200,15 @@


 class Armv84(Armv83):
-extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"]
+extensions = Armv83.extensions +  
["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"]



-class Armv92(Armv84):
-extensions = Armv84.extensions + ["FEAT_SME"]
+class Armv85(Armv84):
+extensions = Armv84.extensions + ["FEAT_FLAGM2"]
+
+
+class Armv92(Armv85):
+extensions = Armv85.extensions + ["FEAT_SME"]


 class ArmSystem(System):
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index c7423d9..4f573fc 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -55,6 +55,27 @@
 }

 std::string
+RegOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab)  
const

+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
+RegImmImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable  
*symtab) const

+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printIntReg(ss, op1);
+ccprintf(ss, "#0x%x", imm1);
+ss << ", ";
+ccprintf(ss, "#0x%x", imm2);
+return ss.str();
+}
+
+std::string
 RegRegImmImmOp64::generateDisassembly(
 Addr pc, const loader::SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index b7b66c2..3a67210 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -57,6 +57,38 @@
 Addr pc, const loader::SymbolTable *symtab) const override;
 };

+class RegOp64 : public ArmISA::ArmStaticInst
+{
+  protected:
+RegIndex op1;
+
+RegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+OpClass __opClass, RegIndex _op1) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
+{}
+
+std::string generateDisassembly(
+Addr pc, const loader::SymbolTable *symtab) const override;
+};
+
+class RegImmImmOp64 : public ArmISA::ArmStaticInst
+{
+  protected:
+RegIndex op1;
+uint64_t imm1;
+uint64_t imm2;
+
+RegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+  OpClass __opClass, RegIndex _op1,
+  uint64_t _imm1, uint64_t _imm2) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
+op1(_op1), imm1(_imm1), imm2(_imm2)
+{}
+
+std::string generateDisassembly(
+Addr pc, const loader::SymbolTable *symtab) const override;
+};
+
 class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 0aafa9e..9ad2de2 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -424,6 +424,15 @@
 // MSR immediate: moving immediate value to  
selected

 // bits of the PSTATE
 switch (op1 << 3 | op2) {
+  case 0x0:
+// CFINV
+return new Cfinv(machInst);
+  case 0x1:
+// XAFLAG
+

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email

to review the following change.


Change subject: arch-arm: Improve debugging of CC regs accesses
..

arch-arm: Improve debugging of CC regs accesses

As of now we are simply printing the CC reg index which is
not particularly helpful. With this patch we actually print
the (NZ|C|V) reg name.

Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/cc.hh
1 file changed, 23 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index ba75527..474e48e 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src/arch/arm/regs/cc.hh
@@ -61,10 +61,31 @@
 NumRegs
 };

+const char * const RegName[NumRegs] = {
+"nz",
+"c",
+"v",
+"ge",
+"fp",
+"zero"
+};
+
 } // namespace cc_reg

-inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName,
-cc_reg::NumRegs, debug::CCRegs);
+class CCRegClassOps : public RegClassOps
+{
+  public:
+std::string
+regName(const RegId ) const override
+{
+return cc_reg::RegName[id.index()];
+}
+};
+
+static inline CCRegClassOps ccRegClassOps;
+
+inline constexpr RegClass ccRegClass = RegClass(CCRegClass, CCRegClassName,
+cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps);

 namespace cc_reg
 {
@@ -77,15 +98,6 @@
 Fp = ccRegClass[_FpIdx],
 Zero = ccRegClass[_ZeroIdx];

-const char * const RegName[NumRegs] = {
-"nz",
-"c",
-"v",
-"ge",
-"fp",
-"zero"
-};
-
 } // namespace cc_reg

 enum ConditionCode

--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Gerrit-Change-Number: 70718
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70722?usp=email

to review the following change.


Change subject: arch-arm: Implement trapping of SME registers
..

arch-arm: Implement trapping of SME registers

Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc.cc
1 file changed, 80 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index df1f6db..10b7d38 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2002,6 +2002,68 @@
 }

 Fault
+faultEsm(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
+if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.esm) {
+return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return NoFault;
+}
+}
+
+Fault
+faultTsmSmen(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+const HCR hcr_el2 = tc->readMiscReg(MISCREG_HCR_EL2);
+const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
+const bool el2_enabled = EL2Enabled(tc);
+if (el2_enabled && !hcr_el2.e2h && cptr_el2.tsm) {
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+} else if (el2_enabled && hcr_el2.e2h && !(cptr_el2.smen & 0b1)) {
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return faultEsm(entry, tc, inst);
+}
+}
+
+Fault
+faultSmenEL1(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+if (!(cpacr.smen & 0b1)) {
+return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return faultTsmSmen(entry, tc, inst);
+}
+}
+
+Fault
+faultSmenEL0(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+const bool el2_enabled = EL2Enabled(tc);
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+const bool in_host = hcr.e2h && hcr.tge;
+
+const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
+if (!(el2_enabled && in_host) && cpacr.smen != 0b11) {
+if (el2_enabled && hcr.tge)
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+else
+return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
+} else if (el2_enabled && in_host && cptr_el2.smen != 0b11) {
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return faultTsmSmen(entry, tc, inst);
+}
+}
+
+Fault
 faultRng(const MiscRegLUTEntry ,
 ThreadContext *tc, const MiscRegOp64 )
 {
@@ -5347,6 +5409,7 @@
 smfr0_el1.fa64 = 0x1;
 return smfr0_el1;
 }())
+.faultRead(EL1, HCR_TRAP(tid3))
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SVCR)
 .res0([](){
@@ -5355,6 +5418,10 @@
 svcr_mask.za = 1;
 return ~svcr_mask;
 }())
+.fault(EL0, faultSmenEL0)
+.fault(EL1, faultSmenEL1)
+.fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .allPrivileges();
 InitReg(MISCREG_SMIDR_EL1)
 .reset([](){
@@ -5364,11 +5431,17 @@
 smidr_el1.implementer = 0x41;
 return smidr_el1;
 }())
+.faultRead(EL1, HCR_TRAP(tid1))
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SMPRI_EL1)
 .res0(mask(63, 4))
-.allPrivileges().exceptUserMode().reads(1);
+.fault(EL1, faultEsm)
+.fault(EL2, faultEsm)
+.fault(EL3, faultEsm)
+.allPrivileges().exceptUserMode();
 InitReg(MISCREG_SMPRIMAP_EL2)
+.fault(EL2, faultEsm)
+.fault(EL3, faultEsm)
 .hyp().mon();
 InitReg(MISCREG_SMCR_EL3)
 .reset([this](){
@@ -5382,6 +5455,7 @@
 smcr_el3.len = smeVL - 1;
 return smcr_el3;
 }())
+.fault(EL3, faultEsm)
 .mon();
 InitReg(MISCREG_SMCR_EL2)
 .reset([this](){
@@ -5395,6 +5469,8 @@
 smcr_el2.len = smeVL - 1;
 return smcr_el2;
 }())
+.fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .hyp().mon();
 InitReg(MISCREG_SMCR_EL12)
 .allPrivileges().exceptUserMode();
@@ -5410,6 +5486,9 @@
 smcr_el1.len = smeVL - 1;
 return smcr_el1;
 }())
+.fault(EL1, faultSmenEL1)
+.fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .allPrivileges().exceptUserMode();
 InitReg(MISCREG_TPIDR2_EL0)
 .allPrivileges();

--
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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70717?usp=email

to review the following change.


Change subject: arch-arm: Split decodeDataProcReg into subfunctions
..

arch-arm: Split decodeDataProcReg into subfunctions

This will increase readibility, it will make it easier
for devs to add new instructions, and it removes some
duplication (some register indexes were read more than
once)

Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/aarch64.isa
1 file changed, 361 insertions(+), 309 deletions(-)



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 2fd28f8..0aafa9e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1958,6 +1958,359 @@
 output decoder {{
 namespace Aarch64
 {
+
+StaticInstPtr
+decodeLogical(ExtMachInst machInst)
+{
+uint8_t imm6 = bits(machInst, 15, 10);
+bool sf = bits(machInst, 31);
+if (!sf && (imm6 & 0x20))
+return new Unknown64(machInst);
+
+RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+RegIndex rdzr = makeZero(rd);
+RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
+ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22);
+
+uint8_t switch_val = (bits(machInst, 21) << 0) |
+(bits(machInst, 30, 29) << 1);
+
+switch (switch_val) {
+  case 0x0:
+return new AndXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x1:
+return new BicXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x2:
+return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x3:
+return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x4:
+return new EorXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x5:
+return new EonXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x6:
+return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  case 0x7:
+return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  default:
+GEM5_UNREACHABLE;
+}
+}
+
+StaticInstPtr
+decodeAddSub(ExtMachInst machInst)
+{
+uint8_t switch_val = bits(machInst, 30, 29);
+if (bits(machInst, 21) == 0) {
+ArmShiftType type =
+(ArmShiftType)(uint8_t)bits(machInst, 23, 22);
+if (type == ROR)
+return new Unknown64(machInst);
+uint8_t imm6 = bits(machInst, 15, 10);
+if (!bits(machInst, 31) && bits(imm6, 5))
+return new Unknown64(machInst);
+RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+RegIndex rdzr = makeZero(rd);
+RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
+switch (switch_val) {
+  case 0x0:
+return new AddXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x1:
+return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  case 0x2:
+return new SubXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x3:
+return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  default:
+GEM5_UNREACHABLE;
+}
+} else {
+if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) >  
0x4)

+   return new Unknown64(machInst);
+ArmExtendType type =
+(ArmExtendType)(uint8_t)bits(machInst, 15, 13);
+uint8_t imm3 = bits(machInst, 12, 10);
+RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+RegIndex rdsp = makeSP(rd);
+RegIndex rdzr = makeZero(rd);
+RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+RegIndex rnsp = makeSP(rn);
+RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
+
+switch (switch_val) {
+  case 0x0:
+return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3);
+  case 0x1:
+return new AddXERegCc(machInst, rdzr, rnsp, rm, type,  
imm3);

+  case 0x2:
+return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3);
+  case 0x3:
+return new SubXERegCc(machInst, rdzr, rnsp, rm, type,  
imm3);

+  default:
+GEM5_UNREACHABLE;
+}
+

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email

to review the following change.


Change subject: arch-arm: Define a AA64ZFR0 data type
..

arch-arm: Define a AA64ZFR0 data type

Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 13 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 214d418..b7a1207 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -203,6 +203,19 @@
 Bitfield<3, 0> el0;
 EndBitUnion(AA64PFR0)

+BitUnion64(AA64ZFR0)
+Bitfield<59, 56> f64mm;
+Bitfield<55, 52> f32mm;
+Bitfield<47, 44> i8mm;
+Bitfield<43, 40> sm4;
+Bitfield<35, 32> sha3;
+Bitfield<27, 24> b16b16;
+Bitfield<23, 20> bf16;
+Bitfield<19, 16> bitPerm;
+Bitfield<7, 4> aes;
+Bitfield<3, 0> sveVer;
+EndBitUnion(AA64ZFR0)
+
 BitUnion64(AA64SMFR0)
 Bitfield<63> fa64;
 Bitfield<59, 56> smEver;

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Gerrit-PatchSet: 1
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Gerrit-Reviewer: Richard Cooper 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email

to review the following change.


Change subject: arch-arm: Implement FEAT_RNG
..

arch-arm: Implement FEAT_RNG

Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
5 files changed, 62 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index e08108f..c3b3cf6 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -88,6 +88,8 @@
 "FEAT_FLAGM",
 # Armv8.5
 "FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -204,7 +206,11 @@


 class Armv85(Armv84):
-extensions = Armv84.extensions + ["FEAT_FLAGM2"]
+extensions = Armv84.extensions + [
+"FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
+]


 class Armv92(Armv85):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9c8e282..0212926 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -49,6 +49,7 @@
 #include "arch/arm/utility.hh"
 #include "arch/generic/decoder.hh"
 #include "base/cprintf.hh"
+#include "base/random.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/reg_class.hh"
@@ -596,6 +597,21 @@
   case MISCREG_HIFAR: // alias for secure IFAR
 return readMiscRegNoEffect(MISCREG_IFAR_S);

+  case MISCREG_RNDR:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+return random_mt.random();
+  case MISCREG_RNDRRS:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+// Note: we are not reseeding
+// The random number generator already has an hardcoded
+// seed for the sake of determinism. There is no point
+// in simulating non-determinism here
+return random_mt.random();
+
   // Generic Timer registers
   case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
   case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9e633c0..df1f6db 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1057,6 +1057,8 @@
 { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
 { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
 { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
+{ MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR },
+{ MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS },
 { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
 { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
 { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
@@ -1999,6 +2001,20 @@
 }
 }

+Fault
+faultRng(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) {
+return inst.generateTrap(EL3);
+} else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) {
+return inst.undefined();
+} else {
+return NoFault;
+}
+}
+
 }

 MiscRegIndex
@@ -5400,6 +5416,21 @@
 InitReg(MISCREG_MPAMSM_EL1)
 .allPrivileges().exceptUserMode();

+InitReg(MISCREG_RNDR)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3, faultRng)
+.unverifiable()
+.allPrivileges().writes(0);
+InitReg(MISCREG_RNDRRS)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3, faultRng)
+.unverifiable()
+.allPrivileges().writes(0);
+
 // Dummy registers
 InitReg(MISCREG_NOP)
   .allPrivileges();
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index c43cf74..429fcb5 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1091,6 +1091,10 @@
 MISCREG_TPIDR2_EL0,
 MISCREG_MPAMSM_EL1,

+// FEAT_RNG
+MISCREG_RNDR,
+MISCREG_RNDRRS,
+
 // NUM_PHYS_MISCREGS specifies the number of actual physical
 // registers, not considering the following pseudo-registers
 // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
@@ -2760,6 +2764,9 @@
 "tpidr2_el0",
 "mpamsm_el1",

+"rndr",
+"rndrrs",
+
 "num_phys_regs",

 // Dummy registers
diff --git a/src/arch/arm/regs/misc_types.hh  

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email

to review the following change.


Change subject: arch-arm: Implement FEAT_IDST
..

arch-arm: Implement FEAT_IDST

Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
2 files changed, 59 insertions(+), 17 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c3b3cf6..b826f0d 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,7 @@
 "FEAT_SEL2",
 "FEAT_TLBIOS",
 "FEAT_FLAGM",
+"FEAT_IDST",
 # Armv8.5
 "FEAT_FLAGM2",
 "FEAT_RNG",
@@ -170,6 +171,7 @@
 "FEAT_SEL2",
 "FEAT_TLBIOS",
 "FEAT_FLAGM",
+"FEAT_IDST",
 # Armv8.5
 "FEAT_FLAGM2",
 # Armv9.2
@@ -202,7 +204,12 @@


 class Armv84(Armv83):
-extensions = Armv83.extensions +  
["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"]

+extensions = Armv83.extensions + [
+"FEAT_SEL2",
+"FEAT_TLBIOS",
+"FEAT_FLAGM",
+"FEAT_IDST",
+]


 class Armv85(Armv84):
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 10b7d38..a151177 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2077,6 +2077,22 @@
 }
 }

+Fault
+faultIdst(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+if (HaveExt(tc, ArmExtension::FEAT_IDST)) {
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+if (EL2Enabled(tc) && hcr.tge) {
+return inst.generateTrap(EL2);
+} else {
+return inst.generateTrap(EL1);
+}
+} else {
+return inst.undefined();
+}
+}
+
 }

 MiscRegIndex
@@ -3828,6 +3844,7 @@
 // AArch64 registers (Op0=1,3);
 InitReg(MISCREG_MIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .mapsTo(MISCREG_MIDR);
 InitReg(MISCREG_MPIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0)
@@ -3923,34 +3940,40 @@
   return pfr0_el1;
   }())
   .unserialize(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64PFR1_EL1)
   .reset(release->has(ArmExtension::FEAT_SME) ?
   0x1 << 24 : 0)
   .unserialize(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64DFR0_EL1)
   .reset([p](){
   AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
   dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
   return dfr0_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64DFR1_EL1)
   .reset(p.id_aa64dfr1_el1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64AFR0_EL1)
   .reset(p.id_aa64afr0_el1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64AFR1_EL1)
   .reset(p.id_aa64afr1_el1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64ISAR0_EL1)
   .reset([p,release=release](){
   AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
@@ -3974,8 +3997,9 @@
   0x1 : 0x0;
   return isar0_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64ISAR1_EL1)
   .reset([p,release=release](){
   AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
@@ -3985,8 +4009,9 @@
   isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 :  
0x0;

   return isar1_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64MMFR0_EL1)
   .reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
   AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
@@ -3994,8 +4019,9 @@
   mmfr0_el1.parange = 

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide

[Giacomo Travaglini (Gerrit) via gem5-dev]

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email

to review the following change.


Change subject: arch-arm: Extend SCR to be 64-bit wide
..

arch-arm: Extend SCR to be 64-bit wide

Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index c139f1a..71fdd60 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -345,7 +345,7 @@
 Bitfield<0>  cp0;
 EndBitUnion(NSACR)

-BitUnion32(SCR)
+BitUnion64(SCR)
 Bitfield<21> fien;
 Bitfield<20> nmea;
 Bitfield<19> ease;

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Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Gerrit-Change-Number: 70720
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix printing of VecElemClass registers

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email )



Change subject: arch-arm: Fix printing of VecElemClass registers
..

arch-arm: Fix printing of VecElemClass registers

At the moment it is not possible to trace the value of VecElemClass
registers. If a AArch32 SIMD binary is run with tracing on,
simulation will fail the following assertion [1].

std::string
valString(const void *val, size_t size) const override
{
assert(size == sizeof(ValueType));

The problem is that Arm VecElems are stored in RegVal (uint64_t),
but the VecElem data type (ValueType above) per se is a uint32_t.

So valString is getting called with size = 8 (coming from RegVal)
but ValueType has size = 4. We fix this problem by using RegVal as
a VecElemRegClassOps template parameter to make them match.
This is not changing anything from a functionality perspective.
The result will be that we will be able to print VecElems as 64bit
values.

This solution is the most simple one but a bit dirty. I believe
in the long term we should make the VecElemClass use the void* interface
rather than the RegVal one. In this way we will be able to correctly
print the VecElem size as 32bit value.

[1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/cpu/reg_class.hh#L362

Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/regs/vec.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
index 00ab87f..19f37c9 100644
--- a/src/arch/arm/regs/vec.hh
+++ b/src/arch/arm/regs/vec.hh
@@ -93,7 +93,7 @@
 const int PREDREG_FFR = 16;
 const int PREDREG_UREG0 = 17;

-static inline VecElemRegClassOps
+static inline VecElemRegClassOps
 vecRegElemClassOps(NumVecElemPerVecReg);
 static inline TypedRegClassOps vecRegClassOps;
 static inline TypedRegClassOps  
vecPredRegClassOps;


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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_TLBIOS

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Implement FEAT_TLBIOS
..

arch-arm: Implement FEAT_TLBIOS

This feature is mandatory in Armv8.4
We are currently not distinguishing Inner and Outer domains.
We therefore implement TLBIOS instructions as TLBIIS

Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70567
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/insts/misc64.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
4 files changed, 151 insertions(+), 1 deletion(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 7367d80..9e2da8e 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -84,6 +84,7 @@
 "FEAT_PAuth",
 # Armv8.4
 "FEAT_SEL2",
+"FEAT_TLBIOS",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -162,6 +163,7 @@
 "FEAT_PAuth",
 # Armv8.4
 "FEAT_SEL2",
+"FEAT_TLBIOS",
 # Armv9.2
 "FEAT_SME",
 ]
@@ -192,7 +194,7 @@


 class Armv84(Armv83):
-extensions = Armv83.extensions + ["FEAT_SEL2"]
+extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"]


 class Armv92(Armv84):
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 40a6ca4..c7423d9 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -241,6 +241,10 @@
 }
   // AArch64 TLB Invalidate All, EL3, Inner Shareable
   case MISCREG_TLBI_ALLE3IS:
+  // AArch64 TLB Invalidate All, EL3, Outer Shareable
+  // We are currently not distinguishing Inner and Outer domains.
+  // We therefore implement TLBIOS instructions as TLBIIS
+  case MISCREG_TLBI_ALLE3OS:
 {
 TLBIALLEL tlbiOp(EL3, true);
 tlbiOp.broadcast(tc);
@@ -258,6 +262,10 @@
 }
   // AArch64 TLB Invalidate All, EL2, Inner Shareable
   case MISCREG_TLBI_ALLE2IS:
+  // AArch64 TLB Invalidate All, EL2, Outer Shareable
+  // We are currently not distinguishing Inner and Outer domains.
+  // We therefore implement TLBIOS instructions as TLBIIS
+  case MISCREG_TLBI_ALLE2OS:
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);

@@ -278,6 +286,10 @@
 }
   // AArch64 TLB Invalidate All, EL1, Inner Shareable
   case MISCREG_TLBI_ALLE1IS:
+  // AArch64 TLB Invalidate All, EL1, Outer Shareable
+  // We are currently not distinguishing Inner and Outer domains.
+  // We therefore implement TLBIOS instructions as TLBIIS
+  case MISCREG_TLBI_ALLE1OS:
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);

@@ -313,6 +325,9 @@
 return;
 }
   case MISCREG_TLBI_VMALLS12E1IS:
+  // We are currently not distinguishing Inner and Outer domains.
+  // We therefore implement TLBIOS instructions as TLBIIS
+  case MISCREG_TLBI_VMALLS12E1OS:
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);

@@ -322,6 +337,9 @@
 return;
 }
   case MISCREG_TLBI_VMALLE1IS:
+  // We are currently not distinguishing Inner and Outer domains.
+  // We therefore implement TLBIOS instructions as TLBIIS
+  case MISCREG_TLBI_VMALLE1OS:
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);

@@ -360,6 +378,10 @@
 }
   // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
   case MISCREG_TLBI_VAE3IS_Xt:
+  // AArch64 TLB Invalidate by VA, EL3, Outer Shareable
+  // We are currently not distinguishing Inner and Outer domains.
+  // We therefore implement TLBIOS instructions as TLBIIS
+  case MISCREG_TLBI_VAE3OS_Xt:
 {
 TLBIMVAA tlbiOp(EL3, true,
 static_cast(bits(value, 43, 0)) << 12,
@@ -370,6 +392,10 @@
 }
   // AArch64 TLB Invalidate by VA, Last Level, EL3, Inner Shareable
   case MISCREG_TLBI_VALE3IS_Xt:
+  // AArch64 TLB Invalidate by VA, Last Level, EL3, Outer Shareable
+  // We are currently not distinguishing Inner and Outer domains.
+  // We therefore implement TLBIOS instructions as TLBIIS
+  case MISCREG_TLBI_VALE3OS_Xt:
 {
 TLBIMVAA tlbiOp(EL3, true,
 static_cast(bits(value, 43, 0)) << 12,
@@ -430,6 +456,10 @@
 }
   // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
   case 

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add UNSERIALIZE flag to address cpt compatibility

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-arm: Add UNSERIALIZE flag to address cpt  
compatibility

..

arch-arm: Add UNSERIALIZE flag to address cpt compatibility

This patch is adding the MISCREG_UNSERIALIZE flag to expose
the user to the following checkpoint compatibility problem:

What happens when a checkpoint is restored with a different
architectural configuration?

The current behaviour is to silently restore the checkpoint
and to populate the ISA registers accordingly. However some of
these restored values will be used and some of them will
be actually discarded.

For example the value of the MISCREG_ID_AA64ISAR0_EL1 register
(initially configured at construction time [1]) will be overwritten by
the checkpointed value in ISA::unserialize (checkpointed params win over
current params). On the other hand we "discard" the checkpointed value
for registers handled in the ISA::readMiscReg method (not accessing the
storage) like MISCREG_ID_AA64PFR0_EL1 [2] (current params win over
checkpointed params).

In other words some registers will be unserialized while some others
will discard the checkpointed value in favour of the current
configuration setup. This categorization is currently implicit and it
ultimately depends on whether or not a register read access its storage
(see MISCREG_ID_AA64PFR0_EL1 above).

With this patch we formalize this distinction. We allow the developer to
be explict on which register should not be unserialized and should
instead use the new simulation parameters.

If there is a mismatch between the reset value of such register and
the checkpointed one, we warn the user and we undo the unserialization
for such register.

[1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L437
[2]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L1019

Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70557
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.hh
2 files changed, 20 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ffd9cfc..f55235d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1879,6 +1879,18 @@
 {
 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
 UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
+
+for (auto idx = 0; idx < NUM_MISCREGS; idx++) {
+if (!lookUpMiscReg[idx].info[MISCREG_UNSERIALIZE] &&
+miscRegs[idx] != lookUpMiscReg[idx].reset()) {
+warn("Checkpoint value for register %s does not match "
+ "current configuration (checkpointed: %#x, current: %#x)",
+ miscRegName[idx], miscRegs[idx],
+ lookUpMiscReg[idx].reset());
+miscRegs[idx] = lookUpMiscReg[idx].reset();
+}
+}
+
 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 updateRegMap(tmp_cpsr);
 }
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 265a697..3a32623 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1125,6 +1125,7 @@
 MISCREG_IMPLEMENTED,
 MISCREG_UNVERIFIABLE,   // Does the value change on every read  
(e.g. a

 // arch generic counter)
+MISCREG_UNSERIALIZE,// Should the checkpointed value be  
restored?

 MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
 // tells whether the instruction should  
raise a

 // warning or fail
@@ -1277,6 +1278,12 @@
 return *this;
 }
 chain
+unserialize(bool v = true) const
+{
+entry.info[MISCREG_UNSERIALIZE] = v;
+return *this;
+}
+chain
 warnNotFail(bool v = true) const
 {
 entry.info[MISCREG_WARN_NOT_FAIL] = v;
@@ -1595,7 +1602,7 @@
   : entry(e)
 {
 // force unimplemented registers to be thusly declared
-implemented(1);
+implemented(1).unserialize(1);
 }
 };


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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement RES0/RES1 with miscreg specifiers

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Implement RES0/RES1 with miscreg specifiers
..

arch-arm: Implement RES0/RES1 with miscreg specifiers

Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70563
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 29 insertions(+), 73 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index bef2db5..ab6e3f7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -421,11 +421,6 @@
 idx = redirectRegVHE(idx);

 switch (unflattenMiscReg(idx)) {
-  case MISCREG_HCR:
-  case MISCREG_HCR2:
-if (!release->has(ArmExtension::VIRTUALIZATION))
-return 0;
-break;
   case MISCREG_CPACR:
 {
 const uint32_t ones = (uint32_t)(-1);
@@ -456,10 +451,6 @@
   case MISCREG_MPIDR:
   case MISCREG_MPIDR_EL1:
 return readMPIDR(system, tc);
-  case MISCREG_VMPIDR:
-  case MISCREG_VMPIDR_EL2:
-// top bit defined as RES1
-return readMiscRegNoEffect(idx) | 0x8000;
   case MISCREG_ID_AFR0: // not implemented, so alias MIDR
   case MISCREG_REVIDR:  // not implemented, so alias MIDR
   case MISCREG_MIDR:
@@ -568,10 +559,6 @@
 {
 return miscRegs[MISCREG_CPSR] & 0x80;
 }
-  case MISCREG_SVCR:
-{
-return miscRegs[MISCREG_SVCR];
-}
   case MISCREG_L2CTLR:
 {
 // mostly unimplemented, just set NumCPUs field from sim and  
return

@@ -594,20 +581,17 @@
 }
   case MISCREG_HCPTR:
 {
-RegVal val = readMiscRegNoEffect(idx);
-// The trap bit associated with CP14 is defined as RAZ
-val &= ~(1 << 14);
-// If a CP bit in NSACR is 0 then the corresponding bit in
-// HCPTR is RAO/WI
+HCPTR val = readMiscRegNoEffect(idx);
 bool secure_lookup = release->has(ArmExtension::SECURITY) &&
 isSecure(tc);
 if (!secure_lookup) {
-RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
-val |= (mask ^ 0x7FFF) & 0xBFFF;
+NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
+if (!nsacr.cp10) {
+val.tcp10 = 1;
+val.tcp11 = 1;
+}
 }
-// Set the bits for unimplemented coprocessors to RAO/WI
-val |= 0x33FF;
-return (val);
+return val;
 }
   case MISCREG_HDFAR: // alias for secure DFAR
 return readMiscRegNoEffect(MISCREG_DFAR_S);
@@ -934,16 +918,10 @@
  (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
 }
 break;
-  case MISCREG_HCR2:
-if (!release->has(ArmExtension::VIRTUALIZATION))
-return;
-break;
   case MISCREG_HCR:
 {
 const HDCR mdcr  =  
tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);

 selfDebug->setenableTDETGE((HCR)val, mdcr);
-if (!release->has(ArmExtension::VIRTUALIZATION))
-return;
 }
 break;

@@ -1016,31 +994,6 @@
   case MISCREG_DBGWCR0_EL1 ... MISCREG_DBGWCR15_EL1:
 selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0_EL1, val);
 break;
-  case MISCREG_IFSR:
-{
-// ARM ARM (ARM DDI 0406C.b) B4.1.96
-const uint32_t ifsrMask =
-mask(31, 13) | mask(11, 11) | mask(8, 6);
-newVal = newVal & ~ifsrMask;
-}
-break;
-  case MISCREG_DFSR:
-{
-// ARM ARM (ARM DDI 0406C.b) B4.1.52
-const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
-newVal = newVal & ~dfsrMask;
-}
-break;
-  case MISCREG_AMAIR0:
-  case MISCREG_AMAIR1:
-{
-// ARM ARM (ARM DDI 0406C.b) B4.1.5
-// Valid only with LPAE
-if (!release->has(ArmExtension::LPAE))
-return;
-DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
-}
-break;
   case MISCREG_SCR:
 getMMUPtr(tc)->invalidateMiscReg();
 

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug  
arch

..

arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70561
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/misc.cc
1 file changed, 1 insertion(+), 4 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6c5a9dd..6f918b2 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2273,10 +2273,7 @@

 // AArch32 CP14 registers
 InitReg(MISCREG_DBGDIDR)
-  /* For now just implement the version number.
-   * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
-   */
-  .reset(0x5 << 16)
+  .reset(0x6 << 16) // Armv8 Debug architecture
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
 InitReg(MISCREG_DBGDSCRint)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Gerrit-Change-Number: 70561
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement RAZ/WI with raz specifier

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Implement RAZ/WI with raz specifier
..

arch-arm: Implement RAZ/WI with raz specifier

Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70560
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 5 insertions(+), 6 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 14349b1..7df8978 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -470,12 +470,6 @@
 return readMiscRegNoEffect(idx);
 }
 break;
-  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_AIDR:  // AUX ID set to 0
-  case MISCREG_TCMTR: // No TCM's
-return 0;

   case MISCREG_CLIDR:
 warn_once("The clidr register always reports 0 caches.\n");
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 960c2be..6c5a9dd 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2505,12 +2505,15 @@
   .unimplemented()
   .allPrivileges();
 InitReg(MISCREG_JIDR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();
 InitReg(MISCREG_TEEHBR)
   .allPrivileges();
 InitReg(MISCREG_JOSCR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();
 InitReg(MISCREG_JMCR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();

 // AArch32 CP15 registers
@@ -2548,6 +2551,7 @@
   .unserialize(0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TCMTR)
+  .raz() // No TCM's
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TLBTR)
   .reset(1) // Separate Instruction and Data TLBs
@@ -2646,6 +2650,7 @@
 InitReg(MISCREG_CLIDR)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_AIDR)
+  .raz() // AUX ID set to 0
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_CSSELR)
   .banked();

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Gerrit-Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Gerrit-Change-Number: 70560
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
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Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Provide default mask for raz/rao helpers

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Provide default mask for raz/rao helpers
..

arch-arm: Provide default mask for raz/rao helpers

Rather than forcing raz registers to write something like:

.raz(uint64_t(-1))

we provide a shorter version where if
no bitmask is specified we assume the entire register is
raz/rao. This won't be probably used by rao but I
am striving for symmetry and providing a default won't
probably hurt

Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70559
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/misc.hh
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 3a32623..abbd1c6 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1249,13 +1249,13 @@
 return *this;
 }
 chain
-raz(uint64_t mask) const
+raz(uint64_t mask = (uint64_t)-1) const
 {
 entry._raz  = mask;
 return *this;
 }
 chain
-rao(uint64_t mask) const
+rao(uint64_t mask = (uint64_t)-1) const
 {
 entry._rao  = mask;
 return *this;

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Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Simplify FPSCR writes

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Simplify FPSCR writes
..

arch-arm: Simplify FPSCR writes

The old logic was setting up a mask which was covering pretty much
the entire register, except for the FPSCR[14:13] and FPSCR[6:5]
register fields. Those RES0 fields were treated as WI.
We simplify this by explicitly marking them as RES0 at construction
time

Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 2 insertions(+), 32 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 83df61f..9c8e282 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -815,38 +815,7 @@
 return;

   case MISCREG_FPSCR:
-{
-const uint32_t ones = (uint32_t)(-1);
-FPSCR fpscrMask = 0;
-fpscrMask.ioc = ones;
-fpscrMask.dzc = ones;
-fpscrMask.ofc = ones;
-fpscrMask.ufc = ones;
-fpscrMask.ixc = ones;
-fpscrMask.idc = ones;
-fpscrMask.ioe = ones;
-fpscrMask.dze = ones;
-fpscrMask.ofe = ones;
-fpscrMask.ufe = ones;
-fpscrMask.ixe = ones;
-fpscrMask.ide = ones;
-fpscrMask.len = ones;
-fpscrMask.fz16 = ones;
-fpscrMask.stride = ones;
-fpscrMask.rMode = ones;
-fpscrMask.fz = ones;
-fpscrMask.dn = ones;
-fpscrMask.ahp = ones;
-fpscrMask.qc = ones;
-fpscrMask.v = ones;
-fpscrMask.c = ones;
-fpscrMask.z = ones;
-fpscrMask.n = ones;
-newVal = (newVal & (uint32_t)fpscrMask) |
- (readMiscRegNoEffect(MISCREG_FPSCR) &
-  ~(uint32_t)fpscrMask);
-tc->getDecoderPtr()->as().setContext(newVal);
-}
+tc->getDecoderPtr()->as().setContext(newVal);
 break;
   case MISCREG_FPSR:
 {
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9203810..2d76143 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2199,6 +2199,7 @@
   .reset(p.fpsid)
   .allPrivileges();
 InitReg(MISCREG_FPSCR)
+  .res0(mask(14, 13) | mask(6, 5))
   .allPrivileges();
 InitReg(MISCREG_MVFR1)
   .reset([] () {

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Gerrit-Change-Number: 70565
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCTLR to be 64-bit wide

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Extend SCTLR to be 64-bit wide
..

arch-arm: Extend SCTLR to be 64-bit wide

In AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide

Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70566
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index e6f7e40..c139f1a 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -371,7 +371,7 @@
 Bitfield<0> ns;
 EndBitUnion(SCR)

-BitUnion32(SCTLR)
+BitUnion64(SCTLR)
 Bitfield<31>   enia;// ARMv8.3 PAuth
 Bitfield<30>   enib;// ARMv8.3 PAuth
 Bitfield<30>   te;  // Thumb Exception Enable (AArch32 only)

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Gerrit-Change-Number: 70566
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Move RO values from ISA::read to the reset field
..

arch-arm: Move RO values from ISA::read to the reset field

This is simplyfying the ISA::readMiscReg, and it is stopping
us from recomputing values that won't change throughout the
simulation

Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70558
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 49 insertions(+), 66 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f55235d..14349b1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -486,35 +486,6 @@
 warn_once("The ccsidr register isn't implemented and "
 "always reads as 0.\n");
 break;
-  case MISCREG_CTR: // AArch32, ARMv7, top bit set
-  case MISCREG_CTR_EL0: // AArch64
-{
-//all caches have the same line size in gem5
-//4 byte words in ARM
-unsigned lineSizeWords =
-tc->getSystemPtr()->cacheLineSize() / 4;
-unsigned log2LineSizeWords = 0;
-
-while (lineSizeWords >>= 1) {
-++log2LineSizeWords;
-}
-
-CTR ctr = 0;
-//log2 of minimun i-cache line size (words)
-ctr.iCacheLineSize = log2LineSizeWords;
-//b11 - gem5 uses pipt
-ctr.l1IndexPolicy = 0x3;
-//log2 of minimum d-cache line size (words)
-ctr.dCacheLineSize = log2LineSizeWords;
-//log2 of max reservation size (words)
-ctr.erg = log2LineSizeWords;
-//log2 of max writeback size (words)
-ctr.cwg = log2LineSizeWords;
-//b100 - gem5 format is ARMv7
-ctr.format = 0x4;
-
-return ctr;
-}
   case MISCREG_ACTLR:
 warn("Not doing anything for miscreg ACTLR\n");
 break;
@@ -615,11 +586,6 @@
 l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
 return l2ctlr;
 }
-  case MISCREG_DBGDIDR:
-/* For now just implement the version number.
- * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
- */
-return 0x5 << 16;
   case MISCREG_DBGDSCRint:
 return readMiscRegNoEffect(MISCREG_DBGDSCRint);
   case MISCREG_ISR:
@@ -632,8 +598,6 @@
 readMiscRegNoEffect(MISCREG_CPSR),
 readMiscRegNoEffect(MISCREG_SCR_EL3));
 }
-  case MISCREG_DCZID_EL0:
-return 0x04;  // DC ZVA clear 64-byte chunks
   case MISCREG_HCPTR:
 {
 RegVal val = readMiscRegNoEffect(idx);
@@ -656,36 +620,6 @@
   case MISCREG_HIFAR: // alias for secure IFAR
 return readMiscRegNoEffect(MISCREG_IFAR_S);

-  case MISCREG_ID_PFR0:
-// !ThumbEE | !Jazelle | Thumb | ARM
-return 0x0031;
-  case MISCREG_ID_PFR1:
-{   // Timer | Virti | !M Profile | TrustZone | ARMv4
-bool have_timer = (system->getGenericTimer() != nullptr);
-return 0x0001 |
-(release->has(ArmExtension::SECURITY) ?
-0x0010 : 0x0) |
-(release->has(ArmExtension::VIRTUALIZATION) ?
-0x1000 : 0x0) |
-(have_timer ? 0x0001 : 0x0);
-}
-  case MISCREG_ID_AA64PFR0_EL1:
-return 0x0002 | // AArch{64,32} supported at EL0
-   0x0020 | // EL1
-   (release->has(ArmExtension::VIRTUALIZATION) ?
-0x0200 : 0) | // EL2
-   (release->has(ArmExtension::SECURITY) ?
-0x2000 : 0) | // EL3
-   (release->has(ArmExtension::FEAT_SVE) ?
-0x0001 : 0) | // SVE
-   (release->has(ArmExtension::FEAT_SEL2) ?
-0x0010 : 0) | // SecEL2
-   (gicv3CpuInterface ? 0x0100 : 0);
-  case MISCREG_ID_AA64PFR1_EL1:
-return 0x0 |
-   (release->has(ArmExtension::FEAT_SME) ?
-0x1 << 24 : 0); // SME
-
   // Generic Timer registers
   case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
   case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/regs/misc.cc 

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Group self hosted debug writes in ISA switch

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70562?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Group self hosted debug writes in ISA switch
..

arch-arm: Group self hosted debug writes in ISA switch

Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70562
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/isa.cc
1 file changed, 8 insertions(+), 188 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 7df8978..bef2db5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -962,101 +962,11 @@
 tc->setMiscReg(MISCREG_DBGOSLSR, r);
 }
 break;
-  case MISCREG_DBGBCR0:
-selfDebug->updateDBGBCR(0, val);
+  case MISCREG_DBGBCR0 ... MISCREG_DBGBCR15:
+selfDebug->updateDBGBCR(idx - MISCREG_DBGBCR0, val);
 break;
-  case MISCREG_DBGBCR1:
-selfDebug->updateDBGBCR(1, val);
-break;
-  case MISCREG_DBGBCR2:
-selfDebug->updateDBGBCR(2, val);
-break;
-  case MISCREG_DBGBCR3:
-selfDebug->updateDBGBCR(3, val);
-break;
-  case MISCREG_DBGBCR4:
-selfDebug->updateDBGBCR(4, val);
-break;
-  case MISCREG_DBGBCR5:
-selfDebug->updateDBGBCR(5, val);
-break;
-  case MISCREG_DBGBCR6:
-selfDebug->updateDBGBCR(6, val);
-break;
-  case MISCREG_DBGBCR7:
-selfDebug->updateDBGBCR(7, val);
-break;
-  case MISCREG_DBGBCR8:
-selfDebug->updateDBGBCR(8, val);
-break;
-  case MISCREG_DBGBCR9:
-selfDebug->updateDBGBCR(9, val);
-break;
-  case MISCREG_DBGBCR10:
-selfDebug->updateDBGBCR(10, val);
-break;
-  case MISCREG_DBGBCR11:
-selfDebug->updateDBGBCR(11, val);
-break;
-  case MISCREG_DBGBCR12:
-selfDebug->updateDBGBCR(12, val);
-break;
-  case MISCREG_DBGBCR13:
-selfDebug->updateDBGBCR(13, val);
-break;
-  case MISCREG_DBGBCR14:
-selfDebug->updateDBGBCR(14, val);
-break;
-  case MISCREG_DBGBCR15:
-selfDebug->updateDBGBCR(15, val);
-break;
-  case MISCREG_DBGWCR0:
-selfDebug->updateDBGWCR(0, val);
-break;
-  case MISCREG_DBGWCR1:
-selfDebug->updateDBGWCR(1, val);
-break;
-  case MISCREG_DBGWCR2:
-selfDebug->updateDBGWCR(2, val);
-break;
-  case MISCREG_DBGWCR3:
-selfDebug->updateDBGWCR(3, val);
-break;
-  case MISCREG_DBGWCR4:
-selfDebug->updateDBGWCR(4, val);
-break;
-  case MISCREG_DBGWCR5:
-selfDebug->updateDBGWCR(5, val);
-break;
-  case MISCREG_DBGWCR6:
-selfDebug->updateDBGWCR(6, val);
-break;
-  case MISCREG_DBGWCR7:
-selfDebug->updateDBGWCR(7, val);
-break;
-  case MISCREG_DBGWCR8:
-selfDebug->updateDBGWCR(8, val);
-break;
-  case MISCREG_DBGWCR9:
-selfDebug->updateDBGWCR(9, val);
-break;
-  case MISCREG_DBGWCR10:
-selfDebug->updateDBGWCR(10, val);
-break;
-  case MISCREG_DBGWCR11:
-selfDebug->updateDBGWCR(11, val);
-break;
-  case MISCREG_DBGWCR12:
-selfDebug->updateDBGWCR(12, val);
-break;
-  case MISCREG_DBGWCR13:
-selfDebug->updateDBGWCR(13, val);
-break;
-  case MISCREG_DBGWCR14:
-selfDebug->updateDBGWCR(14, val);
-break;
-  case MISCREG_DBGWCR15:
-selfDebug->updateDBGWCR(15, val);
+  case MISCREG_DBGWCR0 ... MISCREG_DBGWCR15:
+selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0, val);
 break;

   case MISCREG_MDCR_EL2:
@@ -1100,101 +1010,11 @@
 }
 break;

-  case MISCREG_DBGBCR0_EL1:
-selfDebug->updateDBGBCR(0, val);
+  case MISCREG_DBGBCR0_EL1 ... MISCREG_DBGBCR15_EL1:
+selfDebug->updateDBGBCR(idx - MISCREG_DBGBCR0_EL1, val);
 break;
-  case MISCREG_DBGBCR1_EL1:
-selfDebug->updateDBGBCR(1, val);
-

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Remove unnecessary case in ISA::readMiscReg

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Remove unnecessary case in ISA::readMiscReg
..

arch-arm: Remove unnecessary case in ISA::readMiscReg

Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70564
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ab6e3f7..83df61f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -567,8 +567,6 @@
 l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
 return l2ctlr;
 }
-  case MISCREG_DBGDSCRint:
-return readMiscRegNoEffect(MISCREG_DBGDSCRint);
   case MISCREG_ISR:
   case MISCREG_ISR_EL1:
 {

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Gerrit-Change-Number: 70564
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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