[gem5-dev] [S] Change in gem5/gem5[develop]: base: singleStep can't be interupted by trap from other thread.
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63533?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: base: singleStep can't be interupted by trap from other
thread.
..
base: singleStep can't be interupted by trap from other thread.
Change-Id: I0c46e3ea623b304b7ae8f8867d90c5d0008e8b3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63533
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/base/remote_gdb.cc
1 file changed, 19 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 2c74aa0..da3f113 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -555,6 +555,12 @@
return;
if (tc->contextId() != id) {
+
+//prevent thread switch when single stepping
+if (singleStepEvent.scheduled()){
+return;
+}
+DPRINTF(GDBMisc, "Finishing thread switch");
if (!selectThreadContext(id))
return;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0c46e3ea623b304b7ae8f8867d90c5d0008e8b3f
Gerrit-Change-Number: 63533
Gerrit-PatchSet: 9
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: adding a scheduleTrapEvent
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63532?usp=email )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: base: adding a scheduleTrapEvent
..
base: adding a scheduleTrapEvent
This function centralize setting up a new trapEvent making sure that
the contextId match with the ThreadContext use for the Event.
Change-Id: I2a5f77da049d140b9ceffd42011fd8a1da59092e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63532
Reviewed-by: Bobby Bruce
Tested-by: kokoro
Maintainer: Bobby Bruce
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 41 insertions(+), 10 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index e02ada0..2c74aa0 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -607,9 +607,7 @@
}
if (revent & POLLIN) {
-trapEvent.type(SIGILL);
-trapEvent.id(tc->contextId());
-scheduleInstCommitEvent(, 0);
+scheduleTrapEvent(tc->contextId(),SIGILL,0,"");
} else if (revent & POLLNVAL) {
descheduleInstCommitEvent();
scheduleInstCommitEvent(, 0);
@@ -964,10 +962,23 @@
BaseRemoteGDB::sendOPacket(const std::string message){
send("O" + string2hexS(message));
}
+
void
-BaseRemoteGDB::scheduleInstCommitEvent(Event *ev, int delta)
+BaseRemoteGDB::scheduleTrapEvent(ContextID id,int type,int delta,
+std::string stopReason){
+ThreadContext* _tc = threads[id];
+panic_if(_tc == nullptr, "Unknown context id :%i",id);
+trapEvent.id(id);
+trapEvent.type(type);
+trapEvent.stopReason(stopReason);
+if (!trapEvent.scheduled())
+scheduleInstCommitEvent(,delta,_tc);
+}
+
+void
+BaseRemoteGDB::scheduleInstCommitEvent(Event *ev, int delta,ThreadContext*
_tc)
{
-if (delta == 0 && tc->status() != ThreadContext::Active) {
+if (delta == 0 && _tc->status() != ThreadContext::Active) {
// If delta is zero, we're just trying to wait for an instruction
// boundary. If the CPU is not active, assume we're already at a
// boundary without waiting for the CPU to eventually wake up.
@@ -975,7 +986,7 @@
} else {
// Here "ticks" aren't simulator ticks which measure time, they're
// instructions committed by the CPU.
-tc->scheduleInstCountEvent(ev, tc->getCurrentInstCount() + delta);
+_tc->scheduleInstCountEvent(ev, _tc->getCurrentInstCount() +
delta);
}
}
@@ -1154,8 +1165,7 @@
throw CmdError("E04");
// Line up on an instruction boundary in the new thread.
threadSwitching = true;
-trapEvent.id(tid);
-scheduleInstCommitEvent(, 0);
+scheduleTrapEvent(tid,0,0,"");
return false;
}
} else {
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 280f12c..d4a8a5b 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -173,7 +173,9 @@
void trap(ContextID id, int signum,const std::string& stopReason="");
bool sendMessage(std::string message);
-
+//schedule a trap event with these properties
+void scheduleTrapEvent(ContextID id,int type, int delta,
+ std::string stopReason);
/** @} */ // end of api_remote_gdb
template
@@ -313,7 +315,10 @@
void setSingleStep();
/// Schedule an event which will be triggered "delta" instructions
later.
-void scheduleInstCommitEvent(Event *ev, int delta);
+void scheduleInstCommitEvent(Event *ev, int delta,ThreadContext* _tc);
+void scheduleInstCommitEvent(Event *ev, int delta){
+ scheduleInstCommitEvent(ev, delta,tc);
+};
/// Deschedule an instruction count based event.
void descheduleInstCommitEvent(Event *ev);
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I2a5f77da049d140b9ceffd42011fd8a1da59092e
Gerrit-Change-Number: 63532
Gerrit-PatchSet: 10
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: base, sim: Adding support for message to GDB from python
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63531?usp=email )
(
9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: base, sim: Adding support for message to GDB from python
..
base, sim: Adding support for message to GDB from python
Adding a small python function that allows to display
messages directly in GDB from the python interpreter.
This function is inside the Workload SimObject
(The stub is not a SimObject).
ex:
system.workload.sendToGdb("message to display")
Change-Id: I46ddae079b10d298743e023f95bf15608f50e358
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63531
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/sim/Workload.py
M src/sim/workload.cc
M src/sim/workload.hh
5 files changed, 49 insertions(+), 1 deletion(-)
Approvals:
kokoro: Regressions pass
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 7aafa3d..e02ada0 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -575,6 +575,16 @@
processCommands(signum);
}
+bool
+BaseRemoteGDB::sendMessage(std::string message)
+{
+if (!attached)
+return false;
+DPRINTF(GDBMisc, "passing message %s\n", message);
+sendOPacket(message);
+return true;
+}
+
void
BaseRemoteGDB::incomingConnection(int revent)
{
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 671ee51..280f12c 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -172,6 +172,7 @@
bool selectThreadContext(ContextID id);
void trap(ContextID id, int signum,const std::string& stopReason="");
+bool sendMessage(std::string message);
/** @} */ // end of api_remote_gdb
diff --git a/src/sim/Workload.py b/src/sim/Workload.py
index 3fd4f81..b46c32f 100644
--- a/src/sim/Workload.py
+++ b/src/sim/Workload.py
@@ -24,7 +24,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
-from m5.SimObject import SimObject
+from m5.SimObject import SimObject, cxxMethod
from m5.objects.SimpleMemory import *
@@ -37,6 +37,14 @@
wait_for_remote_gdb = Param.Bool(False, "Wait for a remote GDB
connection")
+@cxxMethod
+def sendToGdb(self, message):
+"""send a message to the GDB client
+Args:
+message (str): message to send
+"""
+pass
+
class StubWorkload(Workload):
type = "StubWorkload"
diff --git a/src/sim/workload.cc b/src/sim/workload.cc
index 1f6e072..ca51bbd 100644
--- a/src/sim/workload.cc
+++ b/src/sim/workload.cc
@@ -80,6 +80,14 @@
}
return false;
};
+bool
+Workload::sendToGdb(std::string msg){
+ if (gdb)
+return gdb->sendMessage(msg);
+else
+return false;
+ }
+
void
Workload::startup()
diff --git a/src/sim/workload.hh b/src/sim/workload.hh
index 9b3ef04..f9bb8db 100644
--- a/src/sim/workload.hh
+++ b/src/sim/workload.hh
@@ -92,6 +92,7 @@
// Once trapping into GDB is no longer a special case routed through
the
// system object, this helper can be removed.
bool trapToGdb(int signal, ContextID ctx_id);
+bool sendToGdb(std::string msg);
virtual void registerThreadContext(ThreadContext *tc);
virtual void replaceThreadContext(ThreadContext *tc);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I46ddae079b10d298743e023f95bf15608f50e358
Gerrit-Change-Number: 63531
Gerrit-PatchSet: 11
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: base: adding queryAttached and querySymbol to GDB
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63530?usp=email )
(
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: base: adding queryAttached and querySymbol to GDB
..
base: adding queryAttached and querySymbol to GDB
In some cases/version these queries might be needed
to make the remote GDB connect correctly to the stub.
Change-Id: I98cdc9b4a952b4dc64f9357e6148af6e3351ef92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63530
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 39 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 4835f00..7aafa3d 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -1299,8 +1299,10 @@
std::map
BaseRemoteGDB::queryMap = {
{ "C", { ::queryC } },
+{ "Attached", { ::queryAttached} },
{ "Supported", { ::querySupported, ";" } },
{ "Xfer", { ::queryXfer } },
+{ "Symbol", { ::querySymbol ,":" } },
{ "fThreadInfo", { ::queryFThreadInfo } },
{ "sThreadInfo", { ::querySThreadInfo } },
};
@@ -1364,6 +1366,25 @@
encodeXferResponse(content, encoded, offset, length);
send(encoded);
}
+void
+BaseRemoteGDB::querySymbol(QuerySetCommand::Context )
+{
+//The target does not need to look up any (more) symbols.
+send("OK");
+}
+
+void
+BaseRemoteGDB::queryAttached(QuerySetCommand::Context )
+{
+std::string pid="";
+if (!ctx.args.empty() && !ctx.args[0].empty()){
+ pid=ctx.args[0];
+}
+DPRINTF(GDBMisc, "QAttached : pid=%s\n",pid);
+//The remote server is attached to an existing process.
+send("1");
+}
+
void
BaseRemoteGDB::queryFThreadInfo(QuerySetCommand::Context )
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index d51268a..671ee51 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -426,6 +426,8 @@
void queryC(QuerySetCommand::Context );
void querySupported(QuerySetCommand::Context );
void queryXfer(QuerySetCommand::Context );
+void querySymbol(QuerySetCommand::Context );
+void queryAttached(QuerySetCommand::Context );
size_t threadInfoIdx = 0;
void queryFThreadInfo(QuerySetCommand::Context );
--
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Gerrit-Change-Id: I98cdc9b4a952b4dc64f9357e6148af6e3351ef92
Gerrit-Change-Number: 63530
Gerrit-PatchSet: 8
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: adding support for O packet
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63529?usp=email )
(
8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: base: adding support for O packet
..
base: adding support for O packet
O packet allow the GDB stub to send a message to display for the GDB
remote.
This function could be used to implement certains specific command
response.
Change-Id: I1c9a1ca956efcf19c93a8503d97c1fb27f555966
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63529
Maintainer: Bobby Bruce
Reviewed-by: Bobby Bruce
Tested-by: kokoro
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 57 insertions(+), 1 deletion(-)
Approvals:
kokoro: Regressions pass
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 6c8d272..4835f00 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -232,6 +232,39 @@
return -1;
}
+//convert a hex to a char
+char
+hex2c(char c0,char c1)
+{
+ char temp[3] = {c0,c1,'\0'};
+ return std::stoi(temp,0,16);
+}
+
+//this function will be used in a future patch
+//convert a encoded string to a string
+[[maybe_unused]] std::string
+hexS2string(std::string hex_in)
+{
+ std::string out="";
+ for (unsigned int i = 0; i + 1 < hex_in.length();i += 2){
+ out.push_back(hex2c(hex_in[i],hex_in[i+1]));
+ }
+ return out;
+}
+
+//convert a string to a hex encoded string
+std::string
+string2hexS(std::string in)
+{
+ std::string out = "";
+ for (auto ch : in){
+ char temp[3] = " ";
+std::snprintf(temp,3,"%02hhx",ch);
+out.append(temp);
+ }
+ return out;
+}
+
// Convert the low 4 bits of an integer into an hex digit.
char
i2digit(int n)
@@ -917,7 +950,10 @@
BaseRemoteGDB::sendSPacket(int errnum){
send("S%02x",errnum);
}
-
+void
+BaseRemoteGDB::sendOPacket(const std::string message){
+ send("O" + string2hexS(message));
+}
void
BaseRemoteGDB::scheduleInstCommitEvent(Event *ev, int delta)
{
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 6f3cbe3..d51268a 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -324,6 +324,8 @@
void sendTPacket(int errnum, ContextID id,const std::string&
stopReason);
void sendSPacket(int errnum);
+//The OPacket allow to send string to be displayed by the remote GDB
+void sendOPacket(const std::string message);
/*
* GDB commands.
*/
--
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Gerrit-Change-Id: I1c9a1ca956efcf19c93a8503d97c1fb27f555966
Gerrit-Change-Number: 63529
Gerrit-PatchSet: 10
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: Adding stop reason and T Packet to the GDB stub
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63528?usp=email )
Change subject: base: Adding stop reason and T Packet to the GDB stub
..
base: Adding stop reason and T Packet to the GDB stub
The remote protocol describes 2 type of stop respond packet.
S packets (which are the one that where used before) and T packets.
T packet support multiple fields to give more information about:
- thread/core which stopped
- registers values
- A stopReason string that are predefined value and that can
differentiate between different types of break that would
issue the same signal.
Change-Id: Id8ed7115898bf825dd14395f586c393d6f5aa2bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63528
Maintainer: Bobby Bruce
Reviewed-by: Bobby Bruce
Tested-by: kokoro
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 49 insertions(+), 6 deletions(-)
Approvals:
kokoro: Regressions pass
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 2cc8402..6c8d272 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -192,7 +192,7 @@
DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc());
if (tc == gdb->tc)
-gdb->trap(tc->contextId(), SIGTRAP);
+gdb->trap(tc->contextId(), SIGTRAP,"");
}
};
@@ -516,7 +516,7 @@
// makes sense to use POSIX errno values, because that is what the
// gdb/remote.c functions want to return.
void
-BaseRemoteGDB::trap(ContextID id, int signum)
+BaseRemoteGDB::trap(ContextID id, int signum,const std::string& stopReason)
{
if (!attached)
return;
@@ -536,7 +536,7 @@
send("OK");
} else {
// Tell remote host that an exception has occurred.
-send("S%02x", signum);
+sendTPacket(signum,id,stopReason);
}
processCommands(signum);
@@ -904,6 +904,21 @@
}
void
+BaseRemoteGDB::sendTPacket(int errnum, ContextID id,
+const std::string& stopReason)
+{
+if (!stopReason.empty()){
+send("T%02xcore:%x;thread:%x;%s;",errnum,id + 1,id + 1,stopReason);
+}else{
+send("T%02xcore:%x;thread:%x;",errnum,id + 1,id + 1);
+}
+}
+void
+BaseRemoteGDB::sendSPacket(int errnum){
+ send("S%02x",errnum);
+}
+
+void
BaseRemoteGDB::scheduleInstCommitEvent(Event *ev, int delta)
{
if (delta == 0 && tc->status() != ThreadContext::Active) {
@@ -1004,7 +1019,7 @@
bool
BaseRemoteGDB::cmdSignal(GdbCommand::Context )
{
-send("S%02x", ctx.type);
+sendTPacket(ctx.type,tc->contextId(),"");
return true;
}
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index d0c4781..6f3cbe3 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -171,7 +171,7 @@
void replaceThreadContext(ThreadContext *_tc);
bool selectThreadContext(ContextID id);
-void trap(ContextID id, int signum);
+void trap(ContextID id, int signum,const std::string& stopReason="");
/** @} */ // end of api_remote_gdb
@@ -280,6 +280,7 @@
protected:
int _type;
ContextID _id;
+std::string _stopReason;
BaseRemoteGDB *gdb;
public:
@@ -287,8 +288,9 @@
{}
void type(int t) { _type = t; }
+void stopReason(std::string s) {_stopReason = s; }
void id(ContextID id) { _id = id; }
-void process() { gdb->trap(_id, _type); }
+ void process() { gdb->trap(_id, _type,_stopReason); }
} trapEvent;
/*
@@ -320,6 +322,8 @@
void insertHardBreak(Addr addr, size_t kind);
void removeHardBreak(Addr addr, size_t kind);
+void sendTPacket(int errnum, ContextID id,const std::string&
stopReason);
+void sendSPacket(int errnum);
/*
* GDB commands.
*/
--
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Gerrit-Change-Id: Id8ed7115898bf825dd14395f586c393d6f5aa2bc
Gerrit-Change-Number: 63528
Gerrit-PatchSet: 9
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: base: cmdIsThreadAlive implementation
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63527?usp=email )
(
9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: base: cmdIsThreadAlive implementation
..
base: cmdIsThreadAlive implementation
Some GDB implementations, specifically ARM's, needed this to be able to
switch between thread.
Change-Id: I0d4db0c008c336eac51008bcfefd04c375c333f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63527
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 34 insertions(+), 1 deletion(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index fb778a6..2cc8402 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -971,7 +971,7 @@
// signal and step
{ 'S', { "KGDB_ASYNC_STEP", ::cmdAsyncStep } },
// find out if the thread is alive
-{ 'T', { "KGDB_THREAD_ALIVE", ::cmdUnsupported } },
+{ 'T', { "KGDB_THREAD_ALIVE", ::cmdIsThreadAlive } },
//multi letter command
{ 'v', { "KGDB_MULTI_LETTER", ::cmdMultiLetter } },
// target exited
@@ -1106,6 +1106,22 @@
}
bool
+BaseRemoteGDB::cmdIsThreadAlive(GdbCommand::Context )
+{
+const char *p = ctx.data;
+int tid = 0;
+bool all, any;
+if (!parseThreadId(, all, any, tid))
+throw CmdError("E01");
+if (all)
+throw CmdError("E03");
+if (threads.find(tid) == threads.end())
+throw CmdError("E04");
+send("OK");
+return true;
+}
+
+bool
BaseRemoteGDB::cmdMemR(GdbCommand::Context )
{
const char *p = ctx.data;
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 3d8f703..d0c4781 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -378,6 +378,7 @@
bool cmdRegR(GdbCommand::Context );
bool cmdRegW(GdbCommand::Context );
bool cmdSetThread(GdbCommand::Context );
+bool cmdIsThreadAlive(GdbCommand::Context );
bool cmdMemR(GdbCommand::Context );
bool cmdMemW(GdbCommand::Context );
bool cmdQueryVar(GdbCommand::Context );
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0d4db0c008c336eac51008bcfefd04c375c333f7
Gerrit-Change-Number: 63527
Gerrit-PatchSet: 11
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: making GDB's getbyte and send more resilient
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63526?usp=email )
Change subject: base: making GDB's getbyte and send more resilient
..
base: making GDB's getbyte and send more resilient
Add a try_getbyte function that feature a timeout. This function uses
select to detect update on the file descriptor used to communicate with
the remote.
It is used to implement getbyte and to clean the file
descriptor before sending a message with send.
Now getbyte and send can recover from certains error like interruption
by other signals (EINTR) or delays causing the remote server to send
error packet to the stub.
Change-Id: Ie06845ba59dee0ad831632d5bc2b15132c9d5450
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63526
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 76 insertions(+), 5 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 4a0c632..fb778a6 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -129,7 +129,9 @@
#include "base/remote_gdb.hh"
+#include
#include
+#include
#include
#include
@@ -575,12 +577,54 @@
BaseRemoteGDB::getbyte()
{
uint8_t b;
-if (::read(fd, , sizeof(b)) == sizeof(b))
-return b;
-
-throw BadClient("Couldn't read data from debugger.");
+while (!try_getbyte(,-1));//no timeout
+ return b;
}
+bool
+BaseRemoteGDB::try_getbyte(uint8_t* c,int timeout_ms)
+{
+if (!c)
+panic("try_getbyte called with a null pointer as c");
+int res,retval;
+//Allow read to fail if it was interrupted by a signal (EINTR).
+errno = 0;
+//preparing fd_sets
+fd_set rfds;
+FD_ZERO();
+FD_SET(fd, );
+
+//setting up a timeout if timeout_ms is positive
+struct timeval tv;struct timeval* tv_ptr;
+if (timeout_ms >= 0){
+tv.tv_sec = timeout_ms/1000;
+tv.tv_usec = timeout_ms%1000;
+tv_ptr =
+}else{
+tv_ptr = NULL;
+}
+//Using select to check if the FD is ready to be read.
+while(true){
+do {
+errno = 0;
+retval = ::select(fd + 1, , NULL, NULL, tv_ptr);
+if (retval < 0 && errno != EINTR){//error
+DPRINTF(GDBMisc,"getbyte failed errno=%i retval=%i\n",
+errno,retval);
+throw BadClient("Couldn't read data from debugger.");
+}
+//a EINTR error means that the select call was interrupted
+//by another signal
+}while (errno == EINTR);
+if (retval == 0)
+return false;//timed out
+//reading (retval>0)
+res = ::read(fd, c, sizeof(*c));
+if (res == sizeof(*c))
+return true;//read successfully
+//read failed (?) retrying select
+}
+}
void
BaseRemoteGDB::putbyte(uint8_t b)
{
@@ -650,7 +694,8 @@
uint8_t csum, c;
DPRINTF(GDBSend, "send: %s\n", bp);
-
+//removing GDBBadP that could be waiting in the buffer
+while (try_getbyte(,0));
do {
p = bp;
// Start sending a packet
@@ -668,6 +713,8 @@
// Try transmitting over and over again until the other end doesn't
// send an error back.
c = getbyte();
+if ((c & 0x7f) == GDBBadP)
+DPRINTF(GDBSend, "PacketError\n");
} while ((c & 0x7f) == GDBBadP);
}
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 53cfedc..3d8f703 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -237,6 +237,7 @@
// Transfer data to/from GDB.
uint8_t getbyte();
+bool try_getbyte(uint8_t* c,int timeout=-1);//return true if successful
void putbyte(uint8_t b);
void recv(std::vector );
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie06845ba59dee0ad831632d5bc2b15132c9d5450
Gerrit-Change-Number: 63526
Gerrit-PatchSet: 11
Gerrit-Owner: Quentin Forcioli
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Quentin Forcioli
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: base: Adding multi-letter command support to GDB stub
Quentin Forcioli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63525?usp=email )
Change subject: base: Adding multi-letter command support to GDB stub
..
base: Adding multi-letter command support to GDB stub
The GDB remote protocol defines multi-letter
command names that start with a "v".
I added vKill and vMustReplyEmpty as an example.
Change-Id: I10177729c7d6a3e7d469ce66a63bfcfd21aa6f83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63525
Maintainer: Giacomo Travaglini
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
Maintainer: Bobby Bruce
Reviewed-by: Bobby Bruce
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 113 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 5c6ea36..4a0c632 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -925,6 +925,8 @@
{ 'S', { "KGDB_ASYNC_STEP", ::cmdAsyncStep } },
// find out if the thread is alive
{ 'T', { "KGDB_THREAD_ALIVE", ::cmdUnsupported } },
+//multi letter command
+{ 'v', { "KGDB_MULTI_LETTER", ::cmdMultiLetter } },
// target exited
{ 'W', { "KGDB_TARGET_EXIT", ::cmdUnsupported } },
// write memory
@@ -1104,6 +1106,67 @@
return true;
}
+bool
+BaseRemoteGDB::cmdMultiLetter(GdbCommand::Context )
+{
+GdbMultiLetterCommand::Context new_ctx;
+new_ctx.type = ctx.type;
+strtok(ctx.data,";?");
+char* sep = strtok(NULL,";:?");
+
+int txt_len = (sep != NULL) ? (sep - ctx.data) : strlen(ctx.data);
+DPRINTF(GDBMisc, "Multi-letter: %s , len=%i\n", ctx.data,txt_len);
+new_ctx.cmdTxt = std::string(ctx.data,txt_len);
+new_ctx.data = sep;
+new_ctx.len = ctx.len - txt_len;
+try {
+auto cmd_it = multiLetterMap.find(new_ctx.cmdTxt);
+if (cmd_it == multiLetterMap.end()) {
+DPRINTF(GDBMisc, "Unknown command: %s\n", new_ctx.cmdTxt);
+throw Unsupported();
+}
+new_ctx.cmd = &(cmd_it->second);
+
+return (this->*(new_ctx.cmd->func))(new_ctx);
+//catching errors: we don't need to catch anything else
+//as it will be handled by processCommands
+} catch (CmdError ) {
+send(e.error);
+}
+return false;
+}
+
+std::map
+BaseRemoteGDB::multiLetterMap = {
+{ "MustReplyEmpty", { "KGDB_REPLY_EMPTY",
::cmdReplyEmpty}},
+{ "Kill", { "KGDB_VKILL", ::cmdVKill}},
+};
+
+
+bool
+BaseRemoteGDB::cmdReplyEmpty(GdbMultiLetterCommand::Context )
+{
+send("");
+return true;
+}
+
+bool
+BaseRemoteGDB::cmdVKill(GdbMultiLetterCommand::Context )
+{
+warn("GDB command for kill received detaching instead");
+detach();
+return false;
+}
+
+bool
+BaseRemoteGDB::cmdMultiUnsupported(GdbMultiLetterCommand::Context )
+{
+DPRINTF(GDBMisc, "Unsupported Multi name command : %s\n",
+ctx.cmd->name);
+DDUMP(GDBMisc, ctx.data, ctx.len);
+throw Unsupported();
+}
+
namespace {
std::pair
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 2c3f6c1..53cfedc 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -344,6 +344,30 @@
static std::map commandMap;
+struct GdbMultiLetterCommand
+{
+ public:
+struct Context
+{
+const GdbMultiLetterCommand *cmd;
+std::string cmdTxt;
+int type;
+char *data;
+int len;
+};
+
+typedef bool (BaseRemoteGDB::*Func)(Context );
+
+const char * const name;
+const Func func;
+
+GdbMultiLetterCommand(const char *_name, Func _func) :
+ name(_name), func(_func) {}
+};
+
+
+static std::map multiLetterMap;
+
bool cmdUnsupported(GdbCommand::Context );
bool cmdSignal(GdbCommand::Context );
@@ -361,6 +385,13 @@
bool cmdClrHwBkpt(GdbCommand::Context );
bool cmdSetHwBkpt(GdbCommand::Context );
bool cmdDumpPageTable(GdbCommand::Context );
+bool cmdMultiLetter(GdbCommand::Context );
+
+//Multi letter command
+bool cmdMultiUnsupported(GdbMultiLetterCommand::Context );
+
+bool cmdReplyEmpty(GdbMultiLetterCommand::Context );
+bool cmdVKill(GdbMultiLetterCommand::Context );
struct QuerySetCommand
{
--
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Gerrit-Change-Id: I10177729c7d6a3e7d469ce6
[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: added errout and output file option in SE process
Zhantong Qiu has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64151?usp=email ) Change subject: stdlib: added errout and output file option in SE process .. stdlib: added errout and output file option in SE process In the set_se_binary_workload(), added stdout_file and stderr_file arguments to setup process.errout and process.output. Change-Id: I54db2248578f485a633d6b6212fa6c62bcbca4de --- M src/python/gem5/components/boards/se_binary_workload.py 1 file changed, 18 insertions(+), 0 deletions(-) diff --git a/src/python/gem5/components/boards/se_binary_workload.py b/src/python/gem5/components/boards/se_binary_workload.py index 62837fd..ea335a8 100644 --- a/src/python/gem5/components/boards/se_binary_workload.py +++ b/src/python/gem5/components/boards/se_binary_workload.py @@ -53,6 +53,8 @@ binary: AbstractResource, exit_on_work_items: bool = True, stdin_file: Optional[AbstractResource] = None, +stdout_file: Optional[AbstractResource] = None, +stderr_file: Optional[AbstractResource] = None, arguments: List[str] = [], simpoint: SimPoint = None, ) -> None: @@ -91,6 +93,10 @@ process.cmd = [binary_path] + arguments if stdin_file is not None: process.input = stdin_file.get_local_path() +if stdout_file is not None: +process.output = stdout_file.get_local_path() +if stderr_file is not None: +process.errout = stderr_file.get_local_path() for core in self.get_processor().get_cores(): core.set_workload(process) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64151?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I54db2248578f485a633d6b6212fa6c62bcbca4de Gerrit-Change-Number: 64151 Gerrit-PatchSet: 1 Gerrit-Owner: Zhantong Qiu Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add 'riscvmatched-fs.py' example to long/nightly tests
Bobby Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64131?usp=email ) Change subject: tests: Add 'riscvmatched-fs.py' example to long/nightly tests .. tests: Add 'riscvmatched-fs.py' example to long/nightly tests This patch adds "configs/example/gem5_library/riscvmatched-fs.py" as a long/nightly test. Change-Id: I2a31832d16a149e81e3a68f8a402d3dc86fb1924 --- M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py 1 file changed, 29 insertions(+), 0 deletions(-) diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index d8bcf6b..47ec60b 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -307,3 +307,20 @@ valid_hosts=constants.supported_hosts, length=constants.long_tag, ) + +gem5_verify_config( +name="test-gem5-library-example-riscvmatched-fs", +fixtures=(), +verifiers=(), +config=joinpath( +config.base_dir, +"configs", +"example", +"gem5_library", +"riscvmatched-fs.py", +), +config_args=[], +valid_isas=(constants.riscv_tag,), +valid_hosts=constants.supported_hosts, +length=constants.long_tag, +) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64131?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2a31832d16a149e81e3a68f8a402d3dc86fb1924 Gerrit-Change-Number: 64131 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-x86: Assign thread context id to APIC id
Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/35837?usp=email ) Change subject: arch-x86: Assign thread context id to APIC id .. arch-x86: Assign thread context id to APIC id This change tries to enable a unique APIC id for a single thread to enable smt support for x86 Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35837 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/x86/interrupts.cc 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index 74df9ab..bfea600 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -317,7 +317,8 @@ BaseInterrupts::setThreadContext(_tc); -initialApicId = tc->cpuId(); +// Update APIC ID to consider SMT threads +initialApicId = tc->contextId(); regs[APIC_ID] = (initialApicId << 24); pioAddr = x86LocalAPICAddress(initialApicId, 0); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35837?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49 Gerrit-Change-Number: 35837 Gerrit-PatchSet: 10 Gerrit-Owner: Ayaz Akram Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-x86, mem: Add support for PCID to x86
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35835?usp=email )
(
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-x86, mem: Add support for PCID to x86
..
arch-x86, mem: Add support for PCID to x86
This change adds Process Context Identifier (PCID) support
to x86, so that tlb entries can be tagged using pcid.
Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35835
Maintainer: Bobby Bruce
Reviewed-by: Bobby Bruce
Tested-by: kokoro
---
M src/arch/x86/cpuid.cc
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
4 files changed, 35 insertions(+), 3 deletions(-)
Approvals:
kokoro: Regressions pass
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 9d1390d..4ce66df 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -109,7 +109,7 @@
break;
case FamilyModelSteppingBrandFeatures:
result = CpuidResult(0x00020f51, 0x0405,
- 0xebd3fbff, 0x0001);
+ 0xebd3fbff, 0x00020001);
break;
case NameString1:
case NameString2:
diff --git a/src/arch/x86/pagetable_walker.cc
b/src/arch/x86/pagetable_walker.cc
index 705a509..f4831b3 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -546,6 +546,7 @@
{
VAddr addr = vaddr;
CR3 cr3 = tc->readMiscRegNoEffect(misc_reg::Cr3);
+CR4 cr4 = tc->readMiscRegNoEffect(misc_reg::Cr4);
// Check if we're in long mode or not
Efer efer = tc->readMiscRegNoEffect(misc_reg::Efer);
dataSize = 8;
@@ -557,7 +558,6 @@
enableNX = efer.nxe;
} else {
// We're in some flavor of legacy mode.
-CR4 cr4 = tc->readMiscRegNoEffect(misc_reg::Cr4);
if (cr4.pae) {
// Do legacy PAE.
state = PAEPDP;
@@ -581,7 +581,10 @@
entry.vaddr = vaddr;
Request::Flags flags = Request::PHYSICAL;
-if (cr3.pcd)
+
+// PCD can't be used if CR4.PCIDE=1 [sec 2.5
+// of Intel's Software Developer's manual]
+if (!cr4.pcide && cr3.pcd)
flags.set(Request::UNCACHEABLE);
RequestPtr request = std::make_shared(
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index bca74d5..a195fdf 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -593,6 +593,17 @@
tc->setMiscReg(misc_reg::Cr0, cr0);
tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
+
+// Setting CR3 to the process pid so that concatinated
+// page addr with lower 12 bits of CR3 can be used in SE
+// mode as well to avoid conflicts between tlb entries with
+// same virtual addresses belonging to different processes
+tc->setMiscReg(misc_reg::Cr3, pTable->pid());
+
+// Setting pcide bit in CR4
+CR4 cr4 = tc->readMiscRegNoEffect(misc_reg::Cr4);
+cr4.pcide = 1;
+tc->setMiscReg(misc_reg::Cr4, cr4);
}
}
}
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 3550384..1784142 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -621,12 +621,14 @@
// Base Address
Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
// Base Address
+Bitfield<11, 0> pcid; // Process-Context Identifier
Bitfield<4> pcd; // Page-Level Cache Disable
Bitfield<3> pwt; // Page-Level Writethrough
EndBitUnion(CR3)
BitUnion64(CR4)
Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
+Bitfield<17> pcide; // PCID Enable
Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
// WRGSBASE instructions
Bitfield<10> osxmmexcpt; // Operating System Unmasked
--
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Gerrit-Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Gerrit-Change-Number: 35835
Gerrit-PatchSet: 7
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-x86, mem: Add support to tag tlb entries with PCID
pcid);
}
DPRINTF(TLB, "Miss was serviced.\n");
}
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 68fe259..95c3482 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -76,6 +76,11 @@
TlbEntry *lookup(Addr va, bool update_lru = true);
void setConfigAddress(uint32_t addr);
+//concatenate Page Addr and pcid
+inline Addr concAddrPcid(Addr vpn, uint64_t pcid)
+{
+ return (vpn | pcid);
+}
protected:
@@ -156,7 +161,7 @@
Fault finalizePhysical(const RequestPtr , ThreadContext *tc,
BaseMMU::Mode mode) const override;
-TlbEntry *insert(Addr vpn, const TlbEntry );
+TlbEntry *insert(Addr vpn, const TlbEntry , uint64_t pcid);
// Checkpointing
void serialize(CheckpointOut ) const override;
--
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Gerrit-Change-Id: Ia91dc371482793962e3fc83afe7a3fd2cdb60eab
Gerrit-Change-Number: 35836
Gerrit-PatchSet: 9
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Exclude ARM KVM tests from nightly run
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64111?usp=email )
Change subject: tests: Exclude ARM KVM tests from nightly run
..
tests: Exclude ARM KVM tests from nightly run
Our Jenkin's server is an X86 host and cannot run ARM KVM.
Change-Id: Id10988aefa2534e73407c6a241fb3d5c9d958b7c
---
M tests/nightly.sh
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/tests/nightly.sh b/tests/nightly.sh
index dc871f6..a503e9e 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -115,7 +115,8 @@
cd "${gem5_root}/tests"
./main.py run -j${compile_threads} -vv \
--exclude-tags ".*" --include-tags kvm --exclude-tags very\-long \
---exclude-tags debug --exclude-tags fast --exclude-tags ARM
+--exclude-tags debug --exclude-tags fast --exclude-tags ARM \
+--exclude-tags aarch64
cd "${gem5_root}"
# For the GPU tests we compile and run the GPU ISA inside a gcn-gpu
container.
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id10988aefa2534e73407c6a241fb3d5c9d958b7c
Gerrit-Change-Number: 64111
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Add 'checkpoint-path' to checkpoint stdlib example
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64091?usp=email )
Change subject: tests: Add 'checkpoint-path' to checkpoint stdlib example
..
tests: Add 'checkpoint-path' to checkpoint stdlib example
The
'configs/example/gem5_library_example_tests/test_gem5_library_examples.py'
example would dump the savepoint in the CWD. This is fine when running
as an example, but we also run this script as a test. In this case the
checkpoint litters the repository.
To fix this, an optional 'checkpoint-path' argument is added to this
example which specifies where the checkpoint is to be saved. In the
tests, the checkpoint is saved to 'tests/gem5/resources'. This is our
default location for resources needed/produced by tests and is ignored
by git.
Change-Id: Ib985433786c99c37794a1c67cc4337a5dfd0498d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64091
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
Maintainer: Jason Lowe-Power
---
M configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 49 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git
a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
index c00b43d..159c4b7 100644
---
a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
+++
b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
@@ -43,6 +43,7 @@
```
"""
+import argparse
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
@@ -53,6 +54,18 @@
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
+parser = argparse.ArgumentParser()
+
+parser.add_argument(
+"--checkpoint-path",
+type=str,
+required=False,
+default="riscv-hello-checkpoint/",
+help="The directory to store the checkpoint.",
+)
+
+args = parser.parse_args()
+
# This check ensures the gem5 binary is compiled to the RISCV ISA target.
# If not, an exception will be thrown.
requires(isa_required=ISA.RISCV)
@@ -102,7 +115,6 @@
)
)
-checkpoint_path = "riscv-hello-checkpoint/"
-print("Taking a checkpoint at", checkpoint_path)
-simulator.save_checkpoint(checkpoint_path)
+print("Taking a checkpoint at", args.checkpoint_path)
+simulator.save_checkpoint(args.checkpoint_path)
print("Done taking a checkpoint")
diff --git
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
index ee212ae..d60fbb3 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -32,6 +32,11 @@
import re
import os
+if config.bin_path:
+resource_path = config.bin_path
+else:
+resource_path = joinpath(absdirpath(__file__), "..", "resources")
+
hello_verifier = verifier.MatchRegex(re.compile(r"Hello world!"))
save_checkpoint_verifier = verifier.MatchRegex(
re.compile(r"Done taking a checkpoint")
@@ -62,7 +67,10 @@
"checkpoints",
"riscv-hello-save-checkpoint.py",
),
-config_args=[],
+config_args=[
+"--checkpoint-path",
+joinpath(resource_path, "riscv-hello-checkpoint-save"),
+],
valid_isas=(constants.all_compiled_tag,),
valid_hosts=constants.supported_hosts,
length=constants.quick_tag,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib985433786c99c37794a1c67cc4337a5dfd0498d
Gerrit-Change-Number: 64091
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add 'checkpoint-path' to simpoints stdlib example
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64092?usp=email )
Change subject: tests: Add 'checkpoint-path' to simpoints stdlib example
..
tests: Add 'checkpoint-path' to simpoints stdlib example
The
'configs/example/gem5_library_checkpoints/simpoints-se-checkpoint.py'
example would dump the savepoint in the CWD. This is fine when running
as an example, but we also run this script as a test. In this case the
checkpoint litters the repository.
To fix this, an optional 'checkpoint-path' argument is added to this
example which specifies where the checkpoint is to be saved. In the
tests, the checkpoint is saved to 'tests/gem5/resources'. This is our
default location for resources needed/produced by tests and is ignored
by git.
Change-Id: I3dccc574b9e64d32386fd822ed7248ee365a0a08
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64092
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 43 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git
a/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
b/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
index 6094f09..e3b3c4c 100644
--- a/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
+++ b/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
@@ -52,6 +52,7 @@
```
"""
+import argparse
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
@@ -68,6 +69,18 @@
save_checkpoint_generator,
)
+parser = argparse.ArgumentParser()
+
+parser.add_argument(
+"--checkpoint-path",
+type=str,
+required=False,
+default="se_checkpoint_folder/",
+help="The directory to store the checkpoint.",
+)
+
+args = parser.parse_args()
+
requires(isa_required=ISA.X86)
# When taking a checkpoint, the cache state is not saved, so the cache
@@ -109,7 +122,7 @@
simpoint=simpoint,
)
-dir = Path("se_checkpoint_folder/")
+dir = Path(args.checkpoint_path)
dir.mkdir(exist_ok=True)
simulator = Simulator(
diff --git
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
index d60fbb3..d8bcf6b 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -106,7 +106,10 @@
"checkpoints",
"simpoints-se-checkpoint.py",
),
-config_args=[],
+config_args=[
+"--checkpoint-path",
+joinpath(resource_path, "se_checkpoint_folder-save"),
+],
valid_isas=(constants.all_compiled_tag,),
valid_hosts=constants.supported_hosts,
length=constants.quick_tag,
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3dccc574b9e64d32386fd822ed7248ee365a0a08
Gerrit-Change-Number: 64092
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Add Simpoints example scripts as tests
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63931?usp=email )
Change subject: tests: Add Simpoints example scripts as tests
..
tests: Add Simpoints example scripts as tests
These both ensure these example scripts still work as intended and
provides tests for the stdlib Simpoint API.
Change-Id: I549c3d22458a5013a335857c83a4e78dc425e37d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63931
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Bobby Bruce
---
M configs/example/gem5_library/checkpoints/simpoints-se-restore.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 59 insertions(+), 6 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git
a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
index 1a1bb05..4d49d9d 100644
--- a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
+++ b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
@@ -107,12 +107,13 @@
binary=Resource("x86-print-this"), arguments=["print this", 15000]
)
-# configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py has
to
-# run before running this script.
-# In here, it will get the path of the first SimPoint checkpoint taken by
the
-# simpoints-se-checkpoint.py
-dir = Path("se_checkpoint_folder")
-subfolder = [int(str(name).split(".")[1]) for name in dir.iterdir()]
+# Here we obtain the checkpoints from gem5 resources, but these are
generated
+# from
`configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py`.If
+# run prior to this script the `dir = Path("se_checkpoint_folder")` line
may be
+# used. The resource is pulled so we may run this script as a test.
+# dir = Path("se_checkpoint_folder")
+dir = Path(Resource("simpoints-se-checkpoints-v22-1").get_local_path())
+subfolder = [int(str(name).rsplit(".", 1)[1]) for name in dir.iterdir()]
dir = Path(dir / f"cpt.{min(subfolder)}").as_posix()
diff --git
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
index 0acc1ae..ee212ae 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -86,6 +86,42 @@
length=constants.quick_tag,
)
+gem5_verify_config(
+name="test-simpoints-se-checkpoint",
+fixtures=(),
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"configs",
+"example",
+"gem5_library",
+"checkpoints",
+"simpoints-se-checkpoint.py",
+),
+config_args=[],
+valid_isas=(constants.all_compiled_tag,),
+valid_hosts=constants.supported_hosts,
+length=constants.quick_tag,
+)
+
+gem5_verify_config(
+name="test-simpoints-se-restore",
+fixtures=(),
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"configs",
+"example",
+"gem5_library",
+"checkpoints",
+"simpoints-se-restore.py",
+),
+config_args=[],
+valid_isas=(constants.all_compiled_tag,),
+valid_hosts=constants.supported_hosts,
+length=constants.quick_tag,
+)
+
if os.access("/dev/kvm", mode=os.R_OK | os.W_OK):
# The x86-ubuntu-run uses KVM cores, this test will therefore only be
run
# on systems that support KVM.
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I549c3d22458a5013a335857c83a4e78dc425e37d
Gerrit-Change-Number: 63931
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add ArmRelease factory function to be used in KVM mode
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64072?usp=email )
Change subject: arch-arm: Add ArmRelease factory function to be used in KVM
mode
..
arch-arm: Add ArmRelease factory function to be used in KVM mode
From gem5 v22.0, EL2 and EL3 are automatically implemented
in the default release object [1]. This means any FS simulation
will start at EL3, which is the highest implemented EL.
Unfortunately this doesn't work in KVM mode, which is assuming
a VM does not start at EL3:
As soon as updateKvmState is called [2] gem5 tries to set
the VM PSTATE to EL3 and KVM fails the ioctl PSTATE write
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/51011
[2]: https://github.com/gem5/gem5/blob/v22.0.0.2/\
src/arch/arm/kvm/armv8_cpu.cc#L237
Signed-off-by: Giacomo Travaglini
Change-Id: Icf951bcfb47e0c2ff9abe64b1b9006934303ad48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64072
Tested-by: kokoro
---
M src/arch/arm/ArmSystem.py
1 file changed, 39 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 3994aee..936c032 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -41,6 +41,8 @@
from m5.objects.System import System
from m5.objects.ArmSemihosting import ArmSemihosting
+from typing import Any
+
class SveVectorLength(UInt8):
min = 1
@@ -108,6 +110,17 @@
else:
return True
+@classmethod
+def for_kvm(cls) -> Any:
+"""
+Generates an ArmRelease for KVM. It simply extracts EL2/EL3 support
+from the current cls object
+"""
+release = cls()
+release.remove(ArmExtension("SECURITY"))
+release.remove(ArmExtension("VIRTUALIZATION"))
+return release
+
class Armv8(ArmRelease):
extensions = ["LPAE", "VIRTUALIZATION", "SECURITY"]
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icf951bcfb47e0c2ff9abe64b1b9006934303ad48
Gerrit-Change-Number: 64072
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs, tests: Use proper releases in KVM simulations
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64073?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: configs, tests: Use proper releases in KVM simulations .. configs, tests: Use proper releases in KVM simulations Signed-off-by: Giacomo Travaglini Change-Id: I071f3d9c4eb5e4c7df3052bb8db93fece30cd069 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64073 Maintainer: Andreas Sandberg Reviewed-by: Andreas Sandberg Reviewed-by: Richard Cooper Tested-by: kokoro --- M configs/example/arm/fs_bigLITTLE.py M tests/gem5/configs/arm_generic.py 2 files changed, 17 insertions(+), 0 deletions(-) Approvals: kokoro: Regressions pass Andreas Sandberg: Looks good to me, approved; Looks good to me, approved Richard Cooper: Looks good to me, approved diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index 2c78a6c..c188de6 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -435,6 +435,7 @@ def _build_kvm(options, system, cpus): system.kvm_vm = KvmVM() +system.release = ArmDefaultRelease.for_kvm() if options.kvm_userspace_gic: # We will use the simulated GIC. diff --git a/tests/gem5/configs/arm_generic.py b/tests/gem5/configs/arm_generic.py index 252ac6c..df118c7 100644 --- a/tests/gem5/configs/arm_generic.py +++ b/tests/gem5/configs/arm_generic.py @@ -96,6 +96,7 @@ system -- System to work on. """ system.kvm_vm = KvmVM() +system.release = ArmDefaultRelease.for_kvm() # Arm KVM regressions will use a simulated GIC. This means that in # order to work we need to remove the system interface of the -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64073?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I071f3d9c4eb5e4c7df3052bb8db93fece30cd069 Gerrit-Change-Number: 64073 Gerrit-PatchSet: 4 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: dev: fix device number check error in IDE controller
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64052?usp=email )
Change subject: dev: fix device number check error in IDE controller
..
dev: fix device number check error in IDE controller
Fixed a typo between 3 and 4.
Change-Id: I1470e30c4d472587db0b9da5512b24ab92f1fd65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64052
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Gabe Black
---
M src/dev/storage/ide_ctrl.cc
1 file changed, 16 insertions(+), 1 deletion(-)
Approvals:
kokoro: Regressions pass
Gabe Black: Looks good to me, approved; Looks good to me, approved
diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 45e6242..3de0268 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -76,7 +76,7 @@
secondary(name() + ".secondary", this, false),
ioShift(p.io_shift), ctrlOffset(p.ctrl_offset)
{
-panic_if(params().disks.size() > 3,
+panic_if(params().disks.size() > 4,
"IDE controllers support a maximum of 4 devices attached!");
// Assign the disks to channels
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I1470e30c4d472587db0b9da5512b24ab92f1fd65
Gerrit-Change-Number: 64052
Gerrit-PatchSet: 2
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add the remove method to the ArmRelease class
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64071?usp=email ) Change subject: arch-arm: Add the remove method to the ArmRelease class .. arch-arm: Add the remove method to the ArmRelease class This allows to remove an extension from a release object Signed-off-by: Giacomo Travaglini Change-Id: I60189c37ffcefab991955c3d0bb560a6a79f0977 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64071 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Reviewed-by: Richard Cooper Tested-by: kokoro --- M src/arch/arm/ArmSystem.py 1 file changed, 26 insertions(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 0179552..3994aee 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -1,4 +1,4 @@ -# Copyright (c) 2009, 2012-2013, 2015-2021 ARM Limited +# Copyright (c) 2009, 2012-2013, 2015-2022 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -91,6 +91,14 @@ if new_ext.value not in [ext.value for ext in self.extensions]: self.extensions.append(new_ext) +def remove(self, ext: ArmExtension) -> None: +""" +Remove the provided extension (ArmExtension) from the system +""" +for curr_ext in list(self.extensions): +if curr_ext.value == ext.value: +self.extensions.remove(curr_ext) + def has(self, new_ext: ArmExtension) -> bool: """ Is the system implementing the provided extension (ArmExtension) ? -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64071?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I60189c37ffcefab991955c3d0bb560a6a79f0977 Gerrit-Change-Number: 64071 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib, configs: Add example FS script for RISCV Matched
Kunal Pai has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64014?usp=email )
Change subject: stdlib, configs: Add example FS script for RISCV Matched
..
stdlib, configs: Add example FS script for RISCV Matched
This script loads riscv-bootloader-vmlinux-5.10 onto a
riscv-ubuntu-20.04-img disk image on the RISCVMatched
prebuilt board found at
src/python/gem5/prebuilt/riscvmatched directory.
Change-Id: Ic2b4b19bac0a66d40d667b82a43c7791ff918847
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64014
Maintainer: Bobby Bruce
Reviewed-by: Bobby Bruce
Tested-by: kokoro
---
A configs/example/gem5_library/riscvmatched-fs.py
1 file changed, 84 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/gem5_library/riscvmatched-fs.py
b/configs/example/gem5_library/riscvmatched-fs.py
new file mode 100644
index 000..da47a4b
--- /dev/null
+++ b/configs/example/gem5_library/riscvmatched-fs.py
@@ -0,0 +1,66 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This gem5 configuration script runs a full system Ubuntu image, Linux
+kernel and calls m5 exit after the kernel is loaded.
+
+Usage
+---
+
+```
+scons build/RISCV/gem5.opt
+
+./build/RISCV/gem5.opt \
+configs/example/gem5_library/riscvmatched-fs.py
+```
+"""
+
+from python.gem5.prebuilt.riscvmatched.riscvmatched_board import (
+RISCVMatchedBoard,
+)
+from gem5.utils.requires import requires
+from gem5.isas import ISA
+from gem5.simulate.simulator import Simulator
+from gem5.resources.workload import Workload
+
+requires(isa_required=ISA.RISCV)
+
+# instantiate the riscv matched board with default parameters
+board = RISCVMatchedBoard(
+clk_freq="1.2GHz",
+l2_size="2MB",
+is_fs=True,
+)
+
+# Here we a full system workload: "riscv-ubuntu-20.04-boot" which boots
+# Ubuntu 20.04. Once the system successfully boots it encounters an
`m5_exit`
+# instruction which stops the simulation. When the simulation has ended
you may
+# inspect `m5out/system.pc.com_1.device` to see the stdout.
+board.set_workload(Workload("riscv-ubuntu-20.04-boot"))
+
+simulator = Simulator(board=board)
+simulator.run()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic2b4b19bac0a66d40d667b82a43c7791ff918847
Gerrit-Change-Number: 64014
Gerrit-PatchSet: 5
Gerrit-Owner: Kunal Pai
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Kunal Pai
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add 'checkpoint-path' to simpoints stdlib example
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64092?usp=email )
Change subject: tests: Add 'checkpoint-path' to simpoints stdlib example
..
tests: Add 'checkpoint-path' to simpoints stdlib example
The
'configs/example/gem5_library_checkpoints/simpoints-se-checkpoint.py'
example would dump the savepoint in the CWD. This is fine when running
as an example, but we also run this script as a test. In this case the
checkpoint litters the repository.
To fix this, an optional 'checkpoint-path' argument is added to this
example which specifies where the checkpoint is to be saved. In the
tests, the checkpoint is saved to 'tests/gem5/resources'. This is our
default location for resources needed/produced by tests and is ignored
by git.
Change-Id: I3dccc574b9e64d32386fd822ed7248ee365a0a08
---
M configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git
a/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
b/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
index 6094f09..e3b3c4c 100644
--- a/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
+++ b/configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
@@ -52,6 +52,7 @@
```
"""
+import argparse
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
@@ -68,6 +69,18 @@
save_checkpoint_generator,
)
+parser = argparse.ArgumentParser()
+
+parser.add_argument(
+"--checkpoint-path",
+type=str,
+required=False,
+default="se_checkpoint_folder/",
+help="The directory to store the checkpoint.",
+)
+
+args = parser.parse_args()
+
requires(isa_required=ISA.X86)
# When taking a checkpoint, the cache state is not saved, so the cache
@@ -109,7 +122,7 @@
simpoint=simpoint,
)
-dir = Path("se_checkpoint_folder/")
+dir = Path(args.checkpoint_path)
dir.mkdir(exist_ok=True)
simulator = Simulator(
diff --git
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
index d60fbb3..d8bcf6b 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -106,7 +106,10 @@
"checkpoints",
"simpoints-se-checkpoint.py",
),
-config_args=[],
+config_args=[
+"--checkpoint-path",
+joinpath(resource_path, "se_checkpoint_folder-save"),
+],
valid_isas=(constants.all_compiled_tag,),
valid_hosts=constants.supported_hosts,
length=constants.quick_tag,
--
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Gerrit-Change-Id: I3dccc574b9e64d32386fd822ed7248ee365a0a08
Gerrit-Change-Number: 64092
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add 'checkpoint-path' to checkpoint stdlib example
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64091?usp=email )
Change subject: tests: Add 'checkpoint-path' to checkpoint stdlib example
..
tests: Add 'checkpoint-path' to checkpoint stdlib example
The
'configs/example/gem5_library_example_tests/test_gem5_library_examples.py'
example would dump the savepoint in the CWD. This is fine when running
as an example, but we also run this script as a test. In this case the
checkpoint litters the repository.
To fix this, an optional 'checkpoint-path' argument is added to this
example which specifies where the checkpoint is to be saved. In the
tests, the checkpoint is saved to 'tests/gem5/resources'. This is our
default location for resources needed/produced by tests and is ignored
by git.
Change-Id: Ib985433786c99c37794a1c67cc4337a5dfd0498d
---
M configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git
a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
index c00b43d..159c4b7 100644
---
a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
+++
b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
@@ -43,6 +43,7 @@
```
"""
+import argparse
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
@@ -53,6 +54,18 @@
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
+parser = argparse.ArgumentParser()
+
+parser.add_argument(
+"--checkpoint-path",
+type=str,
+required=False,
+default="riscv-hello-checkpoint/",
+help="The directory to store the checkpoint.",
+)
+
+args = parser.parse_args()
+
# This check ensures the gem5 binary is compiled to the RISCV ISA target.
# If not, an exception will be thrown.
requires(isa_required=ISA.RISCV)
@@ -102,7 +115,6 @@
)
)
-checkpoint_path = "riscv-hello-checkpoint/"
-print("Taking a checkpoint at", checkpoint_path)
-simulator.save_checkpoint(checkpoint_path)
+print("Taking a checkpoint at", args.checkpoint_path)
+simulator.save_checkpoint(args.checkpoint_path)
print("Done taking a checkpoint")
diff --git
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
index ee212ae..d60fbb3 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -32,6 +32,11 @@
import re
import os
+if config.bin_path:
+resource_path = config.bin_path
+else:
+resource_path = joinpath(absdirpath(__file__), "..", "resources")
+
hello_verifier = verifier.MatchRegex(re.compile(r"Hello world!"))
save_checkpoint_verifier = verifier.MatchRegex(
re.compile(r"Done taking a checkpoint")
@@ -62,7 +67,10 @@
"checkpoints",
"riscv-hello-save-checkpoint.py",
),
-config_args=[],
+config_args=[
+"--checkpoint-path",
+joinpath(resource_path, "riscv-hello-checkpoint-save"),
+],
valid_isas=(constants.all_compiled_tag,),
valid_hosts=constants.supported_hosts,
length=constants.quick_tag,
--
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Gerrit-Change-Id: Ib985433786c99c37794a1c67cc4337a5dfd0498d
Gerrit-Change-Number: 64091
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Fix GICv3 GICD_ITARGETSR address range
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/64074?usp=email ) Change subject: dev-arm: Fix GICv3 GICD_ITARGETSR address range .. dev-arm: Fix GICv3 GICD_ITARGETSR address range According to the GICv3 manual, GICD_ITARGETSR address range goes from 0x0800 to 0x0c00 (as already implemented in the GICv2 model [1]) [1]: https://github.com/gem5/gem5/blob/v22.0.0.0/\ src/dev/arm/gic_v2.cc#L64 Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64074 Maintainer: Andreas Sandberg Reviewed-by: Richard Cooper Reviewed-by: Andreas Sandberg Tested-by: kokoro --- M src/dev/arm/gic_v3_distributor.cc 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass Richard Cooper: Looks good to me, approved diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc index 820f8bc..1cb485c 100644 --- a/src/dev/arm/gic_v3_distributor.cc +++ b/src/dev/arm/gic_v3_distributor.cc @@ -60,7 +60,7 @@ const AddrRange Gicv3Distributor::GICD_ISACTIVER (0x0300, 0x0380); const AddrRange Gicv3Distributor::GICD_ICACTIVER (0x0380, 0x0400); const AddrRange Gicv3Distributor::GICD_IPRIORITYR(0x0400, 0x0800); -const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x0900); +const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x0c00); const AddrRange Gicv3Distributor::GICD_ICFGR (0x0c00, 0x0d00); const AddrRange Gicv3Distributor::GICD_IGRPMODR (0x0d00, 0x0d80); const AddrRange Gicv3Distributor::GICD_NSACR (0x0e00, 0x0f00); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64074?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32 Gerrit-Change-Number: 64074 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Fix GICv3 GICD_ITARGETSR address range
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64074?usp=email ) Change subject: dev-arm: Fix GICv3 GICD_ITARGETSR address range .. dev-arm: Fix GICv3 GICD_ITARGETSR address range According to the GICv3 manual, GICD_ITARGETSR address range goes from 0x0800 to 0x0c00 (as already implemented in the GICv2 model [1]) Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32 Signed-off-by: Giacomo Travaglini --- M src/dev/arm/gic_v3_distributor.cc 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc index 820f8bc..1cb485c 100644 --- a/src/dev/arm/gic_v3_distributor.cc +++ b/src/dev/arm/gic_v3_distributor.cc @@ -60,7 +60,7 @@ const AddrRange Gicv3Distributor::GICD_ISACTIVER (0x0300, 0x0380); const AddrRange Gicv3Distributor::GICD_ICACTIVER (0x0380, 0x0400); const AddrRange Gicv3Distributor::GICD_IPRIORITYR(0x0400, 0x0800); -const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x0900); +const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x0c00); const AddrRange Gicv3Distributor::GICD_ICFGR (0x0c00, 0x0d00); const AddrRange Gicv3Distributor::GICD_IGRPMODR (0x0d00, 0x0d80); const AddrRange Gicv3Distributor::GICD_NSACR (0x0e00, 0x0f00); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64074?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32 Gerrit-Change-Number: 64074 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add the remove method to the ArmRelease class
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64071?usp=email ) Change subject: arch-arm: Add the remove method to the ArmRelease class .. arch-arm: Add the remove method to the ArmRelease class This allows to remove an extension from a release object Signed-off-by: Giacomo Travaglini Change-Id: I60189c37ffcefab991955c3d0bb560a6a79f0977 --- M src/arch/arm/ArmSystem.py 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 0179552..3994aee 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -1,4 +1,4 @@ -# Copyright (c) 2009, 2012-2013, 2015-2021 ARM Limited +# Copyright (c) 2009, 2012-2013, 2015-2022 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -91,6 +91,14 @@ if new_ext.value not in [ext.value for ext in self.extensions]: self.extensions.append(new_ext) +def remove(self, ext: ArmExtension) -> None: +""" +Remove the provided extension (ArmExtension) from the system +""" +for curr_ext in list(self.extensions): +if curr_ext.value == ext.value: +self.extensions.remove(curr_ext) + def has(self, new_ext: ArmExtension) -> bool: """ Is the system implementing the provided extension (ArmExtension) ? -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64071?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I60189c37ffcefab991955c3d0bb560a6a79f0977 Gerrit-Change-Number: 64071 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: configs, tests: Use proper releases in KVM simulations
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64073?usp=email ) Change subject: configs, tests: Use proper releases in KVM simulations .. configs, tests: Use proper releases in KVM simulations Signed-off-by: Giacomo Travaglini Change-Id: I071f3d9c4eb5e4c7df3052bb8db93fece30cd069 --- M configs/example/arm/fs_bigLITTLE.py M tests/gem5/configs/arm_generic.py 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index 2c78a6c..c188de6 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -435,6 +435,7 @@ def _build_kvm(options, system, cpus): system.kvm_vm = KvmVM() +system.release = ArmDefaultRelease.for_kvm() if options.kvm_userspace_gic: # We will use the simulated GIC. diff --git a/tests/gem5/configs/arm_generic.py b/tests/gem5/configs/arm_generic.py index 252ac6c..df118c7 100644 --- a/tests/gem5/configs/arm_generic.py +++ b/tests/gem5/configs/arm_generic.py @@ -96,6 +96,7 @@ system -- System to work on. """ system.kvm_vm = KvmVM() +system.release = ArmDefaultRelease.for_kvm() # Arm KVM regressions will use a simulated GIC. This means that in # order to work we need to remove the system interface of the -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64073?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I071f3d9c4eb5e4c7df3052bb8db93fece30cd069 Gerrit-Change-Number: 64073 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add ArmRelease factory function to be used in KVM mode
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64072?usp=email )
Change subject: arch-arm: Add ArmRelease factory function to be used in KVM
mode
..
arch-arm: Add ArmRelease factory function to be used in KVM mode
From gem5 v22.0, EL2 and EL3 are automatically implemented
in the default release object [1]. This means any FS simulation
will start at EL3, which is the highest implemented EL.
Unfortunately this doesn't work in KVM mode, which is assuming
a VM does not start at EL3:
As soon as updateKvmState is called [2] gem5 tries to set
the VM PSTATE to EL3 and KVM fails the ioctl PSTATE write
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/51011
[2]: https://github.com/gem5/gem5/blob/v22.0.0.2/\
src/arch/arm/kvm/armv8_cpu.cc#L237
Signed-off-by: Giacomo Travaglini
Change-Id: Icf951bcfb47e0c2ff9abe64b1b9006934303ad48
---
M src/arch/arm/ArmSystem.py
1 file changed, 35 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 3994aee..ce26dab 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -41,6 +41,7 @@
from m5.objects.System import System
from m5.objects.ArmSemihosting import ArmSemihosting
+from typing import Any
class SveVectorLength(UInt8):
min = 1
@@ -108,6 +109,16 @@
else:
return True
+@classmethod
+def for_kvm(cls) -> Any:
+"""
+Generates an ArmRelease for KVM. It simply extracts EL2/EL3 support
+from the current cls object
+"""
+release = cls()
+release.remove(ArmExtension("SECURITY"))
+release.remove(ArmExtension("VIRTUALIZATION"))
+return release
class Armv8(ArmRelease):
extensions = ["LPAE", "VIRTUALIZATION", "SECURITY"]
--
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Gerrit-Change-Id: Icf951bcfb47e0c2ff9abe64b1b9006934303ad48
Gerrit-Change-Number: 64072
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Gerrit-Owner: Giacomo Travaglini
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev: fix device number check error in IDE controller
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64052?usp=email )
Change subject: dev: fix device number check error in IDE controller
..
dev: fix device number check error in IDE controller
Fixed a typo between 3 and 4.
Change-Id: I1470e30c4d472587db0b9da5512b24ab92f1fd65
---
M src/dev/storage/ide_ctrl.cc
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 45e6242..3de0268 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -76,7 +76,7 @@
secondary(name() + ".secondary", this, false),
ioShift(p.io_shift), ctrlOffset(p.ctrl_offset)
{
-panic_if(params().disks.size() > 3,
+panic_if(params().disks.size() > 4,
"IDE controllers support a maximum of 4 devices attached!");
// Assign the disks to channels
--
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Gerrit-Change-Id: I1470e30c4d472587db0b9da5512b24ab92f1fd65
Gerrit-Change-Number: 64052
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: [Simbot test] title too long
Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64031?usp=email ) Change subject: [Simbot test] title too long .. [Simbot test] title too long Change-Id: I3299b8d563e8a3e9305f85d5881f5a1e9b360426 --- A tests/tests.txt 1 file changed, 10 insertions(+), 0 deletions(-) diff --git a/tests/tests.txt b/tests/tests.txt new file mode 100644 index 000..68c6d60 --- /dev/null +++ b/tests/tests.txt @@ -0,0 +1 @@ +simbot title too long -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64031?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3299b8d563e8a3e9305f85d5881f5a1e9b360426 Gerrit-Change-Number: 64031 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Chang Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement V_XAD_U32 instruction
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/63972?usp=email )
Change subject: arch-vega: Implement V_XAD_U32 instruction
..
arch-vega: Implement V_XAD_U32 instruction
Used in rodinia:heartwall. This instruction is new in vega and does not
exist in GCN3.
Change-Id: I6127290d1c85688a7f82e149e97762ca55e05fc6
---
M src/arch/amdgpu/vega/decoder.cc
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
3 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/src/arch/amdgpu/vega/decoder.cc
b/src/arch/amdgpu/vega/decoder.cc
index c4dfe9a..18c72a4 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -6872,8 +6872,7 @@
GPUStaticInst*
Decoder::decode_OPU_VOP3__V_XAD_U32(MachInst iFmt)
{
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_VOP3__V_XAD_U32(>iFmt_VOP3A);
}
GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 22cad1c..76bb8aa 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -32215,6 +32215,51 @@
vcc.write();
vdst.write();
} // execute
+// --- Inst_VOP3__V_XAD_U32 class methods ---
+
+Inst_VOP3__V_XAD_U32::Inst_VOP3__V_XAD_U32(InFmt_VOP3A *iFmt)
+: Inst_VOP3A(iFmt, "v_xad_u32", false)
+{
+setFlag(ALU);
+} // Inst_VOP3__V_XAD_U32
+
+Inst_VOP3__V_XAD_U32::~Inst_VOP3__V_XAD_U32()
+{
+} // ~Inst_VOP3__V_XAD_U32
+
+// --- description from .arch file ---
+// D.u32 = (S0.u32 ^ S1.u32) + S2.u32.
+void
+Inst_VOP3__V_XAD_U32::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+src0.readSrc();
+src1.readSrc();
+src2.readSrc();
+
+/**
+ * input modifiers are supported by FP operations only
+ */
+assert(!(instData.ABS & 0x1));
+assert(!(instData.ABS & 0x2));
+assert(!(instData.ABS & 0x4));
+assert(!(extData.NEG & 0x1));
+assert(!(extData.NEG & 0x2));
+assert(!(extData.NEG & 0x4));
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = (src0[lane] ^ src1[lane]) + src2[lane];
+}
+}
+
+vdst.write();
+} // execute
// --- Inst_VOP3__V_LSHL_ADD_U32 class methods ---
Inst_VOP3__V_LSHL_ADD_U32::Inst_VOP3__V_LSHL_ADD_U32(InFmt_VOP3A *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 962cc66..0671df8 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -29664,6 +29664,42 @@
void execute(GPUDynInstPtr) override;
}; // Inst_VOP3__V_MAD_I64_I32
+class Inst_VOP3__V_XAD_U32 : public Inst_VOP3A
+{
+ public:
+Inst_VOP3__V_XAD_U32(InFmt_VOP3A*);
+~Inst_VOP3__V_XAD_U32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 3; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+ case 0: //src_0
+return 4;
+ case 1: //src_1
+return 4;
+ case 2: //src_2
+return 4;
+ case 3: //vdst
+return 4;
+ default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+}; // Inst_VOP3__V_XAD_U32
+
class Inst_VOP3__V_LSHL_ADD_U32 : public Inst_VOP3A
{
public:
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Remove cached copy of device memory
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63951?usp=email )
Change subject: dev-amdgpu: Remove cached copy of device memory
..
dev-amdgpu: Remove cached copy of device memory
This map was originally used for fast access to the GART table. It is no
longer needed as the table has been moved to the AMDGPUVM class. Along
with commit 12ec5f9172301a121a949c622a03a839b0e45d4e which reads
functionally from device memory, this table is no longer needed and is
essentially a duplicate copy of device memory for anything written over
the PCI BAR.
This changeset removes the map entirely which will reduce the memory
footprint of simulations and potentially avoid stale copies of data
when reading over the PCI BAR.
Change-Id: I312ae38f869c6a65e50577b1c33dd055078aaf32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63951
Reviewed-by: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
---
M src/dev/amdgpu/amdgpu_device.cc
M src/dev/amdgpu/amdgpu_device.hh
2 files changed, 29 insertions(+), 11 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
Matt Sinclair: Looks good to me, approved
diff --git a/src/dev/amdgpu/amdgpu_device.cc
b/src/dev/amdgpu/amdgpu_device.cc
index 09e46a5..227e69e 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -182,9 +182,8 @@
/*
* Return data for frame reads in priority order: (1) Special addresses
- * first, ignoring any writes from driver. (2) GART addresses written
- * to frame_regs in writeFrame. (3) Any other address from device
backing
- * store / abstract memory class functionally.
+ * first, ignoring any writes from driver. (2) Any other address from
+ * device backing store / abstract memory class functionally.
*/
if (offset == 0xa28000) {
/*
@@ -198,9 +197,6 @@
}
pkt->setUintX(regs[pkt->getAddr()], ByteOrder::little);
-} else if (frame_regs.find(offset) != frame_regs.end()) {
-/* If the driver wrote something, use that value over the trace. */
-pkt->setUintX(frame_regs[offset], ByteOrder::little);
} else {
/*
* Read the value from device memory. This must be done
functionally
@@ -273,12 +269,10 @@
Addr aperture_offset = offset - aperture;
// Record the value
-frame_regs[offset] = pkt->getUintX(ByteOrder::little);
if (aperture == gpuvm.gartBase()) {
-frame_regs[aperture_offset] = pkt->getLE();
-DPRINTF(AMDGPUDevice, "GART translation %p -> %p\n",
aperture_offset,
-bits(frame_regs[aperture_offset], 48, 12));
gpuvm.gartTable[aperture_offset] = pkt->getLE();
+DPRINTF(AMDGPUDevice, "GART translation %p -> %p\n",
aperture_offset,
+gpuvm.gartTable[aperture_offset]);
}
}
diff --git a/src/dev/amdgpu/amdgpu_device.hh
b/src/dev/amdgpu/amdgpu_device.hh
index fbb0d1c..ac31b95 100644
--- a/src/dev/amdgpu/amdgpu_device.hh
+++ b/src/dev/amdgpu/amdgpu_device.hh
@@ -85,7 +85,6 @@
* Structures to hold registers, doorbells, and some frame memory
*/
using GPURegMap = std::unordered_map;
-GPURegMap frame_regs;
GPURegMap regs;
std::unordered_map doorbells;
--
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Gerrit-Change-Id: I312ae38f869c6a65e50577b1c33dd055078aaf32
Gerrit-Change-Number: 63951
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs, gpu-compute: Add configurable L1 access latencies
VISHNU RAMADAS has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63971?usp=email ) Change subject: configs, gpu-compute: Add configurable L1 access latencies .. configs, gpu-compute: Add configurable L1 access latencies Previously the L1 request and response latencies were not configurable in the GPU config scripts. As a result, the simulations used the default values from GPU.py. This commits adds support to change this value as an input parameter. The parameters to use are "--mem-req-latency" followed by the value and "--mem-resp-latency" followed by the value. The default values are the same as those in GPU.py (which is 50). These new parameters should be set instead of changing the mandatory queue latency when configuring the L1 cache. Change-Id: I812d77758ea12530899953f308c91f4c8b05866d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63971 Reviewed-by: Matt Sinclair Tested-by: kokoro Maintainer: Matt Sinclair --- M configs/example/apu_se.py 1 file changed, 35 insertions(+), 0 deletions(-) Approvals: Matt Sinclair: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py index 16e3365..b33daa5 100644 --- a/configs/example/apu_se.py +++ b/configs/example/apu_se.py @@ -264,6 +264,18 @@ help="Latency while accessing shared memory", ) parser.add_argument( +"--mem-req-latency", +type=int, +default=50, +help="Latency for requests from the cu to ruby.", +) +parser.add_argument( +"--mem-resp-latency", +type=int, +default=50, +help="Latency for responses from ruby to the cu.", +) +parser.add_argument( "--TLB-prefetch", type=int, help="prefetch depth for" "TLBs" ) parser.add_argument( @@ -449,6 +461,8 @@ countPages=args.countPages, max_cu_tokens=args.max_cu_tokens, vrf_lm_bus_latency=args.vrf_lm_bus_latency, +mem_req_latency=args.mem_req_latency, +mem_resp_latency=args.mem_resp_latency, localDataStore=LdsState( banks=args.numLdsBanks, bankConflictPenalty=args.ldsBankConflictPenalty, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63971?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I812d77758ea12530899953f308c91f4c8b05866d Gerrit-Change-Number: 63971 Gerrit-PatchSet: 6 Gerrit-Owner: VISHNU RAMADAS Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: VISHNU RAMADAS Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Edit RiscvMatched RTC
Kunal Pai has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64013?usp=email )
Change subject: stdlib: Edit RiscvMatched RTC
..
stdlib: Edit RiscvMatched RTC
Fixed the bug that made FS mode break.
Changed RTC value as fix.
Change-Id: I0effa1ecd32a8a8845e619d940f8e0efe549cfc1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64013
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
1 file changed, 17 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
index 986f29e..469010c 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -104,8 +104,6 @@
Details can be found on page 77, section 7.1 of the datasheet.
Datasheet for inbuilt params can be found here:
https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
-
-NOTE: FS Mode does not work yet.
"""
def __init__(
@@ -153,7 +151,7 @@
# Add the RTC
self.platform.rtc = RiscvRTC(
-frequency=Frequency("1MHz")
+frequency=Frequency("100MHz")
) # page 77, section 7.1
self.platform.clint.int_pin = self.platform.rtc.int_pin
--
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Gerrit-Change-Id: I0effa1ecd32a8a8845e619d940f8e0efe549cfc1
Gerrit-Change-Number: 64013
Gerrit-PatchSet: 3
Gerrit-Owner: Kunal Pai
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Kunal Pai
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix variable not found error
Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64012?usp=email )
Change subject: scons: Fix variable not found error
..
scons: Fix variable not found error
Change-Id: I09708fea777a57a35e55409c8997ed0b25de2b46
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64012
Tested-by: kokoro
Maintainer: Jason Lowe-Power
Reviewed-by: Melissa Jost
---
M site_scons/gem5_scons/__init__.py
1 file changed, 15 insertions(+), 1 deletion(-)
Approvals:
Melissa Jost: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/site_scons/gem5_scons/__init__.py
b/site_scons/gem5_scons/__init__.py
index c958e22..7214876 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -264,7 +264,7 @@
while path_dirs and path_dirs[-1] != "build":
variant_dir = path_dirs.pop()
if not path_dirs:
-error("No non-leaf 'build' dir found on target path.", t)
+error("No non-leaf 'build' dir found on target path.", target)
return os.path.join("/", *path_dirs), variant_dir
--
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Gerrit-Change-Id: I09708fea777a57a35e55409c8997ed0b25de2b46
Gerrit-Change-Number: 64012
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Melissa Jost
Gerrit-Reviewer: Melissa Jost
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add example memory traffic runscript
enerator as the processor. +memory=memory, +# With no cache hierarchy the test board will directly connect the +# generator to the memory +cache_hierarchy=None, +) + +simulator = Simulator(board=board) +simulator.run() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64018?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6235d0cb11909f5b4cc6442e419496c77425ba37 Gerrit-Change-Number: 64018 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Add _post_instantiate function
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64016?usp=email ) Change subject: stdlib: Add _post_instantiate function .. stdlib: Add _post_instantiate function This function will be called on the board after m5.instantiate is called. This is useful, for instance, to start traffic generators. Currently all implementations simply `pass`. Change-Id: Ie2ab3fdddca5f3978d98191e5c08504561587fbb Signed-off-by: Jason Lowe-Power --- M src/python/gem5/components/boards/abstract_board.py M src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py M src/python/gem5/components/memory/abstract_memory_system.py M src/python/gem5/components/processors/abstract_processor.py M src/python/gem5/simulate/simulator.py 5 files changed, 37 insertions(+), 0 deletions(-) diff --git a/src/python/gem5/components/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py index 1ac31cb..8e3c3a4 100644 --- a/src/python/gem5/components/boards/abstract_board.py +++ b/src/python/gem5/components/boards/abstract_board.py @@ -338,3 +338,10 @@ # Incorporate the processor into the motherboard. self.get_processor().incorporate_processor(self) + +def _post_instantiate(self): +"""Called to set up anything needed after m5.instantiate""" +self.get_processor()._post_instantiate() +if self.get_cache_hierarchy(): +self.get_cache_hierarchy()._post_instantiate() +self.get_memory()._post_instantiate() diff --git a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py index 5f6096e..8d59a38 100644 --- a/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py @@ -70,3 +70,7 @@ :returns: True if the cache hierarchy is ruby. Otherwise False. """ raise NotImplementedError + +def _post_instantiate(self): +"""Called to set up anything needed after m5.instantiate""" +pass diff --git a/src/python/gem5/components/memory/abstract_memory_system.py b/src/python/gem5/components/memory/abstract_memory_system.py index 27bc152..cfbf6ac 100644 --- a/src/python/gem5/components/memory/abstract_memory_system.py +++ b/src/python/gem5/components/memory/abstract_memory_system.py @@ -71,3 +71,7 @@ will be raised. """ raise NotImplementedError + +def _post_instantiate(self) -> None: +"""Called to set up anything needed after m5.instantiate""" +pass diff --git a/src/python/gem5/components/processors/abstract_processor.py b/src/python/gem5/components/processors/abstract_processor.py index 72fa5db..a0f8b5c 100644 --- a/src/python/gem5/components/processors/abstract_processor.py +++ b/src/python/gem5/components/processors/abstract_processor.py @@ -74,3 +74,7 @@ @abstractmethod def incorporate_processor(self, board: AbstractBoard) -> None: raise NotImplementedError + +def _post_instantiate(self) -> None: +"""Called to set up anything needed after m5.instantiate""" +pass diff --git a/src/python/gem5/simulate/simulator.py b/src/python/gem5/simulate/simulator.py index efa7c42..ad16220 100644 --- a/src/python/gem5/simulate/simulator.py +++ b/src/python/gem5/simulate/simulator.py @@ -381,6 +381,10 @@ m5.instantiate(self._checkpoint_path) self._instantiated = True +# Let the board know that instantiate has been called so it can do +# any final things. +self._board._post_instantiate() + def run(self, max_ticks: int = m5.MaxTick) -> None: """ This function will start or continue the simulator run and handle exit -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64016?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie2ab3fdddca5f3978d98191e5c08504561587fbb Gerrit-Change-Number: 64016 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Update TestBoard to work with Simulator
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64017?usp=email )
Change subject: stdlib: Update TestBoard to work with Simulator
..
stdlib: Update TestBoard to work with Simulator
This change makes minor updates to the TestBoard so that it can work
nicely with the Simulator module.
This change also makes the cache hierarchy optional for the TestBoard.
Change-Id: If46d53779164e87b6fc06176355be6b4ae05aa99
Signed-off-by: Jason Lowe-Power
---
M src/python/gem5/components/boards/test_board.py
M src/python/gem5/components/processors/abstract_generator.py
M src/python/gem5/simulate/exit_event.py
3 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/src/python/gem5/components/boards/test_board.py
b/src/python/gem5/components/boards/test_board.py
index 7267f2a..eca8c61 100644
--- a/src/python/gem5/components/boards/test_board.py
+++ b/src/python/gem5/components/boards/test_board.py
@@ -26,15 +26,15 @@
from m5.objects import Port, IOXBar, AddrRange
-from .mem_mode import MemMode, mem_mode_to_string
from ...utils.override import overrides
+from .abstract_board import AbstractBoard
from .abstract_system_board import AbstractSystemBoard
-from ..processors.abstract_processor import AbstractProcessor
+from ..processors.abstract_generator import AbstractGenerator
from ..memory.abstract_memory_system import AbstractMemorySystem
from ..cachehierarchies.abstract_cache_hierarchy import
AbstractCacheHierarchy
-from typing import List
+from typing import List, Optional
class TestBoard(AbstractSystemBoard):
@@ -43,21 +43,24 @@
architecture.
To work as a traffic generator board, pass a generator as a processor.
+
+This board does not require a cache hierarchy (it can be none) in which
+case the processor (generator) will be directly connected to the
memory.
"""
def __init__(
self,
-clk_freq: str,
-processor: AbstractProcessor,
+generator: AbstractGenerator,
memory: AbstractMemorySystem,
-cache_hierarchy: AbstractCacheHierarchy,
+cache_hierarchy: Optional[AbstractCacheHierarchy],
):
super().__init__(
-clk_freq=clk_freq,
-processor=processor,
+clk_freq="1GHz", # Clock frequency is ignored
+processor=generator,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
+self._set_fullsystem(False)
@overrides(AbstractSystemBoard)
def _setup_board(self) -> None:
@@ -108,3 +111,16 @@
@overrides(AbstractSystemBoard)
def has_dma_ports(self) -> bool:
return False
+
+@overrides(AbstractBoard)
+def _connect_things(self) -> None:
+super()._connect_things()
+
+if not self.get_cache_hierarchy():
+# If we have no caches, then there must be a one-to-one
+# connection between the generators and the memories.
+assert len(self.get_processor().get_cores()) == 1
+assert len(self.get_memory().get_mem_ports()) == 1
+self.get_processor().get_cores()[
+0
+].generator.port = self.get_memory().get_mem_ports()[0][1]
diff --git a/src/python/gem5/components/processors/abstract_generator.py
b/src/python/gem5/components/processors/abstract_generator.py
index 41cbf5c..ff5387d 100644
--- a/src/python/gem5/components/processors/abstract_generator.py
+++ b/src/python/gem5/components/processors/abstract_generator.py
@@ -65,3 +65,6 @@
this method needs to be implemented in detail or implmeneted as
pass.
"""
raise NotImplementedError
+
+def _post_instantiate(self) -> None:
+self.start_traffic()
diff --git a/src/python/gem5/simulate/exit_event.py
b/src/python/gem5/simulate/exit_event.py
index 691e41a..29d434c 100644
--- a/src/python/gem5/simulate/exit_event.py
+++ b/src/python/gem5/simulate/exit_event.py
@@ -87,6 +87,9 @@
return ExitEvent.SIMPOINT_BEGIN
elif exit_string == "a thread reached the max instruction count":
return ExitEvent.MAX_INSTS
+elif exit_string.endswith("will terminate the simulation.\n"):
+# This is for the traffic generator exit event
+return ExitEvent.EXIT
raise NotImplementedError(
"Exit event '{}' not implemented".format(exit_string)
)
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Allow cache_hierarchy to be optional
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/64015?usp=email ) Change subject: stdlib: Allow cache_hierarchy to be optional .. stdlib: Allow cache_hierarchy to be optional This changeset makes the cache_hierarchy optional on the board. This will allow us to enable the TestBoard to have memory directly connected to the traffic generator. Change-Id: I62d310e74c43724ea38e3b71a4d91d9e06d6e855 Signed-off-by: Jason Lowe-Power --- M src/python/gem5/components/boards/abstract_board.py 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/src/python/gem5/components/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py index e480190..1ac31cb 100644 --- a/src/python/gem5/components/boards/abstract_board.py +++ b/src/python/gem5/components/boards/abstract_board.py @@ -39,7 +39,7 @@ VoltageDomain, ) -from typing import List +from typing import List, Optional class AbstractBoard: @@ -68,13 +68,15 @@ clk_freq: str, processor: "AbstractProcessor", memory: "AbstractMemorySystem", -cache_hierarchy: "AbstractCacheHierarchy", +cache_hierarchy: Optional["AbstractCacheHierarchy"], ) -> None: """ :param clk_freq: The clock frequency for this board. :param processor: The processor for this board. :param memory: The memory for this board. -:param cache_hierarchy: The Cachie Hierarchy for this board. +:param cache_hierarchy: The Cache Hierarchy for this board. +In some boards caches can be optional. If so, +that board must override `_connect_things`. """ if not isinstance(self, System): @@ -88,7 +90,9 @@ # Set the processor, memory, and cache hierarchy. self.processor = processor self.memory = memory -self.cache_hierarchy = cache_hierarchy +self._cache_hierarchy = cache_hierarchy +if cache_hierarchy is not None: +self.cache_hierarchy = cache_hierarchy # This variable determines whether the board is to be executed in # full-system or syscall-emulation mode. This is set when the workload @@ -124,7 +128,7 @@ :returns: The cache hierarchy. """ -return self.cache_hierarchy +return self._cache_hierarchy def get_cache_line_size(self) -> int: """Get the size of the cache line. @@ -329,7 +333,8 @@ self.get_memory().incorporate_memory(self) # Incorporate the cache hierarchy for the motherboard. -self.get_cache_hierarchy().incorporate_cache(self) +if self.get_cache_hierarchy(): +self.get_cache_hierarchy().incorporate_cache(self) # Incorporate the processor into the motherboard. self.get_processor().incorporate_processor(self) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/64015?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I62d310e74c43724ea38e3b71a4d91d9e06d6e855 Gerrit-Change-Number: 64015 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib, configs: Add example FS script for RISCV Matched
Kunal Pai has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64014?usp=email )
Change subject: stdlib, configs: Add example FS script for RISCV Matched
..
stdlib, configs: Add example FS script for RISCV Matched
This script loads riscv-bootloader-vmlinux-5.10 onto a
riscv-ubuntu-20.04-img disk image on the RISCVMatched
prebuilt board found at
src/python/gem5/prebuilt/riscvmatched directory.
Change-Id: Ic2b4b19bac0a66d40d667b82a43c7791ff918847
---
A configs/example/gem5_library/riscvmatched-fs.py
1 file changed, 85 insertions(+), 0 deletions(-)
diff --git a/configs/example/gem5_library/riscvmatched-fs.py
b/configs/example/gem5_library/riscvmatched-fs.py
new file mode 100644
index 000..12764b4
--- /dev/null
+++ b/configs/example/gem5_library/riscvmatched-fs.py
@@ -0,0 +1,71 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This gem5 configuration script runs a full system Ubuntu image, Linux
+kernel and calls m5 exit after the kernel is loaded.
+
+Usage
+---
+
+```
+scons build/RISCV/gem5.opt
+
+./build/RISCV/gem5.opt \
+configs/example/gem5_library/riscvmatched-fs.py
+```
+"""
+
+from python.gem5.prebuilt.riscvmatched.riscvmatched_board import (
+RISCVMatchedBoard,
+)
+from gem5.utils.requires import requires
+from gem5.isas import ISA
+from gem5.simulate.simulator import Simulator
+from gem5.resources.workload import Workload
+from gem5.resources.resource import Resource
+
+requires(isa_required=ISA.RISCV)
+
+# instantiate the riscv matched board with default parameters
+board = RISCVMatchedBoard(
+clk_freq="1.2GHz",
+l2_size="2MB",
+is_fs=True,
+)
+
+# Here we a full system workload: "riscv-ubuntu-20.04-boot" which boots
+# Ubuntu 20.04. Once the system successfully boots it encounters an
`m5_exit`
+# instruction which stops the simulation. When the simulation has ended
you may
+# inspect `m5out/system.pc.com_1.device` to see the stdout.
+board.set_kernel_disk_workload(
+kernel=Resource("riscv-bootloader-vmlinux-5.10"),
+disk_image=Resource("riscv-ubuntu-20.04-img"),
+kernel_args = board.get_default_kernel_args(),
+)
+
+simulator = Simulator(board=board)
+simulator.run()
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Edit RiscvMatched RTC
Kunal Pai has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64013?usp=email )
Change subject: stdlib: Edit RiscvMatched RTC
..
stdlib: Edit RiscvMatched RTC
Fixed the bug that made FS mode break.
Changed RTC value as fix.
Change-Id: I0effa1ecd32a8a8845e619d940f8e0efe549cfc1
---
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
index 986f29e..469010c 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -104,8 +104,6 @@
Details can be found on page 77, section 7.1 of the datasheet.
Datasheet for inbuilt params can be found here:
https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
-
-NOTE: FS Mode does not work yet.
"""
def __init__(
@@ -153,7 +151,7 @@
# Add the RTC
self.platform.rtc = RiscvRTC(
-frequency=Frequency("1MHz")
+frequency=Frequency("100MHz")
) # page 77, section 7.1
self.platform.clint.int_pin = self.platform.rtc.int_pin
--
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Gerrit-Change-Id: I0effa1ecd32a8a8845e619d940f8e0efe549cfc1
Gerrit-Change-Number: 64013
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Gerrit-Owner: Kunal Pai
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix variable not found error
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64012?usp=email )
Change subject: scons: Fix variable not found error
..
scons: Fix variable not found error
Change-Id: I09708fea777a57a35e55409c8997ed0b25de2b46
Signed-off-by: Jason Lowe-Power
---
M site_scons/gem5_scons/__init__.py
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/site_scons/gem5_scons/__init__.py
b/site_scons/gem5_scons/__init__.py
index c958e22..7214876 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -264,7 +264,7 @@
while path_dirs and path_dirs[-1] != "build":
variant_dir = path_dirs.pop()
if not path_dirs:
-error("No non-leaf 'build' dir found on target path.", t)
+error("No non-leaf 'build' dir found on target path.", target)
return os.path.join("/", *path_dirs), variant_dir
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix error in Arm test
Jason Lowe-Power has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63991?usp=email ) Change subject: tests: Fix error in Arm test .. tests: Fix error in Arm test I missed this one in the last changeset. Change-Id: I71d7fa2ac4ff36d4aef5d950e6ed8973ffc32a4e Signed-off-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63991 Maintainer: Giacomo Travaglini Reviewed-by: Melissa Jost Tested-by: kokoro Maintainer: Jason Lowe-Power --- M tests/gem5/configs/realview64-switcheroo-full.py 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: Melissa Jost: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved Giacomo Travaglini: Looks good to me, approved kokoro: Regressions pass diff --git a/tests/gem5/configs/realview64-switcheroo-full.py b/tests/gem5/configs/realview64-switcheroo-full.py index abc96f9..0209578 100644 --- a/tests/gem5/configs/realview64-switcheroo-full.py +++ b/tests/gem5/configs/realview64-switcheroo-full.py @@ -43,7 +43,7 @@ ArmAtomicSimpleCPU, ArmTimingSimpleCPU, ArmMinorCPU, -ArmDerivO3CPU, +ArmO3CPU, ), ).create_root() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63991?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I71d7fa2ac4ff36d4aef5d950e6ed8973ffc32a4e Gerrit-Change-Number: 63991 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Lowe-Power Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Melissa Jost Gerrit-Reviewer: Melissa Jost Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix error in Arm test
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63991?usp=email ) Change subject: tests: Fix error in Arm test .. tests: Fix error in Arm test I missed this one in the last changeset. Change-Id: I71d7fa2ac4ff36d4aef5d950e6ed8973ffc32a4e Signed-off-by: Jason Lowe-Power --- M tests/gem5/configs/realview64-switcheroo-full.py 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/tests/gem5/configs/realview64-switcheroo-full.py b/tests/gem5/configs/realview64-switcheroo-full.py index abc96f9..0209578 100644 --- a/tests/gem5/configs/realview64-switcheroo-full.py +++ b/tests/gem5/configs/realview64-switcheroo-full.py @@ -43,7 +43,7 @@ ArmAtomicSimpleCPU, ArmTimingSimpleCPU, ArmMinorCPU, -ArmDerivO3CPU, +ArmO3CPU, ), ).create_root() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63991?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I71d7fa2ac4ff36d4aef5d950e6ed8973ffc32a4e Gerrit-Change-Number: 63991 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: configs, gpu-compute: Add configurable L1 access latencies
VISHNU RAMADAS has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63971?usp=email ) Change subject: configs, gpu-compute: Add configurable L1 access latencies .. configs, gpu-compute: Add configurable L1 access latencies Previously the L1 request and response latencies were not configurable in the GPU config scripts. As a result, the simulations used the default values from GPU.py. This commits adds support to change this value as an input parameter. The parameters to use are "--mem_req_latency" followed by the value and "--mem_resp_latency" followed by the value. The default values are the same as those in GPU.py (which is 50). Change-Id: I812d77758ea12530899953f308c91f4c8b05866d --- M configs/example/apu_se.py 1 file changed, 30 insertions(+), 0 deletions(-) diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py index 16e3365..d1a9ec3 100644 --- a/configs/example/apu_se.py +++ b/configs/example/apu_se.py @@ -264,6 +264,18 @@ help="Latency while accessing shared memory", ) parser.add_argument( +"--mem_req_latency", +type=int, +default=50, +help="Latency for requests from the cu to ruby.", +) +parser.add_argument( +"--mem_resp_latency", +type=int, +default=50, +help="Latency for responses from ruby to the cu.", +) +parser.add_argument( "--TLB-prefetch", type=int, help="prefetch depth for" "TLBs" ) parser.add_argument( @@ -449,6 +461,8 @@ countPages=args.countPages, max_cu_tokens=args.max_cu_tokens, vrf_lm_bus_latency=args.vrf_lm_bus_latency, +mem_req_latency=args.mem_req_latency, +mem_resp_latency=args.mem_resp_latency, localDataStore=LdsState( banks=args.numLdsBanks, bankConflictPenalty=args.ldsBankConflictPenalty, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63971?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I812d77758ea12530899953f308c91f4c8b05866d Gerrit-Change-Number: 63971 Gerrit-PatchSet: 1 Gerrit-Owner: VISHNU RAMADAS Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Remove cached copy of device memory
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/63951?usp=email )
Change subject: dev-amdgpu: Remove cached copy of device memory
..
dev-amdgpu: Remove cached copy of device memory
This map was originally used for fast access to the GART table. It is no
longer needed as the table has been moved to the AMDGPUVM class. Along
with commit 12ec5f9172301a121a949c622a03a839b0e45d4e which reads
functionally from device memory, this table is no longer needed and is
essentially a duplicate copy of device memory for anything written over
the PCI BAR.
This changeset removes the map entirely which will reduce the memory
footprint of simulations and potentially avoid stale copies of data
when reading over the PCI BAR.
Change-Id: I312ae38f869c6a65e50577b1c33dd055078aaf32
---
M src/dev/amdgpu/amdgpu_device.cc
M src/dev/amdgpu/amdgpu_device.hh
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/src/dev/amdgpu/amdgpu_device.cc
b/src/dev/amdgpu/amdgpu_device.cc
index 09e46a5..227e69e 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -182,9 +182,8 @@
/*
* Return data for frame reads in priority order: (1) Special addresses
- * first, ignoring any writes from driver. (2) GART addresses written
- * to frame_regs in writeFrame. (3) Any other address from device
backing
- * store / abstract memory class functionally.
+ * first, ignoring any writes from driver. (2) Any other address from
+ * device backing store / abstract memory class functionally.
*/
if (offset == 0xa28000) {
/*
@@ -198,9 +197,6 @@
}
pkt->setUintX(regs[pkt->getAddr()], ByteOrder::little);
-} else if (frame_regs.find(offset) != frame_regs.end()) {
-/* If the driver wrote something, use that value over the trace. */
-pkt->setUintX(frame_regs[offset], ByteOrder::little);
} else {
/*
* Read the value from device memory. This must be done
functionally
@@ -273,12 +269,10 @@
Addr aperture_offset = offset - aperture;
// Record the value
-frame_regs[offset] = pkt->getUintX(ByteOrder::little);
if (aperture == gpuvm.gartBase()) {
-frame_regs[aperture_offset] = pkt->getLE();
-DPRINTF(AMDGPUDevice, "GART translation %p -> %p\n",
aperture_offset,
-bits(frame_regs[aperture_offset], 48, 12));
gpuvm.gartTable[aperture_offset] = pkt->getLE();
+DPRINTF(AMDGPUDevice, "GART translation %p -> %p\n",
aperture_offset,
+gpuvm.gartTable[aperture_offset]);
}
}
diff --git a/src/dev/amdgpu/amdgpu_device.hh
b/src/dev/amdgpu/amdgpu_device.hh
index fbb0d1c..ac31b95 100644
--- a/src/dev/amdgpu/amdgpu_device.hh
+++ b/src/dev/amdgpu/amdgpu_device.hh
@@ -85,7 +85,6 @@
* Structures to hold registers, doorbells, and some frame memory
*/
using GPURegMap = std::unordered_map;
-GPURegMap frame_regs;
GPURegMap regs;
std::unordered_map doorbells;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I312ae38f869c6a65e50577b1c33dd055078aaf32
Gerrit-Change-Number: 63951
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem-garnet: Add masked functionalRead support
;
uint32_t functionalWrite(Packet *);
private:
diff --git a/src/mem/ruby/network/garnet/VirtualChannel.cc
b/src/mem/ruby/network/garnet/VirtualChannel.cc
index a473bca..18e89a0 100644
--- a/src/mem/ruby/network/garnet/VirtualChannel.cc
+++ b/src/mem/ruby/network/garnet/VirtualChannel.cc
@@ -75,6 +75,12 @@
return false;
}
+bool
+VirtualChannel::functionalRead(Packet *pkt, WriteMask )
+{
+return inputBuffer.functionalRead(pkt, mask);
+}
+
uint32_t
VirtualChannel::functionalWrite(Packet *pkt)
{
diff --git a/src/mem/ruby/network/garnet/VirtualChannel.hh
b/src/mem/ruby/network/garnet/VirtualChannel.hh
index 29f3698..04b046b 100644
--- a/src/mem/ruby/network/garnet/VirtualChannel.hh
+++ b/src/mem/ruby/network/garnet/VirtualChannel.hh
@@ -95,6 +95,7 @@
return inputBuffer.getTopFlit();
}
+bool functionalRead(Packet *pkt, WriteMask );
uint32_t functionalWrite(Packet *pkt);
private:
diff --git a/src/mem/ruby/network/garnet/flit.cc
b/src/mem/ruby/network/garnet/flit.cc
index b65297c..d31d826 100644
--- a/src/mem/ruby/network/garnet/flit.cc
+++ b/src/mem/ruby/network/garnet/flit.cc
@@ -126,6 +126,13 @@
}
bool
+flit::functionalRead(Packet *pkt, WriteMask )
+{
+Message *msg = m_msg_ptr.get();
+return msg->functionalRead(pkt, mask);
+}
+
+bool
flit::functionalWrite(Packet *pkt)
{
Message *msg = m_msg_ptr.get();
diff --git a/src/mem/ruby/network/garnet/flit.hh
b/src/mem/ruby/network/garnet/flit.hh
index a84dc57..a52d741 100644
--- a/src/mem/ruby/network/garnet/flit.hh
+++ b/src/mem/ruby/network/garnet/flit.hh
@@ -107,6 +107,7 @@
}
}
+bool functionalRead(Packet *pkt, WriteMask );
bool functionalWrite(Packet *pkt);
virtual flit* serialize(int ser_id, int parts, uint32_t bWidth);
diff --git a/src/mem/ruby/network/garnet/flitBuffer.cc
b/src/mem/ruby/network/garnet/flitBuffer.cc
index b6a2e0a..6b3b56c 100644
--- a/src/mem/ruby/network/garnet/flitBuffer.cc
+++ b/src/mem/ruby/network/garnet/flitBuffer.cc
@@ -85,6 +85,19 @@
max_size = maximum;
}
+bool
+flitBuffer::functionalRead(Packet *pkt, WriteMask )
+{
+bool read = false;
+for (unsigned int i = 0; i < m_buffer.size(); ++i) {
+if (m_buffer[i]->functionalRead(pkt, mask)) {
+read = true;
+}
+}
+
+return read;
+}
+
uint32_t
flitBuffer::functionalWrite(Packet *pkt)
{
diff --git a/src/mem/ruby/network/garnet/flitBuffer.hh
b/src/mem/ruby/network/garnet/flitBuffer.hh
index d37f9a5..089c931 100644
--- a/src/mem/ruby/network/garnet/flitBuffer.hh
+++ b/src/mem/ruby/network/garnet/flitBuffer.hh
@@ -80,6 +80,7 @@
m_buffer.push_back(flt);
}
+bool functionalRead(Packet *pkt, WriteMask );
uint32_t functionalWrite(Packet *pkt);
private:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idd571899d679407b7b000c1a83a0a5420868cf28
Gerrit-Change-Number: 46900
Gerrit-PatchSet: 3
Gerrit-Owner: Carlos Falquez
Gerrit-Reviewer: Carlos Falquez
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Srikant Bharadwaj
Gerrit-Reviewer: Tiago Muck
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: tests: Add Simpoints example scripts as tests
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/63931?usp=email )
Change subject: tests: Add Simpoints example scripts as tests
..
tests: Add Simpoints example scripts as tests
These both ensure the example scripts still work as intended and provide
tests to ensure the stdlib's Simpoint feature still works as intended.
Change-Id: I549c3d22458a5013a335857c83a4e78dc425e37d
---
M configs/example/gem5_library/checkpoints/simpoints-se-restore.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 55 insertions(+), 6 deletions(-)
diff --git
a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
index 1a1bb05..4d49d9d 100644
--- a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
+++ b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py
@@ -107,12 +107,13 @@
binary=Resource("x86-print-this"), arguments=["print this", 15000]
)
-# configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py has
to
-# run before running this script.
-# In here, it will get the path of the first SimPoint checkpoint taken by
the
-# simpoints-se-checkpoint.py
-dir = Path("se_checkpoint_folder")
-subfolder = [int(str(name).split(".")[1]) for name in dir.iterdir()]
+# Here we obtain the checkpoints from gem5 resources, but these are
generated
+# from
`configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py`.If
+# run prior to this script the `dir = Path("se_checkpoint_folder")` line
may be
+# used. The resource is pulled so we may run this script as a test.
+# dir = Path("se_checkpoint_folder")
+dir = Path(Resource("simpoints-se-checkpoints-v22-1").get_local_path())
+subfolder = [int(str(name).rsplit(".", 1)[1]) for name in dir.iterdir()]
dir = Path(dir / f"cpt.{min(subfolder)}").as_posix()
diff --git
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
index 0acc1ae..ee212ae 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -86,6 +86,42 @@
length=constants.quick_tag,
)
+gem5_verify_config(
+name="test-simpoints-se-checkpoint",
+fixtures=(),
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"configs",
+"example",
+"gem5_library",
+"checkpoints",
+"simpoints-se-checkpoint.py",
+),
+config_args=[],
+valid_isas=(constants.all_compiled_tag,),
+valid_hosts=constants.supported_hosts,
+length=constants.quick_tag,
+)
+
+gem5_verify_config(
+name="test-simpoints-se-restore",
+fixtures=(),
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"configs",
+"example",
+"gem5_library",
+"checkpoints",
+"simpoints-se-restore.py",
+),
+config_args=[],
+valid_isas=(constants.all_compiled_tag,),
+valid_hosts=constants.supported_hosts,
+length=constants.quick_tag,
+)
+
if os.access("/dev/kvm", mode=os.R_OK | os.W_OK):
# The x86-ubuntu-run uses KVM cores, this test will therefore only be
run
# on systems that support KVM.
--
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Gerrit-Change-Id: I549c3d22458a5013a335857c83a4e78dc425e37d
Gerrit-Change-Number: 63931
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Allow TarmacTracer to dump trace to a file
const StaticInstPtr staticInst, const PCStateBase , const StaticInstPtr macroStaticInst=nullptr) override; +std::ostream& output(); + protected: typedef std::unique_ptr PEntryPtr; typedef TarmacTracerRecord::InstPtr InstPtr; typedef TarmacTracerRecord::MemPtr MemPtr; typedef TarmacTracerRecord::RegPtr RegPtr; +OutputStream *outstream; + /** * startTick and endTick allow to trace a specific window of ticks * rather than the entire CPU execution. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63892?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icd2bcc721f8598d494c9efabdf5e092666ebdece Gerrit-Change-Number: 63892 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: configs: fix CHI mem buffers
Tiago Muck has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63673?usp=email ) Change subject: configs: fix CHI mem buffers .. configs: fix CHI mem buffers Disabling randomization for the memory request and response buffers. CHI requires that memory responses for the same address arrive in the same order the request was sent. Change-Id: Ia4236188679beaf2969978675414a870ccd9f94a Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63673 Tested-by: kokoro Maintainer: Bobby Bruce Reviewed-by: Jason Lowe-Power --- M configs/ruby/CHI_config.py M src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py 2 files changed, 42 insertions(+), 4 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass Bobby Bruce: Looks good to me, approved diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py index a95efec..25d4f05 100644 --- a/configs/ruby/CHI_config.py +++ b/configs/ruby/CHI_config.py @@ -183,6 +183,16 @@ ordered = True +class MemCtrlMessageBuffer(MessageBuffer): +""" +MessageBuffer exchanging messages with the memory +These buffers should also not be affected by the Ruby tester randomization. +""" + +randomization = "disabled" +ordered = True + + class CHI_Cache_Controller(Cache_Controller): """ Default parameters for a Cache controller @@ -667,8 +677,8 @@ version=Versions.getVersion(Memory_Controller), ruby_system=ruby_system, triggerQueue=TriggerMessageBuffer(), -responseFromMemory=MessageBuffer(), -requestToMemory=MessageBuffer(ordered=True), +responseFromMemory=MemCtrlMessageBuffer(), +requestToMemory=MemCtrlMessageBuffer(), reqRdy=TriggerMessageBuffer(), transitions_per_cycle=1024, ) diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py index 4d05894..bee5e88 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py @@ -37,6 +37,16 @@ from .abstract_node import TriggerMessageBuffer +class MemCtrlMessageBuffer(MessageBuffer): +""" +MessageBuffer exchanging messages with the memory +These buffers should also not be affected by the Ruby tester randomization. +""" + +randomization = "disabled" +ordered = True + + class MemoryController(Memory_Controller): """A controller that connects to memory""" @@ -62,8 +72,8 @@ def connectQueues(self, network): self.triggerQueue = TriggerMessageBuffer() -self.responseFromMemory = MessageBuffer() -self.requestToMemory = MessageBuffer(ordered=True) +self.responseFromMemory = MemCtrlMessageBuffer() +self.requestToMemory = MemCtrlMessageBuffer() self.reqRdy = TriggerMessageBuffer() self.reqOut = MessageBuffer() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63673?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia4236188679beaf2969978675414a870ccd9f94a Gerrit-Change-Number: 63673 Gerrit-PatchSet: 4 Gerrit-Owner: Tiago Muck Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daecheol You Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Muck Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: configs: set requestToMemory buffer size for CHI
Tiago Muck has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63674?usp=email ) Change subject: configs: set requestToMemory buffer size for CHI .. configs: set requestToMemory buffer size for CHI Currently TBEs for write requests are deallocated when the request is pushed to memory, so an unlimited requestToMemory buffers size allows for an unlimited number of outstanding write requests. Set the requestToMemory buffers size prevents this. The buffer size should be greater than the enqueue latency to allow at least one enqueue per cycle. JIRA: https://gem5.atlassian.net/browse/GEM5-1195 Change-Id: I31829b6bbabd8b45e1142790038c27bd459fa709 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63674 Tested-by: kokoro Maintainer: Bobby Bruce Reviewed-by: Jason Lowe-Power --- M configs/ruby/CHI_config.py M src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py 2 files changed, 38 insertions(+), 0 deletions(-) Approvals: kokoro: Regressions pass Bobby Bruce: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py index 25d4f05..6d2084b 100644 --- a/configs/ruby/CHI_config.py +++ b/configs/ruby/CHI_config.py @@ -683,6 +683,13 @@ transitions_per_cycle=1024, ) +# The Memory_Controller implementation deallocates the TBE for +# write requests when they are queue up to memory. The size of this +# buffer must be limited to prevent unlimited outstanding writes. +self._cntrl.requestToMemory.buffer_size = ( +int(self._cntrl.to_memory_controller_latency) + 1 +) + self.connectController(self._cntrl) if parent: diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py index bee5e88..e7cbafe 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py @@ -76,6 +76,13 @@ self.requestToMemory = MemCtrlMessageBuffer() self.reqRdy = TriggerMessageBuffer() +# The Memory_Controller implementation deallocates the TBE for +# write requests when they are queue up to memory. The size of this +# buffer must be limited to prevent unlimited outstanding writes. +self.requestToMemory.buffer_size = ( +int(self.to_memory_controller_latency) + 1 +) + self.reqOut = MessageBuffer() self.rspOut = MessageBuffer() self.snpOut = MessageBuffer() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63674?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I31829b6bbabd8b45e1142790038c27bd459fa709 Gerrit-Change-Number: 63674 Gerrit-PatchSet: 4 Gerrit-Owner: Tiago Muck Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daecheol You Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Muck Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: configs: fix CustomMesh router parent
Tiago Muck has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63677?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: configs: fix CustomMesh router parent .. configs: fix CustomMesh router parent This fixes the routers being set as the links' children. This is necessary here as we only assign the routers to the network once all routers and links are created. Change-Id: I2ac90b575bad593ddbb8ab716872a30a5c4c6979 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63677 Maintainer: Bobby Bruce Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M configs/topologies/CustomMesh.py 1 file changed, 23 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass Bobby Bruce: Looks good to me, approved diff --git a/configs/topologies/CustomMesh.py b/configs/topologies/CustomMesh.py index 545ba4b..088e4b9 100644 --- a/configs/topologies/CustomMesh.py +++ b/configs/topologies/CustomMesh.py @@ -1,4 +1,4 @@ -# Copyright (c) 2021 ARM Limited +# Copyright (c) 2021,2022 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -372,6 +372,10 @@ # Set up network.int_links = self._int_links network.ext_links = self._ext_links +# fix Routers being set as link child +for r in self._routers: +if r.has_parent(): +r.get_parent().clear_child(r.get_name()) network.routers = self._routers pairing = getattr(options, "pairing", None) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63677?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2ac90b575bad593ddbb8ab716872a30a5c4c6979 Gerrit-Change-Number: 63677 Gerrit-PatchSet: 4 Gerrit-Owner: Tiago Muck Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daecheol You Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Muck Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: fix CHI memory controller
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63675?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: fix CHI memory controller
..
mem-ruby: fix CHI memory controller
Break up the transition to READING_MEM into two separate steps so
contention at the requestToMemory queue won't block the TBE
initialization.
JIRA: https://gem5.atlassian.net/browse/GEM5-1195
Change-Id: Ifa0ee589bde67eb30e7c0b315ff41f22b61e8db7
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63675
Reviewed-by: Jason Lowe-Power
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/chi/CHI-mem.sm
1 file changed, 37 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/chi/CHI-mem.sm
b/src/mem/ruby/protocol/chi/CHI-mem.sm
index d7a50fd..c47d20f 100644
--- a/src/mem/ruby/protocol/chi/CHI-mem.sm
+++ b/src/mem/ruby/protocol/chi/CHI-mem.sm
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 ARM Limited
+ * Copyright (c) 2021,2022 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -119,6 +119,7 @@
Trigger_ReceiveDone, desc="";
Trigger_SendRetry, desc="";
Trigger_SendPCrdGrant, desc="";
+Trigger_SendMemoryRead, desc="";
}
@@ -551,6 +552,14 @@
}
}
+ action(triggerSendMemoryRead, "tsmr", desc="Trigger sendMemoryRead") {
+assert(is_valid(tbe));
+enqueue(triggerOutPort, TriggerMsg, 0) {
+ out_msg.addr := address;
+ out_msg.event := Event:Trigger_SendMemoryRead;
+}
+ }
+
action(sendMemoryRead, "smr", desc="Send request to memory") {
assert(is_valid(tbe));
enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
@@ -698,18 +707,23 @@
transition(READY, ReadNoSnp, READING_MEM) {
allocateTBE;
initializeFromReqTBE;
-sendMemoryRead;
+triggerSendMemoryRead;
popReqInQueue;
}
transition(READY, ReadNoSnpSep, READING_MEM) {
allocateTBE;
initializeFromReqTBE;
-sendMemoryRead;
+triggerSendMemoryRead;
sendReadReceipt;
popReqInQueue;
}
+ transition(READING_MEM, Trigger_SendMemoryRead) {
+sendMemoryRead;
+popTriggerQueue;
+ }
+
transition(READING_MEM, MemoryData, SENDING_NET_DATA) {
prepareSend;
sendDataAndCheck;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifa0ee589bde67eb30e7c0b315ff41f22b61e8db7
Gerrit-Change-Number: 63675
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Muck
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daecheol You
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Muck
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: fix CHI config for Garnet
Tiago Muck has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63811?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: configs: fix CHI config for Garnet .. configs: fix CHI config for Garnet CHI.py was not working with Garnet as ruby_system.network.buffer_size only exists in SimpleNetwork. Change-Id: I00e952f8881d385e3591c149e08c9c7a53fda2cd Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63811 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M configs/ruby/CHI.py 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/ruby/CHI.py b/configs/ruby/CHI.py index d31d233..df97b92 100644 --- a/configs/ruby/CHI.py +++ b/configs/ruby/CHI.py @@ -266,7 +266,8 @@ ruby_system.network.control_msg_size = params.cntrl_msg_size ruby_system.network.data_msg_size = params.data_width -ruby_system.network.buffer_size = params.router_buffer_size +if options.network == "simple": +ruby_system.network.buffer_size = params.router_buffer_size # Incorporate the params into options so it's propagated to # makeTopology and create_topology the parent scripts -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63811?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I00e952f8881d385e3591c149e08c9c7a53fda2cd Gerrit-Change-Number: 63811 Gerrit-PatchSet: 3 Gerrit-Owner: Tiago Muck Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Muck Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: fix missing transition in CHI-mem
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63676?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: fix missing transition in CHI-mem
..
mem-ruby: fix missing transition in CHI-mem
JIRA: https://gem5.atlassian.net/browse/GEM5-1195
Change-Id: I0aae4b9042cb6565c77cc8781b514a9e65ab161b
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63676
Reviewed-by: Jason Lowe-Power
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/chi/CHI-mem.sm
1 file changed, 17 insertions(+), 1 deletion(-)
Approvals:
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
diff --git a/src/mem/ruby/protocol/chi/CHI-mem.sm
b/src/mem/ruby/protocol/chi/CHI-mem.sm
index c47d20f..820f2df 100644
--- a/src/mem/ruby/protocol/chi/CHI-mem.sm
+++ b/src/mem/ruby/protocol/chi/CHI-mem.sm
@@ -777,7 +777,7 @@
// Notice we only use this here and call wakeUp when leaving this state
transition({READING_MEM,WAITING_NET_DATA,SENDING_NET_DATA},
- {ReadNoSnp, ReadNoSnpSep, WriteNoSnpPtl}) {
+ {ReadNoSnp, ReadNoSnpSep, WriteNoSnpPtl, WriteNoSnp}) {
stallRequestQueue;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0aae4b9042cb6565c77cc8781b514a9e65ab161b
Gerrit-Change-Number: 63676
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Muck
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daecheol You
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Muck
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: CHI inc transitions_per_cycle
Tiago Muck has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63672?usp=email ) Change subject: configs: CHI inc transitions_per_cycle .. configs: CHI inc transitions_per_cycle Previous limit may unintentionally throttle performance for controllers with a large TBE table and high traffic. Change-Id: I34d6f8727519b259bb3d4a80b1fff6c59197c508 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63672 Maintainer: Bobby Bruce Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M configs/ruby/CHI_config.py M src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py 2 files changed, 21 insertions(+), 3 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Bobby Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py index 98f08c3..a95efec 100644 --- a/configs/ruby/CHI_config.py +++ b/configs/ruby/CHI_config.py @@ -1,4 +1,4 @@ -# Copyright (c) 2021 ARM Limited +# Copyright (c) 2021,2022 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -206,7 +206,7 @@ # triggers. To limit the controller performance, tweak other # params such as: input port buffer size, cache banks, and output # port latency -self.transitions_per_cycle = 128 +self.transitions_per_cycle = 1024 # This should be set to true in the data cache controller to enable # timeouts on unique lines when a store conditional fails self.sc_lock_enabled = False @@ -670,6 +670,7 @@ responseFromMemory=MessageBuffer(), requestToMemory=MessageBuffer(ordered=True), reqRdy=TriggerMessageBuffer(), +transitions_per_cycle=1024, ) self.connectController(self._cntrl) diff --git a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py index d2bde12..9853174 100644 --- a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py +++ b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py @@ -77,7 +77,7 @@ # triggers. To limit the controller performance, tweak other # params such as: input port buffer size, cache banks, and output # port latency -self.transitions_per_cycle = 128 +self.transitions_per_cycle = 1024 # This should be set to true in the data cache controller to enable # timeouts on unique lines when a store conditional fails self.sc_lock_enabled = False -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63672?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I34d6f8727519b259bb3d4a80b1fff6c59197c508 Gerrit-Change-Number: 63672 Gerrit-PatchSet: 4 Gerrit-Owner: Tiago Muck Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daecheol You Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Muck Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: configs,gpu-compute: Add configurable LDS bus latency
VISHNU RAMADAS has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63652?usp=email ) Change subject: configs,gpu-compute: Add configurable LDS bus latency .. configs,gpu-compute: Add configurable LDS bus latency Previously the LDS bus latency was not configurable in the GPU config scripts. As a result, the simulations would use the default value from GPU.py. This commit adds support to change this value as an input option. The option to use is "--vrf_lm_bus_latency". Change-Id: I8d8852e6d7b9d03ebec1fe8b392968f396dd3526 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63652 Maintainer: Matthew Poremba Tested-by: kokoro Reviewed-by: Matt Sinclair --- M configs/example/apu_se.py 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: Matthew Poremba: Looks good to me, approved Matt Sinclair: Looks good to me, approved kokoro: Regressions pass diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py index 1a649d3..16e3365 100644 --- a/configs/example/apu_se.py +++ b/configs/example/apu_se.py @@ -258,6 +258,12 @@ help="Number of coalescer tokens per CU", ) parser.add_argument( +"--vrf_lm_bus_latency", +type=int, +default=1, +help="Latency while accessing shared memory", +) +parser.add_argument( "--TLB-prefetch", type=int, help="prefetch depth for" "TLBs" ) parser.add_argument( @@ -442,6 +448,7 @@ localMemBarrier=args.LocalMemBarrier, countPages=args.countPages, max_cu_tokens=args.max_cu_tokens, +vrf_lm_bus_latency=args.vrf_lm_bus_latency, localDataStore=LdsState( banks=args.numLdsBanks, bankConflictPenalty=args.ldsBankConflictPenalty, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63652?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8d8852e6d7b9d03ebec1fe8b392968f396dd3526 Gerrit-Change-Number: 63652 Gerrit-PatchSet: 5 Gerrit-Owner: VISHNU RAMADAS Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matt Sinclair Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: VISHNU RAMADAS Gerrit-Reviewer: kokoro Gerrit-CC: Jason Lowe-Power Gerrit-CC: Matt Sinclair Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Move the arm+ruby tests to not use ALL
Jason Lowe-Power has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63852?usp=email ) Change subject: tests: Move the arm+ruby tests to not use ALL .. tests: Move the arm+ruby tests to not use ALL The main Ruby.py script does not support the ALL target (it still depends on get_runtime_isa). So, instead of testing these with the all target, move them to be tested with just Arm built. Change-Id: I7942177fffd2bbfb0696b67c1e94e2ec30d8178b Signed-off-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63852 Tested-by: kokoro Maintainer: Jason Lowe-Power Reviewed-by: Bobby Bruce --- M tests/gem5/fs/linux/arm/test.py 1 file changed, 43 insertions(+), 4 deletions(-) Approvals: Bobby Bruce: Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/tests/gem5/fs/linux/arm/test.py b/tests/gem5/fs/linux/arm/test.py index dff2e74..8700247 100644 --- a/tests/gem5/fs/linux/arm/test.py +++ b/tests/gem5/fs/linux/arm/test.py @@ -73,10 +73,6 @@ "realview64-minor-dual", "realview64-switcheroo-o3", "realview64-switcheroo-full", -"realview-simple-timing-ruby", -"realview64-simple-timing-ruby", -"realview64-simple-timing-dual-ruby", -"realview64-o3-dual-ruby", # The following tests fail. These are recorded in the GEM5-640 # Jira issue. # @@ -88,6 +84,14 @@ #'realview-simple-timing-dual-ruby', ] +# These tests are Ruby-based and Ruby does not support multiple ISAs +arm_fs_long_tests_arm_target = [ +"realview-simple-timing-ruby", +"realview64-simple-timing-ruby", +"realview64-simple-timing-dual-ruby", +"realview64-o3-dual-ruby", +] + tarball = "aarch-system-20220707.tar.bz2" url = config.resource_url + "/arm/" + tarball filepath = os.path.dirname(os.path.abspath(__file__)) @@ -157,3 +161,20 @@ fixtures=(arm_fs_binaries,), uses_kvm=name in arm_fs_kvm_tests, ) + +for name in arm_fs_long_tests_arm_target: +args = [ +joinpath(config.base_dir, "tests", "gem5", "configs", name + ".py"), +path, +config.base_dir, +] +gem5_verify_config( +name=name, +verifiers=verifier_list(name), # TODO: Add basic stat verifiers +config=joinpath(filepath, "run.py"), +config_args=args, +valid_isas=(constants.arm_tag,), +length=constants.long_tag, +fixtures=(arm_fs_binaries,), +uses_kvm=name in arm_fs_kvm_tests, +) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63852?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7942177fffd2bbfb0696b67c1e94e2ec30d8178b Gerrit-Change-Number: 63852 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Lowe-Power Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: mem-ruby: fix downstream destinations
visit https://gem5-review.googlesource.com/c/public/gem5/+/63671?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Idd0184da343c46c92a4c86f142938902096c2b1f Gerrit-Change-Number: 63671 Gerrit-PatchSet: 3 Gerrit-Owner: Tiago Muck Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daecheol You Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Muck Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: Fix -Wunused-variable with structured binding
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63831?usp=email ) Change subject: systemc: Fix -Wunused-variable with structured binding .. systemc: Fix -Wunused-variable with structured binding Change-Id: Ied66047c53dfc674557aeaf74fbba04c2b3d8359 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63831 Reviewed-by: Yu-hsin Wang Tested-by: kokoro Maintainer: Jason Lowe-Power --- M src/systemc/tlm_bridge/tlm_to_gem5.cc 1 file changed, 16 insertions(+), 1 deletion(-) Approvals: kokoro: Regressions pass Yu-hsin Wang: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc b/src/systemc/tlm_bridge/tlm_to_gem5.cc index c3313da..84907be 100644 --- a/src/systemc/tlm_bridge/tlm_to_gem5.cc +++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc @@ -218,7 +218,8 @@ trans.acquire(); -auto [pkt, pkt_created] = payload2packet(_id, trans); +auto res = payload2packet(_id, trans); +auto pkt = res.first; pkt->pushSenderState(new Gem5SystemC::TlmSenderState(trans)); // If the packet doesn't need a response, we should send BEGIN_RESP by -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63831?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ied66047c53dfc674557aeaf74fbba04c2b3d8359 Gerrit-Change-Number: 63831 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: fix flexible conversion when reusing transactions
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/63871?usp=email )
Change subject: systemc: fix flexible conversion when reusing transactions
..
systemc: fix flexible conversion when reusing transactions
To make the all extension states correct, we still need to proceed the
plugins when reusing the transactions, since we don't know the detail of
the plugins.
Change-Id: I18acd64f54be4c82a0678b98e834ea9548de1f58
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/tlm_to_gem5.cc
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index 6f17a8b..8d0e39d 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -140,6 +140,10 @@
trans = >trans;
trans->set_address(packet->getAddr());
trans->acquire();
+// Apply all conversion steps necessary in this specific setup.
+for (auto : extraPacketToPayloadSteps) {
+step(packet, *trans);
+}
return trans;
}
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc
b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index c3313da..631f542 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -117,6 +117,10 @@
auto pkt = extension->getPacket();
// Sync the address which could have changed.
pkt->setAddr(trans.get_address());
+// Apply all conversion steps necessary in this specific setup.
+for (auto : extraPayloadToPacketSteps) {
+step(pkt, trans);
+}
return std::make_pair(pkt, false);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I18acd64f54be4c82a0678b98e834ea9548de1f58
Gerrit-Change-Number: 63871
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix errors in arm switcheroo
Jason Lowe-Power has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63851?usp=email ) Change subject: tests: Fix errors in arm switcheroo .. tests: Fix errors in arm switcheroo When switching to the all target, there is no longer a "DerivO3CPU" we now need to drop the "Deriv" Note that there are still some cases where it is valid to use "DerivO3" where it is converted to drop the "Deriv" via a map. Cleaning this up further is for future work. Change-Id: Ide59eb3a5c7daf15c13afe395409f588562c1b54 Signed-off-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63851 Maintainer: Jason Lowe-Power Tested-by: kokoro Maintainer: Giacomo Travaglini Reviewed-by: Giacomo Travaglini --- M tests/gem5/configs/realview-switcheroo-o3.py M tests/gem5/configs/realview64-switcheroo-o3.py 2 files changed, 25 insertions(+), 2 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved diff --git a/tests/gem5/configs/realview-switcheroo-o3.py b/tests/gem5/configs/realview-switcheroo-o3.py index fe3298f..4fca57e 100644 --- a/tests/gem5/configs/realview-switcheroo-o3.py +++ b/tests/gem5/configs/realview-switcheroo-o3.py @@ -41,7 +41,7 @@ aarch64_kernel=False, machine_type="VExpress_GEM5_V1", mem_class=DDR3_1600_8x8, -cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU), +cpu_classes=(ArmO3CPU, ArmO3CPU), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview64-switcheroo-o3.py b/tests/gem5/configs/realview64-switcheroo-o3.py index ddfc73a..f899337 100644 --- a/tests/gem5/configs/realview64-switcheroo-o3.py +++ b/tests/gem5/configs/realview64-switcheroo-o3.py @@ -38,7 +38,7 @@ import switcheroo root = LinuxArmFSSwitcheroo( -mem_class=DDR3_1600_8x8, cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU) +mem_class=DDR3_1600_8x8, cpu_classes=(ArmO3CPU, ArmO3CPU) ).create_root() # Setup a custom test method that uses the switcheroo tester that -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63851?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ide59eb3a5c7daf15c13afe395409f588562c1b54 Gerrit-Change-Number: 63851 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Lowe-Power Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Move the arm+ruby tests to not use ALL
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63852?usp=email ) Change subject: tests: Move the arm+ruby tests to not use ALL .. tests: Move the arm+ruby tests to not use ALL The main Ruby.py script does not support the ALL target (it still depends on get_runtime_isa). So, instead of testing these with the all target, move them to be tested with just Arm built. Change-Id: I7942177fffd2bbfb0696b67c1e94e2ec30d8178b Signed-off-by: Jason Lowe-Power --- M tests/gem5/fs/linux/arm/test.py 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/tests/gem5/fs/linux/arm/test.py b/tests/gem5/fs/linux/arm/test.py index dff2e74..8700247 100644 --- a/tests/gem5/fs/linux/arm/test.py +++ b/tests/gem5/fs/linux/arm/test.py @@ -73,10 +73,6 @@ "realview64-minor-dual", "realview64-switcheroo-o3", "realview64-switcheroo-full", -"realview-simple-timing-ruby", -"realview64-simple-timing-ruby", -"realview64-simple-timing-dual-ruby", -"realview64-o3-dual-ruby", # The following tests fail. These are recorded in the GEM5-640 # Jira issue. # @@ -88,6 +84,14 @@ #'realview-simple-timing-dual-ruby', ] +# These tests are Ruby-based and Ruby does not support multiple ISAs +arm_fs_long_tests_arm_target = [ +"realview-simple-timing-ruby", +"realview64-simple-timing-ruby", +"realview64-simple-timing-dual-ruby", +"realview64-o3-dual-ruby", +] + tarball = "aarch-system-20220707.tar.bz2" url = config.resource_url + "/arm/" + tarball filepath = os.path.dirname(os.path.abspath(__file__)) @@ -157,3 +161,20 @@ fixtures=(arm_fs_binaries,), uses_kvm=name in arm_fs_kvm_tests, ) + +for name in arm_fs_long_tests_arm_target: +args = [ +joinpath(config.base_dir, "tests", "gem5", "configs", name + ".py"), +path, +config.base_dir, +] +gem5_verify_config( +name=name, +verifiers=verifier_list(name), # TODO: Add basic stat verifiers +config=joinpath(filepath, "run.py"), +config_args=args, +valid_isas=(constants.arm_tag,), +length=constants.long_tag, +fixtures=(arm_fs_binaries,), +uses_kvm=name in arm_fs_kvm_tests, +) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63852?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7942177fffd2bbfb0696b67c1e94e2ec30d8178b Gerrit-Change-Number: 63852 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix errors in arm switcheroo
Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63851?usp=email ) Change subject: tests: Fix errors in arm switcheroo .. tests: Fix errors in arm switcheroo When switching to the all target, there is no longer a "DerivO3CPU" we now need to drop the "Deriv" Note that there are still some cases where it is valid to use "DerivO3" where it is converted to drop the "Deriv" via a map. Cleaning this up further is for future work. Change-Id: Ide59eb3a5c7daf15c13afe395409f588562c1b54 Signed-off-by: Jason Lowe-Power --- M tests/gem5/configs/realview-switcheroo-o3.py M tests/gem5/configs/realview64-switcheroo-o3.py 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/tests/gem5/configs/realview-switcheroo-o3.py b/tests/gem5/configs/realview-switcheroo-o3.py index fe3298f..4fca57e 100644 --- a/tests/gem5/configs/realview-switcheroo-o3.py +++ b/tests/gem5/configs/realview-switcheroo-o3.py @@ -41,7 +41,7 @@ aarch64_kernel=False, machine_type="VExpress_GEM5_V1", mem_class=DDR3_1600_8x8, -cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU), +cpu_classes=(ArmO3CPU, ArmO3CPU), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview64-switcheroo-o3.py b/tests/gem5/configs/realview64-switcheroo-o3.py index ddfc73a..f899337 100644 --- a/tests/gem5/configs/realview64-switcheroo-o3.py +++ b/tests/gem5/configs/realview64-switcheroo-o3.py @@ -38,7 +38,7 @@ import switcheroo root = LinuxArmFSSwitcheroo( -mem_class=DDR3_1600_8x8, cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU) +mem_class=DDR3_1600_8x8, cpu_classes=(ArmO3CPU, ArmO3CPU) ).create_root() # Setup a custom test method that uses the switcheroo tester that -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63851?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ide59eb3a5c7daf15c13afe395409f588562c1b54 Gerrit-Change-Number: 63851 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Lowe-Power Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: Fix -Wunused-variable with structured binding
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63831?usp=email ) Change subject: systemc: Fix -Wunused-variable with structured binding .. systemc: Fix -Wunused-variable with structured binding Change-Id: Ied66047c53dfc674557aeaf74fbba04c2b3d8359 Signed-off-by: Giacomo Travaglini --- M src/systemc/tlm_bridge/tlm_to_gem5.cc 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc b/src/systemc/tlm_bridge/tlm_to_gem5.cc index c3313da..84907be 100644 --- a/src/systemc/tlm_bridge/tlm_to_gem5.cc +++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc @@ -218,7 +218,8 @@ trans.acquire(); -auto [pkt, pkt_created] = payload2packet(_id, trans); +auto res = payload2packet(_id, trans); +auto pkt = res.first; pkt->pushSenderState(new Gem5SystemC::TlmSenderState(trans)); // If the packet doesn't need a response, we should send BEGIN_RESP by -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63831?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ied66047c53dfc674557aeaf74fbba04c2b3d8359 Gerrit-Change-Number: 63831 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: correct the control signal for AmbaFromTlmBridge
saction , sc_core::sc_time ); +bool getDirectMemPtr(amba_pv::amba_pv_transaction , + tlm::tlm_dmi _data); +unsigned int transportDbg(amba_pv::amba_pv_transaction ); +void invalidateDirectMemPtr(sc_dt::uint64 start_range, +sc_dt::uint64 end_range); +void syncControlExtension(amba_pv::amba_pv_transaction ); + +tlm_utils::simple_target_socket< +AmbaFromTlmBridge64, 64, tlm::tlm_base_protocol_types> targetProxy; +tlm_utils::simple_initiator_socket< +AmbaFromTlmBridge64, 64, tlm::tlm_base_protocol_types> initiatorProxy; sc_gem5::TlmTargetWrapper<64> tlmWrapper; +AmbaInitiator ambaWrapper; }; } // namespace fastmodel -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63773?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I600be7ba21368f00c05426ac1db3c28efd6ca2ea Gerrit-Change-Number: 63773 Gerrit-PatchSet: 8 Gerrit-Owner: Yu-hsin Wang Gerrit-Reviewer: Earl Ou Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jui-min Lee Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-CC: Philip Metzler Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: gem5_to_tlm bridge should reuse existed tlm payload
*extension = nullptr;
-trans.get_extension(extension);
-
-// If there is an extension, this transaction was initiated by the gem5
-// world and we can pipe through the original packet. Otherwise, we
-// generate a new packet based on the transaction.
-if (extension != nullptr) {
-pkt = extension->getPacket();
-} else {
-pkt = payload2packet(_id, trans);
-}
-
-auto tlmSenderState = new TlmSenderState(trans);
+auto [pkt, pkt_created] = payload2packet(_id, trans);
+auto *tlmSenderState = new Gem5SystemC::TlmSenderState(trans);
pkt->pushSenderState(tlmSenderState);
// If the packet doesn't need a response, we should send BEGIN_RESP by
@@ -323,18 +330,7 @@
TlmToGem5Bridge::b_transport(tlm::tlm_generic_payload ,
sc_core::sc_time )
{
-Gem5SystemC::Gem5Extension *extension = nullptr;
-trans.get_extension(extension);
-
-PacketPtr pkt = nullptr;
-
-// If there is an extension, this transaction was initiated by the gem5
-// world and we can pipe through the original packet.
-if (extension != nullptr) {
-pkt = extension->getPacket();
-} else {
-pkt = payload2packet(_id, trans);
-}
+auto [pkt, pkt_created] = payload2packet(_id, trans);
MemBackdoorPtr backdoor = nullptr;
Tick ticks = bmp.sendAtomicBackdoor(pkt, backdoor);
@@ -352,7 +348,7 @@
// update time
t += delay;
-if (extension == nullptr)
+if (pkt_created)
destroyPacket(pkt);
trans.set_response_status(tlm::TLM_OK_RESPONSE);
@@ -362,19 +358,12 @@
unsigned int
TlmToGem5Bridge::transport_dbg(tlm::tlm_generic_payload )
{
-Gem5SystemC::Gem5Extension *extension = nullptr;
-trans.get_extension(extension);
+auto [pkt, pkt_created] = payload2packet(_id, trans);
+if (pkt != nullptr) {
+bmp.sendFunctional(pkt);
-// If there is an extension, this transaction was initiated by the gem5
-// world and we can pipe through the original packet.
-if (extension != nullptr) {
-bmp.sendFunctional(extension->getPacket());
-} else {
-auto pkt = payload2packet(_id, trans);
-if (pkt) {
-bmp.sendFunctional(pkt);
+if (pkt_created)
destroyPacket(pkt);
-}
}
return trans.get_data_length();
@@ -385,19 +374,7 @@
TlmToGem5Bridge::get_direct_mem_ptr(tlm::tlm_generic_payload
,
tlm::tlm_dmi _data)
{
-Gem5SystemC::Gem5Extension *extension = nullptr;
-trans.get_extension(extension);
-
-PacketPtr pkt = nullptr;
-
-// If there is an extension, this transaction was initiated by the gem5
-// world and we can pipe through the original packet.
-if (extension != nullptr) {
-pkt = extension->getPacket();
-} else {
-pkt = payload2packet(_id, trans);
-pkt->req->setFlags(Request::NO_ACCESS);
-}
+auto [pkt, pkt_created] = payload2packet(_id, trans);
MemBackdoorPtr backdoor = nullptr;
bmp.sendAtomicBackdoor(pkt, backdoor);
@@ -423,7 +400,7 @@
);
}
-if (extension == nullptr)
+if (!pkt_created)
destroyPacket(pkt);
trans.set_response_status(tlm::TLM_OK_RESPONSE);
@@ -455,7 +432,8 @@
pkt->payloadDelay = 0;
pkt->headerDelay = 0;
-auto tlmSenderState =
dynamic_cast(pkt->popSenderState());
+auto *tlmSenderState =
+dynamic_cast(pkt->popSenderState());
sc_assert(tlmSenderState != nullptr);
auto = tlmSenderState->trans;
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh
b/src/systemc/tlm_bridge/tlm_to_gem5.hh
index b0fe62a..e452d8b 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -59,6 +59,7 @@
#define __SYSTEMC_TLM_BRIDGE_TLM_TO_GEM5_HH__
#include
+#include
#include "mem/port.hh"
#include "params/TlmToGem5BridgeBase.hh"
@@ -78,7 +79,7 @@
void addPayloadToPacketConversionStep(PayloadToPacketConversionStep step);
-gem5::PacketPtr payload2packet(gem5::RequestorID _id,
+std::pair payload2packet(gem5::RequestorID _id,
tlm::tlm_generic_payload );
class TlmToGem5BridgeBase : public sc_core::sc_module
@@ -91,12 +92,6 @@
class TlmToGem5Bridge : public TlmToGem5BridgeBase
{
private:
-struct TlmSenderState : public gem5::Packet::SenderState
-{
-tlm::tlm_generic_payload
-TlmSenderState(tlm::tlm_generic_payload ) : trans(trans) {}
-};
-
class BridgeRequestPort : public gem5::RequestPort
{
protected:
--
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Gerrit-Change-Id: Ic6d24e98454f564f7dd6b43ad8c011e1ea7ea433
Gerrit-Change-Number: 63771
Gerrit-PatchSet:
[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: associate tlm payload and gem5 packet in blocking interfaces
Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63772?usp=email )
Change subject: systemc: associate tlm payload and gem5 packet in blocking
interfaces
..
systemc: associate tlm payload and gem5 packet in blocking interfaces
TlmToGem5Bridge only associates the tlm payload and gem5 packet in
nb_transport case. We should also do the samething in blocking
interfaces. Otherwise, the downstream Gem5ToTlmBridge cannot get the
correct payload.
Change-Id: I85b213402d58d68641615a6cea04961f4a15f1ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63772
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
1 file changed, 44 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc
b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index 4cb8194..c3313da 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -219,8 +219,7 @@
trans.acquire();
auto [pkt, pkt_created] = payload2packet(_id, trans);
-auto *tlmSenderState = new Gem5SystemC::TlmSenderState(trans);
-pkt->pushSenderState(tlmSenderState);
+pkt->pushSenderState(new Gem5SystemC::TlmSenderState(trans));
// If the packet doesn't need a response, we should send BEGIN_RESP by
// ourselves.
@@ -331,6 +330,7 @@
sc_core::sc_time )
{
auto [pkt, pkt_created] = payload2packet(_id, trans);
+pkt->pushSenderState(new Gem5SystemC::TlmSenderState(trans));
MemBackdoorPtr backdoor = nullptr;
Tick ticks = bmp.sendAtomicBackdoor(pkt, backdoor);
@@ -348,6 +348,13 @@
// update time
t += delay;
+gem5::Packet::SenderState *senderState = pkt->popSenderState();
+sc_assert(
+nullptr !=
dynamic_cast(senderState));
+
+// clean up
+delete senderState;
+
if (pkt_created)
destroyPacket(pkt);
@@ -360,8 +367,17 @@
{
auto [pkt, pkt_created] = payload2packet(_id, trans);
if (pkt != nullptr) {
+pkt->pushSenderState(new Gem5SystemC::TlmSenderState(trans));
+
bmp.sendFunctional(pkt);
+gem5::Packet::SenderState *senderState = pkt->popSenderState();
+sc_assert(
+nullptr !=
dynamic_cast(senderState));
+
+// clean up
+delete senderState;
+
if (pkt_created)
destroyPacket(pkt);
}
@@ -375,6 +391,7 @@
tlm::tlm_dmi _data)
{
auto [pkt, pkt_created] = payload2packet(_id, trans);
+pkt->pushSenderState(new Gem5SystemC::TlmSenderState(trans));
MemBackdoorPtr backdoor = nullptr;
bmp.sendAtomicBackdoor(pkt, backdoor);
@@ -400,6 +417,13 @@
);
}
+gem5::Packet::SenderState *senderState = pkt->popSenderState();
+sc_assert(
+nullptr !=
dynamic_cast(senderState));
+
+// clean up
+delete senderState;
+
if (!pkt_created)
destroyPacket(pkt);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I85b213402d58d68641615a6cea04961f4a15f1ba
Gerrit-Change-Number: 63772
Gerrit-PatchSet: 8
Gerrit-Owner: Yu-hsin Wang
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Philip Metzler
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: util: added workbegin and workend in m5 util
, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "args.hh"
+#include "command.hh"
+#include "dispatch_table.hh"
+
+namespace
+{
+
+bool
+do_work_end(const DispatchTable , Args )
+{
+uint64_t workid, threadid;
+if (!args.pop(workid, 0) || !args.pop(threadid, 0))
+return false;
+
+(*dt.m5_work_end)(workid, threadid);
+
+return true;
+}
+
+Command workend = {
+"workend", 0, 2, do_work_end, "[workid [threadid]]\n"
+"Exit immediately" };
+
+} // anonymous namespace
--
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Gerrit-Change-Id: Ic2b1ac3c08dcae3f66fb65dffaa3a3358b717251
Gerrit-Change-Number: 63751
Gerrit-PatchSet: 2
Gerrit-Owner: Zhantong Qiu
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Zhantong Qiu
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm,tests: added arm-linux-boot tests for the ArmBoard
ensure the right version of gem5 is being used.
+requires(isa_required=ISA.ARM)
+
+if args.mem_system == "classic":
+from
gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy
import (
+PrivateL1PrivateL2CacheHierarchy,
+)
+
+# Setup the cache hierarchy.
+cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
+)
+else:
+raise NotImplementedError(
+"Memory type '{}' is not supported in the boot tests.".format(
+args.mem_system
+)
+)
+
+# Setup the system memory.
+python_module = "gem5.components.memory"
+memory_class = getattr(importlib.import_module(python_module),
args.dram_class)
+memory = memory_class(size="4GiB")
+
+# Setup a processor.
+
+cpu_type = get_cpu_type_from_str(args.cpu)
+
+processor = SimpleProcessor(
+cpu_type=cpu_type, num_cores=args.num_cpus, isa=ISA.ARM
+)
+
+
+# The ArmBoard requires a `release` to be specified.
+
+release = ArmDefaultRelease()
+
+# The platform sets up the memory ranges of all the on-chip and off-chip
+# devices present on the ARM system.
+
+platform = VExpress_GEM5_Foundation()
+
+# Setup the board.
+board = ArmBoard(
+clk_freq="1GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+release=release,
+platform=platform,
+)
+
+# Set the Full System workload.
+board.set_kernel_disk_workload(
+kernel=Resource(
+"arm64-linux-kernel-5.4.49",
+resource_directory=args.resource_directory,
+),
+bootloader=Resource(
+ "arm64-bootloader-foundation",
+resource_directory=args.resource_directory,
+),
+disk_image=Resource(
+"arm64-ubuntu-20.04-img",
+ resource_directory=args.resource_directory,
+),
+)
+
+simulator = Simulator(board=board)
+
+if args.tick_exit:
+simulator.run(max_ticks=args.tick_exit)
+else:
+simulator.run()
+
+print(
+"Exiting @ tick {} because {}.".format(
+simulator.get_current_tick(),
+simulator.get_last_exit_event_cause(),
+)
+)
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I9cb78424cf236e9092b4d4d34b68b1589b50ef37
Gerrit-Change-Number: 62194
Gerrit-PatchSet: 10
Gerrit-Owner: Kaustav Goswami
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add test for riscvmatched-hello stdlib example
Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63591?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: tests: Add test for riscvmatched-hello stdlib example .. tests: Add test for riscvmatched-hello stdlib example This test ensures the example script is still functioning and, by proxy, does a simple test to ensure the riscvmatched board's SE workload capabilities are still working. Change-Id: I7c79856e84122c6737e1e9667b6e626b4622d04c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63591 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index ae814cb..0acc1ae 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -243,3 +243,20 @@ valid_hosts=constants.supported_hosts, length=constants.long_tag, ) + +gem5_verify_config( +name="test-gem5-library-example-riscvmatched-hello", +fixtures=(), +verifiers=(), +config=joinpath( +config.base_dir, +"configs", +"example", +"gem5_library", +"riscvmatched-hello.py", +), +config_args=[], +valid_isas=(constants.riscv_tag,), +valid_hosts=constants.supported_hosts, +length=constants.long_tag, +) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63591?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7c79856e84122c6737e1e9667b6e626b4622d04c Gerrit-Change-Number: 63591 Gerrit-PatchSet: 7 Gerrit-Owner: Bobby Bruce Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: misc: Reword CONTRIBUTING.md pre-commit documentation
Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63791?usp=email ) Change subject: misc: Reword CONTRIBUTING.md pre-commit documentation .. misc: Reword CONTRIBUTING.md pre-commit documentation This is a slight-rewording to make the usage of the pre-commit checks clearer. Change-Id: I73f9bfe7143a527c9e495cdf4d51e2aa857b43d5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63791 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M CONTRIBUTING.md 1 file changed, 23 insertions(+), 5 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index d81cd9c..ae771d3 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -143,14 +143,17 @@ To help ensure the gem5 style guide is maintained, we use [pre-commit]( https://pre-commit.com) to run checks on changes to be contributed. -To setup pre-commit, run the following in your gem5 directory. +To setup pre-commit, run the following in your gem5 directory to install the +pre-commit and commit message hooks. ```sh pip install pre-commit pre-commit install -t pre-commit -t commit-msg ``` -When you run a `git commit` command the pre-commit will run checks on your +The hooks are also automatically installed when gem5 is compiled. + +When you run a `git commit` command the pre-commit hook will run checks on your committed code. The commit will be blocked if a check fails. The same checks are run as part of Gerrit's CI tests (those required to obtain @@ -158,11 +161,10 @@ Therefore setting up pre-commit in your local gem5 development environment is recommended. -You can automatically format your changed code to pass the pre-commit tests by -running: +You can automatically format files to pass the pre-commit tests by running: ```sh -pre-commit run +pre-commit run --files ``` Requirements for change descriptions -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63791?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I73f9bfe7143a527c9e495cdf4d51e2aa857b43d5 Gerrit-Change-Number: 63791 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby Bruce Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib, configs: Add example SE mode script for RISCV matched
Jasjeet Rangi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63571?usp=email )
Change subject: stdlib, configs: Add example SE mode script for RISCV
matched
..
stdlib, configs: Add example SE mode script for RISCV matched
This script runs the riscv-hello binary from gem5 resources on the
RISCV matched prebuilt board found in the
src/python/gem5/prebuilt/riscvmatched/ directory.
Change-Id: I1b527588b0319e9ab853dfcbfa381db2137d1a98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63571
Maintainer: Bobby Bruce
Tested-by: kokoro
Reviewed-by: Bobby Bruce
---
A configs/example/gem5_library/riscvmatched-hello.py
1 file changed, 82 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/gem5_library/riscvmatched-hello.py
b/configs/example/gem5_library/riscvmatched-hello.py
new file mode 100644
index 000..d8ae8e5
--- /dev/null
+++ b/configs/example/gem5_library/riscvmatched-hello.py
@@ -0,0 +1,65 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+"""
+This gem5 configuation script runs a "hello world" binary on the
+RISCVMatched prebuilt board found in src/python/gem5/prebuilt/riscvmatched/
+
+Usage
+-
+
+```
+scons build/RISCV/gem5.opt
+./build/RISCV/gem5.opt \
+configs/example/gem5_library/riscvmatched-hello.py
+```
+"""
+
+from gem5.resources.resource import Resource
+from gem5.simulate.simulator import Simulator
+from python.gem5.prebuilt.riscvmatched.riscvmatched_board import (
+RISCVMatchedBoard,
+)
+from gem5.isas import ISA
+from gem5.utils.requires import requires
+
+requires(isa_required=ISA.RISCV)
+
+# instantiate the riscv matched board with default parameters
+board = RISCVMatchedBoard()
+
+# set the hello world riscv binary as the board workload
+board.set_se_binary_workload(Resource("riscv-hello"))
+
+# run the simulation with the RISCV Matched board
+simulator = Simulator(board=board, full_system=False)
+simulator.run()
+
+print(
+"Exiting @ tick {} because {}.".format(
+simulator.get_current_tick(),
+simulator.get_last_exit_event_cause(),
+)
+)
--
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Gerrit-Change-Id: I1b527588b0319e9ab853dfcbfa381db2137d1a98
Gerrit-Change-Number: 63571
Gerrit-PatchSet: 10
Gerrit-Owner: Jasjeet Rangi
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jasjeet Rangi
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: bug fix for misc node distribution
Daecheol You has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63731?usp=email ) Change subject: configs: bug fix for misc node distribution .. configs: bug fix for misc node distribution Wrong parameter is removed from the distributeNodes calling Change-Id: I84cdf3e993d6b7852c4f134441d77a4b295e8574 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63731 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Tiago Muck --- M configs/topologies/CustomMesh.py 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: Tiago Muck: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/topologies/CustomMesh.py b/configs/topologies/CustomMesh.py index 2e10fdc..545ba4b 100644 --- a/configs/topologies/CustomMesh.py +++ b/configs/topologies/CustomMesh.py @@ -357,7 +357,7 @@ self.distributeNodes(hnf_params, hnf_nodes) # Place CHI_MN on the mesh -self.distributeNodes(options, mn_params, mn_nodes) +self.distributeNodes(mn_params, mn_nodes) # Place CHI_SNF_MainMem on the mesh self.distributeNodes(mem_params, mem_nodes) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63731?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I84cdf3e993d6b7852c4f134441d77a4b295e8574 Gerrit-Change-Number: 63731 Gerrit-PatchSet: 2 Gerrit-Owner: Daecheol You Gerrit-Reviewer: Daecheol You Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Muck Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: configs: fix CHI config for Garnet
Tiago Muck has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63811?usp=email ) Change subject: configs: fix CHI config for Garnet .. configs: fix CHI config for Garnet CHI.py was not working with Garnet as ruby_system.network.buffer_size only exists in SimpleNetwork. Change-Id: I00e952f8881d385e3591c149e08c9c7a53fda2cd Signed-off-by: Tiago Mück --- M configs/ruby/CHI.py 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/configs/ruby/CHI.py b/configs/ruby/CHI.py index d31d233..df97b92 100644 --- a/configs/ruby/CHI.py +++ b/configs/ruby/CHI.py @@ -266,7 +266,8 @@ ruby_system.network.control_msg_size = params.cntrl_msg_size ruby_system.network.data_msg_size = params.data_width -ruby_system.network.buffer_size = params.router_buffer_size +if options.network == "simple": +ruby_system.network.buffer_size = params.router_buffer_size # Incorporate the params into options so it's propagated to # makeTopology and create_topology the parent scripts -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63811?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I00e952f8881d385e3591c149e08c9c7a53fda2cd Gerrit-Change-Number: 63811 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Muck Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: misc: Reword CONTRIBUTING.md pre-commit documentation
Bobby Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63791?usp=email ) Change subject: misc: Reword CONTRIBUTING.md pre-commit documentation .. misc: Reword CONTRIBUTING.md pre-commit documentation This is a slight-rewording to make the usage of the pre-commit checks clearer. Change-Id: I73f9bfe7143a527c9e495cdf4d51e2aa857b43d5 --- M CONTRIBUTING.md 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index d81cd9c..ae771d3 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -143,14 +143,17 @@ To help ensure the gem5 style guide is maintained, we use [pre-commit]( https://pre-commit.com) to run checks on changes to be contributed. -To setup pre-commit, run the following in your gem5 directory. +To setup pre-commit, run the following in your gem5 directory to install the +pre-commit and commit message hooks. ```sh pip install pre-commit pre-commit install -t pre-commit -t commit-msg ``` -When you run a `git commit` command the pre-commit will run checks on your +The hooks are also automatically installed when gem5 is compiled. + +When you run a `git commit` command the pre-commit hook will run checks on your committed code. The commit will be blocked if a check fails. The same checks are run as part of Gerrit's CI tests (those required to obtain @@ -158,11 +161,10 @@ Therefore setting up pre-commit in your local gem5 development environment is recommended. -You can automatically format your changed code to pass the pre-commit tests by -running: +You can automatically format files to pass the pre-commit tests by running: ```sh -pre-commit run +pre-commit run --files ``` Requirements for change descriptions -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63791?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I73f9bfe7143a527c9e495cdf4d51e2aa857b43d5 Gerrit-Change-Number: 63791 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add 'requires' tests for ALL/gem5
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63433?usp=email )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: tests: Add 'requires' tests for ALL/gem5
..
tests: Add 'requires' tests for ALL/gem5
Change-Id: I58012b092dc1ec027474e2e45ad3e9809b31578b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63433
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
---
M tests/gem5/stdlib/test_requires.py
1 file changed, 30 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/stdlib/test_requires.py
b/tests/gem5/stdlib/test_requires.py
index a70ca6b..293eb3d 100644
--- a/tests/gem5/stdlib/test_requires.py
+++ b/tests/gem5/stdlib/test_requires.py
@@ -58,3 +58,20 @@
valid_isas=(isa_map[isa],),
length=length_map[isa],
)
+
+if isa != "null":
+gem5_verify_config(
+name=f"requires-isa-{isa}-with-all-compiled",
+verifiers=(),
+fixtures=(),
+config=joinpath(
+config.base_dir,
+"tests",
+"gem5",
+"configs",
+"requires_check.py",
+),
+config_args=["-i", isa],
+valid_isas=(constants.all_compiled_tag,),
+length=constants.quick_tag,
+)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I58012b092dc1ec027474e2e45ad3e9809b31578b
Gerrit-Change-Number: 63433
Gerrit-PatchSet: 9
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Update presubmit.sh to compile ALL/gem5.fast
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63371?usp=email )
(
7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: tests: Update presubmit.sh to compile ALL/gem5.fast
..
tests: Update presubmit.sh to compile ALL/gem5.fast
This part of the Kokoro presubmit tests was designed to ensure gem5
still compiled sucessfully with Clang and to the '.fast' variant. ARM
was chosen arbitarily. Now that ALL exists, it makes more sense to use
it for this test.
Change-Id: Ia3593f7dd506205da13802a69094f4dd7019ab90
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63371
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M tests/jenkins/presubmit.sh
1 file changed, 20 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 98c3d17..44ec8cf 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -61,12 +61,9 @@
# DOCKER_IMAGE_ALL_DEP compiles gem5.opt with GCC. We run a compilation of
# gem5.fast on the Clang compiler to ensure changes are compilable with the
-# clang compiler. Due to the costs of compilation, we only compile
-# ARM_MESI_Three_Level_HTM at this point. Further compiler tests are
carried
-# out as part of our weekly "Compiler Checks" tests:
-# http://jenkins.gem5.org/job/Compiler-Checks.
+# clang compiler.
rm -rf build
docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) --rm \
"${DOCKER_IMAGE_CLANG_COMPILE}" /usr/bin/env python3 /usr/bin/scons \
-build/ARM_MESI_Three_Level_HTM/gem5.fast -j4 --no-compress-debug \
+build/ALL/gem5.fast -j4 --no-compress-debug \
--ignore-style
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ia3593f7dd506205da13802a69094f4dd7019ab90
Gerrit-Change-Number: 63371
Gerrit-PatchSet: 12
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [XL] Change in gem5/gem5[develop]: stdlib: Added RiscvMatched prebuilt board
__init__( +self, +core_id, +): +super().__init__(core=U74CPU(cpu_id=core_id), isa=ISA.RISCV) diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py new file mode 100644 index 000..838f810 --- /dev/null +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py @@ -0,0 +1,55 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from gem5.utils.override import overrides +from gem5.components.boards.mem_mode import MemMode + +from m5.util import warn + +from gem5.components.processors.base_cpu_processor import BaseCPUProcessor +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.boards.abstract_board import AbstractBoard +from .riscvmatched_core import U74Core + + +class U74Processor(BaseCPUProcessor): +""" +A U74Processor contains a number of cores of U74Core. +""" + +def __init__( +self, +is_fs: bool, +) -> None: +self._cpu_type = CPUTypes.MINOR +super().__init__(cores=self._create_cores(is_fs)) + +def _create_cores(self, is_fs: bool): +if is_fs: +num_cores = 4 +else: +num_cores = 1 +return [U74Core(core_id=i) for i in range(num_cores)] -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63411?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic2c066bb3a41dc2f42566ce971f9a665542f9771 Gerrit-Change-Number: 63411 Gerrit-PatchSet: 18 Gerrit-Owner: Kunal Pai Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Kunal Pai Gerrit-Reviewer: kokoro Gerrit-CC: Jasjeet Rangi Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix the default KVM_ISA setting.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63752?usp=email )
Change subject: scons: Fix the default KVM_ISA setting.
..
scons: Fix the default KVM_ISA setting.
The KVM_ISA setting was moved into a CONF dict, but the code which
ensured it had a default if there was no possible KVM hosting ISA was
still setting that variable in the base environment dict. This moves
the setting into the CONF dict instead.
Change-Id: I067c969dd761b2cdb098bcba6cd6a4b643d2d427
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63752
Reviewed-by: Earl Ou
Tested-by: kokoro
Maintainer: Gabe Black
---
M src/cpu/kvm/SConsopts
1 file changed, 19 insertions(+), 1 deletion(-)
Approvals:
kokoro: Regressions pass
Gabe Black: Looks good to me, approved
Earl Ou: Looks good to me, approved
diff --git a/src/cpu/kvm/SConsopts b/src/cpu/kvm/SConsopts
index e5818e0..275eeda 100644
--- a/src/cpu/kvm/SConsopts
+++ b/src/cpu/kvm/SConsopts
@@ -30,7 +30,7 @@
import gem5_scons
# ISA code can set this to indicate what ISA KVM can target.
-main.SetDefault(KVM_ISA='')
+main['CONF'].setdefault('KVM_ISA', '')
with gem5_scons.Configure(main) as conf:
# Check if we should enable KVM-based hardware virtualization. The
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I067c969dd761b2cdb098bcba6cd6a4b643d2d427
Gerrit-Change-Number: 63752
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: associate tlm payload and gem5 packet in b_transport case
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/63772?usp=email )
Change subject: systemc: associate tlm payload and gem5 packet in
b_transport case
..
systemc: associate tlm payload and gem5 packet in b_transport case
TlmToGem5Bridge only associates the tlm payload and gem5 packet in
nb_transport case. We should also do the samething in b_transport case.
Otherwise, the downstream Gem5ToTlmBridge cannot get the correct
payload.
Change-Id: I85b213402d58d68641615a6cea04961f4a15f1ba
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
1 file changed, 41 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc
b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index 0c622f6..2547c99 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -338,6 +338,9 @@
pkt = payload2packet(_id, trans);
}
+auto tlmSenderState = new Gem5SystemC::TlmSenderState(trans);
+pkt->pushSenderState(tlmSenderState);
+
MemBackdoorPtr backdoor = nullptr;
Tick ticks = bmp.sendAtomicBackdoor(pkt, backdoor);
if (backdoor)
@@ -354,6 +357,12 @@
// update time
t += delay;
+// clean up
+tlmSenderState =
+dynamic_cast(pkt->popSenderState());
+sc_assert(tlmSenderState != nullptr);
+delete tlmSenderState;
+
if (extension == nullptr)
destroyPacket(pkt);
@@ -378,8 +387,17 @@
pkt = payload2packet(_id, trans);
}
+auto tlmSenderState = new Gem5SystemC::TlmSenderState(trans);
+pkt->pushSenderState(tlmSenderState);
+
bmp.sendFunctional(pkt);
+// clean up
+tlmSenderState =
+dynamic_cast(pkt->popSenderState());
+sc_assert(tlmSenderState != nullptr);
+delete tlmSenderState;
+
if (extension == nullptr)
destroyPacket(pkt);
@@ -406,6 +424,9 @@
pkt->req->setFlags(Request::NO_ACCESS);
}
+auto tlmSenderState = new Gem5SystemC::TlmSenderState(trans);
+pkt->pushSenderState(tlmSenderState);
+
MemBackdoorPtr backdoor = nullptr;
bmp.sendAtomicBackdoor(pkt, backdoor);
if (backdoor) {
@@ -430,6 +451,12 @@
);
}
+// clean up
+tlmSenderState =
+dynamic_cast(pkt->popSenderState());
+sc_assert(tlmSenderState != nullptr);
+delete tlmSenderState;
+
if (extension == nullptr)
destroyPacket(pkt);
--
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Gerrit-Change-Id: I85b213402d58d68641615a6cea04961f4a15f1ba
Gerrit-Change-Number: 63772
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: correct the control signal in the direction from gem5 to amba
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/63773?usp=email )
Change subject: fastmodel: correct the control signal in the direction from
gem5 to amba
..
fastmodel: correct the control signal in the direction from gem5 to amba
Change-Id: I600be7ba21368f00c05426ac1db3c28efd6ca2ea
---
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
2 files changed, 87 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
index 4005355..65d0ee5 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
@@ -28,6 +28,8 @@
#include "arch/arm/fastmodel/amba_from_tlm_bridge.hh"
#include "params/AmbaFromTlmBridge64.hh"
+#include "pv_userpayload_extension.h"
+#include "systemc/tlm_bridge/sc_ext.hh"
namespace gem5
{
@@ -36,11 +38,21 @@
namespace fastmodel
{
-AmbaFromTlmBridge64::AmbaFromTlmBridge64(const char *name) :
+AmbaFromTlmBridge64::AmbaFromTlmBridge64(const sc_core::sc_module_name&
name) :
amba_pv::amba_pv_from_tlm_bridge<64>(name),
-ambaWrapper(amba_pv_m, std::string(name) + ".amba", -1),
-tlmWrapper(tlm_s, std::string(name) + ".tlm", -1)
-{}
+targetProxy("target_proxy"),
+initiatorProxy("initiator_proxy"),
+tlmWrapper(targetProxy, std::string(name) + ".tlm", -1),
+ambaWrapper(amba_pv_m, std::string(name) + ".amba", -1)
+{
+targetProxy.register_b_transport(this,
::bTransport);
+targetProxy.register_get_direct_mem_ptr(
+this, ::getDirectMemPtr);
+targetProxy.register_transport_dbg(this,
::transportDbg);
+initiatorProxy.register_invalidate_direct_mem_ptr(
+this, ::invalidateDirectMemPtr);
+initiatorProxy(tlm_s);
+}
Port &
AmbaFromTlmBridge64::gem5_getPort(const std::string _name, int idx)
@@ -55,6 +67,54 @@
}
}
+void
+AmbaFromTlmBridge64::bTransport(amba_pv::amba_pv_transaction ,
+sc_core::sc_time )
+{
+syncControlExtension(trans);
+return initiatorProxy->b_transport(trans, t);
+}
+
+bool
+AmbaFromTlmBridge64::getDirectMemPtr(amba_pv::amba_pv_transaction ,
+ tlm::tlm_dmi _data)
+{
+return initiatorProxy->get_direct_mem_ptr(trans, dmi_data);
+}
+
+unsigned int
+AmbaFromTlmBridge64::transportDbg(amba_pv::amba_pv_transaction )
+{
+return initiatorProxy->transport_dbg(trans);
+}
+
+void
+AmbaFromTlmBridge64::invalidateDirectMemPtr(sc_dt::uint64 start_range,
+ sc_dt::uint64 end_range)
+{
+targetProxy->invalidate_direct_mem_ptr(start_range, end_range);
+}
+
+void
+AmbaFromTlmBridge64::syncControlExtension(amba_pv::amba_pv_transaction
)
+{
+Gem5SystemC::ControlExtension *control_ex = nullptr;
+trans.get_extension(control_ex);
+if (!control_ex) {
+return;
+}
+
+amba_pv::amba_pv_extension *amba_ex = nullptr;
+trans.get_extension(amba_ex);
+if (!amba_ex) {
+return;
+}
+
+amba_ex->set_privileged(control_ex->isPrivileged());
+amba_ex->set_non_secure(!control_ex->isSecure());
+amba_ex->set_instruction(control_ex->isInstruction());
+}
+
} // namespace fastmodel
fastmodel::AmbaFromTlmBridge64 *
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
index a54617d..4484ea9 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
@@ -47,13 +47,25 @@
class AmbaFromTlmBridge64 : public amba_pv::amba_pv_from_tlm_bridge<64>
{
public:
-AmbaFromTlmBridge64(const char *name);
+AmbaFromTlmBridge64(const sc_core::sc_module_name );
gem5::Port _getPort(const std::string _name, int idx=-1)
override;
private:
-AmbaInitiator ambaWrapper;
+void bTransport(amba_pv::amba_pv_transaction , sc_core::sc_time
);
+bool getDirectMemPtr(amba_pv::amba_pv_transaction ,
+ tlm::tlm_dmi _data);
+unsigned int transportDbg(amba_pv::amba_pv_transaction );
+void invalidateDirectMemPtr(sc_dt::uint64 start_range,
+sc_dt::uint64 end_range);
+void syncControlExtension(amba_pv::amba_pv_transaction );
+
+tlm_utils::simple_target_socket<
+AmbaFromTlmBridge64, 64, tlm::tlm_base_protocol_types> targetProxy;
+tlm_utils::simple_initiator_socket<
+AmbaFromTlmBridge64, 64, tlm::tlm_base_protocol_types>
initiatorProxy;
sc_gem5::TlmTargetWrapper<64> tlmWrapper;
+AmbaInitiator ambaWrapper;
};
} // namespace fastmodel
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: gem5_to_tlm bridge should reuse existed tlm payload
completed");
}
-trans->release();
+if (tlmSenderState != nullptr)
+trans->release();
}
template
diff --git a/src/systemc/tlm_bridge/sc_ext.hh
b/src/systemc/tlm_bridge/sc_ext.hh
index 3f7c320..bb67676 100644
--- a/src/systemc/tlm_bridge/sc_ext.hh
+++ b/src/systemc/tlm_bridge/sc_ext.hh
@@ -44,6 +44,12 @@
namespace Gem5SystemC
{
+struct TlmSenderState : public gem5::Packet::SenderState
+{
+tlm::tlm_generic_payload
+TlmSenderState(tlm::tlm_generic_payload ) : trans(trans) {}
+};
+
class Gem5Extension: public tlm::tlm_extension
{
public:
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc
b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index 9f7c6eb..0c622f6 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -208,11 +208,12 @@
// generate a new packet based on the transaction.
if (extension != nullptr) {
pkt = extension->getPacket();
+pkt->setAddr(trans.get_address());
} else {
pkt = payload2packet(_id, trans);
}
-auto tlmSenderState = new TlmSenderState(trans);
+auto tlmSenderState = new Gem5SystemC::TlmSenderState(trans);
pkt->pushSenderState(tlmSenderState);
// If the packet doesn't need a response, we should send BEGIN_RESP by
@@ -332,6 +333,7 @@
// world and we can pipe through the original packet.
if (extension != nullptr) {
pkt = extension->getPacket();
+pkt->setAddr(trans.get_address());
} else {
pkt = payload2packet(_id, trans);
}
@@ -365,18 +367,22 @@
Gem5SystemC::Gem5Extension *extension = nullptr;
trans.get_extension(extension);
+PacketPtr pkt = nullptr;
+
// If there is an extension, this transaction was initiated by the gem5
// world and we can pipe through the original packet.
if (extension != nullptr) {
-bmp.sendFunctional(extension->getPacket());
+pkt = extension->getPacket();
+pkt->setAddr(trans.get_address());
} else {
-auto pkt = payload2packet(_id, trans);
-if (pkt) {
-bmp.sendFunctional(pkt);
-destroyPacket(pkt);
-}
+pkt = payload2packet(_id, trans);
}
+bmp.sendFunctional(pkt);
+
+if (extension == nullptr)
+destroyPacket(pkt);
+
return trans.get_data_length();
}
@@ -394,6 +400,7 @@
// world and we can pipe through the original packet.
if (extension != nullptr) {
pkt = extension->getPacket();
+pkt->setAddr(trans.get_address());
} else {
pkt = payload2packet(_id, trans);
pkt->req->setFlags(Request::NO_ACCESS);
@@ -455,7 +462,8 @@
pkt->payloadDelay = 0;
pkt->headerDelay = 0;
-auto tlmSenderState =
dynamic_cast(pkt->popSenderState());
+auto tlmSenderState =
+dynamic_cast(pkt->popSenderState());
sc_assert(tlmSenderState != nullptr);
auto = tlmSenderState->trans;
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh
b/src/systemc/tlm_bridge/tlm_to_gem5.hh
index b0fe62a..db430ef 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -91,12 +91,6 @@
class TlmToGem5Bridge : public TlmToGem5BridgeBase
{
private:
-struct TlmSenderState : public gem5::Packet::SenderState
-{
-tlm::tlm_generic_payload
-TlmSenderState(tlm::tlm_generic_payload ) : trans(trans) {}
-};
-
class BridgeRequestPort : public gem5::RequestPort
{
protected:
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix the default KVM_ISA setting.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/63752?usp=email )
Change subject: scons: Fix the default KVM_ISA setting.
..
scons: Fix the default KVM_ISA setting.
The KVM_ISA setting was moved into a CONF dict, but the code which
ensured it had a default if there was no possible KVM hosting ISA was
still setting that variable in the base environment dict. This moves
the setting into the CONF dict instead.
Change-Id: I067c969dd761b2cdb098bcba6cd6a4b643d2d427
---
M src/cpu/kvm/SConsopts
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/cpu/kvm/SConsopts b/src/cpu/kvm/SConsopts
index e5818e0..275eeda 100644
--- a/src/cpu/kvm/SConsopts
+++ b/src/cpu/kvm/SConsopts
@@ -30,7 +30,7 @@
import gem5_scons
# ISA code can set this to indicate what ISA KVM can target.
-main.SetDefault(KVM_ISA='')
+main['CONF'].setdefault('KVM_ISA', '')
with gem5_scons.Configure(main) as conf:
# Check if we should enable KVM-based hardware virtualization. The
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: util: added workbegin and workend in m5 util
HERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "args.hh"
+#include "command.hh"
+#include "dispatch_table.hh"
+
+namespace
+{
+
+bool
+do_work_end(const DispatchTable , Args )
+{
+uint64_t workid, threadid;
+if (!args.pop(workid, 0) || !args.pop(threadid, 0))
+return false;
+
+(*dt.m5_work_end)(workid, threadid);
+
+return true;
+}
+
+Command workend = {
+"workend", 0, 2, do_work_end, "[workid [threadid]]\n"
+"Exit immediately" };
+
+} // anonymous namespace
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: bug fix for misc node distribution
Daecheol You has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/63731?usp=email ) Change subject: configs: bug fix for misc node distribution .. configs: bug fix for misc node distribution Wrong parameter is removed from the distributeNodes calling Change-Id: I84cdf3e993d6b7852c4f134441d77a4b295e8574 --- M configs/topologies/CustomMesh.py 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/configs/topologies/CustomMesh.py b/configs/topologies/CustomMesh.py index 2e10fdc..545ba4b 100644 --- a/configs/topologies/CustomMesh.py +++ b/configs/topologies/CustomMesh.py @@ -357,7 +357,7 @@ self.distributeNodes(hnf_params, hnf_nodes) # Place CHI_MN on the mesh -self.distributeNodes(options, mn_params, mn_nodes) +self.distributeNodes(mn_params, mn_nodes) # Place CHI_SNF_MainMem on the mesh self.distributeNodes(mem_params, mem_nodes) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63731?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I84cdf3e993d6b7852c4f134441d77a4b295e8574 Gerrit-Change-Number: 63731 Gerrit-PatchSet: 1 Gerrit-Owner: Daecheol You Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: bug fix for stale WriteBack
Daecheol You has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63611?usp=email )
Change subject: mem-ruby: bug fix for stale WriteBack
..
mem-ruby: bug fix for stale WriteBack
Finish_CopyBack_Stale is scheduled only when the requestor is the last
sharer. This prevents the cacahe evicting the line which was already
evicted while the stale WriteBack transaction was stalled.
Wrong condition check in Finish_CopyBack_Stale for eviction is also
removed.
Change-Id: Ib66acc1b9e4a6f7cea373e1fb37375427897d48d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63611
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
1 file changed, 25 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
index 2c47ac9..d18c600 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
@@ -891,7 +891,11 @@
tbe.actions.pushNB(Event:SendCompDBIDRespStale);
tbe.actions.pushNB(Event:WriteFEPipe);
- tbe.actions.push(Event:FinishCopyBack_Stale);
+
+ // eviction condition should be examined if it is the last sharer
+ if (tbe.dir_sharers.count() == 1) {
+tbe.actions.push(Event:FinishCopyBack_Stale);
+ }
assert((tbe.dir_ownerExists == false) || (tbe.dir_owner !=
tbe.requestor));
}
@@ -900,7 +904,7 @@
// if it was the last known sharer and we don't have the data do the same
// the Initiate_Evict
if ((is_HN == false) && (tbe.dir_sharers.count() == 0) &&
- tbe.dir_sharers.isElement(tbe.requestor) && (tbe.dataValid ==
false)) {
+ (tbe.dataValid == false)) {
tbe.actions.push(Event:SendEvict);
}
}
--
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Gerrit-Change-Number: 63611
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Gerrit-Owner: Daecheol You
Gerrit-Reviewer: Daecheol You
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Muck
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix compilation error due to getdents* syscalls
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/60189 )
Change subject: arch-riscv: Fix compilation error due to getdents* syscalls
..
arch-riscv: Fix compilation error due to getdents* syscalls
In src/sim/syscall_emul.*, getdents and getdents64 are guarded
by #ifdefs. Similar #ifdefs should be in se_workload.cc for each
arch.
Change-Id: Ie636a739235711c3e6d8256fd7929b7d8b4ec953
Signed-off-by: Hoa Nguyen
---
M src/arch/riscv/linux/se_workload.cc
1 file changed, 30 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index f8053d4..dd9a8a2 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -185,7 +185,11 @@
{ 58, "vhangup" },
{ 59, "pipe2", pipe2Func },
{ 60, "quotactl" },
+#if defined(SYS_getdents64)
{ 61, "getdents64", getdents64Func },
+#else
+{ 61, "getdents64" },
+#endif
{ 62, "lseek", lseekFunc },
{ 63, "read", readFunc },
{ 64, "write", writeFunc },
@@ -436,7 +440,11 @@
{ 1062, "time", timeFunc },
{ 1063, "utime" },
{ 1064, "creat" },
+#if defined(SYS_getdents)
{ 1065, "getdents", getdentsFunc },
+#else
+{ 1065, "getdents" },
+#endif
{ 1066, "futimesat" },
{ 1067, "select", selectFunc },
{ 1068, "poll", pollFunc },
@@ -516,7 +524,11 @@
{ 58, "vhangup" },
{ 59, "pipe2", pipe2Func },
{ 60, "quotactl" },
+#if defined(SYS_getdents64)
{ 61, "getdents64", getdents64Func },
+#else
+{ 61, "getdents64" },
+#endif
{ 62, "lseek", lseekFunc },
{ 63, "read", readFunc },
{ 64, "write", writeFunc },
@@ -767,7 +779,11 @@
{ 1062, "time", timeFunc },
{ 1063, "utime" },
{ 1064, "creat" },
+#if defined(SYS_getdents)
{ 1065, "getdents", getdentsFunc },
+#else
+{ 1065, "getdents" },
+#endif
{ 1066, "futimesat" },
{ 1067, "select", selectFunc },
{ 1068, "poll", pollFunc },
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: sim, arch: Remove Fault debug flag
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/59152 )
Change subject: sim, arch: Remove Fault debug flag
..
sim, arch: Remove Fault debug flag
There is already a Faults debug flag used by Arm and X86 so
having both Fault and Faults is highly confusing
Change-Id: Id5c17f19b51c6257dfc470d07ba050a9de7a9db3
Signed-off-by: Giacomo Travaglini
---
M src/sim/SConscript
M src/sim/faults.cc
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/sim/SConscript b/src/sim/SConscript
index cfeca46..969a3e4 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -122,7 +122,6 @@
DebugFlag('CxxConfig')
DebugFlag('Drain')
DebugFlag('Event')
-DebugFlag('Fault')
DebugFlag('Flow')
DebugFlag('IPI')
DebugFlag('IPR')
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 115c0ed..c0a7d76 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -46,7 +46,7 @@
#include "base/logging.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "debug/Fault.hh"
+#include "debug/Faults.hh"
#include "mem/page_table.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
@@ -59,7 +59,7 @@
{
panic_if(!FullSystem, "fault (%s) detected @ PC %s",
name(), tc->pcState());
-DPRINTF(Fault, "Fault %s at PC: %s\n", name(), tc->pcState());
+DPRINTF(Faults, "Fault %s at PC: %s\n", name(), tc->pcState());
}
void
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Memoize computeAddrTop in the MMU code
evel.hh"
#include "params/ArmMMU.hh"
@@ -130,11 +131,44 @@
S12E1Tran = 0x100
};
-struct CachedState {
-explicit CachedState(MMU *_mmu, bool stage2)
- : mmu(_mmu), isStage2(stage2)
+struct CachedState
+{
+CachedState(MMU *_mmu, bool stage2)
+ : mmu(_mmu), isStage2(stage2),
+computeAddrTop(ArmISA::computeAddrTop)
{}
+CachedState&
+operator=(const CachedState )
+{
+isStage2 = rhs.isStage2;
+cpsr = rhs.cpsr;
+aarch64 = rhs.aarch64;
+aarch64EL = EL0;
+sctlr = rhs.sctlr;
+scr = rhs.scr;
+isPriv = rhs.isPriv;
+isSecure = rhs.isSecure;
+isHyp = rhs.isHyp;
+ttbcr = rhs.ttbcr;
+asid = rhs.asid;
+vmid = rhs.vmid;
+prrr = rhs.prrr;
+nmrr = rhs.nmrr;
+hcr = rhs.hcr;
+dacr = rhs.dacr;
+miscRegValid = rhs.miscRegValid;
+curTranType = rhs.curTranType;
+stage2Req = rhs.stage2Req;
+stage2DescReq = rhs.stage2DescReq;
+directToStage2 = rhs.directToStage2;
+
+// When we copy we just flush the memoizer cache
+computeAddrTop.flush();
+
+return *this;
+}
+
void updateMiscReg(ThreadContext *tc, ArmTranslationType
tran_type);
/** Returns the current VMID
@@ -173,6 +207,8 @@
// Indicates whether all translation requests should
// be routed directly to the stage 2 TLB
bool directToStage2 = false;
+
+decltype(Memoizer(ArmISA::computeAddrTop)) computeAddrTop;
};
MMU(const ArmMMUParams );
@@ -397,7 +433,12 @@
ThreadContext *tc, bool stage2);
Fault checkPermissions64(TlbEntry *te, const RequestPtr , Mode
mode,
ThreadContext *tc, CachedState );
+
protected:
+Addr purifyTaggedAddr(Addr vaddr_tainted, ThreadContext *tc,
+ ExceptionLevel el,
+ TCR tcr, bool is_inst, CachedState& state);
+
bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr ,
Mode mode, const bool is_priv, CachedState );
--
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[gem5-dev] [L] Change in gem5/gem5[develop]: base: Add generic Memoizer class
+
+namespace
+{
+
+uint32_t
+fibonacci(uint32_t n)
+{
+if (n == 0) return 0;
+if (n == 1) return 1;
+
+return fibonacci(n-1) + fibonacci(n-2);
+}
+
+using FibonacciMemoizer = decltype(Memoizer(fibonacci));
+
+class FibonacciMemoizerFixture : public FibonacciMemoizer,
+ public ::testing::Test
+{
+ public:
+FibonacciMemoizerFixture()
+ : FibonacciMemoizer(fibonacci)
+{}
+
+};
+
+}
+
+/**
+ * Testing result cache before and after a memoized call
+ */
+TEST_F(FibonacciMemoizerFixture, Uncached)
+{
+const auto res10 = fibonacci(10);
+
+// Fresh memoizer, input = 10 shouldn't be present
+ASSERT_FALSE(cached(10));
+
+// We are now memoizing the result and making sure
+// it provides the same value
+EXPECT_EQ((*this)(10), res10);
+
+// Now the fibonacci output for input = 10 should be cached
+ASSERT_TRUE(cached(10));
+}
+
+/**
+ * Just checking memoization works for multiple values
+ */
+TEST_F(FibonacciMemoizerFixture, MultipleValues)
+{
+const auto res0 = fibonacci(0);
+const auto res10 = fibonacci(10);
+const auto res20 = fibonacci(20);
+
+EXPECT_EQ((*this)(0), res0);
+EXPECT_EQ((*this)(10), res10);
+EXPECT_EQ((*this)(20), res20);
+
+EXPECT_EQ(cacheSize(), 3);
+
+EXPECT_TRUE(cached(0));
+EXPECT_TRUE(cached(10));
+EXPECT_TRUE(cached(20));
+
+// fibonacci(30) shouldn't be cached
+EXPECT_FALSE(cached(30));
+}
+
+/**
+ * Testing the Memoizer::flush method
+ */
+TEST_F(FibonacciMemoizerFixture, CacheFlush)
+{
+const auto res10 = fibonacci(10);
+
+ASSERT_EQ(cacheSize(), 0);
+
+// Memoizing fibonacci(10)
+EXPECT_EQ((*this)(10), res10);
+ASSERT_EQ(cacheSize(), 1);
+
+// Flushing the cache
+flush();
+
+// Cache should be empty now
+ASSERT_EQ(cacheSize(), 0);
+}
--
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Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Split purifyTaggedAddr in two sub-functions
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/59150 )
Change subject: arch-arm: Split purifyTaggedAddr in two sub-functions
..
arch-arm: Split purifyTaggedAddr in two sub-functions
This patch is splitting the purifyTaggedAddr helper in two
by introducing the maskTaggedAddress utility
* The first part computes the top bit of the address (computeAddrTop)
(This is required as the MSBs of a VA could be used to store
tags like in FEAT_Pauth)
* The second part applies some masking to the supplied
address (maskTaggedAddress) depending on the top bit to
purify the VA from the TAG
The motivation of this split will be clear in the next patch:
we want to memoize the expensive computeAddrTop. Memoizing
purifyTaggedAddr is inefficient as the first argument
is the VA of the memory request so multiple memory requests
will allocate multiple entries in the results cache and
memoization will rarely be used.
We will memoize the VA agnostic computeAddrTop instead
Change-Id: Ib3d8bb521be67a1f21c0891e753396299adf500b
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 6852aed..d9649a6 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -469,6 +469,22 @@
int res = (tbi && (!tbid || !is_instr))? 55: 63;
return res;
}
+
+Addr
+maskTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
+ int topbit)
+{
+if (topbit == 63) {
+return addr;
+} else if (bits(addr,55) && (el <= EL1 || ELIsInHost(tc, el))) {
+uint64_t mask = ((uint64_t)0x1 << topbit) -1;
+addr = addr | ~mask;
+} else {
+addr = bits(addr, topbit, 0);
+}
+return addr; // Nothing to do if this is not a tagged address
+}
+
Addr
purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
TCR tcr, bool is_instr)
@@ -476,15 +492,7 @@
bool selbit = bits(addr, 55);
int topbit = computeAddrTop(tc, selbit, is_instr, tcr, el);
-if (topbit == 63) {
-return addr;
-} else if (selbit && (el == EL1 || el == EL0 || ELIsInHost(tc, el))) {
-uint64_t mask = ((uint64_t)0x1 << topbit) -1;
-addr = addr | ~mask;
-} else {
-addr = bits(addr, topbit, 0);
-}
-return addr; // Nothing to do if this is not a tagged address
+return maskTaggedAddr(addr, tc, el, topbit);
}
Addr
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 00b0acf..523061b 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2016-2020 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2020, 2022 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -207,6 +207,8 @@
TCR tcr, bool isInstr);
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
bool isInstr);
+Addr maskTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
+int topbit);
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
TCR tcr, ExceptionLevel el);
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ib3d8bb521be67a1f21c0891e753396299adf500b
Gerrit-Change-Number: 59150
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: dev: Add a special reset interface to consolidate reset logic
t specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "dev/reset_port.hh"
+
+#include "base/logging.hh"
+
+namespace gem5
+{
+
+void
+ResetRequestPort::bind(Port )
+{
+peer = dynamic_cast();
+fatal_if(peer == nullptr, "Attempt to bind reset request port %s to "
+"incompatible port %s.", name(), p.name());
+Port::bind(p);
+}
+
+void
+ResetRequestPort::unbind()
+{
+peer = nullptr;
+Port::unbind();
+}
+
+void
+ResetRequestPort::requestReset()
+{
+peer->requestReset();
+}
+
+} // namespace gem5
diff --git a/src/dev/reset_port.hh b/src/dev/reset_port.hh
new file mode 100644
index 000..2846900
--- /dev/null
+++ b/src/dev/reset_port.hh
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2022 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DEV_RESET_PORT_HH__
+#define __DEV_RESET_PORT_HH__
+
+#include "sim/port.hh"
+
+#include
+
+namespace gem5
+{
+
+class ResetResponsePortBase : public Port
+{
+ public:
+using Port::Port;
+virtual void requestReset() = 0;
+};
+
+template
+class ResetResponsePort : public ResetResponsePortBase
+{
+ public:
+ResetResponsePort(const std::string , PortID id, Device *dev) :
+ResetResponsePortBase(name, id), device(dev) {}
+void requestReset() override { device->requestReset(); }
+
+ private:
+Device *device = nullptr;
+};
+
+class ResetRequestPort : public Port
+{
+ public:
+using Port::Port;
+void bind(Port ) override;
+void unbind() override;
+void requestReset();
+
+ private:
+ResetResponsePortBase *peer = nullptr;
+};
+
+} // namespace gem5
+
+#endif // __DEV_RESET_PORT_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I746121d16441e021dc3392aeae1a6d9fa33d637a
Gerrit-Change-Number: 58810
Gerrit-PatchSet: 4
Gerrit-Owner: Yu-hsin Wang
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Philip Metzler
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexR52 model reset port
eset debug APB. +this->dbg_reset.signal_out.set_state(0, true); +this->dbg_reset.signal_out.set_state(0, false); +} + Port _getPort(const std::string _name, int idx) override; void -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58813 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa Gerrit-Change-Number: 58813 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-hsin Wang Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-CC: Philip Metzler Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexA76 model reset port
quot; +#include "dev/reset_port.hh" #include "mem/port_proxy.hh" #include "params/FastModelScxEvsCortexA76x1.hh" #include "params/FastModelScxEvsCortexA76x2.hh" @@ -98,6 +99,8 @@ SignalSender dbg_reset; +ResetResponsePort model_reset; + CortexA76Cluster *gem5CpuCluster; const Params @@ -126,6 +129,8 @@ void setCluster(SimObject *cluster) override; void setResetAddr(int core, Addr addr, bool secure) override; + +void requestReset(); }; struct ScxEvsCortexA76x1Types -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58814 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f Gerrit-Change-Number: 58814 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-hsin Wang Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-CC: Philip Metzler Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: nullptr in a DPRINTF statement
Kaustav Goswami has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/59109 )
Change subject: cpu: nullptr in a DPRINTF statement
..
cpu: nullptr in a DPRINTF statement
This change fixes the crashing of gem5 when `Branch` debug flag
is enabled. A DPRINTF statement had a nullptr. This change
prints `INVALID_TARGET` if the nullptr is encountered.
Signed-off-by: Kaustav Goswami
Change-Id: I40bd42c07de25a493a3dd1094a2fd8cc0ce0a79b
---
M src/cpu/pred/bpred_unit.cc
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc
index 0940ae1..0277580 100644
--- a/src/cpu/pred/bpred_unit.cc
+++ b/src/cpu/pred/bpred_unit.cc
@@ -335,10 +335,17 @@
while (!pred_hist.empty() &&
pred_hist.front().seqNum > squashed_sn) {
if (pred_hist.front().usedRAS) {
-DPRINTF(Branch, "[tid:%i] [squash sn:%llu]"
-" Restoring top of RAS to: %i,"
-" target: %s\n", tid, squashed_sn,
-pred_hist.front().RASIndex,
*pred_hist.front().RASTarget);
+if (pred_hist.front().RASTarget != nullptr)
+DPRINTF(Branch, "[tid:%i] [squash sn:%llu]"
+" Restoring top of RAS to: %i,"
+" target: %s\n", tid, squashed_sn,
+pred_hist.front().RASIndex,
+*pred_hist.front().RASTarget);
+else
+DPRINTF(Branch, "[tid:%i] [squash sn:%llu]"
+" Restoring top of RAS to: %i,"
+" target: INVALID_TARGET\n", tid, squashed_sn,
+pred_hist.front().RASIndex);
RAS[tid].restore(pred_hist.front().RASIndex,
pred_hist.front().RASTarget.get());
--
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Gerrit-Change-Id: I40bd42c07de25a493a3dd1094a2fd8cc0ce0a79b
Gerrit-Change-Number: 59109
Gerrit-PatchSet: 1
Gerrit-Owner: Kaustav Goswami
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Fix race condition in creating of resource dir
Bobby Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/59090 ) Change subject: stdlib: Fix race condition in creating of resource dir .. stdlib: Fix race condition in creating of resource dir Found via a failing weekly test: https://jenkins.gem5.org/job/weekly/46/ The following exception was thrown: ``` FileExistsError: [Errno 17] File exists: '/nobackup/jenkins/workspace/weekly/tests/gem5/resources' At: /usr/lib/python3.8/os.py(228): makedirs build/GCN3_X86/python/gem5/resources/resource.py(156): __init__ /nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py(192): build/GCN3_X86/python/m5/main.py(440): main ``` It was found that, in cases where the resource directory does not exist, there is a race condition between gem5 threads to create the directory. This patch fixes this so threads that lose this race continue normally. Change-Id: Ie3323c4df0b247e7830c5d3ab93a4d7f9224fe36 --- M src/python/gem5/resources/resource.py 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/src/python/gem5/resources/resource.py b/src/python/gem5/resources/resource.py index f03490b..f72215a 100644 --- a/src/python/gem5/resources/resource.py +++ b/src/python/gem5/resources/resource.py @@ -153,7 +153,12 @@ ) ) else: -os.makedirs(resource_directory) +# `exist_ok=True` here as, occasionally, if multiple instance of +# gem5 are started simultaneously, a race condition can exist to +# create the resource directory. Without `exit_ok=True`, threads +# which lose this race will thrown a `FileExistsError` exception. +# `exit_ok=True` ensures no exception is thrown. +os.makedirs(resource_directory, exist_ok=True) to_path = os.path.join(resource_directory, resource_name) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/59090 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie3323c4df0b247e7830c5d3ab93a4d7f9224fe36 Gerrit-Change-Number: 59090 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [M] Change in gem5/gem5[develop]: util: Add dockerfile for building GPUFS application
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/59051 )
Change subject: util: Add dockerfile for building GPUFS application
..
util: Add dockerfile for building GPUFS application
In order to compile binaries to run in GPUFS, users would either have to
install ROCm 4.2 locally, use something like docker, or build within
gem5 using KVM and copy the binary out. The simplest way of those is to
use docker. This minimal dockerfile contains only ROCm 4.2 and can build
binaries that will be placed on the host which can be run in gem5.
For example, current gem5-resources can be built for gem5 as follows:
cd util/dockerfiles/gpu-fs
docker build -t rocm42-build .
cd /path/to/gem5-resources/src/gpu/hip-samples
docker run --rm -u $UID:$GID -v ${PWD}:${PWD} \
-w ${PWD} rocm42-build make
Those binaries can then be run in gem5 using the
configs/example/gpufs/vega10_kvm.py script:
build/VEGA_X86/gem5.opt configs/example/gpufs/vega10_kvm.py --app \
/path/to/gem5-resources/src/gpu/hip-samples/bin/MatrixTranspose
Change-Id: Ie76146be0ccf6fcc1941322cacc15965fe70073a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59051
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
Tested-by: kokoro
---
A util/dockerfiles/gpu-fs/Dockerfile
1 file changed, 91 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/dockerfiles/gpu-fs/Dockerfile
b/util/dockerfiles/gpu-fs/Dockerfile
new file mode 100644
index 000..eae6b76
--- /dev/null
+++ b/util/dockerfiles/gpu-fs/Dockerfile
@@ -0,0 +1,56 @@
+# Copyright (c) 2022 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE
+# POSSIBILITY OF SUCH DAMAGE.
+
+FROM ubuntu:20.04
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
+libprotobuf-dev protobuf-compiler libprotoc-dev
libgoogle-perftools-dev \
+python3-dev python-is-python3 doxygen libboost-all-dev \
+libhdf5-serial-dev python3-pydot libpng-dev libelf-dev pkg-config
+
+# Requirements for ROCm
+RUN apt -y install cmake mesa-common-dev libgflags-dev libgoogle-glog-dev
+
+# Needed to get ROCm repo, build packages
+RUN apt -y install wget gnupg2 rpm
+
+# Get the radeon gpg key for apt repository
+RUN wget -q -O - https://repo.radeon.com/rocm/rocm.gpg.key | apt-key add -
+
+# Modify apt sources to pull from ROCm 4.2 repository only
+RUN echo 'deb [arch=amd64] https://repo.radeon.com/rocm/apt/4.2/ ubuntu
main' | tee /etc/apt/sources.list.d/rocm.list
+
+RUN apt-get update
+RUN apt -y install libnuma-dev
+
+# Install the ROCm-dkms source
+RUN apt -y install initramfs-tools
+RUN apt -y install rocm-dkms
--
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Gerrit-Change-Number: 59051
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason
