[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB a...
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/19188 )
Change subject: cpu: Added the Multiperspective Perceptron Predictor with
TAGE (8KB and 64KB)
..
cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and
64KB)
Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).
Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro
Maintainer: Andreas Sandberg
Reviewed-by: Ilias Vougioukas
---
M src/cpu/pred/BranchPredictor.py
M src/cpu/pred/SConscript
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
A src/cpu/pred/multiperspective_perceptron_tage.cc
A src/cpu/pred/multiperspective_perceptron_tage.hh
A src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
A src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
A src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
A src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.cc
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/pred/tage_sc_l_8KB.cc
M src/cpu/pred/tage_sc_l_8KB.hh
22 files changed, 1,909 insertions(+), 77 deletions(-)
Approvals:
Ilias Vougioukas: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/pred/BranchPredictor.py
b/src/cpu/pred/BranchPredictor.py
index 967489a..1196405 100644
--- a/src/cpu/pred/BranchPredictor.py
+++ b/src/cpu/pred/BranchPredictor.py
@@ -133,6 +133,7 @@
logUResetPeriod = Param.Unsigned(18,
"Log period in number of branches to reset TAGE useful counters")
numUseAltOnNa = Param.Unsigned(1, "Number of USE_ALT_ON_NA counters")
+initialTCounterValue = Param.Int(1 << 17, "Initial value of tCounter")
useAltOnNaBits = Param.Unsigned(4, "Size of the USE_ALT_ON_NA
counter(s)")
maxNumAlloc = Param.Unsigned(1,
@@ -210,6 +211,7 @@
pathHistBits = 27
maxNumAlloc = 2
logUResetPeriod = 10
+initialTCounterValue = 1 << 9
useAltOnNaBits = 5
# TODO No speculation implemented as of now
speculativeHistUpdate = False
@@ -334,14 +336,20 @@
bwnb = Param.Unsigned("Num global backward branch GEHL lengths")
bwm = VectorParam.Int("Global backward branch GEHL lengths")
logBwnb = Param.Unsigned("Log num of global backward branch GEHL
entries")
+bwWeightInitValue = Param.Int(
+ "Initial value of the weights of the global backward branch GEHL
entries")
lnb = Param.Unsigned("Num first local history GEHL lenghts")
lm = VectorParam.Int("First local history GEHL lengths")
logLnb = Param.Unsigned("Log number of first local history GEHL
entries")
+lWeightInitValue = Param.Int(
+"Initial value of the weights of the first local history GEHL
entries")
inb = Param.Unsigned(1, "Num IMLI GEHL lenghts")
im = VectorParam.Int([8], "IMLI history GEHL lengths")
logInb = Param.Unsigned("Log number of IMLI GEHL entries")
+iWeightInitValue = Param.Int(
+"Initial value of the weights of the IMLI history GEHL entries")
logBias = Param.Unsigned("Log size of Bias tables")
@@ -362,6 +370,9 @@
scCountersWidth = Param.Unsigned(6, "Statistical corrector counters
width")
+initialUpdateThresholdValue = Param.Int(0,
+"Initial pUpdate threshold counter value")
+
# TAGE-SC-L branch predictor as desribed in
# https://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf
# It is a modified LTAGE predictor plus a statistical corrector predictor
@@ -425,12 +436,15 @@
bwnb = 3
bwm = [40, 24, 10]
logBwnb = 10
+bwWeightInitValue = 7
lnb = 3
lm = [11, 6, 3]
logLnb = 10
+lWeightInitValue = 7
logInb = 8
+iWeightInitValue = 7
class TAGE_SC_L_8KB_StatisticalCorrector(StatisticalCorrector):
type = 'TAGE_SC_L_8KB_StatisticalCorrector'
@@ -447,12 +461,15 @@
bwnb = 2
logBwnb = 7
bwm = [16, 8]
+bwWeightInitValue = 7
lnb = 2
logLnb = 7
lm = [6, 3]
+lWeightInitValue = 7
logInb = 7
+iWeightInitValue = 7
# 64KB TAGE-SC-L branch predictor as described in
# http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf
@@ -536,6 +553,9 @@
speculative_update = Param.Bool(False,
"Use speculative update for histories")
+initial_ghist_length = Param.Int(1, "Initial GHist length value")
+ignore_path_size = Param.Bool(False, "Ignore the path storage")
+
class Multiperspectiv
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB a...
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Ilias Vougioukas, Dam Sunwoo, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19188 to look at the new patch set (#2). Change subject: cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor with TAGE." Championship Branch Prediction (CBP-5) (2016). Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript M src/cpu/pred/loop_predictor.cc M src/cpu/pred/loop_predictor.hh M src/cpu/pred/multiperspective_perceptron.cc M src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_tage.cc A src/cpu/pred/multiperspective_perceptron_tage.hh A src/cpu/pred/multiperspective_perceptron_tage_64KB.cc A src/cpu/pred/multiperspective_perceptron_tage_64KB.hh A src/cpu/pred/multiperspective_perceptron_tage_8KB.cc A src/cpu/pred/multiperspective_perceptron_tage_8KB.hh M src/cpu/pred/statistical_corrector.cc M src/cpu/pred/statistical_corrector.hh M src/cpu/pred/tage_base.cc M src/cpu/pred/tage_base.hh M src/cpu/pred/tage_sc_l.cc M src/cpu/pred/tage_sc_l.hh M src/cpu/pred/tage_sc_l_64KB.cc M src/cpu/pred/tage_sc_l_64KB.hh M src/cpu/pred/tage_sc_l_8KB.cc M src/cpu/pred/tage_sc_l_8KB.hh 22 files changed, 1,909 insertions(+), 77 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19188 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069 Gerrit-Change-Number: 19188 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Dam Sunwoo Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: kokoro Gerrit-CC: Juha Jäykkä Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB a...
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19188
Change subject: cpu: Added the Multiperspective Perceptron Predictor with
TAGE (8KB and 64KB)
..
cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and
64KB)
Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).
Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
---
M src/cpu/pred/BranchPredictor.py
M src/cpu/pred/SConscript
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/multiperspective_perceptron.cc
M src/cpu/pred/multiperspective_perceptron.hh
A src/cpu/pred/multiperspective_perceptron_tage.cc
A src/cpu/pred/multiperspective_perceptron_tage.hh
A src/cpu/pred/multiperspective_perceptron_tage_64KB.cc
A src/cpu/pred/multiperspective_perceptron_tage_64KB.hh
A src/cpu/pred/multiperspective_perceptron_tage_8KB.cc
A src/cpu/pred/multiperspective_perceptron_tage_8KB.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
M src/cpu/pred/tage_sc_l_64KB.cc
M src/cpu/pred/tage_sc_l_64KB.hh
M src/cpu/pred/tage_sc_l_8KB.cc
M src/cpu/pred/tage_sc_l_8KB.hh
22 files changed, 1,875 insertions(+), 75 deletions(-)
diff --git a/src/cpu/pred/BranchPredictor.py
b/src/cpu/pred/BranchPredictor.py
index 967489a..83f3621 100644
--- a/src/cpu/pred/BranchPredictor.py
+++ b/src/cpu/pred/BranchPredictor.py
@@ -334,14 +334,20 @@
bwnb = Param.Unsigned("Num global backward branch GEHL lengths")
bwm = VectorParam.Int("Global backward branch GEHL lengths")
logBwnb = Param.Unsigned("Log num of global backward branch GEHL
entries")
+bwWeightInitValue = Param.Int(
+ "Initial value of the weights of the global backward branch GEHL
entries")
lnb = Param.Unsigned("Num first local history GEHL lenghts")
lm = VectorParam.Int("First local history GEHL lengths")
logLnb = Param.Unsigned("Log number of first local history GEHL
entries")
+lWeightInitValue = Param.Int(
+"Initial value of the weights of the first local history GEHL
entries")
inb = Param.Unsigned(1, "Num IMLI GEHL lenghts")
im = VectorParam.Int([8], "IMLI history GEHL lengths")
logInb = Param.Unsigned("Log number of IMLI GEHL entries")
+iWeightInitValue = Param.Int(
+"Initial value of the weights of the IMLI history GEHL entries")
logBias = Param.Unsigned("Log size of Bias tables")
@@ -362,6 +368,9 @@
scCountersWidth = Param.Unsigned(6, "Statistical corrector counters
width")
+initialUpdateThresholdValue = Param.Int(0,
+"Initial pUpdate threshold counter value")
+
# TAGE-SC-L branch predictor as desribed in
# https://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf
# It is a modified LTAGE predictor plus a statistical corrector predictor
@@ -425,12 +434,15 @@
bwnb = 3
bwm = [40, 24, 10]
logBwnb = 10
+bwWeightInitValue = 7
lnb = 3
lm = [11, 6, 3]
logLnb = 10
+lWeightInitValue = 7
logInb = 8
+iWeightInitValue = 7
class TAGE_SC_L_8KB_StatisticalCorrector(StatisticalCorrector):
type = 'TAGE_SC_L_8KB_StatisticalCorrector'
@@ -447,12 +459,15 @@
bwnb = 2
logBwnb = 7
bwm = [16, 8]
+bwWeightInitValue = 7
lnb = 2
logLnb = 7
lm = [6, 3]
+lWeightInitValue = 7
logInb = 7
+iWeightInitValue = 7
# 64KB TAGE-SC-L branch predictor as described in
# http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf
@@ -536,6 +551,9 @@
speculative_update = Param.Bool(False,
"Use speculative update for histories")
+initial_ghist_length = Param.Int(1, "Initial GHist length value")
+ignore_path_size = Param.Bool(False, "Ignore the path storage")
+
class MultiperspectivePerceptron8KB(MultiperspectivePerceptron):
type = 'MultiperspectivePerceptron8KB'
cxx_class = 'MultiperspectivePerceptron8KB'
@@ -557,3 +575,175 @@
imli_mask1 = 0xc1000
imli_mask4 = 0x80008000
recencypos_mask = 0x10090
+
+class MPP_TAGE(TAGEBase):
+type = 'MPP_TAGE'
+cxx_class = 'MPP_TAGE'
+cxx_header = 'cpu/pred/multiperspective_perceptron_tage.hh'
+nHistoryTables = 15
+pathHistBits = 27
+instShiftAmt = 0
+histBufferSize = 16384
+maxHist = 4096;
+tagTableTagWidths = [0, 7, 9, 9, 9, 10, 11, 11, 12, 12,
+ 12, 13, 14, 15, 15, 15]
+logTagTableSizes = [14, 10, 11, 11, 11, 11, 11, 12, 12,
+ 10, 11, 11, 9, 7, 7, 8]
+tunedHistoryLengths = VectorParam.Unsigned([0, 5, 12, 15, 21, 31, 43,
64,
+93, 137, 200, 292, 424, 612, 877, 1241], "Tuned history lengths")
+
+logUResetPeriod = 10
+numUseAltOn
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15495 )
Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB
and 64KB)
..
cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).
Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg
Reviewed-by: Ilias Vougioukas
Tested-by: kokoro
---
M src/cpu/pred/BranchPredictor.py
M src/cpu/pred/SConscript
A src/cpu/pred/multiperspective_perceptron.cc
A src/cpu/pred/multiperspective_perceptron.hh
A src/cpu/pred/multiperspective_perceptron_64KB.cc
A src/cpu/pred/multiperspective_perceptron_64KB.hh
A src/cpu/pred/multiperspective_perceptron_8KB.cc
A src/cpu/pred/multiperspective_perceptron_8KB.hh
8 files changed, 2,191 insertions(+), 0 deletions(-)
Approvals:
Ilias Vougioukas: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/pred/BranchPredictor.py
b/src/cpu/pred/BranchPredictor.py
index 9c59574..967489a 100644
--- a/src/cpu/pred/BranchPredictor.py
+++ b/src/cpu/pred/BranchPredictor.py
@@ -475,3 +475,85 @@
tage = TAGE_SC_L_TAGE_8KB()
loop_predictor = TAGE_SC_L_8KB_LoopPredictor()
statistical_corrector = TAGE_SC_L_8KB_StatisticalCorrector()
+
+class MultiperspectivePerceptron(BranchPredictor):
+type = 'MultiperspectivePerceptron'
+cxx_class = 'MultiperspectivePerceptron'
+cxx_header = 'cpu/pred/multiperspective_perceptron.hh'
+abstract = True
+
+num_filter_entries = Param.Int("Number of filter entries")
+num_local_histories = Param.Int("Number of local history entries")
+local_history_length = Param.Int(11,
+"Length in bits of each history entry")
+
+block_size = Param.Int(21,
+"number of ghist bits in a 'block'; this is the width of an
initial "
+"hash of ghist")
+pcshift = Param.Int(-10, "Shift for hashing PC")
+threshold = Param.Int(1, "Threshold for deciding low/high confidence")
+bias0 = Param.Int(-5,
+"Bias perceptron output this much on all-bits-zero local history")
+bias1 = Param.Int(5,
+"Bias perceptron output this much on all-bits-one local history")
+biasmostly0 = Param.Int(-1,
+"Bias perceptron output this much on almost-all-bits-zero local "
+"history")
+biasmostly1 = Param.Int(1,
+"Bias perceptron output this much on almost-all-bits-one local "
+"history")
+nbest = Param.Int(20,
+"Use this many of the top performing tables on a low-confidence "
+"branch")
+tunebits = Param.Int(24, "Number of bits in misprediction counters")
+hshift = Param.Int(-6,
+"How much to shift initial feauture hash before XORing with PC
bits")
+imli_mask1 = Param.UInt64(
+"Which tables should have their indices hashed with the first
IMLI "
+"counter")
+imli_mask4 = Param.UInt64(
+"Which tables should have their indices hashed with the fourth
IMLI "
+"counter")
+recencypos_mask = Param.UInt64(
+"Which tables should have their indices hashed with the recency "
+"position")
+fudge = Param.Float(0.245, "Fudge factor to multiply by perceptron
output")
+n_sign_bits = Param.Int(2, "Number of sign bits per magnitude")
+pcbit = Param.Int(2, "Bit from the PC to use for hashing global
history")
+decay = Param.Int(0, "Whether and how often to decay a random weight")
+record_mask = Param.Int(191,
+"Which histories are updated with filtered branch outcomes")
+hash_taken = Param.Bool(False,
+"Hash the taken/not taken value with a PC bit")
+tuneonly = Param.Bool(True,
+"If true, only count mispredictions of low-confidence branches")
+extra_rounds = Param.Int(1,
+"Number of extra rounds of training a single weight on a "
+"low-confidence prediction")
+speed = Param.Int(9, "Adaptive theta learning speed")
+initial_theta = Param.Int(10, "Initial theta")
+budgetbits = Param.Int("Hardware budget in bits")
+speculative_update = Param.Bool(False,
+"Use speculative update for histories")
+
+class MultiperspectivePerceptron8KB(MultiperspectivePerceptron):
+type = 'MultiperspectivePerceptron8KB'
+cxx_class = 'MultiperspectivePerceptron8KB'
+cxx_header = 'cpu/pred/multiperspective_perceptron_8KB.hh'
+budgetbits = 8192 * 8 + 2048
+num_local_histories = 48
+num_filter_entries = 0
+imli_mask1 = 0x6
+imli_mask4 = 0x4400
+recencypos_mask = 0x10090
+
+class MultiperspectivePerceptron64KB(MultiperspectivePerceptron):
+type = 'Multiper
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Ilias Vougioukas, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 to look at the new patch set (#14). Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/multiperspective_perceptron.cc A src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_64KB.cc A src/cpu/pred/multiperspective_perceptron_64KB.hh A src/cpu/pred/multiperspective_perceptron_8KB.cc A src/cpu/pred/multiperspective_perceptron_8KB.hh 8 files changed, 2,191 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Gerrit-Change-Number: 15495 Gerrit-PatchSet: 14 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Ilias Vougioukas, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 to look at the new patch set (#12). Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/multiperspective_perceptron.cc A src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_64KB.cc A src/cpu/pred/multiperspective_perceptron_64KB.hh A src/cpu/pred/multiperspective_perceptron_8KB.cc A src/cpu/pred/multiperspective_perceptron_8KB.hh 8 files changed, 2,191 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Gerrit-Change-Number: 15495 Gerrit-PatchSet: 12 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Ilias Vougioukas, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 to look at the new patch set (#11). Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/multiperspective_perceptron.cc A src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_64KB.cc A src/cpu/pred/multiperspective_perceptron_64KB.hh A src/cpu/pred/multiperspective_perceptron_8KB.cc A src/cpu/pred/multiperspective_perceptron_8KB.hh M tests/jenkins/presubmit.sh 9 files changed, 2,189 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Gerrit-Change-Number: 15495 Gerrit-PatchSet: 11 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Accuracy-based rate control for prefetchers
e/prefetch/queued.hh index 1ffbc9a..ae4c5e4 100644 --- a/src/mem/cache/prefetch/queued.hh +++ b/src/mem/cache/prefetch/queued.hh @@ -163,6 +163,9 @@ /** Tag prefetch with PC of generating access? */ const bool tagPrefetch; +/** Percentage of requests that can be throttled */ +const unsigned int throttleControlPct; + // STATS Stats::Scalar pfIdentified; Stats::Scalar pfBufferHit; @@ -229,6 +232,16 @@ bool alreadyInQueue(std::list &queue, const PrefetchInfo &pfi, int32_t priority); +/** + * Returns the maxmimum number of prefetch requests that are allowed + * to be created from the number of prefetch candidates provided. + * The behavior of this service is controlled with the throttleControlPct + * parameter. + * @param total number of prefetch candidates generated by the prefetcher + * @return the number of these request candidates are allowed to be created + */ +size_t getMaxPermittedPrefetches(size_t total) const; + RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt); }; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18808 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a Gerrit-Change-Number: 18808 Gerrit-PatchSet: 6 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
ze block size used by the prefetcher
+ * @param mid Requester ID of the access that generated this
prefetch
+ * @param tag_prefetch flag to indicate if the packet needs to be
+ *tagged
+ * @param t time when the prefetch becomes ready
+ */
+void createPkt(Addr paddr, unsigned blk_size, MasterID mid,
+ bool tag_prefetch, Tick t);
+
+/**
+ * Sets the translation request needed to obtain the physical
address
+ * of this request.
+ * @param req The Request with the virtual address of this request
+ */
+void setTranslationRequest(const RequestPtr &req)
+{
+translationRequest = req;
+}
+
+void markDelayed() override
+{}
+
+void finish(const Fault &fault, const RequestPtr &req,
+ThreadContext *tc, BaseTLB::Mode mode)
override;
+
+/**
+ * Issues the translation request to the provided TLB
+ * @param tlb the tlb that has to translate the address
+ */
+void startTranslation(BaseTLB *tlb);
};
std::list pfq;
+std::list pfqMissingTranslation;
+
+using const_iterator = std::list::const_iterator;
+using iterator = std::list::iterator;
// PARAMETERS
/** Maximum size of the prefetch queue */
const unsigned queueSize;
+/**
+ * Maximum size of the queue holding prefetch requests with missing
+ * address translations
+ */
+const unsigned missingTranslationQueueSize;
+
/** Cycles after generation when a prefetch can first be issued */
const Cycles latency;
@@ -112,11 +163,6 @@
/** Tag prefetch with PC of generating access? */
const bool tagPrefetch;
-using const_iterator = std::list::const_iterator;
-const_iterator inPrefetch(const PrefetchInfo &pfi) const;
-using iterator = std::list::iterator;
-iterator inPrefetch(const PrefetchInfo &pfi);
-
// STATS
Stats::Scalar pfIdentified;
Stats::Scalar pfBufferHit;
@@ -144,6 +190,47 @@
}
void regStats() override;
+
+ private:
+
+/**
+ * Adds a DeferredPacket to the specified queue
+ * @param queue selected queue to use
+ * @param dpp DeferredPacket to add
+ */
+void addToQueue(std::list &queue, DeferredPacket &dpp);
+
+/**
+ * Starts the translations of the queued prefetches with a
+ * missing translation. It performs a maximum specified number of
+ * translations. Successful translations cause the prefetch request to
be
+ * queued in the queue of ready requests.
+ * @param max maximum number of translations to perform
+ */
+void processMissingTranslations(unsigned max);
+
+/**
+ * Indicates that the translation of the address of the provided
deferred
+ * packet has been successfully completed, and it can be enqueued as a
+ * new prefetch request.
+ * @param dp the deferred packet that has completed the translation
request
+ * @param failed whether the translation was successful
+ */
+void translationComplete(DeferredPacket *dp, bool failed);
+
+/**
+ * Checks whether the specified prefetch request is already in the
+ * specified queue. If the request is found, its priority is updated.
+ * @param queue selected queue to check
+ * @param pfi information of the prefetch request to be added
+ * @param priority priority of the prefetch request to be added
+ * @return True if the prefetch request was found in the queue
+ */
+bool alreadyInQueue(std::list &queue,
+const PrefetchInfo &pfi, int32_t priority);
+
+RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi,
+PacketPtr pkt);
};
#endif //__MEM_CACHE_PREFETCH_QUEUED_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
Gerrit-Change-Number: 14620
Gerrit-PatchSet: 22
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Ivan Pizarro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, kokoro, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#21). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 5 files changed, 388 insertions(+), 112 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 21 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Ilias Vougioukas, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 to look at the new patch set (#10). Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/multiperspective_perceptron.cc A src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_64KB.cc A src/cpu/pred/multiperspective_perceptron_64KB.hh A src/cpu/pred/multiperspective_perceptron_8KB.cc A src/cpu/pred/multiperspective_perceptron_8KB.hh M tests/jenkins/presubmit.sh 9 files changed, 2,188 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Gerrit-Change-Number: 15495 Gerrit-PatchSet: 10 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Accuracy-based rate control for prefetchers
Hello Andreas Sandberg, kokoro, Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18808 to look at the new patch set (#3). Change subject: mem-cache: Accuracy-based rate control for prefetchers .. mem-cache: Accuracy-based rate control for prefetchers Added a mechanism to control the number of prefetches generated based in the effectiveness of the prefetches generated so far. Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 3 files changed, 65 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18808 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a Gerrit-Change-Number: 18808 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Accuracy-based rate control for prefetchers
Hello Andreas Sandberg, Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18808 to look at the new patch set (#2). Change subject: mem-cache: Accuracy-based rate control for prefetchers .. mem-cache: Accuracy-based rate control for prefetchers Added a mechanism to control the number of prefetches generated based in the effectiveness of the prefetches generated so far. Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 3 files changed, 53 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18808 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a Gerrit-Change-Number: 18808 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Accuracy-based rate control for prefetchers
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18808
Change subject: mem-cache: Accuracy-based rate control for prefetchers
..
mem-cache: Accuracy-based rate control for prefetchers
Added a mechanism to control the number of prefetches generated
based in the effectiveness of the prefetches generated so far.
Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index a45f662..304419e 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -122,6 +122,8 @@
cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant
request")
tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating
access")
+throttle_control_percentage = Param.Unsigned(0, "Percentage of
requests \
+that can be throttled depending on the accuracy of the
prefetcher.")
class StridePrefetcher(QueuedPrefetcher):
type = 'StridePrefetcher'
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index 12f4a36..c4dd0e1 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -96,8 +96,11 @@
p->max_prefetch_requests_with_pending_translation),
latency(p->latency), queueSquash(p->queue_squash),
queueFilter(p->queue_filter), cacheSnoop(p->cache_snoop),
- tagPrefetch(p->tag_prefetch)
+ tagPrefetch(p->tag_prefetch),
+ throttleControlPct(p->throttle_control_percentage)
{
+fatal_if(throttleControlPct > 100,
+"throttleControlPct must be a value between 0 and 100.");
}
QueuedPrefetcher::~QueuedPrefetcher()
@@ -132,7 +135,31 @@
std::vector addresses;
calculatePrefetch(pfi, addresses);
+/**
+ * Throttle generated prefetches based in the accuracy of the
prefetcher.
+ * Accuracy is computed based in the ratio of useful prefetches with
+ * respect to the number of issued prefetches.
+ *
+ * The throttleControlPct controls how many of the generated addresses
will
+ * be controled by the throttle control algorithm:
+ * - If set to 100, all requests can potentially be throttle (one
request
+ * will always be allowed to be generated)
+ * - Setting it to 0 will disable the throttle control
+ * - If set to 60, 40% of requests will be generated, and the remaining
+ * 60% will be generated depending on the mentioned accuracy
+ */
+
+size_t max_pfs = addresses.size();
+if (addresses.size() > 0 && issuedPrefetches > 0) {
+size_t throttle_pfs = (addresses.size() * throttleControlPct) /
100;
+size_t min_pfs = (addresses.size() - throttle_pfs) == 0 ?
+1 : (addresses.size() - throttle_pfs);
+max_pfs = min_pfs + (addresses.size() - min_pfs) *
+usefulPrefetches / issuedPrefetches;
+}
+
// Queue up generated prefetches
+size_t num_pfs = 0;
for (AddrPriority& addr_prio : addresses) {
// Block align prefetch address
@@ -150,6 +177,10 @@
"inserting into prefetch queue.\n", new_pfi.getAddr());
// Create and insert the request
insert(pkt, new_pfi, addr_prio.second);
+num_pfs += 1;
+if (num_pfs == max_pfs) {
+break;
+}
} else {
DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
}
diff --git a/src/mem/cache/prefetch/queued.hh
b/src/mem/cache/prefetch/queued.hh
index 1ffbc9a..5e56d2c 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -163,6 +163,9 @@
/** Tag prefetch with PC of generating access? */
const bool tagPrefetch;
+/** Percentage of requests that can be throttled */
+const unsigned int throttleControlPct;
+
// STATS
Stats::Scalar pfIdentified;
Stats::Scalar pfBufferHit;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18808
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a
Gerrit-Change-Number: 18808
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Do not check MustBeOne flag for TLB requests from the prefe...
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18768 )
Change subject: arch-arm: Do not check MustBeOne flag for TLB requests from
the prefetcher
..
arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher
Allow TLB requests generated from prefetchers to override the
MustBeOne arch flag. This allows the prefetchers to issue requests
without having to know architecutre-specific flags.
Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18768
Reviewed-by: Nikos Nikoleris
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/tlb.cc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 4b43a50..f30e195 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -586,7 +586,7 @@
bool is_write = (mode == Write);
if (!is_fetch) {
-assert(flags & MustBeOne);
+assert(flags & MustBeOne || req->isPrefetch());
if (sctlr.a || !(flags & AllowUnaligned)) {
if (vaddr & mask(flags & AlignmentMask)) {
// LPAE is always disabled in SE mode
@@ -1038,7 +1038,7 @@
req->setFlags(Request::STRICT_ORDER);
}
if (!is_fetch) {
-assert(flags & MustBeOne);
+assert(flags & MustBeOne || req->isPrefetch());
if (sctlr.a || !(flags & AllowUnaligned)) {
if (vaddr & mask(flags & AlignmentMask)) {
alignFaults++;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18768
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672
Gerrit-Change-Number: 18768
Gerrit-PatchSet: 2
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Sudhanshu Jha
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: configs: Fix duplicate branchPred reference in Simulation.py
Javier Bueno Hedo has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/18769 ) Change subject: configs: Fix duplicate branchPred reference in Simulation.py .. configs: Fix duplicate branchPred reference in Simulation.py Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18769 Tested-by: kokoro Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- M configs/common/Simulation.py 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 078ec0f..56107c1 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -486,7 +486,7 @@ if options.indirect_bp_type: IndirectBPClass = \ BPConfig.get_indirect(options.indirect_bp_type) -switch_cpus[i].branchPred.branchPred.indirectBranchPred = \ +switch_cpus[i].branchPred.indirectBranchPred = \ IndirectBPClass() # If elastic tracing is enabled attach the elastic trace probe -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18769 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c Gerrit-Change-Number: 18769 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: configs: Fix duplicate branchPred reference in Simulation.py
Javier Bueno Hedo has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/18769 Change subject: configs: Fix duplicate branchPred reference in Simulation.py .. configs: Fix duplicate branchPred reference in Simulation.py Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c --- M configs/common/Simulation.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 078ec0f..56107c1 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -486,7 +486,7 @@ if options.indirect_bp_type: IndirectBPClass = \ BPConfig.get_indirect(options.indirect_bp_type) -switch_cpus[i].branchPred.branchPred.indirectBranchPred = \ +switch_cpus[i].branchPred.indirectBranchPred = \ IndirectBPClass() # If elastic tracing is enabled attach the elastic trace probe -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18769 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c Gerrit-Change-Number: 18769 Gerrit-PatchSet: 1 Gerrit-Owner: Javier Bueno Hedo Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Do not check MustBeOne flag for TLB requests from the prefe...
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18768
Change subject: arch-arm: Do not check MustBeOne flag for TLB requests from
the prefetcher
..
arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher
Allow TLB requests generated from prefetchers to override the
MustBeOne arch flag. This allows the prefetchers to issue requests
without having to know architecutre-specific flags.
Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672
---
M src/arch/arm/tlb.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 4b43a50..f30e195 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -586,7 +586,7 @@
bool is_write = (mode == Write);
if (!is_fetch) {
-assert(flags & MustBeOne);
+assert(flags & MustBeOne || req->isPrefetch());
if (sctlr.a || !(flags & AllowUnaligned)) {
if (vaddr & mask(flags & AlignmentMask)) {
// LPAE is always disabled in SE mode
@@ -1038,7 +1038,7 @@
req->setFlags(Request::STRICT_ORDER);
}
if (!is_fetch) {
-assert(flags & MustBeOne);
+assert(flags & MustBeOne || req->isPrefetch());
if (sctlr.a || !(flags & AllowUnaligned)) {
if (vaddr & mask(flags & AlignmentMask)) {
alignFaults++;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18768
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672
Gerrit-Change-Number: 18768
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, kokoro, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#18). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 6 files changed, 391 insertions(+), 114 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 18 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, kokoro, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#17). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 6 files changed, 390 insertions(+), 113 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 17 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, kokoro, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#16). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 6 files changed, 392 insertions(+), 113 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 16 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, kokoro, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#15). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 6 files changed, 394 insertions(+), 112 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 15 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, kokoro, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#14). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 6 files changed, 404 insertions(+), 110 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 14 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#13). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 6 files changed, 396 insertions(+), 112 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 13 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Andreas Sandberg, Daniel Carvalho, Giacomo Travaglini, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#12). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 6 files changed, 395 insertions(+), 112 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 12 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Hello Andreas Sandberg, Giacomo Travaglini, Ilias Vougioukas, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 to look at the new patch set (#7). Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/multiperspective_perceptron.cc A src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_64KB.cc A src/cpu/pred/multiperspective_perceptron_64KB.hh A src/cpu/pred/multiperspective_perceptron_8KB.cc A src/cpu/pred/multiperspective_perceptron_8KB.hh 8 files changed, 2,187 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Gerrit-Change-Number: 15495 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: config: Add flag options to set the hardware prefetchers to use
IAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Pau Cabre
+
+# This file is a copy of MemConfig.py / CpuConfig.py, but modified to
+# hanle branch predictors instead of memory controllers / CPUs
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+from m5 import fatal
+import m5.objects
+import inspect
+import sys
+from textwrap import TextWrapper
+
+# Dictionary of mapping names of real branch predictor models to classes.
+_hwp_classes = {}
+
+
+def is_hwp_class(cls):
+"""Determine if a class is a prefetcher that can be instantiated"""
+
+# We can't use the normal inspect.isclass because the ParamFactory
+# and ProxyFactory classes have a tendency to confuse it.
+try:
+return issubclass(cls, m5.objects.BasePrefetcher) and \
+not cls.abstract
+except (TypeError, AttributeError):
+return False
+
+def get(name):
+"""Get a HWP class from a user provided class name or alias."""
+
+try:
+hwp_class = _hwp_classes[name]
+return hwp_class
+except KeyError:
+print("%s is not a valid HWP model." % (name,))
+sys.exit(1)
+
+def print_hwp_list():
+"""Print a list of available HWP classes."""
+
+print("Available Hardware Prefetcher classes:")
+doc_wrapper = TextWrapper(initial_indent="\t\t",
subsequent_indent="\t\t")
+for name, cls in _hwp_classes.items():
+print("\t%s" % name)
+
+# Try to extract the class documentation from the class help
+# string.
+doc = inspect.getdoc(cls)
+if doc:
+for line in doc_wrapper.wrap(doc):
+print(line)
+
+def hwp_names():
+"""Return a list of valid Hardware Prefetcher names."""
+return list(_hwp_classes.keys())
+
+# Add all HWPs in the object hierarchy.
+for name, cls in inspect.getmembers(m5.objects, is_hwp_class):
+_hwp_classes[name] = cls
+
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 6d9c9cf..58078ec 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -48,6 +48,7 @@
from .Benchmarks import *
from . import CpuConfig
from . import BPConfig
+from . import HWPConfig
from . import MemConfig
from . import PlatformConfig
@@ -59,6 +60,10 @@
BPConfig.print_bp_list()
sys.exit(0)
+def _listHWPTypes(option, opt, value, parser):
+HWPConfig.print_hwp_list()
+sys.exit(0)
+
def _listMemTypes(option, opt, value, parser):
MemConfig.print_mem_list()
sys.exit(0)
@@ -163,6 +168,29 @@
type of branch predictor to run with
(if not set, use the default branch predictor of
the selected CPU)""")
+parser.add_option("--list-hwp-types",
+ action="callback", callback=_listHWPTypes,
+ help="List available hardware prefetcher types")
+parser.add_option("--l1i-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L1
+ instruction cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
+parser.add_option("--l1d-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L1
+ data cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
+parser.add_option("--l2-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L2 cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
parser.add_option("--checker", action="store_true");
parser.add_option("--cpu-clock", action="store", type="string",
default='2GHz',
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17709
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I310fcd9c49f9554d98cd565a32bdb96a3e165486
Gerrit-Change-Number: 17709
Gerrit-PatchSet: 3
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: AMPM Prefetcher fails when restoring from a checkpoint
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17732 )
Change subject: mem-cache: AMPM Prefetcher fails when restoring from a
checkpoint
..
mem-cache: AMPM Prefetcher fails when restoring from a checkpoint
The preriodic event triggers an assertion due to an incorrect tick value to
schedule when restoring from a checkpoint.
Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/access_map_pattern_matching.hh
2 files changed, 8 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
diff --git a/src/mem/cache/prefetch/access_map_pattern_matching.cc
b/src/mem/cache/prefetch/access_map_pattern_matching.cc
index df2a9f7..731d606 100644
--- a/src/mem/cache/prefetch/access_map_pattern_matching.cc
+++ b/src/mem/cache/prefetch/access_map_pattern_matching.cc
@@ -57,9 +57,12 @@
{
fatal_if(!isPowerOf2(hotZoneSize),
"the hot zone size must be a power of 2");
-if (!epochEvent.scheduled()) {
-schedule(epochEvent, clockEdge(epochCycles));
-}
+}
+
+void
+AccessMapPatternMatching::startup()
+{
+schedule(epochEvent, clockEdge(epochCycles));
}
void
@@ -153,6 +156,7 @@
std::vector &addresses)
{
assert(addresses.empty());
+
bool is_secure = pfi.isSecure();
Addr am_addr = pfi.getAddr() / hotZoneSize;
Addr current_block = (pfi.getAddr() % hotZoneSize) / blkSize;
diff --git a/src/mem/cache/prefetch/access_map_pattern_matching.hh
b/src/mem/cache/prefetch/access_map_pattern_matching.hh
index 0968e64..397bc78 100644
--- a/src/mem/cache/prefetch/access_map_pattern_matching.hh
+++ b/src/mem/cache/prefetch/access_map_pattern_matching.hh
@@ -180,6 +180,7 @@
AccessMapPatternMatching(const AccessMapPatternMatchingParams* p);
~AccessMapPatternMatching()
{}
+void startup() override;
void calculatePrefetch(const BasePrefetcher::PrefetchInfo &pfi,
std::vector &addresses);
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17732
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Gerrit-Change-Number: 17732
Gerrit-PatchSet: 3
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Assignee: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: AMPM Prefetcher fails when restoring from a checkpoint
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17732 to look at the new patch set (#2). Change subject: mem-cache: AMPM Prefetcher fails when restoring from a checkpoint .. mem-cache: AMPM Prefetcher fails when restoring from a checkpoint The preriodic event triggers an assertion due to an incorrect tick value to schedule when restoring from a checkpoint. Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c --- M src/mem/cache/prefetch/access_map_pattern_matching.cc M src/mem/cache/prefetch/access_map_pattern_matching.hh 2 files changed, 8 insertions(+), 3 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17732 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c Gerrit-Change-Number: 17732 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17731 )
Change subject: mem-cache: Fix PIF prefetcher compilation error with NULL
ISA
..
mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.
Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/Prefetcher.py
1 file changed, 2 insertions(+), 3 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 404a442..aaa1408 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -43,7 +43,6 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.BaseCPU import BaseCPU
from m5.objects.ClockedObject import ClockedObject
from m5.objects.IndexingPolicies import *
from m5.objects.ReplacementPolicies import *
@@ -481,6 +480,6 @@
"Replacement policy of the index")
def listenFromProbeRetiredInstructions(self, simObj):
-if not isinstance(simObj, BaseCPU):
-raise TypeError("argument must be of BaseCPU type")
+if not isinstance(simObj, SimObject):
+raise TypeError("argument must be of SimObject type")
self.addEvent(HWPProbeEventRetiredInsts(self,
simObj,"RetiredInstsPC"))
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17731
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Gerrit-Change-Number: 17731
Gerrit-PatchSet: 3
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Ryan Gambord
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Hello Nikos Nikoleris, Ryan Gambord, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17731 to look at the new patch set (#2). Change subject: mem-cache: Fix PIF prefetcher compilation error with NULL ISA .. mem-cache: Fix PIF prefetcher compilation error with NULL ISA Referencing BaseCPU is causing a compilation error when using the NULL ISA. This patch changes the reference to a SimObject, which fixes the problem. Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26 --- M src/mem/cache/prefetch/Prefetcher.py 1 file changed, 2 insertions(+), 3 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17731 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26 Gerrit-Change-Number: 17731 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Ryan Gambord Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: ISB prefetcher was triggering an assertion
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17734 )
Change subject: mem-cache: ISB prefetcher was triggering an assertion
..
mem-cache: ISB prefetcher was triggering an assertion
An assertion ignored the case when an entry of the SP table had been
invalidated.
Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734
Reviewed-by: Daniel Carvalho
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/irregular_stream_buffer.cc
1 file changed, 4 insertions(+), 1 deletion(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
diff --git a/src/mem/cache/prefetch/irregular_stream_buffer.cc
b/src/mem/cache/prefetch/irregular_stream_buffer.cc
index 45aba0b..345fe70 100644
--- a/src/mem/cache/prefetch/irregular_stream_buffer.cc
+++ b/src/mem/cache/prefetch/irregular_stream_buffer.cc
@@ -147,7 +147,10 @@
Addr sp_index = mapping.address % prefetchCandidatesPerEntry;
AddressMappingEntry *sp_am =
spAddressMappingCache.findEntry(sp_address, is_secure);
-assert(sp_am != nullptr);
+if (sp_am == nullptr) {
+// The entry has been evicted, can not generate prefetches
+return;
+}
for (unsigned d = 1;
d <= degree && (sp_index + d) <
prefetchCandidatesPerEntry;
d += 1)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17734
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Gerrit-Change-Number: 17734
Gerrit-PatchSet: 2
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix panic in Indirect Memory prefetcher
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17733 )
Change subject: mem-cache: Fix panic in Indirect Memory prefetcher
..
mem-cache: Fix panic in Indirect Memory prefetcher
Memory requests with a size non-power-of-two and less than 8 values were
causing
a panic, but there these should be allowed and ignored by the prefetcher.
Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/indirect_memory.cc
1 file changed, 5 insertions(+), 3 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
diff --git a/src/mem/cache/prefetch/indirect_memory.cc
b/src/mem/cache/prefetch/indirect_memory.cc
index 393958c..d49652f 100644
--- a/src/mem/cache/prefetch/indirect_memory.cc
+++ b/src/mem/cache/prefetch/indirect_memory.cc
@@ -108,6 +108,7 @@
if (!miss && !pfi.isWrite() && pfi.getSize() <= 8) {
int64_t index = 0;
+bool read_index = true;
switch(pfi.getSize()) {
case sizeof(uint8_t):
index = pfi.get(byteOrder);
@@ -122,14 +123,15 @@
index = pfi.get(byteOrder);
break;
default:
-panic("Invalid access size\n");
+// Ignore non-power-of-two sizes
+read_index = false;
}
-if (!pt_entry->enabled) {
+if (read_index && !pt_entry->enabled) {
// Not enabled (no pattern detected in this
stream),
// add or update an entry in the pattern detector
and
// start tracking misses
allocateOrUpdateIPDEntry(pt_entry, index);
-} else {
+} else if (read_index) {
// Enabled entry, update the index
pt_entry->index = index;
if (!pt_entry->increasedIndirectCounter) {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17733
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Gerrit-Change-Number: 17733
Gerrit-PatchSet: 2
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: ISB prefetcher was triggering an assertion
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17734
Change subject: mem-cache: ISB prefetcher was triggering an assertion
..
mem-cache: ISB prefetcher was triggering an assertion
An assertion ignored the case when an entry of the SP table had been
invalidated.
Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
---
M src/mem/cache/prefetch/irregular_stream_buffer.cc
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mem/cache/prefetch/irregular_stream_buffer.cc
b/src/mem/cache/prefetch/irregular_stream_buffer.cc
index 45aba0b..345fe70 100644
--- a/src/mem/cache/prefetch/irregular_stream_buffer.cc
+++ b/src/mem/cache/prefetch/irregular_stream_buffer.cc
@@ -147,7 +147,10 @@
Addr sp_index = mapping.address % prefetchCandidatesPerEntry;
AddressMappingEntry *sp_am =
spAddressMappingCache.findEntry(sp_address, is_secure);
-assert(sp_am != nullptr);
+if (sp_am == nullptr) {
+// The entry has been evicted, can not generate prefetches
+return;
+}
for (unsigned d = 1;
d <= degree && (sp_index + d) <
prefetchCandidatesPerEntry;
d += 1)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17734
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Gerrit-Change-Number: 17734
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix panic in Indirect Memory prefetcher
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17733
Change subject: mem-cache: Fix panic in Indirect Memory prefetcher
..
mem-cache: Fix panic in Indirect Memory prefetcher
Memory requests with a size non-power-of-two and less than 8 values were
causing
a panic, but there these should be allowed and ignored by the prefetcher.
Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
---
M src/mem/cache/prefetch/indirect_memory.cc
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mem/cache/prefetch/indirect_memory.cc
b/src/mem/cache/prefetch/indirect_memory.cc
index 393958c..d49652f 100644
--- a/src/mem/cache/prefetch/indirect_memory.cc
+++ b/src/mem/cache/prefetch/indirect_memory.cc
@@ -108,6 +108,7 @@
if (!miss && !pfi.isWrite() && pfi.getSize() <= 8) {
int64_t index = 0;
+bool read_index = true;
switch(pfi.getSize()) {
case sizeof(uint8_t):
index = pfi.get(byteOrder);
@@ -122,14 +123,15 @@
index = pfi.get(byteOrder);
break;
default:
-panic("Invalid access size\n");
+// Ignore non-power-of-two sizes
+read_index = false;
}
-if (!pt_entry->enabled) {
+if (read_index && !pt_entry->enabled) {
// Not enabled (no pattern detected in this
stream),
// add or update an entry in the pattern detector
and
// start tracking misses
allocateOrUpdateIPDEntry(pt_entry, index);
-} else {
+} else if (read_index) {
// Enabled entry, update the index
pt_entry->index = index;
if (!pt_entry->increasedIndirectCounter) {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17733
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Gerrit-Change-Number: 17733
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: AMPM Prefetcher fails when restoring from a checkpoint
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17732
Change subject: mem-cache: AMPM Prefetcher fails when restoring from a
checkpoint
..
mem-cache: AMPM Prefetcher fails when restoring from a checkpoint
The preriodic event triggers an assertion due to an incorrect tick value to
schedule when restoring from a checkpoint.
Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
---
M src/mem/cache/prefetch/access_map_pattern_matching.cc
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mem/cache/prefetch/access_map_pattern_matching.cc
b/src/mem/cache/prefetch/access_map_pattern_matching.cc
index df2a9f7..bd06dea 100644
--- a/src/mem/cache/prefetch/access_map_pattern_matching.cc
+++ b/src/mem/cache/prefetch/access_map_pattern_matching.cc
@@ -57,9 +57,6 @@
{
fatal_if(!isPowerOf2(hotZoneSize),
"the hot zone size must be a power of 2");
-if (!epochEvent.scheduled()) {
-schedule(epochEvent, clockEdge(epochCycles));
-}
}
void
@@ -153,6 +150,11 @@
std::vector &addresses)
{
assert(addresses.empty());
+
+if (!epochEvent.scheduled()) {
+schedule(epochEvent, clockEdge(epochCycles));
+}
+
bool is_secure = pfi.isSecure();
Addr am_addr = pfi.getAddr() / hotZoneSize;
Addr current_block = (pfi.getAddr() % hotZoneSize) / blkSize;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17732
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Gerrit-Change-Number: 17732
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17731
Change subject: mem-cache: Fix PIF prefetcher compilation error with NULL
ISA
..
mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.
Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
---
M src/mem/cache/prefetch/Prefetcher.py
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 404a442..8a1517c 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -43,7 +43,6 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.BaseCPU import BaseCPU
from m5.objects.ClockedObject import ClockedObject
from m5.objects.IndexingPolicies import *
from m5.objects.ReplacementPolicies import *
@@ -481,6 +480,6 @@
"Replacement policy of the index")
def listenFromProbeRetiredInstructions(self, simObj):
-if not isinstance(simObj, BaseCPU):
+if not isinstance(simObj, SimObject):
raise TypeError("argument must be of BaseCPU type")
self.addEvent(HWPProbeEventRetiredInsts(self,
simObj,"RetiredInstsPC"))
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17731
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Gerrit-Change-Number: 17731
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
the entry.
+ * @param addr address to compute the distance from the trigger
+ * @param log_blk_distance log_2(block size of the cache)
+ * @result distance in cache blocks from the address to the
trigger
+ */
+unsigned int distanceFromTrigger(Addr addr,
+ unsigned int log_blk_size)
const;
+};
+
+CompactorEntry spatialCompactor;
+std::deque temporalCompactor;
+
+/**
+ * History buffer is a circular buffer that stores the sequence of
+ * retired instructions in FIFO order.
+ */
+std::vector historyBuffer;
+unsigned int historyBufferTail;
+
+struct IndexEntry : public TaggedEntry
+{
+unsigned int historyIndex;
+};
+/**
+ * The index table is a small cache-like structure that facilitates
+ * fast search of the history buffer.
+ */
+AssociativeSet index;
+
+/**
+ * A Stream Address Buffer (SAB) tracks a window of consecutive
+ * spatial regions. The SAB mantains a pointer to the sequence in
the
+ * history buffer, initiallly set to the pointer taken from the
index
+ * table
+ */
+std::deque streamAddressBuffer;
+
+/**
+ * Updates the prefetcher structures upon an instruction retired
+ * @param pc PC of the instruction being retired
+ */
+void notifyRetiredInst(const Addr pc);
+
+/**
+ * Probe Listener to handle probe events from the CPU
+ */
+class PrefetchListenerPC : public ProbeListenerArgBase
+{
+ public:
+PrefetchListenerPC(PIFPrefetcher &_parent, ProbeManager *pm,
+ const std::string &name)
+: ProbeListenerArgBase(pm, name),
+ parent(_parent) {}
+void notify(const Addr& pc) override;
+ protected:
+PIFPrefetcher &parent;
+};
+
+/** Array of probe listeners */
+std::vector listenersPC;
+
+
+public:
+PIFPrefetcher(const PIFPrefetcherParams *p);
+~PIFPrefetcher() {}
+
+void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses);
+
+/**
+ * Add a SimObject and a probe name to monitor the retired
instructions
+ * @param obj The SimObject pointer to listen from
+ * @param name The probe name
+ */
+void addEventProbeRetiredInsts(SimObject *obj, const char *name);
+};
+
+#endif // __MEM_CACHE_PREFETCH_PIF_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e
Gerrit-Change-Number: 16968
Gerrit-PatchSet: 12
Gerrit-Owner: Ivan Pizarro
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Ivan Pizarro
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
Javier Bueno Hedo has uploaded a new patch set (#10) to the change originally created by Ivan Pizarro. ( https://gem5-review.googlesource.com/c/public/gem5/+/16968 ) Change subject: mem-cache: Proactive Instruction Fetch Implementation .. mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/pif.cc A src/mem/cache/prefetch/pif.hh 4 files changed, 491 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Gerrit-Change-Number: 16968 Gerrit-PatchSet: 10 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
Javier Bueno Hedo has uploaded a new patch set (#9) to the change originally created by Ivan Pizarro. ( https://gem5-review.googlesource.com/c/public/gem5/+/16968 ) Change subject: mem-cache: Proactive Instruction Fetch Implementation .. mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/pif.cc A src/mem/cache/prefetch/pif.hh 4 files changed, 495 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Gerrit-Change-Number: 16968 Gerrit-PatchSet: 9 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added a probe to notify the address of retired instructions
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17632 )
Change subject: cpu: Added a probe to notify the address of retired
instructions
..
cpu: Added a probe to notify the address of retired instructions
A probe is added to notify the address of each retired instruction.
Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632
Reviewed-by: Nikos Nikoleris
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/execute.cc
M src/cpu/o3/cpu.cc
M src/cpu/simple/base.cc
5 files changed, 11 insertions(+), 7 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 8dfcf3c..8e49fb1 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -391,6 +391,7 @@
ppActiveCycles = pmuProbePoint("ActiveCycles");
ppRetiredInsts = pmuProbePoint("RetiredInsts");
+ppRetiredInstsPC = pmuProbePoint("RetiredInstsPC");
ppRetiredLoads = pmuProbePoint("RetiredLoads");
ppRetiredStores = pmuProbePoint("RetiredStores");
ppRetiredBranches = pmuProbePoint("RetiredBranches");
@@ -400,11 +401,12 @@
}
void
-BaseCPU::probeInstCommit(const StaticInstPtr &inst)
+BaseCPU::probeInstCommit(const StaticInstPtr &inst, Addr pc)
{
-if (!inst->isMicroop() || inst->isLastMicroop())
+if (!inst->isMicroop() || inst->isLastMicroop()) {
ppRetiredInsts->notify(1);
-
+ppRetiredInstsPC->notify(pc);
+}
if (inst->isLoad())
ppRetiredLoads->notify(1);
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 9075d4b..f9b24b9 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -487,8 +487,9 @@
* instruction.
*
* @param inst Instruction that just committed
+ * @param pc PC of the instruction that just committed
*/
-virtual void probeInstCommit(const StaticInstPtr &inst);
+virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
protected:
/**
@@ -509,6 +510,7 @@
* instructions may call notify once for the entire bundle.
*/
ProbePoints::PMUUPtr ppRetiredInsts;
+ProbePoints::PMUUPtr ppRetiredInstsPC;
/** Retired load instructions */
ProbePoints::PMUUPtr ppRetiredLoads;
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 6a41820..47f3cbc 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -872,7 +872,7 @@
if (inst->traceData)
inst->traceData->setCPSeq(thread->numOp);
-cpu.probeInstCommit(inst->staticInst);
+cpu.probeInstCommit(inst->staticInst, inst->pc.instAddr());
}
bool
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 965ab04..9da5b43 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1623,7 +1623,7 @@
thread[tid]->numOps++;
committedOps[tid]++;
-probeInstCommit(inst->staticInst);
+probeInstCommit(inst->staticInst, inst->instAddr());
}
template
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 422c732..b243dcc 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -661,7 +661,7 @@
}
// Call CPU instruction commit probes
-probeInstCommit(curStaticInst);
+probeInstCommit(curStaticInst, instAddr);
}
void
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17632
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Gerrit-Change-Number: 17632
Gerrit-PatchSet: 3
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added a probe to notify the address of retired instructions
Hello Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17632 to look at the new patch set (#2). Change subject: cpu: Added a probe to notify the address of retired instructions .. cpu: Added a probe to notify the address of retired instructions A probe is added to notify the address of each retired instruction. Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9 --- M src/cpu/base.cc M src/cpu/base.hh M src/cpu/minor/execute.cc M src/cpu/o3/cpu.cc M src/cpu/simple/base.cc 5 files changed, 11 insertions(+), 7 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17632 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9 Gerrit-Change-Number: 17632 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Daniel Carvalho Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: config: Add flag options to set the hardware prefetchers to use
SED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Pau Cabre
+
+# This file is a copy of MemConfig.py / CpuConfig.py, but modified to
+# hanle branch predictors instead of memory controllers / CPUs
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+from m5 import fatal
+import m5.objects
+import inspect
+import sys
+from textwrap import TextWrapper
+
+# Dictionary of mapping names of real branch predictor models to classes.
+_hwp_classes = {}
+
+
+def is_hwp_class(cls):
+"""Determine if a class is a prefetcher that can be instantiated"""
+
+# We can't use the normal inspect.isclass because the ParamFactory
+# and ProxyFactory classes have a tendency to confuse it.
+try:
+return issubclass(cls, m5.objects.BasePrefetcher) and \
+not cls.abstract
+except (TypeError, AttributeError):
+return False
+
+def get(name):
+"""Get a HWP class from a user provided class name or alias."""
+
+try:
+hwp_class = _hwp_classes[name]
+return hwp_class
+except KeyError:
+print("%s is not a valid HWP model." % (name,))
+sys.exit(1)
+
+def print_hwp_list():
+"""Print a list of available HWP classes."""
+
+print("Available Hardware Prefetcher classes:")
+doc_wrapper = TextWrapper(initial_indent="\t\t",
subsequent_indent="\t\t")
+for name, cls in _hwp_classes.items():
+print("\t%s" % name)
+
+# Try to extract the class documentation from the class help
+# string.
+doc = inspect.getdoc(cls)
+if doc:
+for line in doc_wrapper.wrap(doc):
+print(line)
+
+def hwp_names():
+"""Return a list of valid Hardware Prefetcher names."""
+return list(_hwp_classes.keys())
+
+# Add all HWPs in the object hierarchy.
+for name, cls in inspect.getmembers(m5.objects, is_hwp_class):
+_hwp_classes[name] = cls
+
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 6d9c9cf..58078ec 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -48,6 +48,7 @@
from .Benchmarks import *
from . import CpuConfig
from . import BPConfig
+from . import HWPConfig
from . import MemConfig
from . import PlatformConfig
@@ -59,6 +60,10 @@
BPConfig.print_bp_list()
sys.exit(0)
+def _listHWPTypes(option, opt, value, parser):
+HWPConfig.print_hwp_list()
+sys.exit(0)
+
def _listMemTypes(option, opt, value, parser):
MemConfig.print_mem_list()
sys.exit(0)
@@ -163,6 +168,29 @@
type of branch predictor to run with
(if not set, use the default branch predictor of
the selected CPU)""")
+parser.add_option("--list-hwp-types",
+ action="callback", callback=_listHWPTypes,
+ help="List available hardware prefetcher types")
+parser.add_option("--l1i-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L1
+ instruction cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
+parser.add_option("--l1d-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L1
+ data cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
+parser.add_option("--l2-hwp-type", type="choice", default=None,
+ choices=HWPConfig.hwp_names(),
+ help = """
+ type of hardware prefetcher to use with the L2 cache.
+ (if not set, use the default prefetcher of
+ the selected cache)""")
parser.add_option("--checker", action="store_true");
parser.add_option("--cpu-clock", action="store", type="string",
default='2GHz',
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17709
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I310fcd9c49f9554d98cd565a32bdb96a3e165486
Gerrit-Change-Number: 17709
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: config: Use the corresponding HPI Caches when using the HPI cpu
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17708 )
Change subject: config: Use the corresponding HPI Caches when using the HPI
cpu
..
config: Use the corresponding HPI Caches when using the HPI cpu
The HPI cpu comes with specific cache definitions, but they
are ignored when using this cpu. This patch solves this in the same
way it is done for the O3_ARM_v7a cpu.
Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M configs/common/CacheConfig.py
1 file changed, 9 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 35e1473..9460607 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -67,6 +67,15 @@
core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
core.O3_ARM_v7aL2, \
core.O3_ARM_v7aWalkCache
+elif options.cpu_type == "HPI":
+try:
+import cores.arm.HPI as core
+except:
+print("HPI is unavailable.")
+sys.exit(1)
+
+dcache_class, icache_class, l2_cache_class, walk_cache_class = \
+core.HPI_DCache, core.HPI_ICache, core.HPI_L2,
core.HPI_WalkCache
else:
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17708
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Gerrit-Change-Number: 17708
Gerrit-PatchSet: 3
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: config: Use the corresponding HPI Caches when using the HPI cpu
Hello Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17708 to look at the new patch set (#2). Change subject: config: Use the corresponding HPI Caches when using the HPI cpu .. config: Use the corresponding HPI Caches when using the HPI cpu The HPI cpu comes with specific cache definitions, but they are ignored when using this cpu. This patch solves this in the same way it is done for the O3_ARM_v7a cpu. Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b --- M configs/common/CacheConfig.py 1 file changed, 9 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17708 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b Gerrit-Change-Number: 17708 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Javier Bueno Hedo Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: config: Use the corresponding HPI Caches when using the HPI cpu
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17708
Change subject: config: Use the corresponding HPI Caches when using the HPI
cpu
..
config: Use the corresponding HPI Caches when using the HPI cpu
The HPI cpu comes with specific cache definitions, but they
are ignored when using this cpu. This patch solves this un the same
wayt it is done for the O3_ARM_v7a cpu.
Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
---
M configs/common/CacheConfig.py
1 file changed, 9 insertions(+), 0 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 35e1473..9460607 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -67,6 +67,15 @@
core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
core.O3_ARM_v7aL2, \
core.O3_ARM_v7aWalkCache
+elif options.cpu_type == "HPI":
+try:
+import cores.arm.HPI as core
+except:
+print("HPI is unavailable.")
+sys.exit(1)
+
+dcache_class, icache_class, l2_cache_class, walk_cache_class = \
+core.HPI_DCache, core.HPI_ICache, core.HPI_L2,
core.HPI_WalkCache
else:
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17708
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Gerrit-Change-Number: 17708
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
Javier Bueno Hedo has uploaded a new patch set (#7) to the change originally created by Ivan Pizarro. ( https://gem5-review.googlesource.com/c/public/gem5/+/16968 ) Change subject: mem-cache: Proactive Instruction Fetch Implementation .. mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/pif.cc A src/mem/cache/prefetch/pif.hh 4 files changed, 509 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Gerrit-Change-Number: 16968 Gerrit-PatchSet: 7 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added a probe to notify the address of retired instructions
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17632
Change subject: cpu: Added a probe to notify the address of retired
instructions
..
cpu: Added a probe to notify the address of retired instructions
A probe is added to notify the address of each retired instruction.
Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/execute.cc
M src/cpu/o3/cpu.cc
M src/cpu/simple/base.cc
5 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 8dfcf3c..0f239d8 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -391,6 +391,7 @@
ppActiveCycles = pmuProbePoint("ActiveCycles");
ppRetiredInsts = pmuProbePoint("RetiredInsts");
+ppRetiredInstsPC = pmuProbePoint("RetiredInstsPC");
ppRetiredLoads = pmuProbePoint("RetiredLoads");
ppRetiredStores = pmuProbePoint("RetiredStores");
ppRetiredBranches = pmuProbePoint("RetiredBranches");
@@ -400,7 +401,7 @@
}
void
-BaseCPU::probeInstCommit(const StaticInstPtr &inst)
+BaseCPU::probeInstCommit(const StaticInstPtr &inst, Addr pc)
{
if (!inst->isMicroop() || inst->isLastMicroop())
ppRetiredInsts->notify(1);
@@ -414,6 +415,10 @@
if (inst->isControl())
ppRetiredBranches->notify(1);
+
+if (!inst->isMicroop() || inst->isLastMicroop()) {
+ppRetiredInstsPC->notify(pc);
+}
}
void
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 9075d4b..f9b24b9 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -487,8 +487,9 @@
* instruction.
*
* @param inst Instruction that just committed
+ * @param pc PC of the instruction that just committed
*/
-virtual void probeInstCommit(const StaticInstPtr &inst);
+virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
protected:
/**
@@ -509,6 +510,7 @@
* instructions may call notify once for the entire bundle.
*/
ProbePoints::PMUUPtr ppRetiredInsts;
+ProbePoints::PMUUPtr ppRetiredInstsPC;
/** Retired load instructions */
ProbePoints::PMUUPtr ppRetiredLoads;
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 6a41820..47f3cbc 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -872,7 +872,7 @@
if (inst->traceData)
inst->traceData->setCPSeq(thread->numOp);
-cpu.probeInstCommit(inst->staticInst);
+cpu.probeInstCommit(inst->staticInst, inst->pc.instAddr());
}
bool
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 965ab04..9da5b43 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1623,7 +1623,7 @@
thread[tid]->numOps++;
committedOps[tid]++;
-probeInstCommit(inst->staticInst);
+probeInstCommit(inst->staticInst, inst->instAddr());
}
template
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 422c732..b243dcc 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -661,7 +661,7 @@
}
// Call CPU instruction commit probes
-probeInstCommit(curStaticInst);
+probeInstCommit(curStaticInst, instAddr);
}
void
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17632
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Gerrit-Change-Number: 17632
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: configs: fix class reference in CacheConfigs
Javier Bueno Hedo has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/17541 ) Change subject: configs: fix class reference in CacheConfigs .. configs: fix class reference in CacheConfigs One reference was not properly updated when changing to absolute import paths Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- M configs/common/CacheConfig.py 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index ab9d267..35e1473 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -66,7 +66,7 @@ dcache_class, icache_class, l2_cache_class, walk_cache_class = \ core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \ core.O3_ARM_v7aL2, \ -O3_ARM_v7aWalkCache +core.O3_ARM_v7aWalkCache else: dcache_class, icache_class, l2_cache_class, walk_cache_class = \ L1_DCache, L1_ICache, L2Cache, None -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17541 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a Gerrit-Change-Number: 17541 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Javier Bueno Hedo Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: configs: fix class reference in CacheConfigs
Javier Bueno Hedo has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17541 Change subject: configs: fix class reference in CacheConfigs .. configs: fix class reference in CacheConfigs One reference was not properly updated when changing to absolute import paths Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a --- M configs/common/CacheConfig.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index ab9d267..35e1473 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -66,7 +66,7 @@ dcache_class, icache_class, l2_cache_class, walk_cache_class = \ core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \ core.O3_ARM_v7aL2, \ -O3_ARM_v7aWalkCache +core.O3_ARM_v7aWalkCache else: dcache_class, icache_class, l2_cache_class, walk_cache_class = \ L1_DCache, L1_ICache, L2Cache, None -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17541 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a Gerrit-Change-Number: 17541 Gerrit-PatchSet: 1 Gerrit-Owner: Javier Bueno Hedo Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
Javier Bueno Hedo has uploaded a new patch set (#6) to the change originally created by Ivan Pizarro. ( https://gem5-review.googlesource.com/c/public/gem5/+/16968 ) Change subject: mem-cache: Proactive Instruction Fetch Implementation .. mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e --- M src/cpu/base.cc M src/cpu/base.hh M src/cpu/o3/cpu.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/pif.cc A src/mem/cache/prefetch/pif.hh 7 files changed, 529 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Gerrit-Change-Number: 16968 Gerrit-PatchSet: 6 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
Javier Bueno Hedo has uploaded a new patch set (#5) to the change originally created by Ivan Pizarro. ( https://gem5-review.googlesource.com/c/public/gem5/+/16968 ) Change subject: mem-cache: Proactive Instruction Fetch Implementation .. mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e --- M src/cpu/base.cc M src/cpu/base.hh M src/cpu/o3/cpu.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/pif.cc A src/mem/cache/prefetch/pif.hh 7 files changed, 530 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Gerrit-Change-Number: 16968 Gerrit-PatchSet: 5 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
Javier Bueno Hedo has uploaded a new patch set (#4) to the change originally created by Ivan Pizarro. ( https://gem5-review.googlesource.com/c/public/gem5/+/16968 ) Change subject: mem-cache: Proactive Instruction Fetch Implementation .. mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e --- M src/cpu/base.cc M src/cpu/base.hh M src/cpu/o3/cpu.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh A src/mem/cache/prefetch/pif.cc A src/mem/cache/prefetch/pif.hh 9 files changed, 539 insertions(+), 4 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Gerrit-Change-Number: 16968 Gerrit-PatchSet: 4 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Proactive Instruction Fetch Implementation
Javier Bueno Hedo has uploaded a new patch set (#3) to the change originally created by Ivan Pizarro. ( https://gem5-review.googlesource.com/c/public/gem5/+/16968 ) Change subject: mem-cache: Proactive Instruction Fetch Implementation .. mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e --- M src/cpu/base.cc M src/cpu/base.hh M src/cpu/o3/cpu.cc M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh A src/mem/cache/prefetch/pif.cc A src/mem/cache/prefetch/pif.hh 9 files changed, 540 insertions(+), 4 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16968 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Gerrit-Change-Number: 16968 Gerrit-PatchSet: 3 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the STeMS prefetcher
ta = 0;
+}
+}
+
+/**
+ * Update the entry data with an entry from a generation that just
+ * ended. This operation can not be done with the copy constructor,
+ * becasuse the TaggedEntry component must not be copied.
+ * @param e entry which generation has ended
+ */
+void update(ActiveGenerationTableEntry const &e)
+{
+paddress = e.paddress;
+pc = e.pc;
+seqCounter = e.seqCounter;
+sequence = e.sequence;
+}
+
+/**
+ * Add a new access to the sequence
+ * @param offset offset in cachelines within the spatial region
+ */
+void addOffset(unsigned int offset) {
+// Search for the offset in the deltas array, if it exist,
update
+// the corresponding counter, if not, add the offset to the
array
+for (auto &seq_entry : sequence) {
+if (seq_entry.counter > 0) {
+if (seq_entry.offset == offset) {
+//2 bit counter, saturates at 3
+if (seq_entry.counter < 3) {
+seq_entry.counter += 1;
+}
+}
+} else {
+// If the counter is 0 it means that this position is
not
+// being used, and we can allocate the new offset here
+seq_entry.counter = 1;
+seq_entry.offset = offset;
+seq_entry.delta = seqCounter;
+break;
+}
+}
+seqCounter = 0;
+}
+};
+
+/** Active Generation Table (AGT) */
+AssociativeSet activeGenerationTable;
+/** Pattern Sequence Table (PST) */
+AssociativeSet patternSequenceTable;
+
+/** Data type of the Region Miss Order Buffer entry */
+struct RegionMissOrderBufferEntry {
+/** Address of the spatial region */
+Addr srAddress;
+/**
+ * Address used to index the PST table, generated using the PC and
the
+ * offset within the spatial region
+ */
+Addr pstAddress;
+/** Delta within the global miss order sequence */
+unsigned int delta;
+/** Valid bit */
+bool valid;
+};
+
+/** Region Miss Order Buffer (RMOB) */
+std::vector rmob;
+/** First free position (or older, if it is full) of the RMOB */
+unsigned int rmobHead;
+
+/** Counter to keep the count of accesses between trigger accesses */
+unsigned int lastTriggerCounter;
+
+/** Checks if the active generations have ended */
+void checkForActiveGenerationsEnd();
+/**
+ * Adds an entry to the RMOB
+ * @param sr_addr Spatial region address
+ * @param pst_addr Corresponding PST address
+ * @param delta Number of entries skipped in the global miss order
+ */
+void addToRMOB(Addr sr_addr, Addr pst_addr, unsigned int delta);
+
+/**
+ * Reconstructs a sequence of accesses and generates the prefetch
+ * addresses, adding them to the addresses vector
+ * @param rmob_idx rmob position to start generating from
+ * @param addresses vector to add the addresses to be prefetched
+ */
+void reconstructSequence(unsigned int rmob_idx,
+ std::vector &addresses);
+ public:
+STeMSPrefetcher(const STeMSPrefetcherParams* p);
+~STeMSPrefetcher() {}
+void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+
+#endif//__MEM_CACHE_PREFETCH_SPATIO_TEMPORAL_MEMORY_STREAMING_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16423
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Gerrit-Change-Number: 16423
Gerrit-PatchSet: 5
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
* This variable is set to indicate that there has been at least
one
+ * match with the current index value. This information is later
used
+ * when a new index is updated. If there were no increases in the
+ * indirectCounter, the counter is decremented.
+ */
+bool increasedIndirectCounter;
+
+PrefetchTableEntry() : TaggedEntry(), address(0), secure(false),
+streamCounter(0), enabled(false), index(0), baseAddr(0),
shift(0),
+indirectCounter(0), increasedIndirectCounter(false)
+{}
+
+void reset() override {
+address = 0;
+secure = false;
+streamCounter = 0;
+enabled = false;
+index = 0;
+baseAddr = 0;
+shift = 0;
+indirectCounter = 0;
+increasedIndirectCounter = false;
+}
+};
+/** Prefetch table */
+AssociativeSet prefetchTable;
+
+/** Indirect Pattern Detector entrt */
+struct IndirectPatternDetectorEntry : public TaggedEntry
+{
+/** First index */
+int64_t idx1;
+/** Second index */
+int64_t idx2;
+/** Valid bit for the second index */
+bool secondIndexSet;
+/** Number of misses currently recorded */
+int numMisses;
+/**
+ * Potential BaseAddr candidates for each recorded miss.
+ * The number of candidates per miss is determined by the number of
+ * elements in the shiftValues array.
+ */
+std::vector> baseAddr;
+
+IndirectPatternDetectorEntry(unsigned int num_addresses,
+ unsigned int num_shifts)
+ : idx1(0), idx2(0), secondIndexSet(false), numMisses(0),
+baseAddr(num_addresses, std::vector(num_shifts))
+{}
+
+void reset() override {
+idx1 = 0;
+idx2 = 0;
+secondIndexSet = false;
+numMisses = 0;
+setInvalid();
+}
+};
+/** Indirect Pattern Detector (IPD) table */
+AssociativeSet ipd;
+
+/** Entry currently tracking misses */
+IndirectPatternDetectorEntry *ipdEntryTrackingMisses;
+
+/** Byte order used to access the cache */
+const ByteOrder byteOrder;
+
+/**
+ * Allocate or update an entry in the IPD
+ * @param pt_entry Pointer to the associated page table entry
+ * @param index Detected first index value
+ */
+void allocateOrUpdateIPDEntry(const PrefetchTableEntry *pt_entry,
+ int64_t index);
+/**
+ * Update an IPD entry with a detected miss address, when the first
index
+ * is being tracked
+ * @param miss_addr The address that caused the miss
+ */
+void trackMissIndex1(Addr miss_addr);
+
+/**
+ * Update an IPD entry with a detected miss address, when the second
index
+ * is being tracked
+ * @param miss_addr The address that caused the miss
+ */
+void trackMissIndex2(Addr miss_addr);
+
+/**
+ * Checks if an access to the cache matches any active PT entry, if so,
+ * the indirect confidence counter is incremented
+ * @param addr address of the access
+ */
+void checkAccessMatchOnActiveEntries(Addr addr);
+
+ public:
+IndirectMemoryPrefetcher(const IndirectMemoryPrefetcherParams *p);
+~IndirectMemoryPrefetcher() {}
+
+ void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+#endif//__MEM_CACHE_PREFETCH_INDIRECT_MEMORY_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797
Gerrit-Change-Number: 16223
Gerrit-PatchSet: 14
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Assignee: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch: added a function to get the arch-dependant flags of a TLB request
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17189
Change subject: arch: added a function to get the arch-dependant flags of a
TLB request
..
arch: added a function to get the arch-dependant flags of a TLB request
A function has been added to the TLB class to get the architecture specific
flags required to construct a TLB request.
Change-Id: I82dda9d8b20daa34527119f82cee9f57f452b9a5
---
M src/arch/generic/tlb.hh
1 file changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 7865d8a..f0af80e 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -104,6 +104,14 @@
}
/**
+ * Gets the Architecture-dependant flags required to generate a TLB
Request
+ * @return the flags
+ */
+virtual uint8_t getTLBRequestArchFlags() const {
+return 0;
+}
+
+/**
* Do post-translation physical address finalization.
*
* This method is used by some architectures that need
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17189
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I82dda9d8b20daa34527119f82cee9f57f452b9a5
Gerrit-Change-Number: 17189
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#12). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 4 files changed, 499 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 12 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the STeMS prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16423 to look at the new patch set (#3). Change subject: mem-cache: Added the STeMS prefetcher .. mem-cache: Added the STeMS prefetcher Reference: Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and Babak Falsafi. 2009. Spatio-temporal memory streaming. In Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80. Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc A src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh 4 files changed, 493 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16423 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a Gerrit-Change-Number: 16423 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Jason Lowe-Power, Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#11). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/arch/arm/tlb.hh M src/arch/generic/tlb.hh M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 8 files changed, 391 insertions(+), 110 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 11 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the STeMS prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16423 to look at the new patch set (#2). Change subject: mem-cache: Added the STeMS prefetcher .. mem-cache: Added the STeMS prefetcher Reference: Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and Babak Falsafi. 2009. Spatio-temporal memory streaming. In Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80. Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc A src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh 4 files changed, 496 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16423 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a Gerrit-Change-Number: 16423 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added extra information to PrefetchInfo
object, this address is
+ *used to train the prefetcher
+ * @param miss whether this event comes from a cache miss
*/
-PrefetchInfo(PacketPtr pkt, Addr addr);
+PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
/**
* Constructs a PrefetchInfo using a new address value and
@@ -168,6 +245,11 @@
* @param addr the address value of the new object
*/
PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
+
+~PrefetchInfo()
+{
+delete data;
+}
};
protected:
@@ -209,8 +291,12 @@
/** Use Virtual Addresses for prefetching */
const bool useVirtualAddresses;
-/** Determine if this access should be observed */
-bool observeAccess(const PacketPtr &pkt) const;
+/**
+ * Determine if this access should be observed
+ * @param pkt The memory request causing the event
+ * @param miss whether this event comes from a cache miss
+ */
+bool observeAccess(const PacketPtr &pkt, bool miss) const;
/** Determine if address is in cache */
bool inCache(Addr addr, bool is_secure) const;
@@ -275,8 +361,9 @@
/**
* Process a notification event from the ProbeListener.
* @param pkt The memory request causing the event
+ * @param miss whether this event comes from a cache miss
*/
-void probeNotify(const PacketPtr &pkt);
+void probeNotify(const PacketPtr &pkt, bool miss);
/**
* Add a SimObject and a probe name to listen events from
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
Gerrit-Change-Number: 16583
Gerrit-PatchSet: 9
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added extra information to PrefetchInfo
Hello Nikos Nikoleris, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 to look at the new patch set (#7). Change subject: mem-cache: Added extra information to PrefetchInfo .. mem-cache: Added extra information to PrefetchInfo Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c --- M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh 2 files changed, 126 insertions(+), 26 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Gerrit-Change-Number: 16583 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added extra information to PrefetchInfo
Hello Nikos Nikoleris, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 to look at the new patch set (#6). Change subject: mem-cache: Added extra information to PrefetchInfo .. mem-cache: Added extra information to PrefetchInfo Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c --- M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh 2 files changed, 125 insertions(+), 25 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Gerrit-Change-Number: 16583 Gerrit-PatchSet: 6 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#10). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 4 files changed, 490 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 10 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added extra information to PrefetchInfo
Hello Nikos Nikoleris, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 to look at the new patch set (#4). Change subject: mem-cache: Added extra information to PrefetchInfo .. mem-cache: Added extra information to PrefetchInfo Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c --- M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh 2 files changed, 124 insertions(+), 24 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Gerrit-Change-Number: 16583 Gerrit-PatchSet: 4 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Jason Lowe-Power, Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#8). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.cc M src/arch/arm/tlb.hh M src/arch/generic/tlb.hh M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 8 files changed, 392 insertions(+), 110 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 8 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added extra information to PrefetchInfo
Hello Nikos Nikoleris, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 to look at the new patch set (#3). Change subject: mem-cache: Added extra information to PrefetchInfo .. mem-cache: Added extra information to PrefetchInfo Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c --- M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh 2 files changed, 115 insertions(+), 24 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Gerrit-Change-Number: 16583 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add a mechanism to iterate all entries of an AssociativeSet
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16582 )
Change subject: mem-cache: Add a mechanism to iterate all entries of an
AssociativeSet
..
mem-cache: Add a mechanism to iterate all entries of an AssociativeSet
Added functions to obtain an iterator to access all entries of
an AssociativeSet container.
Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Reviewed-on: https://gem5-review.googlesource.com/c/16582
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/associative_set.hh
1 file changed, 42 insertions(+), 0 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
diff --git a/src/mem/cache/prefetch/associative_set.hh
b/src/mem/cache/prefetch/associative_set.hh
index 99b6a6d..e4e1b04 100644
--- a/src/mem/cache/prefetch/associative_set.hh
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -195,6 +195,48 @@
* @param entry pointer to the container entry to be inserted
*/
void insertEntry(Addr addr, bool is_secure, Entry* entry);
+
+/** Iterator types */
+using const_iterator = typename std::vector::const_iterator;
+using iterator = typename std::vector::iterator;
+
+/**
+ * Returns an iterator to the first entry of the dictionary
+ * @result iterator to the first element
+ */
+iterator begin()
+{
+return entries.begin();
+}
+
+/**
+ * Returns an iterator pointing to the end of the the dictionary
+ * (placeholder element, should not be accessed)
+ * @result iterator to the end element
+ */
+iterator end()
+{
+return entries.end();
+}
+
+/**
+ * Returns an iterator to the first entry of the dictionary
+ * @result iterator to the first element
+ */
+const_iterator begin() const
+{
+return entries.begin();
+}
+
+/**
+ * Returns an iterator pointing to the end of the the dictionary
+ * (placeholder element, should not be accessed)
+ * @result iterator to the end element
+ */
+const_iterator end() const
+{
+return entries.end();
+}
};
#endif//__CACHE_PREFETCH_ASSOCIATIVE_SET_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16582
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Gerrit-Change-Number: 16582
Gerrit-PatchSet: 2
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added extra information to PrefetchInfo
Javier Bueno Hedo has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/16583 ) Change subject: mem-cache: Added extra information to PrefetchInfo .. mem-cache: Added extra information to PrefetchInfo Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c --- M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh 2 files changed, 98 insertions(+), 24 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Gerrit-Change-Number: 16583 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-CC: Daniel Carvalho Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch: Add lookUpTiming to BaseTLB
Hello Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16543 to look at the new patch set (#2). Change subject: arch: Add lookUpTiming to BaseTLB .. arch: Add lookUpTiming to BaseTLB lookUpTiming performs a timed translation look up. If the entry exists in the TLB, the translation is performed, otherwise the translation does not occur and the state of the TLB is not modified. Change-Id: I07e4a4f1ecf8e5b5874fad80fc20b45f9dbbda00 --- M src/arch/generic/tlb.cc M src/arch/generic/tlb.hh 2 files changed, 29 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16543 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I07e4a4f1ecf8e5b5874fad80fc20b45f9dbbda00 Gerrit-Change-Number: 16543 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Javier Bueno Hedo Gerrit-CC: Ivan Pizarro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#8). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 4 files changed, 475 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 8 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#7). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 4 files changed, 489 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#6). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 4 files changed, 494 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 6 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added extra information to PrefetchInfo
c/mem/cache/prefetch/base.hh
@@ -67,12 +67,13 @@
{
public:
PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
- const std::string &name)
+ const std::string &name, bool miss = false)
: ProbeListenerArgBase(pm, name),
parent(_parent) {}
void notify(const PacketPtr &pkt) override;
protected:
BasePrefetcher &parent;
+bool miss;
};
std::vector listeners;
@@ -84,7 +85,7 @@
* generate new prefetch requests.
*/
class PrefetchInfo {
-/** The address. */
+/** The address used to train and generate prefetches */
Addr address;
/** The program counter that generated this address. */
Addr pc;
@@ -94,6 +95,16 @@
bool validPC;
/** Whether this address targets the secure memory space. */
bool secure;
+/** Size in bytes of the request triggering this event */
+unsigned int size;
+/** Whether this event comes from a write request */
+bool write;
+/** Physical address, needed because address can be virtual */
+Addr paddress;
+/** Whether this event comes from a cache miss */
+bool cacheMiss;
+/** Pointer to the associated request data */
+uint8_t *data;
public:
/**
@@ -143,6 +154,53 @@
}
/**
+ * Gets the size of the request triggering this event
+ * @return the size in bytes of the request triggering this event
+ */
+unsigned int getSize() const
+{
+return size;
+}
+
+/**
+ * Checks if the request that caused this prefetch event was a
write
+ * request
+ * @return true if the request causing this event is a write
request
+ */
+bool isWrite() const
+{
+return write;
+}
+
+/**
+ * Gets the physical address of the request
+ * @return physical address of the request
+ */
+Addr getPaddr() const
+{
+return paddress;
+}
+
+/**
+ * Check if this event comes from a cache miss
+ * @result true if this event comes from a cache miss
+ */
+bool isCacheMiss() const
+{
+return cacheMiss;
+}
+
+/**
+ * Copies the associated data of the request triggering the event
to
+ * the provided memory location.
+ * @return pointer to copy the data
+ */
+void getData(uint8_t *ptr) const
+{
+std::memcpy(ptr, data, size);
+}
+
+/**
* Check for equality
* @param pfi PrefetchInfo to compare against
* @return True if this object and the provided one are equal
@@ -156,9 +214,11 @@
/**
* Constructs a PrefetchInfo using a PacketPtr.
* @param pkt PacketPtr used to generate the PrefetchInfo
- * @param addr the address value of the new object
+ * @param addr the address value of the new object, this address is
+ *used to train the prefetcher
+ * @param miss whether this event comes from a cache miss
*/
-PrefetchInfo(PacketPtr pkt, Addr addr);
+PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
/**
* Constructs a PrefetchInfo using a new address value and
@@ -167,6 +227,11 @@
* @param addr the address value of the new object
*/
PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
+
+~PrefetchInfo()
+{
+delete data;
+}
};
protected:
@@ -208,8 +273,12 @@
/** Use Virtual Addresses for prefetching */
const bool useVirtualAddresses;
-/** Determine if this access should be observed */
-bool observeAccess(const PacketPtr &pkt) const;
+/**
+ * Determine if this access should be observed
+ * @param pkt The memory request causing the event
+ * @param miss whether this event comes from a cache miss
+ */
+bool observeAccess(const PacketPtr &pkt, bool miss) const;
/** Determine if address is in cache */
bool inCache(Addr addr, bool is_secure) const;
@@ -270,8 +339,9 @@
/**
* Process a notification event from the ProbeListener.
* @param pkt The memory request causing the event
+ * @param miss whether this event comes from a cache miss
*/
-void probeNotify(const PacketPtr &pkt);
+void probeNotify(const PacketPtr &pkt, bool miss);
/**
* Add a SimObject and a probe name to listen events from
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
Gerrit-Change-Number: 16583
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add a mechanism to iterate all entries of an AssociativeSet
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16582
Change subject: mem-cache: Add a mechanism to iterate all entries of an
AssociativeSet
..
mem-cache: Add a mechanism to iterate all entries of an AssociativeSet
Added functions to obtain an iterator to access all entries of
an AssociativeSet container.
Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
---
M src/mem/cache/prefetch/associative_set.hh
1 file changed, 42 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/prefetch/associative_set.hh
b/src/mem/cache/prefetch/associative_set.hh
index 99b6a6d..e4e1b04 100644
--- a/src/mem/cache/prefetch/associative_set.hh
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -195,6 +195,48 @@
* @param entry pointer to the container entry to be inserted
*/
void insertEntry(Addr addr, bool is_secure, Entry* entry);
+
+/** Iterator types */
+using const_iterator = typename std::vector::const_iterator;
+using iterator = typename std::vector::iterator;
+
+/**
+ * Returns an iterator to the first entry of the dictionary
+ * @result iterator to the first element
+ */
+iterator begin()
+{
+return entries.begin();
+}
+
+/**
+ * Returns an iterator pointing to the end of the the dictionary
+ * (placeholder element, should not be accessed)
+ * @result iterator to the end element
+ */
+iterator end()
+{
+return entries.end();
+}
+
+/**
+ * Returns an iterator to the first entry of the dictionary
+ * @result iterator to the first element
+ */
+const_iterator begin() const
+{
+return entries.begin();
+}
+
+/**
+ * Returns an iterator pointing to the end of the the dictionary
+ * (placeholder element, should not be accessed)
+ * @result iterator to the end element
+ */
+const_iterator end() const
+{
+return entries.end();
+}
};
#endif//__CACHE_PREFETCH_ASSOCIATIVE_SET_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16582
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26
Gerrit-Change-Number: 16582
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Slim AMPM Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16383 to look at the new patch set (#3). Change subject: mem-cache: Added the Slim AMPM Prefetcher .. mem-cache: Added the Slim AMPM Prefetcher Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship. Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already in gem5). Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/access_map_pattern_matching.cc M src/mem/cache/prefetch/access_map_pattern_matching.hh A src/mem/cache/prefetch/slim_ampm.cc A src/mem/cache/prefetch/slim_ampm.hh 6 files changed, 214 insertions(+), 24 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16383 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a Gerrit-Change-Number: 16383 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Slim AMPM Prefetcher
*/
+
+#ifndef __MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
+#define __MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
+
+#include "mem/cache/prefetch/access_map_pattern_matching.hh"
+#include "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
+#include "mem/cache/prefetch/queued.hh"
+
+/**
+ * The SlimAMPM Prefetcher
+ * Reference:
+ *Towards Bandwidth-Efficient Prefetching with Slim AMPM.
+ *Young, Vinson, and A. Krishna.
+ *The 2nd Data Prefetching Championship (2015).
+ *
+ * This prefetcher uses two other prefetchers, the AMPM and the DCPT.
+ */
+
+struct SlimAMPMPrefetcherParams;
+
+class SlimAMPMPrefetcher : public QueuedPrefetcher
+{
+ /** AMPM prefetcher object */
+ AccessMapPatternMatching &m;
+ /** DCPT prefetcher object */
+ DeltaCorrelatingPredictionTables &dcpt;
+ public:
+ SlimAMPMPrefetcher(const SlimAMPMPrefetcherParams *p);
+ ~SlimAMPMPrefetcher()
+ {}
+
+ void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+#endif//__MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16383
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Gerrit-Change-Number: 16383
Gerrit-PatchSet: 4
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Assignee: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch: Add lookUp to BaseTLB
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16543
Change subject: arch: Add lookUp to BaseTLB
..
arch: Add lookUp to BaseTLB
lookUp performs a non-timed translation lookUp. A parameter controls
wether a pt walk is allowed to solve the translation request.
Change-Id: I07e4a4f1ecf8e5b5874fad80fc20b45f9dbbda00
---
M src/arch/generic/tlb.cc
M src/arch/generic/tlb.hh
2 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/src/arch/generic/tlb.cc b/src/arch/generic/tlb.cc
index aebdd4b..8c6815a 100644
--- a/src/arch/generic/tlb.cc
+++ b/src/arch/generic/tlb.cc
@@ -71,3 +71,10 @@
{
warn("Demapping pages in the generic TLB is unnecessary.\n");
}
+
+Fault
+GenericTLB::lookUp(const RequestPtr &req, ThreadContext *tc, Mode mode,
+ bool walk)
+{
+return translateAtomic(req, tc, mode);
+}
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 91f8f86..a1d9b0a 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -103,6 +103,25 @@
}
/**
+ * Do an untimed address look up. If the entry exists for the requested
+ * address, the physical address is updated in the corresponding
Request
+ * object. If the entry does not exist, a PT walk is done only if the
+ * parameter 'walk' is true. If 'walk' is false and the entry does not
+ * exist, a fault is returned and the state of the TLB is not modified.
+ *
+ * @param req Request to updated in-place.
+ * @param tc Thread context that created the request.
+ * @param mode Request type (read/write/execute).
+ * @param walk Do a pt walk if needed.
+ * @return A fault on failure, NoFault otherwise.
+ */
+virtual Fault
+lookUp(const RequestPtr &req, ThreadContext *tc, Mode mode, bool walk)
+{
+panic("Not implemented.\n");
+}
+
+/**
* Do post-translation physical address finalization.
*
* This method is used by some architectures that need
@@ -161,6 +180,10 @@
Fault finalizePhysical(
const RequestPtr &req, ThreadContext *tc, Mode mode) const
override;
+
+Fault lookUp(
+const RequestPtr &req, ThreadContext *tc,
+Mode mode, bool walk) override;
};
#endif // __ARCH_GENERIC_TLB_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16543
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I07e4a4f1ecf8e5b5874fad80fc20b45f9dbbda00
Gerrit-Change-Number: 16543
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#5). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/associative_set.hh M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 9 files changed, 608 insertions(+), 5 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 5 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#4). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/associative_set.hh M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 9 files changed, 608 insertions(+), 5 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 4 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches
Hello Jason Lowe-Power, Nikos Nikoleris, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 to look at the new patch set (#7). Change subject: mem-cache: Support for page crossing prefetches .. mem-cache: Support for page crossing prefetches Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b --- M src/arch/arm/tlb.hh M src/arch/generic/tlb.cc M src/arch/generic/tlb.hh M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh M src/mem/cache/prefetch/queued.cc M src/mem/cache/prefetch/queued.hh 8 files changed, 385 insertions(+), 109 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Gerrit-Change-Number: 14620 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)
Hello Ilias Vougioukas, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 to look at the new patch set (#6). Change subject: cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) .. cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) Described by the following article: Jiménez, D. "Multiperspective perceptron predictor." Championship Branch Prediction (CBP-5) (2016). Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/multiperspective_perceptron.cc A src/cpu/pred/multiperspective_perceptron.hh A src/cpu/pred/multiperspective_perceptron_64KB.cc A src/cpu/pred/multiperspective_perceptron_64KB.hh A src/cpu/pred/multiperspective_perceptron_8KB.cc A src/cpu/pred/multiperspective_perceptron_8KB.hh 8 files changed, 2,169 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15495 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30 Gerrit-Change-Number: 15495 Gerrit-PatchSet: 6 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ilias Vougioukas Gerrit-Reviewer: Javier Bueno Hedo Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the STeMS prefetcher
update
+// the corresponding counter, if not, add the offset to the
array
+for (auto &seq_entry : sequence) {
+if (seq_entry.counter > 0) {
+if (seq_entry.offset == offset) {
+//2 bit counter, saturates at 3
+if (seq_entry.counter < 3) {
+seq_entry.counter += 1;
+}
+}
+} else {
+// If the counter is 0 it means that this position is
not
+// being used, and we can allocate the new offset here
+seq_entry.counter = 1;
+seq_entry.offset = offset;
+seq_entry.delta = seqCounter;
+break;
+}
+}
+seqCounter = 0;
+}
+};
+
+/** Active Generation Table (AGT) */
+AssociativeSet activeGenerationTable;
+/** Pattern Sequence Table (PST) */
+AssociativeSet patternSequenceTable;
+
+/** Data type of the Region Miss Order Buffer entry */
+struct RegionMissOrderBufferEntry {
+Addr srAddress;
+Addr pstAddress;
+unsigned int delta;
+bool valid;
+};
+
+/** Region Miss Order Buffer (RMOB) */
+std::vector rmob;
+/** First free position (or older, if it is full) of the RMOB */
+unsigned int rmobHead;
+
+/** Counter to keep the count of accesses between trigger accesses */
+unsigned int lastTriggerCounter;
+
+/** Checks if the active generations have ended */
+void checkForActiveGenerationsEnd();
+/**
+ * Adds an entry to the RMOB
+ * @param sr_addr Spatial region address
+ * @param pst_addr Corresponding PST address
+ * @param delta Number of entries skipped in the global miss order
+ */
+void addToRMOB(Addr sr_addr, Addr pst_addr, unsigned int delta);
+
+/**
+ * Reconstructs a sequence of accesses and generates the prefetch
+ * addresses, adding them to the addresses vector
+ * @param rmob_idx rmob position to start generating from
+ * @param addresses vector to add the addresses to be prefetched
+ */
+void reconstructSequence(unsigned int rmob_idx,
+ std::vector &addresses);
+ public:
+STeMSPrefetcher(const STeMSPrefetcherParams* p);
+ ~STeMSPrefetcher() {}
+void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+
+#endif//__MEM_CACHE_PREFETCH_SPATIO_TEMPORAL_MEMORY_STREAMING_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16423
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Gerrit-Change-Number: 16423
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 to look at the new patch set (#3). Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/associative_set.hh M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 9 files changed, 562 insertions(+), 5 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 3 Gerrit-Owner: Javier Bueno Hedo Gerrit-Assignee: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Slim AMPM Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16383 to look at the new patch set (#2). Change subject: mem-cache: Added the Slim AMPM Prefetcher .. mem-cache: Added the Slim AMPM Prefetcher Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship. Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already in gem5). Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/access_map_pattern_matching.cc M src/mem/cache/prefetch/access_map_pattern_matching.hh A src/mem/cache/prefetch/slim_ampm.cc A src/mem/cache/prefetch/slim_ampm.hh 6 files changed, 213 insertions(+), 24 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16383 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a Gerrit-Change-Number: 16383 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Javier Bueno
+ */
+
+/**
+ * Implementation of the Irregular Stream Buffer prefetcher
+ * Reference:
+ * Jain, A., & Lin, C. (2013, December). Linearizing irregular memory
+ * accesses for improved correlated prefetching. In Proceedings of the
+ * 46th Annual IEEE/ACM International Symposium on Microarchitecture
+ * (pp. 247-259). ACM.
+ */
+
+#ifndef __MEM_CACHE_PREFETCH_IRREGULAR_STREAM_BUFFER_HH__
+#define __MEM_CACHE_PREFETCH_IRREGULAR_STREAM_BUFFER_HH__
+
+#include "base/callback.hh"
+#include "mem/cache/prefetch/associative_set.hh"
+#include "mem/cache/prefetch/queued.hh"
+
+struct IrregularStreamBufferPrefetcherParams;
+
+class IrregularStreamBufferPrefetcher : public QueuedPrefetcher
+{
+/** Maximum value of the confidence counters */
+const unsigned maxCounterValue;
+/** Size in bytes of a temporal stream */
+const size_t chunkSize;
+/** Number of prefetch candidates per Physical-to-Structural entry */
+const unsigned prefetchCandidatesPerEntry;
+/** Number of maximum prefetches requests created when predicting */
+const unsigned degree;
+
+/**
+ * Training Unit Entry datatype, it holds the last accessed address and
+ * its secure flag
+ */
+struct TrainingUnitEntry : public TaggedEntry {
+Addr lastAddress;
+bool lastAddressSecure;
+};
+/** Map of PCs to Training unit entries */
+AssociativeSet trainingUnit;
+
+/** Address Mapping entry, holds an address and a confidence counter */
+struct AddressMapping {
+Addr address;
+unsigned counter;
+AddressMapping() : address(0), counter(0)
+{}
+};
+
+/**
+ * Maps a set of contiguous addresses to another set of (not
necessarily
+ * contiguos) addresses, with their corresponding confidence counters
+ */
+struct AddressMappingEntry : public TaggedEntry {
+std::vector mappings;
+AddressMappingEntry(size_t num_mappings) : mappings(num_mappings)
+{}
+void reset() override
+{
+for (auto &entry : mappings) {
+entry.address = 0;
+entry.counter = 0;
+}
+}
+};
+
+/** Physical-to-Structured mappings table */
+AssociativeSet psAddressMappingCache;
+/** Structured-to-Physical mappings table */
+AssociativeSet spAddressMappingCache;
+/**
+ * Counter of allocated structural addresses, increased by "chunkSize",
+ * each time a new structured address is allocated
+ */
+uint64_t structuralAddressCounter;
+
+/**
+ * Add a mapping to the Structured-to-Physica mapping table
+ * @param structuralAddress structural address
+ * @param is_secure whether this page is inside the secure memory area
+ * @param physical_address corresponding physical address
+ */
+void addStructuralToPhysicalEntry(Addr structuralAddress, bool
is_secure,
+ Addr physical_address);
+
+/**
+ * Obtain the Physical-to-Structured mapping entry of the given
physical
+ * address. If the entry does not exist a new one is allocated,
replacing
+ * an existing one if needed.
+ * @param paddr physical address
+ * @param is_secure whether this page is inside the secure memory area
+ * @result reference to the entry
+ */
+AddressMapping& getPSMapping(Addr paddr, bool is_secure);
+ public:
+IrregularStreamBufferPrefetcher(
+const IrregularStreamBufferPrefetcherParams *p);
+~IrregularStreamBufferPrefetcher() {}
+ void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+#endif//__MEM_CACHE_PREFETCH_IRREGULAR_STREAM_BUFFER_HH__
--
To view, visit https://gem5-
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Slim AMPM Prefetcher
Slim AMPM.
+ *Young, Vinson, and A. Krishna.
+ *The 2nd Data Prefetching Championship (2015).
+ *
+ * This prefetcher uses two other prefetchers, the AMPM and the DCPT.
+ */
+
+struct SlimAMPMPrefetcherParams;
+
+class SlimAMPMPrefetcher : public QueuedPrefetcher
+{
+ /** AMPM prefetcher object */
+ AccessMapPatternMatching &m;
+ /** DCPT prefetcher object */
+ DeltaCorrelatingPredictionTables &dcpt;
+ public:
+ SlimAMPMPrefetcher(const SlimAMPMPrefetcherParams *p);
+ ~SlimAMPMPrefetcher()
+ {}
+
+ void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+#endif//__MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16383
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
Gerrit-Change-Number: 16383
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, krishnendra nathella, Dam Sunwoo, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#7). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 385 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Dam Sunwoo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: krishnendra nathella Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Delta Correlating Prediction Tables Prefetcher
ttempt to generate prefetch candidates using the two most
recent
+ * deltas. Prefetch candidates are added to the provided vector.
+ * @param pfs reference to a vector where candidates will be added
+ * @param mask_bits the number of lower bits that should be masked
+ *(ignored) when comparing deltas
+ */
+void getCandidates(std::vector
&pfs,
+ unsigned int mask_bits) const;
+
+};
+/** The main table */
+AssociativeSet table;
+
+ public:
+DeltaCorrelatingPredictionTables(
+DeltaCorrelatingPredictionTablesParams *p);
+~DeltaCorrelatingPredictionTables()
+{}
+
+/**
+ * Computes the prefetch candidates given a prefetch event.
+ * @param pfi The prefetch event information
+ * @param addresses prefetch candidates generated
+ */
+void calculatePrefetch(const BasePrefetcher::PrefetchInfo &pfi,
+std::vector &addresses);
+
+};
+
+struct DCPTPrefetcherParams;
+
+/** The prefetcher object using the DCPT */
+class DCPTPrefetcher : public QueuedPrefetcher
+{
+/** DCPT object */
+DeltaCorrelatingPredictionTables &dcpt;
+ public:
+DCPTPrefetcher(const DCPTPrefetcherParams *p);
+~DCPTPrefetcher()
+{}
+void calculatePrefetch(const PrefetchInfo &pfi,
+std::vector &addresses) override;
+};
+#endif//__MEM_CACHE_PREFETCH_DELTA_CORRELATING_PREDICTION_TABLES_HH_
diff --git a/src/mem/cache/prefetch/queued.hh
b/src/mem/cache/prefetch/queued.hh
index 1c63977..97a7ec6 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -89,7 +89,6 @@
return !(*this > that);
}
};
-using AddrPriority = std::pair;
std::list pfq;
@@ -126,6 +125,8 @@
Stats::Scalar pfSpanPage;
public:
+using AddrPriority = std::pair;
+
QueuedPrefetcher(const QueuedPrefetcherParams *p);
virtual ~QueuedPrefetcher();
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16062
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Gerrit-Change-Number: 16062
Gerrit-PatchSet: 4
Gerrit-Owner: Javier Bueno Hedo
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
Javier Bueno Hedo has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/16223 ) Change subject: mem-cache: Added the Indirect Memory Prefetcher .. mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 --- M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/associative_set.hh M src/mem/cache/prefetch/base.cc M src/mem/cache/prefetch/base.hh A src/mem/cache/prefetch/indirect_memory.cc A src/mem/cache/prefetch/indirect_memory.hh 9 files changed, 562 insertions(+), 5 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Gerrit-Change-Number: 16223 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-CC: Daniel Carvalho Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Indirect Memory Prefetcher
irectCounter(false)
+{}
+
+void reset() override {
+address = 0;
+secure = false;
+streamCounter = 0;
+enabled = false;
+index = 0;
+baseAddr = 0;
+shift = 0;
+indirectCounter = 0;
+increasedIndirectCounter = false;
+}
+};
+/** Prefetch table */
+AssociativeSet prefetchTable;
+
+/** Indirect Pattern Detector entrt */
+struct IndirectPatternDetectorEntry : public TaggedEntry
+{
+/** First index */
+int64_t idx1;
+/** Second index */
+int64_t idx2;
+/** Valid bit for the second index */
+bool secondIndexSet;
+/** Number of misses currently recorded */
+int numMisses;
+/** Potential BaseAddr candidates */
+std::vector> baseAddr;
+
+IndirectPatternDetectorEntry(unsigned int num_addresses,
+ unsigned int num_shifts)
+ : idx1(0), idx2(0), secondIndexSet(false), numMisses(0),
+baseAddr(num_addresses, std::vector(num_shifts))
+{}
+
+void reset() override {
+idx1 = 0;
+idx2 = 0;
+secondIndexSet = false;
+numMisses = 0;
+}
+};
+/** Indirect Pattern Detector (IPD) table */
+AssociativeSet ipd;
+
+/** Entry currently tracking misses */
+IndirectPatternDetectorEntry *ipdEntryTrackingMisses;
+
+/**
+ * Allocate or update an entry in the IPD
+ * @param pt_entry Pointer to the associated page table entry
+ * @param index Detected first index value
+ */
+void allocateOrUpdateIPDEntry(const PrefetchTableEntry *pt_entry,
+ int64_t index);
+/**
+ * Update an IPD entry with a detected miss address, when the first
index
+ * is being tracked
+ * @param entry Pointer to the corresponding IPD entry
+ * @param miss_addr The address that caused the miss
+ */
+void trackMissIndex1(IndirectPatternDetectorEntry *entry, Addr
miss_addr);
+
+/**
+ * Update an IPD entry with a detected miss address, when the second
index
+ * is being tracked
+ * @param entry Pointer to the corresponding IPD entry
+ * @param miss_addr The address that caused the miss
+ */
+void trackMissIndex2(IndirectPatternDetectorEntry *entry, Addr
miss_addr);
+
+/**
+ * Checks if an access to the cache matches any active PT entry, if so,
+ * the indirect confidence counter is incremented
+ * @param addr address of the access
+ */
+void checkAccessMatchOnActiveEntries(Addr addr);
+
+ public:
+IndirectMemoryPrefetcher(const IndirectMemoryPrefetcherParams *p);
+~IndirectMemoryPrefetcher() {}
+
+void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+#endif//__MEM_CACHE_PREFETCH_INDIRECT_MEMORY_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16223
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797
Gerrit-Change-Number: 16223
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, krishnendra nathella, Dam Sunwoo, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#6). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 387 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 6 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Dam Sunwoo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: krishnendra nathella Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Delta Correlating Prediction Tables Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16062 to look at the new patch set (#2). Change subject: mem-cache: Added the Delta Correlating Prediction Tables Prefetcher .. mem-cache: Added the Delta Correlating Prediction Tables Prefetcher Reference: Multi-level hardware prefetching using low complexity delta correlating prediction tables with partial matching. Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010. In Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers (HiPEAC'10) Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/base.hh A src/mem/cache/prefetch/delta_correlating_prediction_tables.cc A src/mem/cache/prefetch/delta_correlating_prediction_tables.hh M src/mem/cache/prefetch/queued.hh 6 files changed, 347 insertions(+), 2 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16062 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d Gerrit-Change-Number: 16062 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Slim AMPM Prefetcher and the DCPT Prefetcher
@ -0,0 +1,54 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Javier Bueno
+ */
+
+#include "mem/cache/prefetch/slim_ampm.hh"
+
+#include "params/SlimAMPMPrefetcher.hh"
+
+SlimAMPMPrefetcher::SlimAMPMPrefetcher(const SlimAMPMPrefetcherParams* p)
+ : QueuedPrefetcher(p), ampm(*p->ampm), dcpt(*p->dcpt)
+{
+}
+
+void
+SlimAMPMPrefetcher::calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses)
+{
+dcpt.calculatePrefetch(pfi, addresses);
+if (addresses.empty()) {
+ampm.calculatePrefetch(pfi, addresses);
+}
+}
+
+SlimAMPMPrefetcher*
+SlimAMPMPrefetcherParams::create()
+{
+return new SlimAMPMPrefetcher(this);
+}
diff --git a/src/mem/cache/prefetch/slim_ampm.hh
b/src/mem/cache/prefetch/slim_ampm.hh
new file mode 100644
index 000..310a165
--- /dev/null
+++ b/src/mem/cache/prefetch/slim_ampm.hh
@@ -0,0 +1,64 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Javier Bueno
+ */
+
+#ifndef __MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
+#define __MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
+
+#include "mem/cache/prefetch/access_map_pattern_matching.hh"
+#include "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
+#include "mem/cache/prefetch/queued.hh"
+
+/**
+ * The SlimAMPM Prefetcher
+ * Reference:
+ *Towards Bandwidth-Efficient Prefetching with Slim AMPM.
+ *Young, Vinson, and A. Krishna.
+ *The 2nd Data Prefetching Championship (2015).
+ *
+ * This prefetcher uses two other prefetchers, the AMPM and the DCPT.
+ */
+
+struct SlimAMPMPrefetcherParams;
+
+class SlimAMPMPrefetcher : public QueuedPrefetcher
+{
+ /** AMPM prefetcher object */
+ AccessMapPatternMatching &m;
+ /** DCPT prefetcher object */
+ DeltaCorrelatingPredictionTables &dcpt;
+ public:
+ SlimAMPMPrefetcher(const SlimAMPMPrefetcherParams *p);
+ ~SlimAMPMPrefetcher()
+ {}
+
+ void calculatePrefetch(const PrefetchInfo &pfi,
+ std::vector &addresses) override;
+};
+#endif//__MEM_CACHE_PREFETCH_SLIM_AMPM_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16062
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Gerrit-Change-Number: 16062
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Updated version of the Signature Path Prefetcher
ageCrossingLookahead(signature_t
signature,
+stride_t last_offset, stride_t delta, double path_confidence)
+{
+// Always use the replacement policy to assign new entries, as all
+// of them are unique, there are never "hits" in the GHR
+GlobalHistoryEntry *gh_entry = globalHistoryRegister.findVictim(0);
+assert(gh_entry != nullptr);
+// Any address value works, as it is never used
+globalHistoryRegister.insertEntry(0, false, gh_entry);
+
+gh_entry->signature = signature;
+gh_entry->lastBlock = last_offset;
+gh_entry->delta = delta;
+gh_entry->confidence = path_confidence;
+}
+
+SignaturePathPrefetcherV2*
+SignaturePathPrefetcherV2Params::create()
+{
+return new SignaturePathPrefetcherV2(this);
+}
diff --git a/src/mem/cache/prefetch/signature_path_v2.hh
b/src/mem/cache/prefetch/signature_path_v2.hh
new file mode 100644
index 000..2eed18d
--- /dev/null
+++ b/src/mem/cache/prefetch/signature_path_v2.hh
@@ -0,0 +1,97 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Javier Bueno
+ */
+
+ /**
+ * Implementation of the Signature Path Prefetcher (v2)
+ *
+ * References:
+ * Path confidence based lookahead prefetching
+ * Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy,
+ * Chris Wilkerson, and Zeshan Chishti. 2016.
+ * In The 49th Annual IEEE/ACM International Symposium on
+ * Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA,
+ * Article 60, 12 pages.
+ */
+
+#ifndef __MEM_CACHE_PREFETCH_SIGNATURE_PATH_V2_HH__
+#define __MEM_CACHE_PREFETCH_SIGNATURE_PATH_V2_HH__
+
+#include "mem/cache/prefetch/associative_set.hh"
+#include "mem/cache/prefetch/signature_path.hh"
+#include "mem/packet.hh"
+
+struct SignaturePathPrefetcherV2Params;
+
+class SignaturePathPrefetcherV2 : public SignaturePathPrefetcher
+{
+/** Global History Register entry datatype */
+struct GlobalHistoryEntry : public TaggedEntry
+{
+signature_t signature;
+double confidence;
+stride_t lastBlock;
+stride_t delta;
+GlobalHistoryEntry() : signature(0), confidence(0.0), lastBlock(0),
+ delta(0) {}
+};
+/** Global History Register */
+AssociativeSet globalHistoryRegister;
+
+double calculateLookaheadConfidence(PatternEntry const &sig,
+PatternStrideEntry const &lookahead) const override;
+
+double calculatePrefetchConfidence(PatternEntry const &sig,
+PatternStrideEntry const &lookahead) const override;
+
+void increasePatternEntryCounter(PatternEntry &pattern_entry,
+PatternStrideEntry &pstride_entry) override;
+
+void handleSignatureTableMiss(stride_t current_block,
+signature_t &new_signature, double &new_conf,
+stride_t &new_stride) override;
+
+/**
+ * In this version of the Signature Path Prefetcher, there is no
auxiliary
+ * prefetcher, so this function does not perform any actions.
+ */
+void auxiliaryPrefetcher(Addr ppn, stride_t current_block, bool
is_secure,
+std::vector &addresses) override
+{}
+
+virtual void handlePageCrossingLookahead(signature_t signature,
+ stride_t last_offset, stride_t delta, double path_confidence)
+override;
+
+ public:
+SignaturePathPrefetc
[gem5-dev] Change in gem5/gem5[master]: cpu: Move the Loop Predictor from LTAGE to an external class
Hello Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15775 to look at the new patch set (#7). Change subject: cpu: Move the Loop Predictor from LTAGE to an external class .. cpu: Move the Loop Predictor from LTAGE to an external class This code could be reused by other predictors requiring a loop predictor. Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/loop_predictor.cc A src/cpu/pred/loop_predictor.hh M src/cpu/pred/ltage.cc M src/cpu/pred/ltage.hh 6 files changed, 705 insertions(+), 383 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15775 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Gerrit-Change-Number: 15775 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-CC: Pau Cabre Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: Move the Loop Predictor from LTAGE to an external class
Hello Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15775 to look at the new patch set (#6). Change subject: cpu: Move the Loop Predictor from LTAGE to an external class .. cpu: Move the Loop Predictor from LTAGE to an external class This code could be reused by other predictors requiring a loop predictor. Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript A src/cpu/pred/loop_predictor.cc A src/cpu/pred/loop_predictor.hh M src/cpu/pred/ltage.cc M src/cpu/pred/ltage.hh 6 files changed, 705 insertions(+), 383 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15775 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Gerrit-Change-Number: 15775 Gerrit-PatchSet: 6 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-CC: Pau Cabre Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: move TAGE predictor code to a base class not inheriting from BPr...
Javier Bueno Hedo has uploaded a new patch set (#3) to the change originally created by Jairo Balart. ( https://gem5-review.googlesource.com/c/public/gem5/+/15317 ) Change subject: cpu: move TAGE predictor code to a base class not inheriting from BPredUnit. .. cpu: move TAGE predictor code to a base class not inheriting from BPredUnit. This base code can be used for TAGE-based indirect base predictors. Change-Id: I2251b8b2d7f94124f9955f52b917dc3b064f090e --- M src/cpu/pred/2bit_local.cc M src/cpu/pred/2bit_local.hh M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript M src/cpu/pred/bi_mode.cc M src/cpu/pred/bi_mode.hh M src/cpu/pred/bpred_unit.cc M src/cpu/pred/bpred_unit.hh M src/cpu/pred/ltage.cc M src/cpu/pred/ltage.hh M src/cpu/pred/tage.cc M src/cpu/pred/tage.hh A src/cpu/pred/tage_base.cc A src/cpu/pred/tage_base.hh M src/cpu/pred/tournament.cc M src/cpu/pred/tournament.hh 16 files changed, 1,504 insertions(+), 1,062 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15317 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I2251b8b2d7f94124f9955f52b917dc3b064f090e Gerrit-Change-Number: 15317 Gerrit-PatchSet: 3 Gerrit-Owner: Jairo Balart Gerrit-Assignee: Giacomo Travaglini Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jairo Balart Gerrit-Reviewer: Javier Bueno Hedo Gerrit-CC: Andreas Sandberg Gerrit-CC: Ilias Vougioukas Gerrit-CC: Pau Cabre Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu: move TAGE predictor code to a base class not inheriting from BPr...
Javier Bueno Hedo has uploaded a new patch set (#2) to the change originally created by Jairo Balart. ( https://gem5-review.googlesource.com/c/public/gem5/+/15317 ) Change subject: cpu: move TAGE predictor code to a base class not inheriting from BPredUnit. .. cpu: move TAGE predictor code to a base class not inheriting from BPredUnit. This base code can be used for TAGE-based indirect base predictors. Change-Id: I2251b8b2d7f94124f9955f52b917dc3b064f090e --- M src/cpu/pred/2bit_local.cc M src/cpu/pred/2bit_local.hh M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript M src/cpu/pred/bi_mode.cc M src/cpu/pred/bi_mode.hh M src/cpu/pred/bpred_unit.cc M src/cpu/pred/bpred_unit.hh M src/cpu/pred/ltage.cc M src/cpu/pred/ltage.hh M src/cpu/pred/tage.cc M src/cpu/pred/tage.hh A src/cpu/pred/tage_base.cc A src/cpu/pred/tage_base.hh M src/cpu/pred/tournament.cc M src/cpu/pred/tournament.hh 16 files changed, 1,505 insertions(+), 1,062 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15317 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I2251b8b2d7f94124f9955f52b917dc3b064f090e Gerrit-Change-Number: 15317 Gerrit-PatchSet: 2 Gerrit-Owner: Jairo Balart Gerrit-Assignee: Giacomo Travaglini Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jairo Balart Gerrit-Reviewer: Javier Bueno Hedo Gerrit-CC: Andreas Sandberg Gerrit-CC: Ilias Vougioukas Gerrit-CC: Pau Cabre Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
