Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/52123 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Add partial param to TlbEntry
..
arch-arm: Add partial param to TlbEntry
The boolean will flag a partial translation
JIRA: https://gem5.atlassian.net/browse/GEM5-1108
Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52123
Reviewed-by: Jason Lowe-Power
Reviewed-by: Andreas Sandberg
Maintainer: Jason Lowe-Power
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/pagetable.hh
1 file changed, 24 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 4cfdf2a..8300175 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -244,6 +244,8 @@
// This is used to distinguish between instruction and data entries
// in unified TLBs
TypeTLB type;
+// True if the entry is caching a partial translation (a table walk)
+bool partial;
// Type of memory
bool nonCacheable; // Can we wrap this in mtype?
@@ -266,6 +268,7 @@
domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
longDescFormat(false), isHyp(false), global(false), valid(true),
ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
+ partial(false),
nonCacheable(uncacheable),
shareable(false), outerShareable(false), xn(0), pxn(0)
{
@@ -283,7 +286,7 @@
domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
longDescFormat(false), isHyp(false), global(false), valid(false),
ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
- nonCacheable(false),
+ partial(false), nonCacheable(false),
shareable(false), outerShareable(false), xn(0), pxn(0)
{
// no restrictions by default, hap = 0x3
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Gerrit-Change-Number: 52123
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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