[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: functions for connecting sequencer ports
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31417 ) Change subject: mem-ruby: functions for connecting sequencer ports .. mem-ruby: functions for connecting sequencer ports Added functions for connecting the sequencer and cpu ports. Using these functions instead of wiring up the ports directly allow protocols to provide specialized sequencer implementations. For instance, connecting the cpu icache_port and dcache_port to different sequencer ports or to different sequencers. A follow-up patch will update the configurations to use these functions. Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31417 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/mem/ruby/system/Sequencer.py 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 0e23fc0..f56574c 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -99,6 +99,32 @@ # 99 is the dummy default value coreid = Param.Int(99, "CorePair core id") + def connectCpuPorts(self, cpu): + """ + Helper for connecting all cpu memory request output ports to this + object's in_ports. + This assumes the provided cpu object is an instance of BaseCPU. Non-cpu + objects should use connectInstPort and connectDataPort. + """ + import m5.objects + assert(isinstance(cpu, m5.objects.BaseCPU)) + # this connects all cpu mem-side ports to self.in_ports + cpu.connectAllPorts(self) + + def connectIOPorts(self, piobus): + """ + Helper for connecting this object's IO request and response ports to the + provided bus object. Usually a iobus object is used to wireup IO + components in a full system simulation. Incoming/Outgoing IO requests do + not go though the SLICC protocol so the iobus must be connected to the + sequencer directly. + """ + import m5.defines + self.pio_request_port = piobus.cpu_side_ports + self.mem_request_port = piobus.cpu_side_ports + if m5.defines.buildEnv['TARGET_ISA'] == "x86": + self.pio_response_port = piobus.mem_side_ports + class RubyHTMSequencer(RubySequencer): type = 'RubyHTMSequencer' cxx_class = 'HTMSequencer' -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31417 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Gerrit-Change-Number: 31417 Gerrit-PatchSet: 7 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: functions for connecting sequencer ports
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31417 ) Change subject: mem-ruby: functions for connecting sequencer ports .. mem-ruby: functions for connecting sequencer ports Added functions for connecting the sequencer and cpu ports. Using these functions instead of wiring up the ports directly allow protocols to provide specialized sequencer implementations. For instance, connecting the cpu icache_port and dcache_port to different sequencer ports or to different sequencers. A follow-up patch will update the configurations to use these functions. Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Signed-off-by: Tiago Mück --- M src/mem/ruby/system/Sequencer.py M tests/gem5/cpu_tests/ref/Bubblesort 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 0a231a9..d6e9bfb 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -81,6 +81,16 @@ # 99 is the dummy default value coreid = Param.Int(99, "CorePair core id") + def connectCpuPorts(self, cpu): + assert(isinstance(cpu, BaseCPU)) + cpu.connectAllPorts(self) + + def connectInstPort(self, object, portname): + setattr(object, portname, self.slave) + + def connectDataPort(self, object, portname): + setattr(object, portname, self.slave) + class DMASequencer(RubyPort): type = 'DMASequencer' cxx_header = "mem/ruby/system/DMASequencer.hh" diff --git a/tests/gem5/cpu_tests/ref/Bubblesort b/tests/gem5/cpu_tests/ref/Bubblesort index 79d2ae3..e69de29 100644 --- a/tests/gem5/cpu_tests/ref/Bubblesort +++ b/tests/gem5/cpu_tests/ref/Bubblesort @@ -1,6 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - - -Global frequency set at 1 ticks per second --5 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31417 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b Gerrit-Change-Number: 31417 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
