Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10995 )
Change subject: misc: Substitute pointer to Request with aliased RequestPtr
......................................................................
misc: Substitute pointer to Request with aliased RequestPtr
Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.
Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutier...@amd.com>
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutier...@amd.com>
---
M src/arch/alpha/locked_mem.hh
M src/arch/arm/locked_mem.hh
M src/arch/generic/locked_mem.hh
M src/arch/hsail/insts/mem.hh
M src/arch/mips/locked_mem.hh
M src/arch/riscv/locked_mem.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/traffic_gen/base_gen.cc
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/shader.cc
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
M src/mem/cache/prefetch/queued.cc
32 files changed, 68 insertions(+), 66 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 36a6a03..a71a24c 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -85,7 +85,7 @@
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
xc->setMiscReg(MISCREG_LOCKFLAG, true);
@@ -99,7 +99,7 @@
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index 2fcbc4a..d339785 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -91,7 +91,7 @@
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
xc->setMiscReg(MISCREG_LOCKFLAG, true);
@@ -111,7 +111,7 @@
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
if (req->isSwap())
return true;
diff --git a/src/arch/generic/locked_mem.hh b/src/arch/generic/locked_mem.hh
index 68a4ff5..f653799 100644
--- a/src/arch/generic/locked_mem.hh
+++ b/src/arch/generic/locked_mem.hh
@@ -63,7 +63,7 @@
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
}
@@ -76,7 +76,7 @@
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
return true;
}
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index 36a6cbc..68a61fe 100644
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -461,9 +461,10 @@
*d = gpuDynInst->wavefront()->ldsChunk->
read<c0>(vaddr);
} else {
- Request *req = new Request(0, vaddr,
sizeof(c0), 0,
-
gpuDynInst->computeUnit()->masterId(),
- 0, gpuDynInst->wfDynId);
+ RequestPtr req = new Request(0,
+ vaddr, sizeof(c0), 0,
+ gpuDynInst->computeUnit()->masterId(),
+ 0, gpuDynInst->wfDynId);
gpuDynInst->setRequestFlags(req);
PacketPtr pkt = new Packet(req,
MemCmd::ReadReq);
@@ -588,7 +589,7 @@
gpuDynInst->statusBitVector = VectorMask(1);
gpuDynInst->useContinuation = false;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::ACQUIRE);
@@ -1014,7 +1015,7 @@
gpuDynInst->execContinuation = &GPUStaticInst::execSt;
gpuDynInst->useContinuation = true;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::RELEASE);
@@ -1065,7 +1066,7 @@
gpuDynInst->wavefront()->ldsChunk->write<c0>(vaddr,
*d);
} else {
- Request *req =
+ RequestPtr req =
new Request(0, vaddr, sizeof(c0), 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
@@ -1488,7 +1489,7 @@
gpuDynInst->useContinuation = true;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::RELEASE);
@@ -1620,7 +1621,7 @@
"type.\n");
}
} else {
- Request *req =
+ RequestPtr req =
new Request(0, vaddr, sizeof(c0), 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId,
@@ -1675,7 +1676,7 @@
// the acquire completes
gpuDynInst->useContinuation = false;
// create request
- Request *req = new Request(0, 0, 0, 0,
+ RequestPtr req = new Request(0, 0, 0, 0,
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId);
req->setFlags(Request::ACQUIRE);
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 5c1e60a..7fa1642 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -75,7 +75,7 @@
template <class XC>
inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
xc->setMiscReg(MISCREG_LLFLAG, true);
@@ -92,7 +92,7 @@
template <class XC>
inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index 61fbe0d..1583258 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -82,7 +82,7 @@
template <class XC> inline void
-handleLockedRead(XC *xc, Request *req)
+handleLockedRead(XC *xc, RequestPtr req)
{
locked_addrs.push(req->getPaddr() & ~0xF);
DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
@@ -94,7 +94,7 @@
{}
template <class XC> inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
{
// Normally RISC-V uses zero to indicate success and nonzero to
indicate
// failure (right now only 1 is reserved), but in gem5 zero indicates
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index ae408e3..e94f500 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -893,9 +893,9 @@
Request::Flags flags)
{
instFlags[ReqMade] = true;
- Request *req = NULL;
- Request *sreqLow = NULL;
- Request *sreqHigh = NULL;
+ RequestPtr req = NULL;
+ RequestPtr sreqLow = NULL;
+ RequestPtr sreqHigh = NULL;
if (instFlags[ReqMade] && translationStarted()) {
req = savedReq;
@@ -949,9 +949,9 @@
traceData->setMem(addr, size, flags);
instFlags[ReqMade] = true;
- Request *req = NULL;
- Request *sreqLow = NULL;
- Request *sreqHigh = NULL;
+ RequestPtr req = NULL;
+ RequestPtr sreqLow = NULL;
+ RequestPtr sreqHigh = NULL;
if (instFlags[ReqMade] && translationStarted()) {
req = savedReq;
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 07b6553..1533d74 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -337,7 +337,7 @@
* Checks if the flags set by the Checker and Checkee match.
*/
bool
-CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
+CheckerCPU::checkFlags(RequestPtr unverified_req, Addr vAddr,
Addr pAddr, int flags)
{
Addr unverifiedVAddr = unverified_req->getVaddr();
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index f79aa08..101a16b 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -531,7 +531,7 @@
dumpAndExit();
}
- bool checkFlags(Request *unverified_req, Addr vAddr,
+ bool checkFlags(RequestPtr unverified_req, Addr vAddr,
Addr pAddr, int flags);
void dumpAndExit();
@@ -540,7 +540,7 @@
SimpleThread *threadBase() { return thread; }
InstResult unverifiedResult;
- Request *unverifiedReq;
+ RequestPtr unverifiedReq;
uint8_t *unverifiedMemData;
bool changedPC;
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index cb0611b..822df02 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -423,7 +423,7 @@
}
}
- Request *fragment = new Request();
+ RequestPtr fragment = new Request();
fragment->setContext(request.contextId());
fragment->setVirt(0 /* asid */,
@@ -452,7 +452,7 @@
for (unsigned int fragment_index = 0; fragment_index < numFragments;
fragment_index++)
{
- Request *fragment = fragmentRequests[fragment_index];
+ RequestPtr fragment = fragmentRequests[fragment_index];
DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s"
" (%d, 0x%x)\n",
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index d4973f5..9ee40f5 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -399,7 +399,7 @@
/** Fragment Requests corresponding to the address ranges of
* each fragment */
- std::vector<Request *> fragmentRequests;
+ std::vector<RequestPtr> fragmentRequests;
/** Packets matching fragmentRequests to issue fragments to memory
*/
std::vector<Packet *> fragmentPackets;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a2813b3..a7a095c 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -510,11 +510,11 @@
public:
/** Executes the load at the given index. */
- Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
+ Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
int load_idx);
/** Executes the store at the given index. */
- Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
+ Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
uint8_t *data, int store_idx);
/** Returns the index of the head load instruction. */
@@ -549,7 +549,7 @@
template <class Impl>
Fault
-LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
+LSQUnit<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr
sreqHigh,
int load_idx)
{
DynInstPtr load_inst = loadQueue[load_idx];
@@ -883,7 +883,7 @@
template <class Impl>
Fault
-LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
+LSQUnit<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr
sreqHigh,
uint8_t *data, int store_idx)
{
assert(storeQueue[store_idx].inst);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index ca6a7f3..e8e2c18 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -831,7 +831,7 @@
DynInstPtr inst = storeQueue[storeWBIdx].inst;
- Request *req = storeQueue[storeWBIdx].req;
+ RequestPtr req = storeQueue[storeWBIdx].req;
RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 7a368ab..0e7c59f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -331,7 +331,7 @@
SimpleThread* thread = t_info.thread;
// use the CPU's statically allocated read request and packet objects
- Request *req = &data_read_req;
+ RequestPtr req = &data_read_req;
if (traceData)
traceData->setMem(addr, size, flags);
@@ -435,7 +435,7 @@
}
// use the CPU's statically allocated write request and packet objects
- Request *req = &data_write_req;
+ RequestPtr req = &data_write_req;
if (traceData)
traceData->setMem(addr, size, flags);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 36a2cb0..025c7a3 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -468,7 +468,7 @@
void
-BaseSimpleCPU::setupFetchRequest(Request *req)
+BaseSimpleCPU::setupFetchRequest(RequestPtr req)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 15ab2ab..64fa58d 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -129,7 +129,7 @@
void checkForInterrupts();
- void setupFetchRequest(Request *req);
+ void setupFetchRequest(RequestPtr req);
void preExecute();
void postExecute();
void advancePC(const Fault &fault);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 083de2b..657c297 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -620,7 +620,7 @@
if (needToFetch) {
_status = BaseSimpleCPU::Running;
- Request *ifetch_req = new Request();
+ RequestPtr ifetch_req = new Request();
ifetch_req->taskId(taskId());
ifetch_req->setContext(thread->contextId());
setupFetchRequest(ifetch_req);
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc
b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index c5c48f1..3319e84 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -60,7 +60,7 @@
Packet::Command cmd;
// For simplicity, requests are assumed to be 1 byte-sized
- Request *req = new Request(m_address, 1, flags, masterId);
+ RequestPtr req = new Request(m_address, 1, flags, masterId);
//
// Based on the current state, issue a load or a store
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 386a498..17ae04c 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -60,7 +60,7 @@
Request::Flags flags;
// For simplicity, requests are assumed to be 1 byte-sized
- Request *req = new Request(m_address, 1, flags, masterId);
+ RequestPtr req = new Request(m_address, 1, flags, masterId);
Packet::Command cmd;
bool do_write = (random_mt.random(0, 100) < m_percent_writes);
diff --git
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
index 56edd84..be1921a 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
@@ -129,7 +129,7 @@
void
GarnetSyntheticTraffic::completeRequest(PacketPtr pkt)
{
- Request *req = pkt->req;
+ RequestPtr req = pkt->req;
DPRINTF(GarnetSyntheticTraffic,
"Completed injection of %s packet for address %x\n",
@@ -279,7 +279,7 @@
//
MemCmd::Command requestType;
- Request *req = nullptr;
+ RequestPtr req = nullptr;
Request::Flags flags;
// Inject in specific Vnet
diff --git a/src/cpu/testers/memtest/memtest.cc
b/src/cpu/testers/memtest/memtest.cc
index ccd978c..89b4d11 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -136,7 +136,7 @@
void
MemTest::completeRequest(PacketPtr pkt, bool functional)
{
- Request *req = pkt->req;
+ RequestPtr req = pkt->req;
assert(req->getSize() == 1);
// this address is no longer outstanding
@@ -246,7 +246,7 @@
bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
!uncacheable;
- Request *req = new Request(paddr, 1, flags, masterId);
+ RequestPtr req = new Request(paddr, 1, flags, masterId);
req->setContext(id);
outstandingAddrs.insert(paddr);
diff --git a/src/cpu/testers/rubytest/Check.cc
b/src/cpu/testers/rubytest/Check.cc
index 2ce79e7..776d711 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -107,7 +107,7 @@
}
// Prefetches are assumed to be 0 sized
- Request *req = new Request(m_address, 0, flags,
+ RequestPtr req = new Request(m_address, 0, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
req->setContext(index);
@@ -146,7 +146,7 @@
Request::Flags flags;
- Request *req = new Request(m_address, CHECK_SIZE, flags,
+ RequestPtr req = new Request(m_address, CHECK_SIZE, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
Packet::Command cmd;
@@ -179,7 +179,7 @@
Addr writeAddr(m_address + m_store_count);
// Stores are assumed to be 1 byte-sized
- Request *req = new Request(writeAddr, 1, flags,
m_tester_ptr->masterId(),
+ RequestPtr req = new Request(writeAddr, 1, flags,
m_tester_ptr->masterId(),
curTick(), m_pc);
req->setContext(index);
@@ -244,7 +244,7 @@
}
// Checks are sized depending on the number of bytes written
- Request *req = new Request(m_address, CHECK_SIZE, flags,
+ RequestPtr req = new Request(m_address, CHECK_SIZE, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
req->setContext(index);
diff --git a/src/cpu/testers/traffic_gen/base_gen.cc
b/src/cpu/testers/traffic_gen/base_gen.cc
index cd568f1..b5b4f58 100644
--- a/src/cpu/testers/traffic_gen/base_gen.cc
+++ b/src/cpu/testers/traffic_gen/base_gen.cc
@@ -59,7 +59,7 @@
Request::FlagsType flags)
{
// Create new request
- Request *req = new Request(addr, size, flags, masterID);
+ RequestPtr req = new Request(addr, size, flags, masterID);
// Dummy PC to have PC-based prefetchers latch on; get entropy into
higher
// bits
req->setPC(((Addr)masterID) << 2);
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index aa4f0a3..042347c 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -1178,7 +1178,7 @@
if (!stride)
break;
- Request *prefetch_req = new Request(0, vaddr + stride * pf *
+ RequestPtr prefetch_req = new Request(0, vaddr + stride * pf *
TheISA::PageBytes,
sizeof(uint8_t), 0,
computeUnit->masterId(),
@@ -1801,7 +1801,7 @@
{
// this is just a request to carry the GPUDynInstPtr
// back and forth
- Request *newRequest = new Request();
+ RequestPtr newRequest = new Request();
newRequest->setPaddr(0x0);
// ReadReq is not evaluted by the LDS but the Packet ctor requires this
diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc
index c989d67..36ef1e1 100644
--- a/src/gpu-compute/fetch_unit.cc
+++ b/src/gpu-compute/fetch_unit.cc
@@ -145,7 +145,7 @@
}
// set up virtual request
- Request *req = new Request(0, vaddr, size, Request::INST_FETCH,
+ RequestPtr req = new Request(0, vaddr, size, Request::INST_FETCH,
computeUnit->masterId(), 0, 0, 0);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
diff --git a/src/gpu-compute/gpu_dyn_inst.hh
b/src/gpu-compute/gpu_dyn_inst.hh
index 8d259cb..4b1c9fd 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -382,7 +382,7 @@
}
void
- setRequestFlags(Request *req, bool setMemOrder=true)
+ setRequestFlags(RequestPtr req, bool setMemOrder=true)
{
// currently these are the easy scopes to deduce
if (isPrivateSeg()) {
diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc
index d3453c2..8e7ba9a 100644
--- a/src/gpu-compute/shader.cc
+++ b/src/gpu-compute/shader.cc
@@ -338,7 +338,7 @@
for (ChunkGenerator gen(address, size,
cuList.at(cu_id)->cacheLineSize());
!gen.done(); gen.next()) {
- Request *req = new Request(0, gen.addr(), gen.size(), 0,
+ RequestPtr req = new Request(0, gen.addr(), gen.size(), 0,
cuList[0]->masterId(), 0, 0, 0);
doFunctionalAccess(req, cmd, data_buf, suppress_func_errors,
cu_id);
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index b41c82b..1d112dc 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -199,7 +199,7 @@
void
AbstractMemory::trackLoadLocked(PacketPtr pkt)
{
- Request *req = pkt->req;
+ RequestPtr req = pkt->req;
Addr paddr = LockedAddr::mask(req->getPaddr());
// first we check if we already have a locked addr for this
@@ -230,7 +230,7 @@
bool
AbstractMemory::checkLockedAddrList(PacketPtr pkt)
{
- Request *req = pkt->req;
+ RequestPtr req = pkt->req;
Addr paddr = LockedAddr::mask(req->getPaddr());
bool isLLSC = pkt->isLLSC();
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index b57f73b..29c8c3f 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -79,12 +79,12 @@
static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
// check for matching execution context
- bool matchesContext(Request *req) const
+ bool matchesContext(RequestPtr req) const
{
return (contextId == req->contextId());
}
- LockedAddr(Request *req) : addr(mask(req->getPaddr())),
+ LockedAddr(RequestPtr req) : addr(mask(req->getPaddr())),
contextId(req->contextId())
{}
@@ -140,7 +140,7 @@
// this method must be called on *all* stores since even
// non-conditional stores must clear any matching lock addresses.
bool writeOK(PacketPtr pkt) {
- Request *req = pkt->req;
+ RequestPtr req = pkt->req;
if (lockedAddrList.empty()) {
// no locked addrs: nothing to check, store_conditional fails
bool isLLSC = pkt->isLLSC();
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index a8f29e3..f753cc3 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1278,7 +1278,7 @@
writebacks[Request::wbMasterId]++;
- Request *req = new Request(regenerateBlkAddr(blk), blkSize, 0,
+ RequestPtr req = new Request(regenerateBlkAddr(blk), blkSize, 0,
Request::wbMasterId);
if (blk->isSecure())
req->setFlags(Request::SECURE);
@@ -1313,7 +1313,7 @@
PacketPtr
BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
{
- Request *req = new Request(regenerateBlkAddr(blk), blkSize, 0,
+ RequestPtr req = new Request(regenerateBlkAddr(blk), blkSize, 0,
Request::wbMasterId);
if (blk->isSecure()) {
req->setFlags(Request::SECURE);
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 34f3dc5..86c1640 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -872,7 +872,8 @@
assert(!writebackClean);
assert(blk && blk->isValid() && !blk->isDirty());
// Creating a zero sized write, a message to the snoop filter
- Request *req =
+
+ RequestPtr req =
new Request(regenerateBlkAddr(blk), blkSize, 0,
Request::wbMasterId);
if (blk->isSecure())
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index bf3a384..00d62f1 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -223,7 +223,7 @@
}
/* Create a prefetch memory request */
- Request *pf_req =
+ RequestPtr pf_req =
new Request(pf_info.first, blkSize, 0, masterId);
if (is_secure) {
--
To view, visit https://gem5-review.googlesource.com/10995
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Gerrit-Change-Number: 10995
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Anthony Gutierrez <anthony.gutier...@amd.com>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-MessageType: merged
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