[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementation of Hardware Breakpoint exception
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27967 )
Change subject: arch-arm: Implementation of Hardware Breakpoint exception
..
arch-arm: Implementation of Hardware Breakpoint exception
This code implementes hardware breakpoint exception as part of
software debug explained in ARMv8 reference manual ChapterD2.
+ ArmISA.py: Modify register to allow up to 15 Breakpoint registers
+ Sconscript: Add new file self_debug
+ faults.cc/hh: Defintion and implementation of HardwareBreakpoint
exception inheriting ArmFault.
+ isa.cc/hh: ArmISA contains now an attribute pointing to the SelfDebug
object that will be used to be access SelfDebug infrastructure
Added special cases for setMiscReg to cache debug enable bits.
+ miscregs.hh/cc: Definition and initialization of DBGDCn and DBGDVn
registers.
+ tlb.cc/hh: We include the access to check for breakpoint instruction as
part of the tlb translation process, checking if it comes from
a
fetch in the itlb
+ types.hh: Definition of new bitwise register types.
+ utility.cc/hh: Definition and implementation of auxiliar functions for
the selfDebug.
+ self_debug.hh/cc: Main files that include the implemenattion of
breakpoint checks, selfdebug enable and auxiliar functions.
Change-Id: I0e2a4be7f778de560c512253a9148da61e3e7e7a
---
M src/arch/arm/ArmISA.py
M src/arch/arm/SConscript
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
A src/arch/arm/self_debug.cc
A src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
18 files changed, 1,682 insertions(+), 71 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 2641ec3..b030e6c 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -90,8 +90,8 @@
id_aa64afr1_el1 = Param.UInt64(0x,
"AArch64 Auxiliary Feature Register 1")
-# 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
-id_aa64dfr0_el1 = Param.UInt64(0x00101006,
+# 1 CTX CMPs | 2 WRPs | 16 BRPs | !PMU | !Trace | Debug v8-A
+id_aa64dfr0_el1 = Param.UInt64(0x0010F006,
"AArch64 Debug Feature Register 0")
# Reserved for future expansion
id_aa64dfr1_el1 = Param.UInt64(0x,
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index e51437e..958236e 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -83,6 +83,7 @@
Source('stacktrace.cc')
Source('system.cc')
Source('table_walker.cc')
+Source('self_debug.cc')
Source('stage2_mmu.cc')
Source('stage2_lookup.cc')
Source('tlb.cc')
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 22894f3..ba8369a 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -281,6 +281,10 @@
"Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT
);
+template<> ArmFault::FaultVals ArmFaultVals::vals(
+"Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
+0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT
+);
template<> ArmFault::FaultVals ArmFaultVals::vals(
// Some dummy values
"ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
@@ -1075,6 +1079,16 @@
} else if (stage2) {
tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
tc->setMiscReg(T::HFarIndex, OVAddr);
+} else if (debug > ArmFault::NODEBUG) {
+DBGDS32 Rext = tc->readMiscReg(MISCREG_DBGDSCRext);
+tc->setMiscReg(T::FarIndex, faultAddr);
+if (debug == ArmFault::BRKPOINT){
+Rext.moe = 0x1;
+}
+
+tc->setMiscReg(T::FsrIndex, fsr);
+tc->setMiscReg(MISCREG_DBGDSCRext, Rext);
+
} else {
tc->setMiscReg(T::FsrIndex, fsr);
tc->setMiscReg(T::FarIndex, faultAddr);
@@ -1277,9 +1291,10 @@
toHyp = scr.ns && (currEL(tc) == EL2);
// otherwise, check whether to take to Hyp mode through Hyp Trap vector
toHyp |= (stage2 ||
- ((source == DebugEvent) && hdcr.tde && (currEL(tc) != EL2)) |
|
- ((source == SynchronousExternalAbort) && hcr.tge &&
-(currEL(tc) == EL0))) && !inSecureState(tc);
+ ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
+ (currEL(tc) != EL2)) ||
+ ((source == SynchronousExternalAbort) && hcr.tge &&
+
[gem5-dev] Change in gem5/gem5[develop]: misc, tests: Updated and generalized the resource url for tests
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27987 )
Change subject: misc, tests: Updated and generalized the resource url for
tests
..
misc, tests: Updated and generalized the resource url for tests
As we are now going to maintain different bundles of resources for each
gem5 release, the resources have been archived to
http://dist.gem5.org/dist/current for gem5 19. The development branch
will use http://dist.gem5.org/dist/develop going forward. New releases
will follow the format http://dist.gem5.org/dist/{VERSION}.
This patch makes the resources url a command-line parameter, set to the
"correct" url by default. This will be updated to the correct, archived,
version subdirectory upon release of a new gem5 version. E.g.:
http://dist.gem5.org/dist/v20 for the gem5 20 release.
Change-Id: Ia16c496be3a60283ecc431ffaa5b059e1932b526
Issue-on: https://gem5.atlassian.net/browse/GEM5-431
---
M ext/testlib/config.py
M tests/gem5/cpu_tests/test.py
M tests/gem5/fs/linux/arm/test.py
M tests/gem5/hello_se/test_hello_se.py
M tests/gem5/insttest_se/test.py
M tests/gem5/m5_util/test_exit.py
M tests/gem5/m5threads_test_atomic/test.py
M tests/gem5/x86-boot-tests/test_linux_boot.py
M tests/test-progs/hello/src/Makefile.arm
M tests/test-progs/hello/src/Makefile.x86
M tests/test-progs/m5-exit/src/Makefile.x86
11 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/ext/testlib/config.py b/ext/testlib/config.py
index 39d6a24..348d0a8 100644
--- a/ext/testlib/config.py
+++ b/ext/testlib/config.py
@@ -220,6 +220,7 @@
os.pardir))
defaults.result_path = os.path.join(os.getcwd(), '.testing-results')
defaults.list_only_failed = False
+defaults.resource_url = 'http://dist.gem5.org/dist/develop'
def define_constants(constants):
'''
@@ -579,6 +580,12 @@
default=None,
help='Path where binaries are stored (downloaded if not
present)'
),
+Argument(
+'--resource-url',
+action='store',
+default=config._defaults.resource_url,
+help='The URL where the resources reside.'
+),
]
diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index ba90e2a..339d15a 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -56,7 +56,7 @@
else:
base_path = joinpath(absdirpath(__file__), 'benchmarks', 'bin')
-base_url
= 'http://dist.gem5.org/dist/current/gem5/cpu_tests/benchmarks/bin/'
+base_url = config.resource_url + '/gem5/cpu_tests/benchmarks/bin/'
for isa in valid_isas:
path = joinpath(base_path, isa)
for workload in workloads:
diff --git a/tests/gem5/fs/linux/arm/test.py
b/tests/gem5/fs/linux/arm/test.py
index f90299b..39cb011 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -81,7 +81,7 @@
]
tarball = 'aarch-system-201901106.tar.bz2'
-url = "http://dist.gem5.org/dist/current/arm/; + tarball
+url = config.resource_url + "/arm/" + tarball
filepath = os.path.dirname(os.path.abspath(__file__))
path = config.bin_path if config.bin_path else filepath
arm_fs_binaries = DownloadedArchive(url, path, tarball)
diff --git a/tests/gem5/hello_se/test_hello_se.py
b/tests/gem5/hello_se/test_hello_se.py
index 75043b9..260daad 100644
--- a/tests/gem5/hello_se/test_hello_se.py
+++ b/tests/gem5/hello_se/test_hello_se.py
@@ -81,7 +81,7 @@
base_path = joinpath(absdirpath(__file__), '..', 'test-progs', 'hello',
'bin')
-urlbase = 'http://dist.gem5.org/dist/current/test-progs/hello/bin/'
+urlbase = config.resource_url + '/test-progs/hello/bin/'
ref_path = joinpath(getcwd(), 'ref')
verifiers = (
diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py
index c3fa322..6bddc86 100644
--- a/tests/gem5/insttest_se/test.py
+++ b/tests/gem5/insttest_se/test.py
@@ -51,7 +51,7 @@
else:
base_path = joinpath(absdirpath(__file__), '..', 'test-progs')
-urlbase = 'http://dist.gem5.org/dist/current/test-progs/insttest/bin/'
+urlbase = config.resource_url + '/test-progs/insttest/bin/'
for isa in test_progs:
for binary in test_progs[isa]:
for operating_s in supported_os[isa]:
diff --git a/tests/gem5/m5_util/test_exit.py
b/tests/gem5/m5_util/test_exit.py
index 02e97cf..0a0dc16 100644
--- a/tests/gem5/m5_util/test_exit.py
+++ b/tests/gem5/m5_util/test_exit.py
@@ -53,8 +53,7 @@
path = joinpath(absdirpath(__file__), '..',
'test-progs', 'hello', 'bin', 'x86', 'linux')
filename = 'm5_exit'
-url = ('http://dist.gem5.org/dist/current/test-progs/' +
- 'm5-exit/bin/x86/linux/m5_exit')
+url = (config.resource_url + '/test-progs/m5-exit/bin/x86/linux/m5_exit')
test_program = DownloadedProgram(url, path, filename)
a = verifier.MatchRegex(m5_exit_regex)
diff --git
[gem5-dev] Change in gem5/gem5[develop]: cpu: Check for a switch in renaming at startup stage
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28007 )
Change subject: cpu: Check for a switch in renaming at startup stage
..
cpu: Check for a switch in renaming at startup stage
This needs to be done since setting up vector renaming mode during
construction time might not be possible if some SimObject haven't been
initialized yet. By adding the extra check at startup time we are sure
the vector renaming mode is set up right.
JIRA: https://gem5.atlassian.net/browse/GEM5-438
Change-Id: Ibe3e9881e62c26c0a322232fb9651683155c2be8
Signed-off-by: Giacomo Travaglini
---
M src/cpu/o3/cpu.cc
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 5f0a98b..e90617d 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -599,8 +599,10 @@
FullO3CPU::startup()
{
BaseCPU::startup();
-for (int tid = 0; tid < numThreads; ++tid)
+for (int tid = 0; tid < numThreads; ++tid) {
isa[tid]->startup(threadContexts[tid]);
+switchRenameMode(tid, );
+}
fetch.startupStage();
decode.startupStage();
--
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[gem5-dev] Change in gem5/gem5[develop]: arch: Fix VecReg container alignement to 128bits view
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27968 )
Change subject: arch: Fix VecReg container alignement to 128bits view
..
arch: Fix VecReg container alignement to 128bits view
This Patch will fix the alignment problem that appears sometimes
when we try to create a view of 128 bits over the VecRegContainer
object.
That container is initially created as std::array, so
there is no obligation to be aligned to 16 bytes. This patches forces
all containers to be aligned to 16 bytes.
The problem has been observed in the Jira Issue:
https://gem5.atlassian.net/browse/GEM5-320
Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
---
M src/arch/generic/vec_reg.hh
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 4156ac5..e26cf8b 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -279,7 +279,8 @@
static constexpr inline size_t size() { return SIZE; };
using Container = std::array;
private:
-Container container;
+// 16-byte aligned to support 128bit element view
+alignas(16) Container container;
using MyClass = VecRegContainer;
public:
--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Produce list of workload types in workloads.py
Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/27970 to review the following change. Change subject: configs: Produce list of workload types in workloads.py .. configs: Produce list of workload types in workloads.py Change-Id: I3f585e006704e671775af8d66d241e555d34cb08 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris --- M configs/example/arm/workloads.py 1 file changed, 8 insertions(+), 0 deletions(-) diff --git a/configs/example/arm/workloads.py b/configs/example/arm/workloads.py index 61e57f6..dd00819 100644 --- a/configs/example/arm/workloads.py +++ b/configs/example/arm/workloads.py @@ -37,6 +37,7 @@ from __future__ import print_function from __future__ import absolute_import +import inspect import m5 from m5.objects import * from m5.options import * @@ -83,3 +84,10 @@ # Arm Trusted Firmware will provide a PSCI implementation system._have_psci = True + +def _is_workload(cls): +""" Just a wrapper around the issubclass """ +return inspect.isclass(cls) and \ +issubclass(cls, ArmFsWorkload) + +workload_types = dict(inspect.getmembers(sys.modules[__name__], _is_workload)) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27970 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3f585e006704e671775af8d66d241e555d34cb08 Gerrit-Change-Number: 27970 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[develop]: configs: Add an example workloads module
Hello Ciro Santilli, Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/27969
to review the following change.
Change subject: configs: Add an example workloads module
..
configs: Add an example workloads module
This will be a collection of Workload types.
At the moment we provide the following:
* ArmBaremetal: modelling a simple baremetal workload
* ArmTrustedFirmware: modelling the arm trusted firmware workload
Change-Id: Ib46286c03a1c952f981b172c1ea6aa4a6668757e
Signed-off-by: Giacomo Travaglini
Reviewed-by: Ciro Santilli
Reviewed-by: Nikos Nikoleris
---
A configs/example/arm/workloads.py
1 file changed, 85 insertions(+), 0 deletions(-)
diff --git a/configs/example/arm/workloads.py
b/configs/example/arm/workloads.py
new file mode 100644
index 000..61e57f6
--- /dev/null
+++ b/configs/example/arm/workloads.py
@@ -0,0 +1,85 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+import m5
+from m5.objects import *
+from m5.options import *
+
+from common.SysPaths import binary, disk
+
+class ArmBaremetal(ArmFsWorkload):
+""" Baremetal workload """
+atags_addr = 0
+
+def __init__(self, obj, system, **kwargs):
+super(ArmBaremetal, self).__init__(**kwargs)
+
+self.object_file = obj
+
+class ArmTrustedFirmware(ArmFsWorkload):
+"""
+Arm Trusted Firmware (TFA) workload.
+
+It models the firmware design described at:
+
+
https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html
+
+The Workload is expecting to find a set of firmare images under
+the M5_PATH/binaries path. Those images are:
+* bl1.bin (BL1 = Stage 1 Bootloader)
+* fip.bin (FIP = Firmware Image Package):
+BL2, BL31, BL33 binaries compiled under a singe package
+
+These are the results of the compilation of Arm Trusted Firmware.
+https://github.com/ARM-software/arm-trusted-firmware
+
+"""
+atags_addr = 0
+
+def __init__(self, obj, system, **kwargs):
+super(ArmTrustedFirmware, self).__init__(**kwargs)
+
+self.extras = [ binary('bl1.bin'), binary('fip.bin'), ]
+self.extras_addrs = [
+system.realview.bootmem.range.start,
+system.realview.flash0.range.start
+]
+
+# Arm Trusted Firmware will provide a PSCI implementation
+system._have_psci = True
--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Use workloads.py in baremetal.py
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/27971
to review the following change.
Change subject: configs: Use workloads.py in baremetal.py
..
configs: Use workloads.py in baremetal.py
Change-Id: I806b771df448241a7a61f496ac22c29d5bc6b84c
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
---
M configs/example/arm/baremetal.py
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/configs/example/arm/baremetal.py
b/configs/example/arm/baremetal.py
index 00a350a..00fe5e7 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -57,6 +57,7 @@
from common.cores.arm import HPI
import devices
+import workloads
# Pre-defined CPU configurations. Each tuple must be ordered as :
(cpu_class,
# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any
of
@@ -100,9 +101,6 @@
args.mem_size,
platform=platform(),
mem_mode=mem_mode,
- workload=ArmFsWorkload(
- atags_addr=0,
- object_file=args.kernel),
readfile=args.readfile)
MemConfig.config_mem(args, system)
@@ -162,6 +160,10 @@
system.have_virtualization = True
system.have_security = True
+workload_class = getattr(workloads, args.workload)
+system.workload = workload_class(
+args.kernel, system)
+
return system
def run(args):
@@ -190,6 +192,10 @@
parser.add_argument("--kernel", type=str,
default=None,
help="Binary to run")
+parser.add_argument("--workload", type=str,
+default="ArmBaremetal",
+choices=workloads.workload_types.keys(),
+help="Workload type")
parser.add_argument("--disk-image", type=str,
default=None,
help="Disk to instantiate")
--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add --machine-type option to baremetal.py
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27952 )
Change subject: configs: Add --machine-type option to baremetal.py
..
configs: Add --machine-type option to baremetal.py
Change-Id: Ie5d81b455b86f456a49ba91aa231169be319fa73
Signed-off-by: Giacomo Travaglini
Reviewed-by: Adrian Herrera
Reviewed-by: Ciro Santilli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27952
Tested-by: kokoro
---
M configs/example/arm/baremetal.py
1 file changed, 7 insertions(+), 1 deletion(-)
Approvals:
Ciro Santilli: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/arm/baremetal.py
b/configs/example/arm/baremetal.py
index 36928ec..00a350a 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -93,10 +93,12 @@
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
+platform = ObjectList.platform_list.get(args.machine_type)
+
system = devices.simpleSystem(ArmSystem,
want_caches,
args.mem_size,
- platform=VExpress_GEM5_V2(),
+ platform=platform(),
mem_mode=mem_mode,
workload=ArmFsWorkload(
atags_addr=0,
@@ -199,6 +201,10 @@
parser.add_argument("--cpu-freq", type=str, default="4GHz")
parser.add_argument("--num-cores", type=int, default=1,
help="Number of CPU cores")
+parser.add_argument("--machine-type", type=str,
+choices=ObjectList.platform_list.get_names(),
+default="VExpress_GEM5_V2",
+help="Hardware platform class")
parser.add_argument("--mem-type", default="DDR3_1600_8x8",
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie5d81b455b86f456a49ba91aa231169be319fa73
Gerrit-Change-Number: 27952
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Adrian Herrera
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add --semi-path option to baremetal.py
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27951 )
Change subject: configs: Add --semi-path option to baremetal.py
..
configs: Add --semi-path option to baremetal.py
This is to make it possible to configure the semihosting
root directory via commandline.
Change-Id: If5167abc19eb8d78db37ebc854c336fe778a8a6f
Signed-off-by: Giacomo Travaglini
Reviewed-by: Adrian Herrera
Reviewed-by: Ciro Santilli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27951
Tested-by: kokoro
---
M configs/example/arm/baremetal.py
1 file changed, 5 insertions(+), 0 deletions(-)
Approvals:
Ciro Santilli: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/arm/baremetal.py
b/configs/example/arm/baremetal.py
index 87e8952..36928ec 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -110,6 +110,7 @@
stdin=args.semi_stdin,
stdout=args.semi_stdout,
stderr=args.semi_stderr,
+files_root_dir=args.semi_path,
cmd_line = " ".join([ args.kernel ] + args.args)
)
@@ -223,6 +224,10 @@
parser.add_argument("--semi-stderr", type=str, default="stderr",
help="Standard error for semihosting " \
"(default: gem5's stderr)")
+parser.add_argument('--semi-path', type=str,
+default="",
+help=('Search path for files to be loaded through '
+ 'Arm Semihosting'))
parser.add_argument("args", default=[], nargs="*",
help="Semihosting arguments to pass to benchmark")
parser.add_argument("-P", "--param", action="append", default=[],
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27951
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If5167abc19eb8d78db37ebc854c336fe778a8a6f
Gerrit-Change-Number: 27951
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Adrian Herrera
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch,sim,kern,dev,cpu: Create a Workload SimObject.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24283 )
Change subject: arch,sim,kern,dev,cpu: Create a Workload SimObject.
..
arch,sim,kern,dev,cpu: Create a Workload SimObject.
This generalized Workload SimObject is not geared towards FS or SE
simulations, although currently it's only used in FS. This gets rid
of the ARM specific highestELIs64 property (from the workload, not the
system) and replaces it with a generic getArch.
The old globally accessible kernel symtab has been replaced with a
symtab accessor which takes a ThreadContext *. The parameter isn't used
for anything for now, but in cases where there might be multiple
symbol tables to choose from (kernel vs. current user space?) the
method will now be able to distinguish which to use. This also makes
it possible for the workload to manage its symbol table with whatever
policy makes sense for it.
That method returns a const SymbolTable * since most of the time the
symbol table doesn't need to be modified. In the one case where an
external entity needs to modify the table, two pseudo instructions,
the table to modify isn't necessarily the one that's currently active.
For instance, the pseudo instruction will likely execute in user space,
but might be intended to add a symbol to the kernel in case something
like a module was loaded.
To support that usage, the workload has a generic "insertSymbol" method
which will insert the symbol in the table that "makes sense". There is
a lot of ambiguity what that means, but it's no less ambiguous than
today where we're only saved by the fact that there is generally only
one active symbol table to worry about.
This change also introduces a KernelWorkload SimObject class which
inherits from Workload and adds in kernel related members for cases
where the kernel is specified in the config and loaded by gem5 itself.
That's the common case, but the base Workload class would be used
directly when, for instance, doing a baremetal simulation or if the
kernel is loaded by software within the simulation as is the case for
SPARC FS.
Because a given architecture specific workload class needs to inherit
from either Workload or KernelWorkload, this change removes the
ability to boot ARM without a kernel. This ability should be restored
in the future.
To make having or not having a kernel more flexible, the kernel
specific members of the KernelWorkload should be factored out into
their own object which can then be attached to a workload through a
(potentially unused) property rather than inheritance.
Change-Id: Idf72615260266d7b4478d20d4035ed5a1e7aa241
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24283
Reviewed-by: Giacomo Travaglini
Maintainer: Gabe Black
Tested-by: kokoro
---
M configs/common/FSConfig.py
M src/arch/arm/ArmFsWorkload.py
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/fs_workload.cc
M src/arch/arm/fs_workload.hh
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/stacktrace.cc
M src/arch/arm/system.cc
M src/arch/generic/linux/threadinfo.hh
M src/arch/riscv/RiscvFsWorkload.py
M src/arch/riscv/bare_metal/fs_workload.cc
M src/arch/riscv/bare_metal/fs_workload.hh
D src/arch/riscv/bare_metal/system.cc
M src/arch/riscv/fs_workload.hh
M src/arch/sparc/SparcFsWorkload.py
M src/arch/sparc/fs_workload.cc
M src/arch/sparc/fs_workload.hh
M src/arch/x86/X86FsWorkload.py
M src/arch/x86/fs_workload.cc
M src/arch/x86/fs_workload.hh
M src/arch/x86/stacktrace.cc
M src/cpu/o3/thread_state.hh
M src/cpu/simple_thread.cc
M src/kern/linux/helpers.cc
M src/sim/SConscript
M src/sim/System.py
R src/sim/Workload.py
M src/sim/debug.cc
A src/sim/kernel_workload.cc
A src/sim/kernel_workload.hh
D src/sim/os_kernel.cc
D src/sim/os_kernel.hh
M src/sim/pseudo_inst.cc
M src/sim/system.hh
R src/sim/workload.cc
A src/sim/workload.hh
36 files changed, 562 insertions(+), 572 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index a424a30..b3e248e 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -388,7 +388,7 @@
self.console = binary('mips/console')
if not cmdline:
cmdline = 'root=/dev/hda1 console=ttyS0'
-self.workload = OsKernel(command_line=fillInCmdline(mdesc, cmdline))
+self.workload = KernelWorkload(command_line=fillInCmdline(mdesc,
cmdline))
self.system_port = self.membus.slave
diff --git a/src/arch/arm/ArmFsWorkload.py b/src/arch/arm/ArmFsWorkload.py
index 459f830..bc27c6d 100644
--- a/src/arch/arm/ArmFsWorkload.py
+++ b/src/arch/arm/ArmFsWorkload.py
@@ -36,7 +36,7 @@
from m5.params import *
from m5.options import *
from m5.SimObject import *
-from m5.objects.OsKernel import OsKernel
+from m5.objects.Workload import KernelWorkload
class ArmMachineType(Enum):
[gem5-dev] Change in gem5/gem5[develop]: configs,arch,sim: Move fixFuncEventAddr into the Workload class.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24287 )
Change subject: configs,arch,sim: Move fixFuncEventAddr into the Workload
class.
..
configs,arch,sim: Move fixFuncEventAddr into the Workload class.
This is specialized per arch, and the Workload class is the only thing
actually using it. It doesn't make any sense to dispatch those calls
over to the System object, especially since that was, in most cases,
the only reason an ISA specific system class even still existed.
After this change, only ARM still has an architecture specific System
class.
Change-Id: I81b6c4db14b612bff8840157cfc56393370095e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24287
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M configs/common/FSConfig.py
M src/arch/arm/fs_workload.hh
M src/arch/arm/system.hh
D src/arch/mips/MipsSystem.py
M src/arch/mips/SConscript
D src/arch/mips/bare_iron/system.cc
D src/arch/mips/bare_iron/system.hh
D src/arch/mips/linux/system.cc
D src/arch/mips/linux/system.hh
D src/arch/mips/system.cc
D src/arch/mips/system.hh
D src/arch/riscv/RiscvSystem.py
M src/arch/riscv/SConscript
D src/arch/riscv/system.cc
D src/arch/riscv/system.hh
M src/arch/riscv/tlb.cc
M src/arch/sparc/SConscript
D src/arch/sparc/SparcSystem.py
D src/arch/sparc/system.cc
D src/arch/sparc/system.hh
M src/arch/x86/SConscript
D src/arch/x86/X86System.py
M src/arch/x86/pagetable.hh
M src/arch/x86/process.cc
D src/arch/x86/system.cc
D src/arch/x86/system.hh
M src/arch/x86/tlb.hh
M src/mem/multi_level_page_table.hh
M src/sim/SConscript
M src/sim/system.hh
D src/sim/workload.cc
M src/sim/workload.hh
32 files changed, 17 insertions(+), 957 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index b3e248e..7fc5557 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -108,7 +108,7 @@
def childImage(self, ci):
self.image.child.image_file = ci
-self = SparcSystem()
+self = System()
if not mdesc:
# generic system
mdesc = SysConfig()
@@ -362,7 +362,7 @@
ide = IdeController(disks=Parent.disks,
pci_func=0, pci_dev=0, pci_bus=0)
-self = LinuxMipsSystem()
+self = System()
if not mdesc:
# generic system
mdesc = SysConfig()
@@ -453,7 +453,7 @@
def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None,
Ruby=False):
-self = X86System()
+self = System()
if workload is None:
workload = X86FsWorkload()
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index d6e375c..46694eb 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -117,6 +117,14 @@
FsWorkload(Params *p);
void initState() override;
+
+Addr
+fixFuncEventAddr(Addr addr) const override
+{
+// Remove the low bit that thumb symbols have set
+// but that aren't actually odd aligned
+return addr & ~1;
+}
};
} // namespace ArmISA
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 1339c1c..203be1a 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -143,14 +143,6 @@
ArmSystem(Params *p);
-Addr
-fixFuncEventAddr(Addr addr) override
-{
-// Remove the low bit that thumb symbols have set
-// but that aren't actually odd aligned
-return addr & ~1;
-}
-
/** true if this a multiprocessor system */
bool multiProc;
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
deleted file mode 100644
index d32f30a..000
--- a/src/arch/mips/MipsSystem.py
+++ /dev/null
@@ -1,61 +0,0 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2007 MIPS Technologies, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE
[gem5-dev] [NOTICE] Mailing lists successfully migrated!
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[gem5-dev] Change in gem5/gem5[master]: arch-x86, cpu: Fix bpred by annotating branch instructions in x86
Juan Manuel Cebrián González has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/27972 )
Change subject: arch-x86,cpu: Fix bpred by annotating branch instructions
in x86
..
arch-x86,cpu: Fix bpred by annotating branch instructions in x86
Original Creator: Adria Armejach.
Branch instructions needed to be annotated in x86 as direct/indirect and
conditional/unconditional. These annotations where not present causing the
branch predictor to misbehave, not using the BTB. In addition, logic to
determine the real branch target at decode needed to be added as it was
also missing.
Change-Id: I91e707452c1825b9bb4ae75c3f599da489ae5b9a
---
M src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
M
src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
M src/arch/x86/isa/macroop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/isa/microops/seqop.isa
M src/cpu/o3/decode_impl.hh
9 files changed, 112 insertions(+), 6 deletions(-)
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
index c58152c..edc0007 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
@@ -41,6 +41,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_direct
limm t1, imm
rdip t7
@@ -55,6 +56,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_indirect
rdip t1
# Check target of call
@@ -68,6 +70,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_indirect
rdip t7
ld t1, seg, sib, disp
@@ -82,6 +85,7 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
+.control_indirect
rdip t7
ld t1, seg, riprel, disp
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
index 87b2e6a..f92935d 100644
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
@@ -40,6 +40,7 @@
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -50,6 +51,7 @@
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -60,6 +62,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -70,6 +73,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -80,6 +84,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -90,6 +95,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -100,6 +106,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -110,6 +117,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -120,6 +128,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -130,6 +139,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -140,6 +150,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -150,6 +161,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+.control_direct
rdip t1
limm t2, imm
@@ -160,6 +172,7 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
+
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