date:20090220

Re: [m5-dev] problems with CPU models

2009-02-20 Thread Korey Sewell

looking in src/cpu/inorder/SConstruct, I see that the inorder model
wants to compile these files from O3:
Source('../o3/btb.cc')
Source('../o3/tournament_pred.cc')
Source('../o3/2bit_local_pred.cc')
Source('../o3/free_list.cc')
Source('../o3/rename_map)

Of those files, free_list and rename_map seem to be unnecessary for a
inorder_model. I believe those are relics from when the mixie model
was being dual-designed as both an inorder and out-of-order model.
Since M5 is just using for inorder, feel free to take out those 2
files.


On Fri, Feb 20, 2009 at 2:35 AM, Gabe Black gbl...@eecs.umich.edu wrote:
Since I'm rearranging the CPU models a bit to get rid of the
 translate... functions, I want to try at least compiling them to make
 sure everything still works. Unfortunately the FreeList traceflag is
 defined in I think both the in order and o3 models which makes scons
 choke. There also seem to be places where o3 is partially compiled even
 when it's left out for Alpha. I'm not sure exactly what's going on
 there. There may be some interaction between the in order model and o3
 there.

 Gabe
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 m5-dev@m5sim.org
 http://m5sim.org/mailman/listinfo/m5-dev




-- 
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science  Engineering
University of Michigan
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Re: [m5-dev] problems with CPU models

2009-02-20 Thread Korey Sewell

typo:
*SConscript

AND

there is a TraceFlag('FreeList') in there that can be whacked as well.

On Fri, Feb 20, 2009 at 9:00 AM, Korey Sewell ksew...@umich.edu wrote:
 looking in src/cpu/inorder/SConstruct, I see that the inorder model
 wants to compile these files from O3:
Source('../o3/btb.cc')
Source('../o3/tournament_pred.cc')
Source('../o3/2bit_local_pred.cc')
Source('../o3/free_list.cc')
Source('../o3/rename_map)

 Of those files, free_list and rename_map seem to be unnecessary for a
 inorder_model. I believe those are relics from when the mixie model
 was being dual-designed as both an inorder and out-of-order model.
 Since M5 is just using for inorder, feel free to take out those 2
 files.


 On Fri, Feb 20, 2009 at 2:35 AM, Gabe Black gbl...@eecs.umich.edu wrote:
Since I'm rearranging the CPU models a bit to get rid of the
 translate... functions, I want to try at least compiling them to make
 sure everything still works. Unfortunately the FreeList traceflag is
 defined in I think both the in order and o3 models which makes scons
 choke. There also seem to be places where o3 is partially compiled even
 when it's left out for Alpha. I'm not sure exactly what's going on
 there. There may be some interaction between the in order model and o3
 there.

 Gabe
 ___
 m5-dev mailing list
 m5-dev@m5sim.org
 http://m5sim.org/mailman/listinfo/m5-dev




 --
 --
 Korey L Sewell
 Graduate Student - PhD Candidate
 Computer Science  Engineering
 University of Michigan




-- 
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science  Engineering
University of Michigan
___
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m5-dev@m5sim.org
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[m5-dev] [PATCH] imported patch inorder-alpha-port

2009-02-20 Thread Korey Sewell

# HG changeset patch
# User Korey Sewell ksew...@umich.edu
# Date 1235138771 18000
# Node ID b6e4240c46e429bf99fefd0d61fef1465de86e49
# Parent  7a74edaa8741dd7fb541ef6d404dac3a9ebc86f9
imported patch inorder-alpha-port

diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/SConscript
--- a/src/arch/SConscript   Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/SConscript   Fri Feb 20 09:06:11 2009 -0500
@@ -51,6 +51,7 @@ isa_switch_hdrs = Split('''
 locked_mem.hh
 microcode_rom.hh
 mmaped_ipr.hh
+mt.hh
 process.hh
 predecoder.hh
 regfile.hh
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh
--- a/src/arch/alpha/floatregfile.hhSun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/floatregfile.hhFri Feb 20 09:06:11 2009 -0500
@@ -48,6 +48,13 @@ getFloatRegName(RegIndex)
 return ;
 }
 
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
 class FloatRegFile
 {
   public:
@@ -60,6 +67,55 @@ class FloatRegFile
 
 void serialize(std::ostream os);
 void unserialize(Checkpoint *cp, const std::string section);
+
+FloatReg
+readReg(int floatReg)
+{
+return d[floatReg];
+}
+
+FloatReg
+readReg(int floatReg, int width)
+{
+return readReg(floatReg);
+}
+
+FloatRegBits
+readRegBits(int floatReg)
+{
+return q[floatReg];
+}
+
+FloatRegBits
+readRegBits(int floatReg, int width)
+{
+return readRegBits(floatReg);
+}
+
+void
+setReg(int floatReg, const FloatReg val)
+{
+d[floatReg] = val;
+}
+
+void
+setReg(int floatReg, const FloatReg val, int width)
+{
+setReg(floatReg, val);
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val)
+{
+q[floatReg] = val;
+}
+
+void
+setRegBits(int floatReg, const FloatRegBits val, int width)
+{
+setRegBits(floatReg, val);
+}
+
 };
 
 } // namespace AlphaISA
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.cc
--- a/src/arch/alpha/miscregfile.cc Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/miscregfile.cc Fri Feb 20 09:06:11 2009 -0500
@@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp,
 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
 }
 
+MiscRegFile::MiscRegFile(BaseCPU *_cpu)
+{
+cpu = _cpu;
+initializeIprTable();
+}
+
+
 MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg)
+MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
 {
 switch (misc_reg) {
   case MISCREG_FPCR:
@@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re
 }
 
 MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
+MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
 {
 switch (misc_reg) {
   case MISCREG_FPCR:
@@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, Threa
 }
 
 void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val)
+MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val, unsigned tid)
 {
 switch (misc_reg) {
   case MISCREG_FPCR:
@@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg
 }
 
 void
-MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc)
+MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc,
+unsigned tid)
 {
 switch (misc_reg) {
   case MISCREG_FPCR:
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.hh
--- a/src/arch/alpha/miscregfile.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/arch/alpha/miscregfile.hh Fri Feb 20 09:06:11 2009 -0500
@@ -41,6 +41,7 @@
 
 class Checkpoint;
 class ThreadContext;
+class BaseCPU;
 
 namespace AlphaISA {
 
@@ -74,6 +75,8 @@ class MiscRegFile
 
 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 
+BaseCPU *cpu;
+
   protected:
 InternalProcReg readIpr(int idx, ThreadContext *tc);
 void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
@@ -84,16 +87,18 @@ class MiscRegFile
 initializeIprTable();
 }
 
+MiscRegFile(BaseCPU *cpu);
+
 // These functions should be removed once the simplescalar cpu
 // model has been replaced.
 int getInstAsid();
 int getDataAsid();
 
-MiscReg readRegNoEffect(int misc_reg);
-MiscReg readReg(int misc_reg, ThreadContext *tc);
+MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0);
 
-void setRegNoEffect(int misc_reg, const MiscReg val);
-void setReg(int misc_reg, const MiscReg val, ThreadContext *tc);
+void setRegNoEffect(int misc_reg, const MiscReg val, unsigned tid = 0);
+void setReg(int misc_reg, const MiscReg val, ThreadContext *tc, unsigned 
tid = 0);
 
 void
 clear()
@@ -107,6 +112,16 @@ class MiscRegFile

Re: [m5-dev] [PATCH] imported patch inorder-alpha-port

2009-02-20 Thread Korey Sewell

Before this ALPHA port for the InOrder model can make it to a
changeset, there are few issues that need to be resolved in this
patch:

- Adding member get/setReg functions to FloatRegFile:
The inorder model would like to instantiate multiple int/float
register files and just one miscellaneous register file. The MIPS
misc. regfile has register banks where some are per-core, some are
per-thread, and some are per vpe (virtual processing element). Thus,
it would be undesirable to have one misc. regfile per thread, when
that system state is so closely tied to each other and varies
depending on which register bank you're accesssing.

The ALPHA register file defines the float register file as just an
array of registers without any member functions and then lets the
bigger 'regfile' object have public access to it's data. To allow the
inorder model to use the float-register file independently of the
other register files I gave that object it's member functions back
 Is that reverting someone's previous change or an OK addition?

- Misc. RegFile takes a CPU object to assist in MT execution:
If you are running a multithreaded CPU, then potentially two threads
can make changes to the misc. register file on the same cycle. In that
case, you don't want to immediately take action on the effects of your
system changes as soon as the instruction is executed. Instead,you
want to save that there has been changes to the system file and then
re-evaluate those changes at the end of the cycle. Adding the CPU
object, allows the regfile to create an event for itself at the end of
the cycle and then make system changes once all values have been
settled.

- Add thread identifer to misc. regfile functions
To identify the correct misc. register, you need to identify if that
register index is per-Thread and if so, use that thread ID to access
the right register.
-- 
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science  Engineering
University of Michigan



On Fri, Feb 20, 2009 at 9:27 AM, Korey Sewell ksew...@eecs.umich.edu wrote:
 # HG changeset patch
 # User Korey Sewell ksew...@umich.edu
 # Date 1235138771 18000
 # Node ID b6e4240c46e429bf99fefd0d61fef1465de86e49
 # Parent  7a74edaa8741dd7fb541ef6d404dac3a9ebc86f9
 imported patch inorder-alpha-port

 diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/SConscript
 --- a/src/arch/SConscript   Sun Feb 15 23:43:39 2009 -0800
 +++ b/src/arch/SConscript   Fri Feb 20 09:06:11 2009 -0500
 @@ -51,6 +51,7 @@ isa_switch_hdrs = Split('''
 locked_mem.hh
 microcode_rom.hh
 mmaped_ipr.hh
 +mt.hh
 process.hh
 predecoder.hh
 regfile.hh
 diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh
 --- a/src/arch/alpha/floatregfile.hhSun Feb 15 23:43:39 2009 -0800
 +++ b/src/arch/alpha/floatregfile.hhFri Feb 20 09:06:11 2009 -0500
 @@ -48,6 +48,13 @@ getFloatRegName(RegIndex)
 return ;
  }

 +const int SingleWidth = 32;
 +const int SingleBytes = SingleWidth / 4;
 +const int DoubleWidth = 64;
 +const int DoubleBytes = DoubleWidth / 4;
 +const int QuadWidth = 128;
 +const int QuadBytes = QuadWidth / 4;
 +
  class FloatRegFile
  {
   public:
 @@ -60,6 +67,55 @@ class FloatRegFile

 void serialize(std::ostream os);
 void unserialize(Checkpoint *cp, const std::string section);
 +
 +FloatReg
 +readReg(int floatReg)
 +{
 +return d[floatReg];
 +}
 +
 +FloatReg
 +readReg(int floatReg, int width)
 +{
 +return readReg(floatReg);
 +}
 +
 +FloatRegBits
 +readRegBits(int floatReg)
 +{
 +return q[floatReg];
 +}
 +
 +FloatRegBits
 +readRegBits(int floatReg, int width)
 +{
 +return readRegBits(floatReg);
 +}
 +
 +void
 +setReg(int floatReg, const FloatReg val)
 +{
 +d[floatReg] = val;
 +}
 +
 +void
 +setReg(int floatReg, const FloatReg val, int width)
 +{
 +setReg(floatReg, val);
 +}
 +
 +void
 +setRegBits(int floatReg, const FloatRegBits val)
 +{
 +q[floatReg] = val;
 +}
 +
 +void
 +setRegBits(int floatReg, const FloatRegBits val, int width)
 +{
 +setRegBits(floatReg, val);
 +}
 +
  };

  } // namespace AlphaISA
 diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.cc
 --- a/src/arch/alpha/miscregfile.cc Sun Feb 15 23:43:39 2009 -0800
 +++ b/src/arch/alpha/miscregfile.cc Fri Feb 20 09:06:11 2009 -0500
 @@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp,
 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
  }

 +MiscRegFile::MiscRegFile(BaseCPU *_cpu)
 +{
 +cpu = _cpu;
 +initializeIprTable();
 +}
 +
 +
  MiscReg
 -MiscRegFile::readRegNoEffect(int misc_reg)
 +MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
  {
 switch (misc_reg) {
   case MISCREG_FPCR:
 @@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re
  }

  MiscReg
 -MiscRegFile::readReg(int misc_reg,

[m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

2009-02-20 Thread Korey Sewell

changeset 6fd7648e1b8d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6fd7648e1b8d
description:
Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up 
comments and O3 extensions InOrder Thread Context

diffstat:

5 files changed, 4 insertions(+), 111 deletions(-)
src/arch/mips/regfile.cc  |6 --
src/cpu/inorder/SConscript|5 -
src/cpu/inorder/cpu.hh|9 ---
src/cpu/inorder/thread_context.cc |   93 -
src/cpu/inorder/thread_context.hh |2 

diffs (266 lines):

diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/arch/mips/regfile.cc
--- a/src/arch/mips/regfile.cc  Wed Feb 18 10:00:15 2009 -0800
+++ b/src/arch/mips/regfile.cc  Fri Feb 20 11:02:48 2009 -0500
@@ -200,12 +200,6 @@
 }
 
 void
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
-{
-panic(Copy Regs Not Implemented Yet\n);
-}
-
-void
 MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
 panic(Copy Misc. Regs Not Implemented Yet\n);
diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscriptWed Feb 18 10:00:15 2009 -0800
+++ b/src/cpu/inorder/SConscriptFri Feb 20 11:02:48 2009 -0500
@@ -42,13 +42,12 @@
TraceFlag('InOrderCPU')
TraceFlag('InOrderMDU')
TraceFlag('RegDepMap')
-   TraceFlag('Rename')
TraceFlag('InOrderDynInst')
TraceFlag('Resource')
TraceFlag('RefCount')
 
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 
'InOrderCPU',
-  'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
+  'InOrderMDU', 'RegDepMap', 'Resource'])
 
Source('pipeline_traits.cc')
Source('inorder_dyn_inst.cc')
@@ -74,8 +73,6 @@
Source('../o3/btb.cc')
Source('../o3/tournament_pred.cc')
Source('../o3/2bit_local_pred.cc')
-   Source('../o3/free_list.cc')
-   Source('../o3/rename_map.cc')
Source('../o3/ras.cc')
Source('thread_context.cc')
Source('cpu.cc')
diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hhWed Feb 18 10:00:15 2009 -0800
+++ b/src/cpu/inorder/cpu.hhFri Feb 20 11:02:48 2009 -0500
@@ -77,7 +77,6 @@
 typedef TheISA::FloatRegBits FloatRegBits;
 typedef TheISA::MiscReg MiscReg;
 typedef TheISA::RegFile RegFile;
-typedef SimpleRenameMap RenameMap;
 
 //DynInstPtr TypeDefs
 typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -586,14 +585,6 @@
 
 std::listunsigned fetchPriorityList;
 
- /** Rename Map for architectural-to-physical register mappings.
-  *  In a In-order processor, the mapping is fixed
-  *  (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.)
-  *  In a Out-of-Order processor, this is used to maintain
-  *  sequential consistency (?right word here?).
-  */
- RenameMap renameMap[ThePipeline::MaxThreads];
-
   protected:
 /** Active Threads List */
 std::listunsigned activeThreads;
diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/thread_context.cc
--- a/src/cpu/inorder/thread_context.cc Wed Feb 18 10:00:15 2009 -0800
+++ b/src/cpu/inorder/thread_context.cc Fri Feb 20 11:02:48 2009 -0500
@@ -44,7 +44,6 @@
 // copy over functional state
 setStatus(old_context-status());
 copyArchRegs(old_context);
-//setCpuId(0/*old_context-readCpuId()*/);
 
 thread-funcExeInst = old_context-readFuncExeInst();
 old_context-setStatus(ThreadContext::Unallocated);
@@ -61,18 +60,8 @@
 if (thread-status() == ThreadContext::Active)
 return;
 
-// @TODO: Make this process useful again...
-//if (thread-status() == ThreadContext::Unallocated) {
-// Allows the CPU to drain partitioned resources
-// before inserting thread into the CPU
-// (e.g. bind physical registers)
-//cpu-activateWhenReady(thread-readTid());
-//return;
-//}
-
 thread-setStatus(ThreadContext::Active);
 
-// status() == Suspended
 cpu-activateContext(thread-readTid(), delay);
 }
 
@@ -157,37 +146,9 @@
 
 
 void
-InOrderThreadContext::copyArchRegs(ThreadContext *tc)
+InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
 {
-unsigned tid = thread-readTid();
-PhysRegIndex renamed_reg;
-
-// First loop through the integer registers.
-for (int i = 0; i  TheISA::NumIntRegs; ++i) {
-renamed_reg = cpu-renameMap[tid].lookup(i);
-
-DPRINTF(InOrderCPU, Copying over register %i, had data %lli, 
-now has data %lli.\n,
-renamed_reg, cpu-readIntReg(renamed_reg, tid),
-tc-readIntReg(i));
-
-cpu-setIntReg(renamed_reg, tc-readIntReg(i), tid);
-}
-
-// Then loop through the floating point registers.
-for (int i = 0; i  TheISA::NumFloatRegs; ++i) {
-renamed_reg = cpu-renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
-cpu-setFloatRegBits(renamed_reg,

Re: [m5-dev] [PATCH] imported patch inorder-alpha-port

2009-02-20 Thread Gabriel Michael Black

I haven't looked at this incredibly closely yet, but I have a few  
questions. First, what's this mt.hh file? You made it an ISA switched  
header, but I don't see anything by that name being added. What does  
it do?

Second, you shouldn't add a comment out include of cpu/inorder/cpu.hh.

Third, why did you add the SingleWidth, SingleBytes, etc values to  
floatregfile.hh?

Fourth, have we actually decided how this threading thing is going to  
work? I see an expandForMultithreading function which I'm guessing  
sets the thread width, so to speak, for the misc reg file? The float  
reg file also seems to be split out so it can be instantiated more  
than the misc reg file. I'm not saying this stuff is right or wrong,  
but I did't think we'd figured out what the big picture strategy was.

Gabe

Quoting Korey Sewell ksew...@eecs.umich.edu:

 # HG changeset patch
 # User Korey Sewell ksew...@umich.edu
 # Date 1235138771 18000
 # Node ID b6e4240c46e429bf99fefd0d61fef1465de86e49
 # Parent  7a74edaa8741dd7fb541ef6d404dac3a9ebc86f9
 imported patch inorder-alpha-port

 diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/SConscript
 --- a/src/arch/SConscript Sun Feb 15 23:43:39 2009 -0800
 +++ b/src/arch/SConscript Fri Feb 20 09:06:11 2009 -0500
 @@ -51,6 +51,7 @@ isa_switch_hdrs = Split('''
  locked_mem.hh
  microcode_rom.hh
  mmaped_ipr.hh
 +mt.hh
  process.hh
  predecoder.hh
  regfile.hh
 diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh
 --- a/src/arch/alpha/floatregfile.hh  Sun Feb 15 23:43:39 2009 -0800
 +++ b/src/arch/alpha/floatregfile.hh  Fri Feb 20 09:06:11 2009 -0500
 @@ -48,6 +48,13 @@ getFloatRegName(RegIndex)
  return ;
  }

 +const int SingleWidth = 32;
 +const int SingleBytes = SingleWidth / 4;
 +const int DoubleWidth = 64;
 +const int DoubleBytes = DoubleWidth / 4;
 +const int QuadWidth = 128;
 +const int QuadBytes = QuadWidth / 4;
 +
  class FloatRegFile
  {
public:
 @@ -60,6 +67,55 @@ class FloatRegFile

  void serialize(std::ostream os);
  void unserialize(Checkpoint *cp, const std::string section);
 +
 +FloatReg
 +readReg(int floatReg)
 +{
 +return d[floatReg];
 +}
 +
 +FloatReg
 +readReg(int floatReg, int width)
 +{
 +return readReg(floatReg);
 +}
 +
 +FloatRegBits
 +readRegBits(int floatReg)
 +{
 +return q[floatReg];
 +}
 +
 +FloatRegBits
 +readRegBits(int floatReg, int width)
 +{
 +return readRegBits(floatReg);
 +}
 +
 +void
 +setReg(int floatReg, const FloatReg val)
 +{
 +d[floatReg] = val;
 +}
 +
 +void
 +setReg(int floatReg, const FloatReg val, int width)
 +{
 +setReg(floatReg, val);
 +}
 +
 +void
 +setRegBits(int floatReg, const FloatRegBits val)
 +{
 +q[floatReg] = val;
 +}
 +
 +void
 +setRegBits(int floatReg, const FloatRegBits val, int width)
 +{
 +setRegBits(floatReg, val);
 +}
 +
  };

  } // namespace AlphaISA
 diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.cc
 --- a/src/arch/alpha/miscregfile.cc   Sun Feb 15 23:43:39 2009 -0800
 +++ b/src/arch/alpha/miscregfile.cc   Fri Feb 20 09:06:11 2009 -0500
 @@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp,
  UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
  }

 +MiscRegFile::MiscRegFile(BaseCPU *_cpu)
 +{
 +cpu = _cpu;
 +initializeIprTable();
 +}
 +
 +
  MiscReg
 -MiscRegFile::readRegNoEffect(int misc_reg)
 +MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
  {
  switch (misc_reg) {
case MISCREG_FPCR:
 @@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re
  }

  MiscReg
 -MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
 +MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
  {
  switch (misc_reg) {
case MISCREG_FPCR:
 @@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, Threa
  }

  void
 -MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val)
 +MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg val, unsigned tid)
  {
  switch (misc_reg) {
case MISCREG_FPCR:
 @@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg
  }

  void
 -MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc)
 +MiscRegFile::setReg(int misc_reg, const MiscReg val, ThreadContext *tc,
 +unsigned tid)
  {
  switch (misc_reg) {
case MISCREG_FPCR:
 diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.hh
 --- a/src/arch/alpha/miscregfile.hh   Sun Feb 15 23:43:39 2009 -0800
 +++ b/src/arch/alpha/miscregfile.hh   Fri Feb 20 09:06:11 2009 -0500
 @@ -41,6 +41,7 @@

  class Checkpoint;
  class ThreadContext;
 +class BaseCPU;

  namespace AlphaISA {

 @@ -74,6 +75,8 @@ class MiscRegFile

  InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs

 +BaseCPU *cpu;
 +
protected:

Re: [m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

2009-02-20 Thread Gabriel Michael Black

Why is the in order model asking for O3 source files to be compiled in  
the first place?

Gabe

Quoting Korey Sewell ksew...@umich.edu:

 changeset 6fd7648e1b8d in /z/repo/m5
 details: http://repo.m5sim.org/m5?cmd=changeset;node=6fd7648e1b8d
 description:
   Remove unnecessary building of FreeList/RenameMap in InOrder.  
 Clean-up comments and O3 extensions InOrder Thread Context

 diffstat:

 5 files changed, 4 insertions(+), 111 deletions(-)
 src/arch/mips/regfile.cc  |6 --
 src/cpu/inorder/SConscript|5 -
 src/cpu/inorder/cpu.hh|9 ---
 src/cpu/inorder/thread_context.cc |   93  
 -
 src/cpu/inorder/thread_context.hh |2

 diffs (266 lines):

 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/arch/mips/regfile.cc
 --- a/src/arch/mips/regfile.ccWed Feb 18 10:00:15 2009 -0800
 +++ b/src/arch/mips/regfile.ccFri Feb 20 11:02:48 2009 -0500
 @@ -200,12 +200,6 @@
  }

  void
 -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
 -{
 -panic(Copy Regs Not Implemented Yet\n);
 -}
 -
 -void
  MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
  {
  panic(Copy Misc. Regs Not Implemented Yet\n);
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/SConscript
 --- a/src/cpu/inorder/SConscript  Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/SConscript  Fri Feb 20 11:02:48 2009 -0500
 @@ -42,13 +42,12 @@
   TraceFlag('InOrderCPU')
   TraceFlag('InOrderMDU')
   TraceFlag('RegDepMap')
 - TraceFlag('Rename')
   TraceFlag('InOrderDynInst')
   TraceFlag('Resource')
   TraceFlag('RefCount')

   CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',  
 'InOrderCPU',
 -'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
 +'InOrderMDU', 'RegDepMap', 'Resource'])

   Source('pipeline_traits.cc')
   Source('inorder_dyn_inst.cc')
 @@ -74,8 +73,6 @@
   Source('../o3/btb.cc')
   Source('../o3/tournament_pred.cc')
   Source('../o3/2bit_local_pred.cc')
 - Source('../o3/free_list.cc')
 - Source('../o3/rename_map.cc')
   Source('../o3/ras.cc')
   Source('thread_context.cc')
   Source('cpu.cc')
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/cpu.hh
 --- a/src/cpu/inorder/cpu.hh  Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/cpu.hh  Fri Feb 20 11:02:48 2009 -0500
 @@ -77,7 +77,6 @@
  typedef TheISA::FloatRegBits FloatRegBits;
  typedef TheISA::MiscReg MiscReg;
  typedef TheISA::RegFile RegFile;
 -typedef SimpleRenameMap RenameMap;

  //DynInstPtr TypeDefs
  typedef ThePipeline::DynInstPtr DynInstPtr;
 @@ -586,14 +585,6 @@

  std::listunsigned fetchPriorityList;

 - /** Rename Map for architectural-to-physical register mappings.
 -  *  In a In-order processor, the mapping is fixed
 -  *  (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.)
 -  *  In a Out-of-Order processor, this is used to maintain
 -  *  sequential consistency (?right word here?).
 -  */
 - RenameMap renameMap[ThePipeline::MaxThreads];
 -
protected:
  /** Active Threads List */
  std::listunsigned activeThreads;
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/thread_context.cc
 --- a/src/cpu/inorder/thread_context.cc   Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/thread_context.cc   Fri Feb 20 11:02:48 2009 -0500
 @@ -44,7 +44,6 @@
  // copy over functional state
  setStatus(old_context-status());
  copyArchRegs(old_context);
 -//setCpuId(0/*old_context-readCpuId()*/);

  thread-funcExeInst = old_context-readFuncExeInst();
  old_context-setStatus(ThreadContext::Unallocated);
 @@ -61,18 +60,8 @@
  if (thread-status() == ThreadContext::Active)
  return;

 -// @TODO: Make this process useful again...
 -//if (thread-status() == ThreadContext::Unallocated) {
 -// Allows the CPU to drain partitioned resources
 -// before inserting thread into the CPU
 -// (e.g. bind physical registers)
 -//cpu-activateWhenReady(thread-readTid());
 -//return;
 -//}
 -
  thread-setStatus(ThreadContext::Active);

 -// status() == Suspended
  cpu-activateContext(thread-readTid(), delay);
  }

 @@ -157,37 +146,9 @@


  void
 -InOrderThreadContext::copyArchRegs(ThreadContext *tc)
 +InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
  {
 -unsigned tid = thread-readTid();
 -PhysRegIndex renamed_reg;
 -
 -// First loop through the integer registers.
 -for (int i = 0; i  TheISA::NumIntRegs; ++i) {
 -renamed_reg = cpu-renameMap[tid].lookup(i);
 -
 -DPRINTF(InOrderCPU, Copying over register %i, had data %lli, 
 -now has data %lli.\n,
 -renamed_reg, cpu-readIntReg(renamed_reg, tid),
 -tc-readIntReg(i));
 -
 -cpu-setIntReg(renamed_reg, tc-readIntReg(i), tid);
 -}
 -
 -// Then loop

Re: [m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

2009-02-20 Thread Korey Sewell

Because things like branch predictors, return address stacks, and
branch target buffers are good for use in a InOrder model.

And originally, the inorder model (originally called 'mixie') was
something that would work for both inorder and out-of-order models.
It's supposed to be flexible enough that it isnt tied to any style of
pipelining and simply changing the resources that a instruction needs
to obtain would change the style of pipelining. Since M5 already has a
O3 model, then the out of order functionality is no longer required or
desirable for 99% of users.

On Fri, Feb 20, 2009 at 2:46 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
 Why is the in order model asking for O3 source files to be compiled in
 the first place?

 Gabe

 Quoting Korey Sewell ksew...@umich.edu:

 changeset 6fd7648e1b8d in /z/repo/m5
 details: http://repo.m5sim.org/m5?cmd=changeset;node=6fd7648e1b8d
 description:
   Remove unnecessary building of FreeList/RenameMap in InOrder.
 Clean-up comments and O3 extensions InOrder Thread Context

 diffstat:

 5 files changed, 4 insertions(+), 111 deletions(-)
 src/arch/mips/regfile.cc  |6 --
 src/cpu/inorder/SConscript|5 -
 src/cpu/inorder/cpu.hh|9 ---
 src/cpu/inorder/thread_context.cc |   93
 -
 src/cpu/inorder/thread_context.hh |2

 diffs (266 lines):

 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/arch/mips/regfile.cc
 --- a/src/arch/mips/regfile.ccWed Feb 18 10:00:15 2009 -0800
 +++ b/src/arch/mips/regfile.ccFri Feb 20 11:02:48 2009 -0500
 @@ -200,12 +200,6 @@
  }

  void
 -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
 -{
 -panic(Copy Regs Not Implemented Yet\n);
 -}
 -
 -void
  MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
  {
  panic(Copy Misc. Regs Not Implemented Yet\n);
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/SConscript
 --- a/src/cpu/inorder/SConscript  Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/SConscript  Fri Feb 20 11:02:48 2009 -0500
 @@ -42,13 +42,12 @@
   TraceFlag('InOrderCPU')
   TraceFlag('InOrderMDU')
   TraceFlag('RegDepMap')
 - TraceFlag('Rename')
   TraceFlag('InOrderDynInst')
   TraceFlag('Resource')
   TraceFlag('RefCount')

   CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
 'InOrderCPU',
 -'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
 +'InOrderMDU', 'RegDepMap', 'Resource'])

   Source('pipeline_traits.cc')
   Source('inorder_dyn_inst.cc')
 @@ -74,8 +73,6 @@
   Source('../o3/btb.cc')
   Source('../o3/tournament_pred.cc')
   Source('../o3/2bit_local_pred.cc')
 - Source('../o3/free_list.cc')
 - Source('../o3/rename_map.cc')
   Source('../o3/ras.cc')
   Source('thread_context.cc')
   Source('cpu.cc')
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/cpu.hh
 --- a/src/cpu/inorder/cpu.hh  Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/cpu.hh  Fri Feb 20 11:02:48 2009 -0500
 @@ -77,7 +77,6 @@
  typedef TheISA::FloatRegBits FloatRegBits;
  typedef TheISA::MiscReg MiscReg;
  typedef TheISA::RegFile RegFile;
 -typedef SimpleRenameMap RenameMap;

  //DynInstPtr TypeDefs
  typedef ThePipeline::DynInstPtr DynInstPtr;
 @@ -586,14 +585,6 @@

  std::listunsigned fetchPriorityList;

 - /** Rename Map for architectural-to-physical register mappings.
 -  *  In a In-order processor, the mapping is fixed
 -  *  (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.)
 -  *  In a Out-of-Order processor, this is used to maintain
 -  *  sequential consistency (?right word here?).
 -  */
 - RenameMap renameMap[ThePipeline::MaxThreads];
 -
protected:
  /** Active Threads List */
  std::listunsigned activeThreads;
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/thread_context.cc
 --- a/src/cpu/inorder/thread_context.cc   Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/thread_context.cc   Fri Feb 20 11:02:48 2009 -0500
 @@ -44,7 +44,6 @@
  // copy over functional state
  setStatus(old_context-status());
  copyArchRegs(old_context);
 -//setCpuId(0/*old_context-readCpuId()*/);

  thread-funcExeInst = old_context-readFuncExeInst();
  old_context-setStatus(ThreadContext::Unallocated);
 @@ -61,18 +60,8 @@
  if (thread-status() == ThreadContext::Active)
  return;

 -// @TODO: Make this process useful again...
 -//if (thread-status() == ThreadContext::Unallocated) {
 -// Allows the CPU to drain partitioned resources
 -// before inserting thread into the CPU
 -// (e.g. bind physical registers)
 -//cpu-activateWhenReady(thread-readTid());
 -//return;
 -//}
 -
  thread-setStatus(ThreadContext::Active);

 -// status() == Suspended
  cpu-activateContext(thread-readTid(), delay);
  }

 @@ -157,37 +146,9 @@


  void

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Re: [m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

2009-02-20 Thread Gabriel Michael Black

Ok. I figured it was something like that. Rather than use those in  
place in O3, we might want to try to put them in a neutral spot and  
then make them available for both. It would probably be confusing for  
someone working on o3 if they ended up changing in order accidentally  
in the process. I think generally decoupling o3 a little bit from its  
innards would be a good thing since it can be hard to move things  
around in there.

Gabe

Quoting Korey Sewell ksew...@umich.edu:

 Because things like branch predictors, return address stacks, and
 branch target buffers are good for use in a InOrder model.

 And originally, the inorder model (originally called 'mixie') was
 something that would work for both inorder and out-of-order models.
 It's supposed to be flexible enough that it isnt tied to any style of
 pipelining and simply changing the resources that a instruction needs
 to obtain would change the style of pipelining. Since M5 already has a
 O3 model, then the out of order functionality is no longer required or
 desirable for 99% of users.

 On Fri, Feb 20, 2009 at 2:46 PM, Gabriel Michael Black
 gbl...@eecs.umich.edu wrote:
 Why is the in order model asking for O3 source files to be compiled in
 the first place?

 Gabe

 Quoting Korey Sewell ksew...@umich.edu:

 changeset 6fd7648e1b8d in /z/repo/m5
 details: http://repo.m5sim.org/m5?cmd=changeset;node=6fd7648e1b8d
 description:
   Remove unnecessary building of FreeList/RenameMap in InOrder.
 Clean-up comments and O3 extensions InOrder Thread Context

 diffstat:

 5 files changed, 4 insertions(+), 111 deletions(-)
 src/arch/mips/regfile.cc  |6 --
 src/cpu/inorder/SConscript|5 -
 src/cpu/inorder/cpu.hh|9 ---
 src/cpu/inorder/thread_context.cc |   93
 -
 src/cpu/inorder/thread_context.hh |2

 diffs (266 lines):

 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/arch/mips/regfile.cc
 --- a/src/arch/mips/regfile.ccWed Feb 18 10:00:15 2009 -0800
 +++ b/src/arch/mips/regfile.ccFri Feb 20 11:02:48 2009 -0500
 @@ -200,12 +200,6 @@
  }

  void
 -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
 -{
 -panic(Copy Regs Not Implemented Yet\n);
 -}
 -
 -void
  MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
  {
  panic(Copy Misc. Regs Not Implemented Yet\n);
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/SConscript
 --- a/src/cpu/inorder/SConscript  Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/SConscript  Fri Feb 20 11:02:48 2009 -0500
 @@ -42,13 +42,12 @@
   TraceFlag('InOrderCPU')
   TraceFlag('InOrderMDU')
   TraceFlag('RegDepMap')
 - TraceFlag('Rename')
   TraceFlag('InOrderDynInst')
   TraceFlag('Resource')
   TraceFlag('RefCount')

   CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
 'InOrderCPU',
 -'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
 +'InOrderMDU', 'RegDepMap', 'Resource'])

   Source('pipeline_traits.cc')
   Source('inorder_dyn_inst.cc')
 @@ -74,8 +73,6 @@
   Source('../o3/btb.cc')
   Source('../o3/tournament_pred.cc')
   Source('../o3/2bit_local_pred.cc')
 - Source('../o3/free_list.cc')
 - Source('../o3/rename_map.cc')
   Source('../o3/ras.cc')
   Source('thread_context.cc')
   Source('cpu.cc')
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/cpu.hh
 --- a/src/cpu/inorder/cpu.hh  Wed Feb 18 10:00:15 2009 -0800
 +++ b/src/cpu/inorder/cpu.hh  Fri Feb 20 11:02:48 2009 -0500
 @@ -77,7 +77,6 @@
  typedef TheISA::FloatRegBits FloatRegBits;
  typedef TheISA::MiscReg MiscReg;
  typedef TheISA::RegFile RegFile;
 -typedef SimpleRenameMap RenameMap;

  //DynInstPtr TypeDefs
  typedef ThePipeline::DynInstPtr DynInstPtr;
 @@ -586,14 +585,6 @@

  std::listunsigned fetchPriorityList;

 - /** Rename Map for architectural-to-physical register mappings.
 -  *  In a In-order processor, the mapping is fixed
 -  *  (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.)
 -  *  In a Out-of-Order processor, this is used to maintain
 -  *  sequential consistency (?right word here?).
 -  */
 - RenameMap renameMap[ThePipeline::MaxThreads];
 -
protected:
  /** Active Threads List */
  std::listunsigned activeThreads;
 diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/thread_context.cc
 --- a/src/cpu/inorder/thread_context.cc   Wed Feb 18 10:00:15  
 2009 -0800
 +++ b/src/cpu/inorder/thread_context.cc   Fri Feb 20 11:02:48  
 2009 -0500
 @@ -44,7 +44,6 @@
  // copy over functional state
  setStatus(old_context-status());
  copyArchRegs(old_context);
 -//setCpuId(0/*old_context-readCpuId()*/);

  thread-funcExeInst = old_context-readFuncExeInst();
  old_context-setStatus(ThreadContext::Unallocated);
 @@ -61,18 +60,8 @@
  if (thread-status() == ThreadContext::Active)
  return;

 -// @TODO: Make

Re: [m5-dev] problems with CPU models

Re: [m5-dev] problems with CPU models

[m5-dev] [PATCH] imported patch inorder-alpha-port

Re: [m5-dev] [PATCH] imported patch inorder-alpha-port

[m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

Re: [m5-dev] [PATCH] imported patch inorder-alpha-port

Re: [m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

Re: [m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

[m5-dev] Undelivered Mail Returned to Sender

Re: [m5-dev] changeset in m5: Remove unnecessary building of FreeList/RenameM...

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