Re: [m5-dev] [PATCH] imported patch inorder-alpha-port
I'm a little unsure of what you are saying here Nate. I am trying to add a mt.hh for ALPHA (so it can use the InOrder model) but through some fault of mines the alpha version of the mt.hh file got omitted. Eventually, any ISA wanting to use InOrder would need to at the very least have some bare MT functions since there is no base or generic ISA subdirectory that contains bare-bone implementations of ISA functions needed by the CPUs. On Sat, Feb 21, 2009 at 11:22 PM, nathan binkert n...@binkert.org wrote: 1) not sure why the mt.hh file didnt get added to the patch, but it should be there I think the real problem is that you're adding an mt.hh, but only for mips. That doesn't work so well with the switching directory code. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] running SPARC_FS
Hi, I am trying to run SPARC_FS and it's not clear what the kernel should be set to. It is set to vmlinux for Alpha, so I do the same thing for SPARC_FS but I doubt that is the right thing to do. Regardless of what the kernel is set to I get the following error: REAL SIMULATION warn: Entering event queue @ 0. Starting simulation... panic: What state are we in?! @ cycle 1 [readFSReg:build/SPARC_FS/arch/sparc/ua2005.cc, line 280] Program aborted at cycle 1 Abort When I run: ./build/SPARC_FS/m5.debug configs/example/fs.py -n 2 Could it be a problem with fs.py? Thanks. Polina ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] running SPARC_FS
You're probably the first person to ever try an run two processors in SPARC_FS. One processor should work fine. You're getting an error because the second processor is never reset. Getting two processors to work will be some work. The code was written, but never really tested. The best way to make two processors work is: a) Get 2 processor versions of the hv.bin and md.bin from Sun's Legion simulator (part of the OpenSPARC tools). They have premade ones or you can use the included tools to make your own based on the configuration you want. Unfortunately, we never wrote code in m5 to automatically generate these files as we were hoping to get the actual hypervisor that would create them from Sun. They describe the system (processors, memory addresses, etc). b) Get the Legion simulator from Sun's website. c) Run the two in lockstep fixing any problems as they occur. I have an interface I wrote for m5 and modified for legion for the communication. However, it would have to be expanded to multiple processors. Ali On Feb 22, 2009, at 6:01 PM, Polina Dudnik wrote: Hi, I am trying to run SPARC_FS and it's not clear what the kernel should be set to. It is set to vmlinux for Alpha, so I do the same thing for SPARC_FS but I doubt that is the right thing to do. Regardless of what the kernel is set to I get the following error: REAL SIMULATION warn: Entering event queue @ 0. Starting simulation... panic: What state are we in?! @ cycle 1 [readFSReg:build/SPARC_FS/arch/sparc/ua2005.cc, line 280] Program aborted at cycle 1 Abort When I run: ./build/SPARC_FS/m5.debug configs/example/fs.py -n 2 Could it be a problem with fs.py? Thanks. Polina ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
See /z/m5/regression/regress-2009-02-23-03:00:01 for details. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
