[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression --scratch all
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing passed. * build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 passed. * build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed. * build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic passed. * build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic passed. * build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic passed. * build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing passed. * build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing passed. * build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing passed. * build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic passed. * build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic passed. * build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing passed. * build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing passed. * build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing passed. *
Re: [m5-dev] changeset in m5: build: fix compiler warnings in g++ 3.4
nathan binkert wrote: Seems like it would be worth setting up a slew of g++ revs on zizzer and running regressions under all of them, maybe on a rotating basis... Yeah, I agree. Multiple revs of swig and maybe scons would be good too. I think we should set up a separate compile everything regression actually. It doesn't take that long to compile the tree, and with the pool being available, we could just compile a bunch of combinations. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev This sounds like a good idea, and I think as long as we compile under the different versions we'll get 95% of the benefit. I think any difference in correctness of execution would be very unlikely, so running the regressions themselves more than once would probably not be worth the effort. Maybe a rotation like you suggested would hit all the variations often enough that if it -does- happen then we'll catch it eventually. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] X86 support
Hello Gabe, Thanks for the reply. I have used Simics for booting a disk image and running workloads for the X86 architecture and I would like to try the same on M5. I have a few questions regarding this. 1) Is M5 currently capable of doing this? 2) Is the X86 processor model cycle accurate? 3) If the answers to bot the above questions are No - then this question i smoot. Otherwise, how does the X86 cpu model simulate memory hierarchy timing - specifically TLBs and the caches - in terms of lookup and replacement functionality? Thanks, Girish Date: Sat, 07 Mar 2009 10:55:19 -0800 From: Gabe Black gbl...@eecs.umich.edu Subject: Re: [m5-dev] X86 support To: M5 Developer List m5-dev@m5sim.org Message-ID: 49b2c317.5050...@eecs.umich.edu Content-Type: text/plain; charset=ISO-8859-1 Hi Girish. We don't have a specific date in mind when we'll consider X86 finished, at least not yet. Almost all of the work we've done on it is available in our repositories though, and while it can't do everything it does support a lot. If you can describe what you need I could give you a better idea of what to expect. Gabe Girish Venkatasubramanian wrote: Hello, I am Girish, a grad student from University of Florida. I came across M5 and found it very interesting. I am interested in trying out M5 to see if I can use that for my work. One question - I see from the Main Page that support for X86 is under development. Do you have a target date for releasing this model? Thanks, Girish ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] X86 support
That depends on what's on the disk image. If it's a 64 bit uniprocessor Linux kernel, it will likely almost work, or possibly actually work. If it's any other OS I don't know what will happen since I haven't tried it myself. In M5, CPU models are not generally for one ISA or another. Theoretically, you should be able to plug any ISA into any CPU model we have and it should work. In reality, the simple atomic CPU model supports x86 the best, followed by the simple timing CPU. We have two other main CPU models as well, but those need work before they support x86. We have a TLB for each ISA which behaves like you would expect a TLB to in each case, as well as a common memory system which simulates timing, caches, various coherence protocols, etc. The TLB for x86 uses a simple idealized LRU replacement policy, but it wouldn't be hard, relatively speaking, to replace that with whatever you wanted. The other M5 developers can probably give you a better picture of how accurate the various CPU models are, what the memory system simulates, etc. Gabe Girish Venkatasubramanian wrote: Hello Gabe, Thanks for the reply. I have used Simics for booting a disk image and running workloads for the X86 architecture and I would like to try the same on M5. I have a few questions regarding this. 1) Is M5 currently capable of doing this? 2) Is the X86 processor model cycle accurate? 3) If the answers to bot the above questions are No - then this question i smoot. Otherwise, how does the X86 cpu model simulate memory hierarchy timing - specifically TLBs and the caches - in terms of lookup and replacement functionality? Thanks, Girish Date: Sat, 07 Mar 2009 10:55:19 -0800 From: Gabe Black gbl...@eecs.umich.edu Subject: Re: [m5-dev] X86 support To: M5 Developer List m5-dev@m5sim.org Message-ID: 49b2c317.5050...@eecs.umich.edu Content-Type: text/plain; charset=ISO-8859-1 Hi Girish. We don't have a specific date in mind when we'll consider X86 finished, at least not yet. Almost all of the work we've done on it is available in our repositories though, and while it can't do everything it does support a lot. If you can describe what you need I could give you a better idea of what to expect. Gabe Girish Venkatasubramanian wrote: Hello, I am Girish, a grad student from University of Florida. I came across M5 and found it very interesting. I am interested in trying out M5 to see if I can use that for my work. One question - I see from the Main Page that support for X86 is under development. Do you have a target date for releasing this model? Thanks, Girish ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] old code
Please don't do anything with the TLBs yet. I'm hoping to send out a patch tonight. Gabe nathan binkert wrote: 1) Anybody have any problems if I remove the last remnants of turbolaser code that's in the TLB? We haven't had the devices in forever and I just don't see it ever being used? 2) There's a bunch of code to make stats compatible with simplescalar output. Can I clobber it all and use the normal M5 output? This would change statistics output for distributions mostly, but it would actually make it easier to parse if you wanted to. 3) We have SS_COMPATIBLE_FP and default it to being on. Do we still care about this? I'm guessing the answer is Yes and we want it for EIO. Do we want to default to it being on? I'd really like to ditch the first two, I can see steve saying that we should leave #3 alone (which I'm fine with.) Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] old code
Please don't do anything with the TLBs yet. I'm hoping to send out a patch tonight. No problem. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH] imported patch unifytlb.patch
Patch subject is complete summary.
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1236576344 25200
# Node ID 1c069851445b283974b8c1ed4102659ef86b96e4
# Parent 74bc713c71ce4e2a2e29958ff2f4c6f5c6ab6aa0
imported patch unifytlb.patch
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -33,15 +33,5 @@
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
-abstract = True
-size = Param.Int(TLB size)
-
-class AlphaDTB(AlphaTLB):
-type = 'AlphaDTB'
-cxx_class = 'AlphaISA::DTB'
-size = 64
-
-class AlphaITB(AlphaTLB):
-type = 'AlphaITB'
-cxx_class = 'AlphaISA::ITB'
-size = 48
+cxx_class = 'AlphaISA::TLB'
+size = Param.Int(64, TLB size)
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -70,6 +70,90 @@
{
if (table)
delete [] table;
+}
+
+void
+TLB::regStats()
+{
+fetch_hits
+.name(name() + .fetch_hits)
+.desc(ITB hits);
+fetch_misses
+.name(name() + .fetch_misses)
+.desc(ITB misses);
+fetch_acv
+.name(name() + .fetch_acv)
+.desc(ITB acv);
+fetch_accesses
+.name(name() + .fetch_accesses)
+.desc(ITB accesses);
+
+fetch_accesses = fetch_hits + fetch_misses;
+
+read_hits
+.name(name() + .read_hits)
+.desc(DTB read hits)
+;
+
+read_misses
+.name(name() + .read_misses)
+.desc(DTB read misses)
+;
+
+read_acv
+.name(name() + .read_acv)
+.desc(DTB read access violations)
+;
+
+read_accesses
+.name(name() + .read_accesses)
+.desc(DTB read accesses)
+;
+
+write_hits
+.name(name() + .write_hits)
+.desc(DTB write hits)
+;
+
+write_misses
+.name(name() + .write_misses)
+.desc(DTB write misses)
+;
+
+write_acv
+.name(name() + .write_acv)
+.desc(DTB write access violations)
+;
+
+write_accesses
+.name(name() + .write_accesses)
+.desc(DTB write accesses)
+;
+
+data_hits
+.name(name() + .data_hits)
+.desc(DTB hits)
+;
+
+data_misses
+.name(name() + .data_misses)
+.desc(DTB misses)
+;
+
+data_acv
+.name(name() + .data_acv)
+.desc(DTB access violations)
+;
+
+data_accesses
+.name(name() + .data_accesses)
+.desc(DTB accesses)
+;
+
+data_hits = read_hits + write_hits;
+data_misses = read_misses + write_misses;
+data_acv = read_acv + write_acv;
+data_accesses = read_accesses + write_accesses;
}
// look up an entry in the TLB
@@ -288,36 +372,8 @@
}
}
-///
-//
-// Alpha ITB
-//
-ITB::ITB(const Params *p)
-: TLB(p)
-{}
-
-
-void
-ITB::regStats()
-{
-hits
-.name(name() + .hits)
-.desc(ITB hits);
-misses
-.name(name() + .misses)
-.desc(ITB misses);
-acv
-.name(name() + .acv)
-.desc(ITB acv);
-accesses
-.name(name() + .accesses)
-.desc(ITB accesses);
-
-accesses = hits + misses;
-}
-
Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM PcPAL(req-getPC()))
@@ -326,7 +382,7 @@
if (PcPAL(req-getPC())) {
// strip off PAL PC marker (lsb is 1)
req-setPaddr((req-getVaddr() ~3) PAddrImplMask);
-hits++;
+fetch_hits++;
return NoFault;
}
@@ -335,7 +391,7 @@
} else {
// verify that this is a good virtual address
if (!validVirtualAddress(req-getVaddr())) {
-acv++;
+fetch_acv++;
return new ItbAcvFault(req-getVaddr());
}
@@ -352,7 +408,7 @@
// only valid in kernel mode
if (ICM_CM(tc-readMiscRegNoEffect(IPR_ICM)) !=
mode_kernel) {
-acv++;
+fetch_acv++;
return new ItbAcvFault(req-getVaddr());
}
@@ -373,7 +429,7 @@
asn);
if (!entry) {
-misses++;
+fetch_misses++;
return new ItbPageFault(req-getVaddr());
}
@@ -385,11 +441,11 @@
if (!(entry-xre
(1 ICM_CM(tc-readMiscRegNoEffect(IPR_ICM) {
// instruction access fault
-acv++;
+fetch_acv++;
return new ItbAcvFault(req-getVaddr());
}
-hits++;
+fetch_hits++;
}
}
@@ -401,93 +457,8 @@
}
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-Translation
