[m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp passed. *
Re: [m5-dev] Review Request: SCons: Clean up some inconsistent capitalization in scons options.
I don't think so. update_refs/UPDATE_REFS is used to replace the expected regression outputs, so that shouldn't have any impact on actually running the regressions. If that's not right somebody please speak up. Gabe On 02/28/11 18:32, nathan binkert wrote: Do the regression scripts need to be fixed? On Mon, Feb 28, 2011 at 11:59 AM, Ali Saidi sa...@umich.edu mailto:sa...@umich.edu wrote: This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/522/ Ship it! Looks fine. Two things though: 1) The documentation on the wiki needs to be updated along with this change. 2) I would like a separate email sent to the list saying that update_refs - UPDATE_REFS. - Ali On February 28th, 2011, 4:54 a.m., Gabe Black wrote: Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. By Gabe Black. /Updated 2011-02-28 04:54:41/ Description SCons: Clean up some inconsistent capitalization in scons options. Diffs * SConstruct (c6ba129c2764) * src/mem/protocol/SConsopts (c6ba129c2764) * tests/SConscript (c6ba129c2764) View Diff http://reviews.m5sim.org/r/522/diff/ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: Ruby: Mention that Ruby's bound checking option...
changeset 265202bbac87 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=265202bbac87
description:
Ruby: Mention that Ruby's bound checking option only applies to Ruby.
diffstat:
src/mem/ruby/SConsopts | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diffs (13 lines):
diff -r 59a19310ca65 -r 265202bbac87 src/mem/ruby/SConsopts
--- a/src/mem/ruby/SConsoptsSun Feb 27 16:25:06 2011 -0800
+++ b/src/mem/ruby/SConsoptsTue Mar 01 02:59:09 2011 -0800
@@ -31,7 +31,8 @@
Import('*')
sticky_vars.AddVariables(
-BoolVariable('NO_VECTOR_BOUNDS_CHECKS', Don't do bounds checks, True),
+BoolVariable('NO_VECTOR_BOUNDS_CHECKS', Don't do bounds checks in Ruby,
+ True),
('GEMS_ROOT', Add debugging stuff to Ruby, Dir('..').srcnode().abspath),
)
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[m5-dev] changeset in m5: SCons: Separately label the global non-sticky o...
changeset cf1afc88070f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cf1afc88070f
description:
SCons: Separately label the global non-sticky options.
The global sticky options were being printed with a heading, and then
the
global nonsticky options were being printed immediately after them
without a
heading. Because the two lists ran together and the first had its own
heading,
it looked like -all- those options where sticky even though some of them
aren't. This change adds a label to the second list so it's clear
they're
different.
diffstat:
SConstruct | 19 +++
1 files changed, 11 insertions(+), 8 deletions(-)
diffs (35 lines):
diff -r 265202bbac87 -r cf1afc88070f SConstruct
--- a/SConstructTue Mar 01 02:59:09 2011 -0800
+++ b/SConstructTue Mar 01 03:00:42 2011 -0800
@@ -338,20 +338,23 @@
('update_ref', 'Update test reference outputs', False)
)
+# Update main environment with values from ARGUMENTS global_sticky_vars_file
+global_sticky_vars.Update(main)
+global_nonsticky_vars.Update(main)
+global_help_texts = {
+global_sticky : global_sticky_vars.GenerateHelpText(main),
+global_nonsticky : global_nonsticky_vars.GenerateHelpText(main)
+}
# base help text
help_text = '''
Usage: scons [scons options] [build options] [target(s)]
Global sticky options:
-'''
-
-# Update main environment with values from ARGUMENTS global_sticky_vars_file
-global_sticky_vars.Update(main)
-global_nonsticky_vars.Update(main)
-
-help_text += global_sticky_vars.GenerateHelpText(main)
-help_text += global_nonsticky_vars.GenerateHelpText(main)
+%(global_sticky)s
+Global nonsticky options:
+%(global_nonsticky)s
+''' % global_help_texts
# Save sticky variable settings back to current variables file
global_sticky_vars.Save(global_sticky_vars_file, main)
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[m5-dev] Testing Functional Access
How can I test whether or not functional accesses to the memory are working correctly? Do we have some regression test for this? Thanks Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Testing Functional Access
Hi Nilay, I would suggest a few different tests. The first one would be to run a simple binary under Alpha SE mode using Ruby. You should first observe a bunch of functional accesses that initialize memory and then (if I recall correctly) dynamic accesses will load the TLB. After passing that test, I would try loading a SE checkpoint and running. After that, I would move on to similar tests using FS mode. I hope that helps. Please let me know if you have any specific questions. Brad -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Nilay Sent: Tuesday, March 01, 2011 6:51 AM To: m5-dev@m5sim.org Subject: [m5-dev] Testing Functional Access How can I test whether or not functional accesses to the memory are working correctly? Do we have some regression test for this? Thanks Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Testing Functional Access
Hi Nilay, I don't know if there is a regression for it, but the M5 utility (./util/m5/) sets up functional accesses to memory. For instance, in FS, if you specify an rcS script to fs.py and call % /sbin/m5 readfile from the command line of the simulated system, it will read the specified rcS file off the host machine's disk and send it to the memory of the simulated system using functional accesses. I think there are other functional access examples in the magic that the M5 utility provides. Hope this helps, Joel On Tue, Mar 1, 2011 at 8:51 AM, Nilay ni...@cs.wisc.edu wrote: How can I test whether or not functional accesses to the memory are working correctly? Do we have some regression test for this? Thanks Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Testing Functional Access
The m5 memtester supports functional accesses (there's a percent_functional parameter on the MemTest object). I don't know if anyone's run the memtester with Ruby though. Seems like it should work. Steve On Tue, Mar 1, 2011 at 8:39 AM, Joel Hestness hestn...@cs.utexas.eduwrote: Hi Nilay, I don't know if there is a regression for it, but the M5 utility (./util/m5/) sets up functional accesses to memory. For instance, in FS, if you specify an rcS script to fs.py and call % /sbin/m5 readfile from the command line of the simulated system, it will read the specified rcS file off the host machine's disk and send it to the memory of the simulated system using functional accesses. I think there are other functional access examples in the magic that the M5 utility provides. Hope this helps, Joel On Tue, Mar 1, 2011 at 8:51 AM, Nilay ni...@cs.wisc.edu wrote: How can I test whether or not functional accesses to the memory are working correctly? Do we have some regression test for this? Thanks Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Testing Functional Access
I forgot that the memtester includes functional accesses. That is a good suggestion, especially when it comes to testing the situations where Ruby can't satisfy the functional access due to contention with timing accesses. The memtester does run with Ruby (it actually runs every night in the regression tester), however the percentage of functional accesses is currently set to zero. See configs/example/ruby_mem_test.py. You'll obviously want to change that and include code within src/cpu/testers/memtest/* to handle failed functional accesses. If you don't want to initially deal with the failure situations, you can set the functional access percentage to 100% and that should always work. Brad -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Steve Reinhardt Sent: Tuesday, March 01, 2011 10:49 AM To: M5 Developer List Subject: Re: [m5-dev] Testing Functional Access The m5 memtester supports functional accesses (there's a percent_functional parameter on the MemTest object). I don't know if anyone's run the memtester with Ruby though. Seems like it should work. Steve On Tue, Mar 1, 2011 at 8:39 AM, Joel Hestness hestn...@cs.utexas.eduwrote: Hi Nilay, I don't know if there is a regression for it, but the M5 utility (./util/m5/) sets up functional accesses to memory. For instance, in FS, if you specify an rcS script to fs.py and call % /sbin/m5 readfile from the command line of the simulated system, it will read the specified rcS file off the host machine's disk and send it to the memory of the simulated system using functional accesses. I think there are other functional access examples in the magic that the M5 utility provides. Hope this helps, Joel On Tue, Mar 1, 2011 at 8:51 AM, Nilay ni...@cs.wisc.edu wrote: How can I test whether or not functional accesses to the memory are working correctly? Do we have some regression test for this? Thanks Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/505/ --- Review request for Default. Summary --- At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF() has not been provided with correct number of arguments. The patch fixes these bugs. Diffs - src/mem/ruby/buffers/MessageBuffer.cc UNKNOWN src/mem/ruby/network/simple/PerfectSwitch.cc UNKNOWN Diff: http://reviews.m5sim.org/r/505/diff Testing --- Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/505/#review921 --- Ship it! - Brad On 2011-03-01 13:31:45, Nilay Vaish wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/505/ --- (Updated 2011-03-01 13:31:45) Review request for Default. Summary --- At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF() has not been provided with correct number of arguments. The patch fixes these bugs. Diffs - src/mem/ruby/buffers/MessageBuffer.cc UNKNOWN src/mem/ruby/network/simple/PerfectSwitch.cc UNKNOWN Diff: http://reviews.m5sim.org/r/505/diff Testing --- Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
Hi Nilay, In the future, feel free to directly check in these sort of minor bug fixes. Thanks, Brad -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Nilay Vaish Sent: Tuesday, March 01, 2011 1:32 PM To: Nilay Vaish; Default Subject: [m5-dev] Review Request: Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/505/ --- Review request for Default. Summary --- At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF() has not been provided with correct number of arguments. The patch fixes these bugs. Diffs - src/mem/ruby/buffers/MessageBuffer.cc UNKNOWN src/mem/ruby/network/simple/PerfectSwitch.cc UNKNOWN Diff: http://reviews.m5sim.org/r/505/diff Testing --- Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: cpu: split o3-specific parts out of BaseDynInst
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/529/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- cpu: split o3-specific parts out of BaseDynInst The bigger picture goal is that I want to get the InorderDynInst class derived from the BaseDynInst, since there is no need to replicate a lot of useful code already defined in BaseDynInst (e.g. microcode identification, etc.) and Inorder can take advantage of common code that handles microcode and other features that other ISAs need. But to do this, there are a lot of o3-specific things that are in BaseDynInst, that I pushed to O3DynInst in this patch. Book-keeping variables that handle the IQ,LSQ,ROB are unnecessary in the base class but generic variables that will work across CPUs (IsSquashed, IsCompleted, etc.) are kept in the base class. The upside is more consistency across the simple models (branch prediction and instruction identification are all in one common place). I really wanted to define pure virtual functions for read/write(to memory) and the setInt/FloatRegOperand, but virtual functions in a templated class is a no-no and I couldn't get around that (suggestions?). Also, I'd rather not use the this- pointer all over the place to access member variables of the templated Base class, but it had to be done. Other than those quirks, simulator functionality should stay the same as the O3 Model always references the O3DynInst pointer and the InOrder model doesnt currently make use of the base dyn inst. class. (but it will be easier to derive from now...) Diffs - src/cpu/base_dyn_inst.hh cf1afc88070f src/cpu/base_dyn_inst_impl.hh cf1afc88070f src/cpu/o3/dyn_inst.hh cf1afc88070f src/cpu/o3/dyn_inst_impl.hh cf1afc88070f Diff: http://reviews.m5sim.org/r/529/diff Testing --- Thanks, Korey ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: Ruby: Fix DPRINTF bugs in PerfectSwitch and Mes...
changeset 2e1ee8ec6266 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2e1ee8ec6266
description:
Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc,
DPRINTF()
has not been provided with correct number of arguments. The patch fixes
these
bugs.
diffstat:
src/mem/ruby/buffers/MessageBuffer.cc| 2 +-
src/mem/ruby/network/simple/PerfectSwitch.cc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diffs (24 lines):
diff -r cf1afc88070f -r 2e1ee8ec6266 src/mem/ruby/buffers/MessageBuffer.cc
--- a/src/mem/ruby/buffers/MessageBuffer.cc Tue Mar 01 03:00:42 2011 -0800
+++ b/src/mem/ruby/buffers/MessageBuffer.cc Tue Mar 01 15:26:11 2011 -0600
@@ -380,7 +380,7 @@
void
MessageBuffer::stallMessage(const Address addr)
{
-DPRINTF(RubyQueue, Stalling %s\n);
+DPRINTF(RubyQueue, Stalling due to %s\n, addr);
assert(isReady());
assert(addr.getOffset() == 0);
MsgPtr message = m_prio_heap.front().m_msgptr;
diff -r cf1afc88070f -r 2e1ee8ec6266
src/mem/ruby/network/simple/PerfectSwitch.cc
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc Tue Mar 01 03:00:42
2011 -0800
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc Tue Mar 01 15:26:11
2011 -0600
@@ -300,7 +300,7 @@
output_link_destinations[i];
// Enqeue msg
-DPRINTF(RubyNetwork, %d enqueuing net msg from
+DPRINTF(RubyNetwork, Enqueuing net msg from
inport[%d][%d] to outport [%d][%d] time:
%lld.\n,
incoming, vnet, outgoing, vnet,
g_eventQueue_ptr-getTime());
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[m5-dev] changeset in m5: X86: Mark prefetches as such in their instructi...
changeset 77ee9ad2e113 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=77ee9ad2e113
description:
X86: Mark prefetches as such in their instruction and request flags.
diffstat:
src/arch/x86/isa/microops/ldstop.isa | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diffs (23 lines):
diff -r 2e1ee8ec6266 -r 77ee9ad2e113 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Tue Mar 01 15:26:11 2011 -0600
+++ b/src/arch/x86/isa/microops/ldstop.isa Tue Mar 01 22:42:18 2011 -0800
@@ -282,8 +282,10 @@
self.memFlags = baseFlags
if atCPL0:
self.memFlags += | (CPL0FlagBit FlagShift)
+self.instFlags =
if prefetch:
self.memFlags += | Request::PREFETCH
+self.instFlags += | StaticInst::IsDataPrefetch
self.memFlags += | (machInst.legacy.addr ? + \
(AddrSizeFlagBit FlagShift) : 0)
@@ -293,7 +295,7 @@
%(disp)s, %(segment)s, %(data)s,
%(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
class_name : self.className,
-flags : self.microFlagsText(microFlags),
+flags : self.microFlagsText(microFlags) + self.instFlags,
scale : self.scale, index : self.index,
base : self.base,
disp : self.disp,
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[m5-dev] changeset in m5: X86: Mark IO reads and writes as non-speculative.
changeset 53c2d9b1c15d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=53c2d9b1c15d
description:
X86: Mark IO reads and writes as non-speculative.
diffstat:
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 12 ++-
src/arch/x86/isa/insts/general_purpose/input_output/string_io.py | 12 ++-
src/arch/x86/isa/microops/ldstop.isa | 34
++---
3 files changed, 37 insertions(+), 21 deletions(-)
diffs (188 lines):
diff -r 77ee9ad2e113 -r 53c2d9b1c15d
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Tue Mar
01 22:42:18 2011 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Tue Mar
01 22:42:59 2011 -0800
@@ -42,22 +42,26 @@
def macroop IN_R_I {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=asz
-ld reg, intseg, [1, t1, t0], IntAddrPrefixIO 3, addressSize=8
+ld reg, intseg, [1, t1, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
};
def macroop IN_R_R {
zexti t2, regm, 15, dataSize=8
-ld reg, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8
+ld reg, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
};
def macroop OUT_I_R {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=8
-st reg, intseg, [1, t1, t0], IntAddrPrefixIO 3, addressSize=8
+st reg, intseg, [1, t1, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
};
def macroop OUT_R_R {
zexti t2, reg, 15, dataSize=8
-st regm, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8
+st regm, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
};
'''
diff -r 77ee9ad2e113 -r 53c2d9b1c15d
src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py Tue Mar
01 22:42:18 2011 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py Tue Mar
01 22:42:59 2011 -0800
@@ -45,7 +45,8 @@
zexti t2, reg, 15, dataSize=8
-ld t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8
+ld t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
st t6, es, [1, t0, rdi]
add rdi, rdi, t3, dataSize=asz
@@ -63,7 +64,8 @@
zexti t2, reg, 15, dataSize=8
topOfLoop:
-ld t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8
+ld t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
st t6, es, [1, t0, rdi]
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
@@ -83,7 +85,8 @@
zexti t2, reg, 15, dataSize=8
ld t6, ds, [1, t0, rsi]
-st t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8
+st t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
add rsi, rsi, t3, dataSize=asz
};
@@ -101,7 +104,8 @@
topOfLoop:
ld t6, ds, [1, t0, rsi]
-st t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8
+st t6, intseg, [1, t2, t0], IntAddrPrefixIO 3, addressSize=8, \
+nonSpec=True
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
add rsi, rsi, t3, dataSize=asz
diff -r 77ee9ad2e113 -r 53c2d9b1c15d src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Tue Mar 01 22:42:18 2011 -0800
+++ b/src/arch/x86/isa/microops/ldstop.isa Tue Mar 01 22:42:59 2011 -0800
@@ -272,7 +272,7 @@
let {{
class LdStOp(X86Microop):
def __init__(self, data, segment, addr, disp,
-dataSize, addressSize, baseFlags, atCPL0, prefetch):
+dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
self.data = data
[self.scale, self.index, self.base] = addr
self.disp = disp
@@ -285,7 +285,9 @@
self.instFlags =
if prefetch:
self.memFlags += | Request::PREFETCH
-self.instFlags += | StaticInst::IsDataPrefetch
+self.instFlags += | (1ULL StaticInst::IsDataPrefetch)
+if nonSpec:
+self.instFlags += | (1ULL StaticInst::IsNonSpeculative)
self.memFlags += | (machInst.legacy.addr ? + \
(AddrSizeFlagBit FlagShift) : 0)
@@ -306,7 +308,7 @@
class BigLdStOp(X86Microop):
def __init__(self, data, segment, addr, disp,
-dataSize, addressSize, baseFlags, atCPL0, prefetch):
+dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
self.data = data
[self.scale, self.index, self.base] = addr
self.disp = disp
@@ -316,8 +318,12 @@
self.memFlags = baseFlags
if atCPL0:
self.memFlags += |
[m5-dev] changeset in m5: X86: Update stats for the x86 o3 hello world re...
changeset 0dcd19617556 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0dcd19617556 description: X86: Update stats for the x86 o3 hello world regression. diffstat: tests/quick/00.hello/ref/x86/linux/o3-timing/simout| 6 +- tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 66 +- 2 files changed, 36 insertions(+), 36 deletions(-) diffs (175 lines): diff -r 53c2d9b1c15d -r 0dcd19617556 tests/quick/00.hello/ref/x86/linux/o3-timing/simout --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout Tue Mar 01 22:42:59 2011 -0800 +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout Tue Mar 01 23:18:00 2011 -0800 @@ -5,9 +5,9 @@ All Rights Reserved -M5 compiled Feb 12 2011 02:22:23 -M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch -M5 started Feb 12 2011 02:22:27 +M5 compiled Mar 1 2011 23:14:11 +M5 revision 42f62a19a71d 8104 default qbase qtip tip x86seo3stats.patch +M5 started Mar 1 2011 23:14:13 M5 executing on burrito command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1 ticks per second diff -r 53c2d9b1c15d -r 0dcd19617556 tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txtTue Mar 01 22:42:59 2011 -0800 +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txtTue Mar 01 23:18:00 2011 -0800 @@ -1,9 +1,9 @@ -- Begin Simulation Statistics -- -host_inst_rate 47598 # Simulator instruction rate (inst/s) -host_mem_usage 231896 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 55349277 # Simulator tick rate (ticks/s) +host_inst_rate 103787 # Simulator instruction rate (inst/s) +host_mem_usage 224152 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 120600528 # Simulator tick rate (ticks/s) sim_freq 1 # Frequency of simulated ticks sim_insts9809 # Number of instructions simulated sim_seconds 0.11 # Number of seconds simulated @@ -213,28 +213,28 @@ system.cpu.idleCycles9434 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 1551 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.676151 # Inst execution rate -system.cpu.iew.EXEC:refs 2971 # number of memory reference insts executed +system.cpu.iew.EXEC:rate 0.676108 # Inst execution rate +system.cpu.iew.EXEC:refs 2970 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1306 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 14704 # num instructions consuming a value +system.cpu.iew.WB:consumers 14702 # num instructions consuming a value system.cpu.iew.WB:count 15138 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.679747 # average fanout of values written-back +system.cpu.iew.WB:fanout 0.679703 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 9995 # num instructions producing a value +system.cpu.iew.WB:producers 9993 # num instructions producing a
[m5-dev] changeset in m5: Spelling: Fix the a spelling error by changing ...
changeset 906864dd0937 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=906864dd0937
description:
Spelling: Fix the a spelling error by changing mmaped to mmapped.
There may not be a formally correct spelling for the past tense of
mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes
sense
because it mirrors the past tense of map-mapped and not the past tense
of
cape-caped.
diffstat:
src/arch/SConscript | 2 +-
src/arch/alpha/mmaped_ipr.hh | 63 -
src/arch/alpha/mmapped_ipr.hh | 63 +
src/arch/arm/mmaped_ipr.hh| 64 -
src/arch/arm/mmapped_ipr.hh | 64 +
src/arch/mips/mmaped_ipr.hh | 62
src/arch/mips/mmapped_ipr.hh | 62
src/arch/power/mmaped_ipr.hh | 66 --
src/arch/power/mmapped_ipr.hh | 66 ++
src/arch/sparc/mmaped_ipr.hh | 72 -
src/arch/sparc/mmapped_ipr.hh | 72 +
src/arch/sparc/tlb.cc | 2 +-
src/arch/x86/mmaped_ipr.hh| 92 ---
src/arch/x86/mmapped_ipr.hh | 92 +++
src/arch/x86/tlb.cc | 4 +-
src/cpu/simple/atomic.cc | 6 +-
src/cpu/simple/timing.cc | 8 +-
src/mem/physical.cc | 2 +-
src/mem/request.hh| 4 +-
19 files changed, 433 insertions(+), 433 deletions(-)
diffs (truncated from 1033 to 300 lines):
diff -r 0dcd19617556 -r 906864dd0937 src/arch/SConscript
--- a/src/arch/SConscript Tue Mar 01 23:18:00 2011 -0800
+++ b/src/arch/SConscript Tue Mar 01 23:18:47 2011 -0800
@@ -50,7 +50,7 @@
kernel_stats.hh
locked_mem.hh
microcode_rom.hh
-mmaped_ipr.hh
+mmapped_ipr.hh
mt.hh
process.hh
predecoder.hh
diff -r 0dcd19617556 -r 906864dd0937 src/arch/alpha/mmaped_ipr.hh
--- a/src/arch/alpha/mmaped_ipr.hh Tue Mar 01 23:18:00 2011 -0800
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__
-#define __ARCH_ALPHA_MMAPED_IPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include base/types.hh
-#include mem/packet.hh
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-inline Tick
-handleIprRead(ThreadContext *xc, Packet *pkt)
-{
-panic(No handleIprRead implementation in Alpha\n);
-}
-
-
-inline Tick
-handleIprWrite(ThreadContext *xc, Packet *pkt)
-{
-panic(No handleIprWrite implementation in Alpha\n);
-}
-
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_MMAPED_IPR_HH__
diff -r 0dcd19617556 -r 906864dd0937 src/arch/alpha/mmapped_ipr.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/src/arch/alpha/mmapped_ipr.hh Tue Mar 01 23:18:47 2011 -0800
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain
