Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick
IIRC, I was expecting some response from Ali as to why M5_DUMMY_RETURN should or should not work. I did not poke in any further. To me it is a compiler bug that we have to work with. I think return panic(); works with both 4.2 and 4.4 series, but we probably do not want that. -- Nilay On Tue, March 8, 2011 11:37 pm, nathan binkert wrote: Nilay, I know that this is a way old e-mail, but did you ever figure this out? Nate On Fri, Dec 24, 2010 at 8:57 AM, Nilay Vaish ni...@cs.wisc.edu wrote: I tried M5_DUMMY_RETURN and it it not working. I checked its definition. It would evaluate to nothing, in which case I do not see why it should help in avoiding the warning. I tried putting a return statement before panic(); return panic(not implemented); This works with GCC 4.2.2. I checked whether GCC has some recorded bug reports for this. I found the following two - http://gcc.gnu.org/bugzilla/show_bug.cgi?id=30988 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42674 I tried the provided codes. For the first one, 4.2.2 raises a warning but 4.4.0 does not. For the second one, 4.4.0 raises a warning but 4.2.2 does not. -- Nilay On Thu, 23 Dec 2010, Ali Saidi wrote: A better solution would be to put M5_DUMMY_RETURN there. I know there'd were some issues with some versions of gcc not respecting the attribute no return. This might be the case. Ali Sent from my ARM powered device ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Functional Interface in Ruby
Does the RubySystem object have a pointer to a RubyCache object? You could also go into the python code and add some print statements to get a clue about where the cycle is occurring. Steve On Wed, Mar 9, 2011 at 4:51 AM, Nilay ni...@cs.wisc.edu wrote: Brad, given current versions of MESI_CMP_directory.py and Ruby.py, the following change to the way cache memory is added to the system creates a loop. What am I missing here? class RubyAbstractMemory(SimObject): type = 'RubyAbstractMemory' cxx_class = 'AbstractMemory' system = Param.RubySystem(Parent.any,Ruby System); class RubyCache(RubyAbstractMemory): type = 'RubyCache' cxx_class = 'CacheMemory' size = Param.MemorySize(capacity in bytes); latency = Param.Int(); assoc = Param.Int(); replacement_policy = Param.String(PSEUDO_LRU, ); start_index_bit = Param.Int(6, index start, default 6 for 64-byte line); -- Nilay On Tue, March 8, 2011 6:35 pm, Steve Reinhardt wrote: It probably means that two objects have pointers to each other as parameters (or more generally there's a cycle). See step 3 here: http://m5sim.org/wiki/index.php/SimObject_Initialization On Tue, Mar 8, 2011 at 4:27 PM, Nilay Vaish ni...@cs.wisc.edu wrote: When does the following error occurs? Is it that an object is being accessed while it is being created? File /afs/ cs.wisc.edu/u/n/i/nilay/private/Architecture/GEM5/m5/src/python/m5/SimObject.py , line 834, in getCCObject raise RuntimeError, %s: Cycle found in configuration hierarchy. \ RuntimeError: system.l1_cntrl0.L1DcacheMemory: Cycle found in configuration hierarchy. -- Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick
IIRC, I was expecting some response from Ali as to why M5_DUMMY_RETURN should or should not work. I did not poke in any further. To me it is a compiler bug that we have to work with. I think return panic(); works with both 4.2 and 4.4 series, but we probably do not want that. What I didn't understand was why this was an issue for this file, but not others that are in a similar situation. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Functional Interface in Ruby
What exactly happens on the function call Param.RubySystem(Parent.any, Ruby System) ? Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: Does the RubySystem object have a pointer to a RubyCache object? You could also go into the python code and add some print statements to get a clue about where the cycle is occurring. Steve On Wed, Mar 9, 2011 at 4:51 AM, Nilay ni...@cs.wisc.edu wrote: Brad, given current versions of MESI_CMP_directory.py and Ruby.py, the following change to the way cache memory is added to the system creates a loop. What am I missing here? class RubyAbstractMemory(SimObject): type = 'RubyAbstractMemory' cxx_class = 'AbstractMemory' system = Param.RubySystem(Parent.any,Ruby System); class RubyCache(RubyAbstractMemory): type = 'RubyCache' cxx_class = 'CacheMemory' size = Param.MemorySize(capacity in bytes); latency = Param.Int(); assoc = Param.Int(); replacement_policy = Param.String(PSEUDO_LRU, ); start_index_bit = Param.Int(6, index start, default 6 for 64-byte line); -- Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Functional Interface in Ruby
I think you're looking in the wrong place... you want to look at getCCObject() in src/python/m5/SimObject.py where the error message is coming from, and see if you can add some print statements there. Steve On Wed, Mar 9, 2011 at 11:27 AM, Nilay Vaish ni...@cs.wisc.edu wrote: What exactly happens on the function call Param.RubySystem(Parent.any, Ruby System) ? Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: Does the RubySystem object have a pointer to a RubyCache object? You could also go into the python code and add some print statements to get a clue about where the cycle is occurring. Steve On Wed, Mar 9, 2011 at 4:51 AM, Nilay ni...@cs.wisc.edu wrote: Brad, given current versions of MESI_CMP_directory.py and Ruby.py, the following change to the way cache memory is added to the system creates a loop. What am I missing here? class RubyAbstractMemory(SimObject): type = 'RubyAbstractMemory' cxx_class = 'AbstractMemory' system = Param.RubySystem(Parent.any,Ruby System); class RubyCache(RubyAbstractMemory): type = 'RubyCache' cxx_class = 'CacheMemory' size = Param.MemorySize(capacity in bytes); latency = Param.Int(); assoc = Param.Int(); replacement_policy = Param.String(PSEUDO_LRU, ); start_index_bit = Param.Int(6, index start, default 6 for 64-byte line); -- Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset number in binary
A while back I proposed we add the mercurial changeset to the binary so that it could print it out as it started up. The idea was that if somebody showed us some output where something was broken or we found a random binary, we could tell what the underlying code was without having to ask. Have people found that to be useful so far? I don't think I've ever actually seen it in output somebody posted to m5-users in a way that helped solve their problem. Often people don't paste in output at all, or just include an error message. This change also had the unfortunate side effect of forcing scons to rebuild the m5 binary every time a patch was pushed or popped even if ultimately nothing changed. I'd like to determine if this mechanism has been useful for anyone else, or if it's just a nice idea that didn't pan out and is now only getting in the way. If it's the later, we should probably get rid of it. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Functional Interface in Ruby
Creating root Creating system.physmem Creating system Creating system.l1_cntrl0.L1DcacheMemory Creating system.ruby Creating system.ruby.network Creating system.ruby.network.topology Creating system.ruby.network.topology.ext_links0 Creating system.l1_cntrl0 Creating system.l1_cntrl0.L1DcacheMemory This is the output I obtained from SimObject.py, clearly there is a cycle. Should not the cache controllers be part of ruby, instead of being part of system? Once they become part of ruby, it should be possible to traverse the controller array and figure out all the caches. Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: I think you're looking in the wrong place... you want to look at getCCObject() in src/python/m5/SimObject.py where the error message is coming from, and see if you can add some print statements there. Steve On Wed, Mar 9, 2011 at 11:27 AM, Nilay Vaish ni...@cs.wisc.edu wrote: What exactly happens on the function call Param.RubySystem(Parent.any, Ruby System) ? Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: Does the RubySystem object have a pointer to a RubyCache object? You could also go into the python code and add some print statements to get a clue about where the cycle is occurring. Steve On Wed, Mar 9, 2011 at 4:51 AM, Nilay ni...@cs.wisc.edu wrote: Brad, given current versions of MESI_CMP_directory.py and Ruby.py, the following change to the way cache memory is added to the system creates a loop. What am I missing here? class RubyAbstractMemory(SimObject): type = 'RubyAbstractMemory' cxx_class = 'AbstractMemory' system = Param.RubySystem(Parent.any,Ruby System); class RubyCache(RubyAbstractMemory): type = 'RubyCache' cxx_class = 'CacheMemory' size = Param.MemorySize(capacity in bytes); latency = Param.Int(); assoc = Param.Int(); replacement_policy = Param.String(PSEUDO_LRU, ); start_index_bit = Param.Int(6, index start, default 6 for 64-byte line); -- Nilay ___ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Ruby FS - DMA Controller problem?
Hi all, I'm trying to run Ruby in FS mode for the FFT benchmark. However, I've been unable to fully boot the kernel and error with a panic in the IDE disk controller: panic: Inconsistent DMA transfer state: dmaState = 2 devState = 1 @ cycle 62640732569001 [doDmaTransfer:build/ALPHA_FS_MOESI_CMP_directory/dev/ide_disk.cc, line 323] Has anybody run into a similar error or does anyone have any suggestions for debugging the problem? I can run the same code using the M5 memory system and FFT finishes properly so it's definitely a ruby-specific thing. It seems to track this down , I could diff instruction traces (M5 v. Ruby) or maybe even diff trace output from the IdeDisk trace flags but those routes seem a bit heavy-handed considering the amount of trace output generated. The command line this was run with is: build/ALPHA_FS_MOESI_CMP_directory/m5.opt configs/example/ruby_fs.py -b fft_64t_base -n 1 The output in system.terminal is: hda: M5 IDE Disk, ATA DISK drive hdb: M5 IDE Disk, ATA DISK drive hda: UDMA/33 mode selected hdb: UDMA/33 mode selected hdc: M5 IDE Disk, ATA DISK drive hdc: UDMA/33 mode selected ide0 at 0x8410-0x8417,0x8422 on irq 31 ide1 at 0x8418-0x841f,0x8426 on irq 31 ide_generic: please use probe_mask=0x3f module parameter for probing all legacy ISA IDE ports ide2 at 0x1f0-0x1f7,0x3f6 on irq 14 ide3 at 0x170-0x177,0x376 on irq 15 hda: max request size: 128KiB hda: 2866752 sectors (1467 MB), CHS=2844/16/63 hda:4hda: dma_timer_expiry: dma status == 0x65 hda: DMA interrupt recovery hda: lost interrupt unknown partition table hdb: max request size: 128KiB hdb: 1008000 sectors (516 MB), CHS=1000/16/63 hdb:4hdb: dma_timer_expiry: dma status == 0x65 hdb: DMA interrupt recovery hdb: lost interrupt Thanks again, any help or thoughts would be well appreciated. -- - Korey ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset number in binary
I'm fine with getting rid of it. For me it's been the source of problems, particularly with update_ref, and I haven't personally seen a benefit. Steve On Wed, Mar 9, 2011 at 2:19 PM, Gabe Black gbl...@eecs.umich.edu wrote: A while back I proposed we add the mercurial changeset to the binary so that it could print it out as it started up. The idea was that if somebody showed us some output where something was broken or we found a random binary, we could tell what the underlying code was without having to ask. Have people found that to be useful so far? I don't think I've ever actually seen it in output somebody posted to m5-users in a way that helped solve their problem. Often people don't paste in output at all, or just include an error message. This change also had the unfortunate side effect of forcing scons to rebuild the m5 binary every time a patch was pushed or popped even if ultimately nothing changed. I'd like to determine if this mechanism has been useful for anyone else, or if it's just a nice idea that didn't pan out and is now only getting in the way. If it's the later, we should probably get rid of it. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick
The reason M5_DUMMY_RETURN didn't work is for gcc it's #defined to nothing because in theory gcc respects __attribute__(no return), but apparently not in this case. Ali On Mar 9, 2011, at 7:00 AM, Nilay wrote: IIRC, I was expecting some response from Ali as to why M5_DUMMY_RETURN should or should not work. I did not poke in any further. To me it is a compiler bug that we have to work with. I think return panic(); works with both 4.2 and 4.4 series, but we probably do not want that. -- Nilay On Tue, March 8, 2011 11:37 pm, nathan binkert wrote: Nilay, I know that this is a way old e-mail, but did you ever figure this out? Nate On Fri, Dec 24, 2010 at 8:57 AM, Nilay Vaish ni...@cs.wisc.edu wrote: I tried M5_DUMMY_RETURN and it it not working. I checked its definition. It would evaluate to nothing, in which case I do not see why it should help in avoiding the warning. I tried putting a return statement before panic(); return panic(not implemented); This works with GCC 4.2.2. I checked whether GCC has some recorded bug reports for this. I found the following two - http://gcc.gnu.org/bugzilla/show_bug.cgi?id=30988 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42674 I tried the provided codes. For the first one, 4.2.2 raises a warning but 4.4.0 does not. For the second one, 4.4.0 raises a warning but 4.2.2 does not. -- Nilay On Thu, 23 Dec 2010, Ali Saidi wrote: A better solution would be to put M5_DUMMY_RETURN there. I know there'd were some issues with some versions of gcc not respecting the attribute no return. This might be the case. Ali Sent from my ARM powered device ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Ruby FS - DMA Controller problem?
Hi Korey, I ran into a similar problem with a different benchmark/boot up attempt. There is another thread on m5-dev with 'Ruby FS failing with recent changesets' as the subject. I was able to track down the changeset which it was coming from, but I did not look further into the changeset as to why it was causing it. Brad said he would take a look at it, but I am not sure if he was able to reproduce the problem. Malek On Wed, Mar 9, 2011 at 7:08 PM, Korey Sewell ksew...@umich.edu wrote: Hi all, I'm trying to run Ruby in FS mode for the FFT benchmark. However, I've been unable to fully boot the kernel and error with a panic in the IDE disk controller: panic: Inconsistent DMA transfer state: dmaState = 2 devState = 1 @ cycle 62640732569001 [doDmaTransfer:build/ALPHA_FS_MOESI_CMP_directory/dev/ide_disk.cc, line 323] Has anybody run into a similar error or does anyone have any suggestions for debugging the problem? I can run the same code using the M5 memory system and FFT finishes properly so it's definitely a ruby-specific thing. It seems to track this down , I could diff instruction traces (M5 v. Ruby) or maybe even diff trace output from the IdeDisk trace flags but those routes seem a bit heavy-handed considering the amount of trace output generated. The command line this was run with is: build/ALPHA_FS_MOESI_CMP_directory/m5.opt configs/example/ruby_fs.py -b fft_64t_base -n 1 The output in system.terminal is: hda: M5 IDE Disk, ATA DISK drive hdb: M5 IDE Disk, ATA DISK drive hda: UDMA/33 mode selected hdb: UDMA/33 mode selected hdc: M5 IDE Disk, ATA DISK drive hdc: UDMA/33 mode selected ide0 at 0x8410-0x8417,0x8422 on irq 31 ide1 at 0x8418-0x841f,0x8426 on irq 31 ide_generic: please use probe_mask=0x3f module parameter for probing all legacy ISA IDE ports ide2 at 0x1f0-0x1f7,0x3f6 on irq 14 ide3 at 0x170-0x177,0x376 on irq 15 hda: max request size: 128KiB hda: 2866752 sectors (1467 MB), CHS=2844/16/63 hda:4hda: dma_timer_expiry: dma status == 0x65 hda: DMA interrupt recovery hda: lost interrupt unknown partition table hdb: max request size: 128KiB hdb: 1008000 sectors (516 MB), CHS=1000/16/63 hdb:4hdb: dma_timer_expiry: dma status == 0x65 hdb: DMA interrupt recovery hdb: lost interrupt Thanks again, any help or thoughts would be well appreciated. -- - Korey ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Functional Interface in Ruby
It seems odd that it tries to create L1DcacheMemory right after it creates system. Can you add print statements like in this patch and see what it shows? diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -843,8 +843,11 @@ # Call C++ to create C++ object corresponding to this object def createCCObject(self): +print Creating, self, params self.getCCParams() +print Creating, self self.getCCObject() # force creation +print Done creating, self def getValue(self): return self.getCCObject() On Wed, Mar 9, 2011 at 2:34 PM, Nilay Vaish ni...@cs.wisc.edu wrote: Creating root Creating system.physmem Creating system Creating system.l1_cntrl0.L1DcacheMemory Creating system.ruby Creating system.ruby.network Creating system.ruby.network.topology Creating system.ruby.network.topology.ext_links0 Creating system.l1_cntrl0 Creating system.l1_cntrl0.L1DcacheMemory This is the output I obtained from SimObject.py, clearly there is a cycle. Should not the cache controllers be part of ruby, instead of being part of system? Once they become part of ruby, it should be possible to traverse the controller array and figure out all the caches. Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: I think you're looking in the wrong place... you want to look at getCCObject() in src/python/m5/SimObject.py where the error message is coming from, and see if you can add some print statements there. Steve On Wed, Mar 9, 2011 at 11:27 AM, Nilay Vaish ni...@cs.wisc.edu wrote: What exactly happens on the function call Param.RubySystem(Parent.any, Ruby System) ? Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: Does the RubySystem object have a pointer to a RubyCache object? You could also go into the python code and add some print statements to get a clue about where the cycle is occurring. Steve On Wed, Mar 9, 2011 at 4:51 AM, Nilay ni...@cs.wisc.edu wrote: Brad, given current versions of MESI_CMP_directory.py and Ruby.py, the following change to the way cache memory is added to the system creates a loop. What am I missing here? class RubyAbstractMemory(SimObject): type = 'RubyAbstractMemory' cxx_class = 'AbstractMemory' system = Param.RubySystem(Parent.any,Ruby System); class RubyCache(RubyAbstractMemory): type = 'RubyCache' cxx_class = 'CacheMemory' size = Param.MemorySize(capacity in bytes); latency = Param.Int(); assoc = Param.Int(); replacement_policy = Param.String(PSEUDO_LRU, ); start_index_bit = Param.Int(6, index start, default 6 for 64-byte line); -- Nilay ___ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Ruby FS - DMA Controller problem?
I still have not been able to reproduce the problem, but I haven't tried in a few weeks. So does this happen when booting up the system, independent of what benchmark you are running? If so, could you send me your command line? I'm sure the disk image and kernel binaries between us are different, so I don't necessarily think I'll be able to reproduce your problem, but at least I'll be able to isolate it. Brad -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Malek Musleh Sent: Wednesday, March 09, 2011 4:41 PM To: M5 Developer List Subject: Re: [m5-dev] Ruby FS - DMA Controller problem? Hi Korey, I ran into a similar problem with a different benchmark/boot up attempt. There is another thread on m5-dev with 'Ruby FS failing with recent changesets' as the subject. I was able to track down the changeset which it was coming from, but I did not look further into the changeset as to why it was causing it. Brad said he would take a look at it, but I am not sure if he was able to reproduce the problem. Malek On Wed, Mar 9, 2011 at 7:08 PM, Korey Sewell ksew...@umich.edu wrote: Hi all, I'm trying to run Ruby in FS mode for the FFT benchmark. However, I've been unable to fully boot the kernel and error with a panic in the IDE disk controller: panic: Inconsistent DMA transfer state: dmaState = 2 devState = 1 @ cycle 62640732569001 [doDmaTransfer:build/ALPHA_FS_MOESI_CMP_directory/dev/ide_disk.cc, line 323] Has anybody run into a similar error or does anyone have any suggestions for debugging the problem? I can run the same code using the M5 memory system and FFT finishes properly so it's definitely a ruby-specific thing. It seems to track this down , I could diff instruction traces (M5 v. Ruby) or maybe even diff trace output from the IdeDisk trace flags but those routes seem a bit heavy-handed considering the amount of trace output generated. The command line this was run with is: build/ALPHA_FS_MOESI_CMP_directory/m5.opt configs/example/ruby_fs.py -b fft_64t_base -n 1 The output in system.terminal is: hda: M5 IDE Disk, ATA DISK drive hdb: M5 IDE Disk, ATA DISK drive hda: UDMA/33 mode selected hdb: UDMA/33 mode selected hdc: M5 IDE Disk, ATA DISK drive hdc: UDMA/33 mode selected ide0 at 0x8410-0x8417,0x8422 on irq 31 ide1 at 0x8418-0x841f,0x8426 on irq 31 ide_generic: please use probe_mask=0x3f module parameter for probing all legacy ISA IDE ports ide2 at 0x1f0-0x1f7,0x3f6 on irq 14 ide3 at 0x170-0x177,0x376 on irq 15 hda: max request size: 128KiB hda: 2866752 sectors (1467 MB), CHS=2844/16/63 hda:4hda: dma_timer_expiry: dma status == 0x65 hda: DMA interrupt recovery hda: lost interrupt unknown partition table hdb: max request size: 128KiB hdb: 1008000 sectors (516 MB), CHS=1000/16/63 hdb:4hdb: dma_timer_expiry: dma status == 0x65 hdb: DMA interrupt recovery hdb: lost interrupt Thanks again, any help or thoughts would be well appreciated. -- - Korey ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Functional Interface in Ruby
I believe the L1DcacheMemory is created right after system because inside each protocol file the first thing attached to the system is the l1 controllers. That way the controllers get a more descriptive name than what they are as related to the topology. I'm still a little confused by the cycle error. If the parent.any call searches the graph for the close object of that particular type, wouldn't you always get a cycle using parent.any? Or are other uses of parent.any more of an uncle search than a true parent search? Brad -Original Message- From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On Behalf Of Steve Reinhardt Sent: Wednesday, March 09, 2011 5:22 PM To: M5 Developer List Subject: Re: [m5-dev] Functional Interface in Ruby It seems odd that it tries to create L1DcacheMemory right after it creates system. Can you add print statements like in this patch and see what it shows? diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -843,8 +843,11 @@ # Call C++ to create C++ object corresponding to this object def createCCObject(self): +print Creating, self, params self.getCCParams() +print Creating, self self.getCCObject() # force creation +print Done creating, self def getValue(self): return self.getCCObject() On Wed, Mar 9, 2011 at 2:34 PM, Nilay Vaish ni...@cs.wisc.edu wrote: Creating root Creating system.physmem Creating system Creating system.l1_cntrl0.L1DcacheMemory Creating system.ruby Creating system.ruby.network Creating system.ruby.network.topology Creating system.ruby.network.topology.ext_links0 Creating system.l1_cntrl0 Creating system.l1_cntrl0.L1DcacheMemory This is the output I obtained from SimObject.py, clearly there is a cycle. Should not the cache controllers be part of ruby, instead of being part of system? Once they become part of ruby, it should be possible to traverse the controller array and figure out all the caches. Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: I think you're looking in the wrong place... you want to look at getCCObject() in src/python/m5/SimObject.py where the error message is coming from, and see if you can add some print statements there. Steve On Wed, Mar 9, 2011 at 11:27 AM, Nilay Vaish ni...@cs.wisc.edu wrote: What exactly happens on the function call Param.RubySystem(Parent.any, Ruby System) ? Nilay On Wed, 9 Mar 2011, Steve Reinhardt wrote: Does the RubySystem object have a pointer to a RubyCache object? You could also go into the python code and add some print statements to get a clue about where the cycle is occurring. Steve On Wed, Mar 9, 2011 at 4:51 AM, Nilay ni...@cs.wisc.edu wrote: Brad, given current versions of MESI_CMP_directory.py and Ruby.py, the following change to the way cache memory is added to the system creates a loop. What am I missing here? class RubyAbstractMemory(SimObject): type = 'RubyAbstractMemory' cxx_class = 'AbstractMemory' system = Param.RubySystem(Parent.any,Ruby System); class RubyCache(RubyAbstractMemory): type = 'RubyCache' cxx_class = 'CacheMemory' size = Param.MemorySize(capacity in bytes); latency = Param.Int(); assoc = Param.Int(); replacement_policy = Param.String(PSEUDO_LRU, ); start_index_bit = Param.Int(6, index start, default 6 for 64-byte line); -- Nilay ___ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset number in binary
I'm fine with getting rid of it. For me it's been the source of problems, particularly with update_ref, and I haven't personally seen a benefit. I don't object either. Though one simpler solution may to find out if there's a qparent tag and use that, but it still may not be useful enough. If we ever support stable again, we could tag that and use it. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset number in binary
On 03/09/11 18:44, nathan binkert wrote: I'm fine with getting rid of it. For me it's been the source of problems, particularly with update_ref, and I haven't personally seen a benefit. I don't object either. Though one simpler solution may to find out if there's a qparent tag and use that, but it still may not be useful enough. If we ever support stable again, we could tag that and use it. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev Yeah, if we'd ever used it and it was at least sort of useful the qparent idea would probably be worthwhile, but since it doesn't sound like that's the case we should probably just nuke it. I'll put a change together and get it up on review board soonish. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Captcha on wiki
Everyone, I've just added math captcha to the wiki to prevent spam. Please let me know if you run into any issues. Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
