[m5-dev] Miscreg dependents in O3CPU
Hi all, So now I've posted my PowerPC ISA patches, I'm trying to get it all working with O3CPU :-). I've come up against a difficulty right away. The processor is deadlocked because a branch instruction at the head of the ROB isn't marked as ready to execute. This is because it depends on a miscreg. When I look at the code, I can't see where this should be sorted out. In inst_queue_impl.hh in wakeDependents, we have the following comment before the code that skips over dependents on miscregs: // Special case of uniq or control registers. They are not // handled by the IQ and thus have no dependency graph entry. // @todo Figure out a cleaner way to handle this. My question is this: since they are not handled by the IQ, where are the miscreg dependents woken? I can't find this anywhere in the code. Can someone point me to the place it happens? In PowerPC, a lot of branches depend on a miscreg (the control register, possibly also the count register) so this could be a problem for me. Thanks Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Miscreg dependents in O3CPU
In PowerPC, a lot of branches depend on a miscreg (the control register, possibly also the count register) so this could be a problem for me. A question would be: is it reasonable to consider the misc. registers that you are referring to in PowerPC as integer registers? For example, in MIPS there are HI/LO registers that need to be accounted for. You could call those misc. registers, but in reality those are part of the integer register file. So what I'm getting at is, are you sure that those registers (control/count/etc.) should be specified as misc. registers? To my understanding, misc. registers should be registers that are controlled by the kernel (and probably some larger system state), thus you want to be careful about speculating on those types of registers. If you are convinced that the registers that you refer to are really just extra integer registers, than adding them to the Integer register file will probably solve your problem. But if those registers are indicative of some other system state then a more elegant solution is probably in order... Any one else have thoughts? -- - Korey ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Miscreg dependents in O3CPU
I don't know where this happens, but I second Korey's suggestion. The O3 cpu doesn't speculate around misc registers, so if you want to be able to speculate at all with an ISA that has a condition code or other such register, renaming it (or part of it) as an integer register is normally the way to go. Ali On Oct 8, 2009, at 8:26 AM, Korey Sewell wrote: In PowerPC, a lot of branches depend on a miscreg (the control register, possibly also the count register) so this could be a problem for me. A question would be: is it reasonable to consider the misc. registers that you are referring to in PowerPC as integer registers? For example, in MIPS there are HI/LO registers that need to be accounted for. You could call those misc. registers, but in reality those are part of the integer register file. So what I'm getting at is, are you sure that those registers (control/count/ etc.) should be specified as misc. registers? To my understanding, misc. registers should be registers that are controlled by the kernel (and probably some larger system state), thus you want to be careful about speculating on those types of registers. If you are convinced that the registers that you refer to are really just extra integer registers, than adding them to the Integer register file will probably solve your problem. But if those registers are indicative of some other system state then a more elegant solution is probably in order... Any one else have thoughts? -- - Korey ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Miscreg dependents in O3CPU
I agree with both Ali and Korey that MiscRegs that don't actually control anything and just pass around data (like condition codes) should be honorary integer registers. There are a number of examples of this, some of which are in SPARC specifically. One issue, though, is that by my understanding O3 should automatically mark MiscReg operands as ready. This can actually be a problem if you need the affect of changing one to impact instructions that might be in flight by the time it gets written. That means the instructions that change them need to block other instructions from starting, and if that happens often it can lead to simulated performance problems, leading to the suggestion in the first paragraph. Kevin can comment on this in more detail. Gabe Quoting Ali Saidi sa...@umich.edu: I don't know where this happens, but I second Korey's suggestion. The O3 cpu doesn't speculate around misc registers, so if you want to be able to speculate at all with an ISA that has a condition code or other such register, renaming it (or part of it) as an integer register is normally the way to go. Ali On Oct 8, 2009, at 8:26 AM, Korey Sewell wrote: In PowerPC, a lot of branches depend on a miscreg (the control register, possibly also the count register) so this could be a problem for me. A question would be: is it reasonable to consider the misc. registers that you are referring to in PowerPC as integer registers? For example, in MIPS there are HI/LO registers that need to be accounted for. You could call those misc. registers, but in reality those are part of the integer register file. So what I'm getting at is, are you sure that those registers (control/count/ etc.) should be specified as misc. registers? To my understanding, misc. registers should be registers that are controlled by the kernel (and probably some larger system state), thus you want to be careful about speculating on those types of registers. If you are convinced that the registers that you refer to are really just extra integer registers, than adding them to the Integer register file will probably solve your problem. But if those registers are indicative of some other system state then a more elegant solution is probably in order... Any one else have thoughts? -- - Korey ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
