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src/arch/arm/faults.cc
http://reviews.m5sim.org/r/681/#comment1661
The CPSR type has elements for some of these. You could add one for nz.
That would eliminate the need for the shifts, and is a large part of what the
bitunion types are for. Also be careful of order of operations.
src/arch/arm/isa/formats/pred.isa
http://reviews.m5sim.org/r/681/#comment1664
Watch order of operations. Even if it's technically correct, it's not
immediately obvious. You might want to throw in parenthesis just to be clearer
to a reader.
src/arch/arm/isa/formats/pred.isa
http://reviews.m5sim.org/r/681/#comment1665
It's not part of your change, but there should be a space around the :, I
think.
src/arch/arm/isa/insts/data.isa
http://reviews.m5sim.org/r/681/#comment1666
Parenthesis, bitfields.
src/arch/arm/isa/insts/fp.isa
http://reviews.m5sim.org/r/681/#comment1667
Doesn't this change the behavior of this instruction? It used to write to a
gpr, now it writes to the condition codes. Is that on purpose?
src/arch/arm/isa/insts/ldr.isa
http://reviews.m5sim.org/r/681/#comment1668
Parenthesis, bitfields.
src/arch/arm/isa/insts/macromem.isa
http://reviews.m5sim.org/r/681/#comment1669
Parenthesis, bitfields.
src/arch/arm/isa/insts/macromem.isa
http://reviews.m5sim.org/r/681/#comment1670
Bitfields.
src/arch/arm/isa/insts/macromem.isa
http://reviews.m5sim.org/r/681/#comment1671
Bitfields.
src/arch/arm/isa/templates/pred.isa
http://reviews.m5sim.org/r/681/#comment1672
Spaces after commas.
src/arch/arm/nativetrace.cc
http://reviews.m5sim.org/r/681/#comment1662
Why the shift up above but not here?
src/arch/arm/utility.hh
http://reviews.m5sim.org/r/681/#comment1663
The == 0x2 isn't needed since (nz 0x2) will either be 0x2 or 0. That maps
to true and false naturally.
- Gabe
On 2011-05-04 18:44:54, Ali Saidi wrote:
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(Updated 2011-05-04 18:44:54)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
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ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are
individually
written and this removes some incorrect dependencies between instructions.
Diffs
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src/arch/arm/faults.cc 5a9a639ce16f
src/arch/arm/intregs.hh 5a9a639ce16f
src/arch/arm/isa/formats/fp.isa 5a9a639ce16f
src/arch/arm/isa/formats/pred.isa 5a9a639ce16f
src/arch/arm/isa/insts/data.isa 5a9a639ce16f
src/arch/arm/isa/insts/fp.isa 5a9a639ce16f
src/arch/arm/isa/insts/ldr.isa 5a9a639ce16f
src/arch/arm/isa/insts/macromem.isa 5a9a639ce16f
src/arch/arm/isa/insts/mem.isa 5a9a639ce16f
src/arch/arm/isa/insts/misc.isa 5a9a639ce16f
src/arch/arm/isa/insts/mult.isa 5a9a639ce16f
src/arch/arm/isa/insts/str.isa 5a9a639ce16f
src/arch/arm/isa/operands.isa 5a9a639ce16f
src/arch/arm/isa/templates/pred.isa 5a9a639ce16f
src/arch/arm/isa/templates/vfp.isa 5a9a639ce16f
src/arch/arm/miscregs.hh 5a9a639ce16f
src/arch/arm/nativetrace.cc 5a9a639ce16f
src/arch/arm/utility.hh 5a9a639ce16f
Diff: http://reviews.m5sim.org/r/681/diff
Testing
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Thanks,
Ali
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